DS1647P-150 [MAXIM]
Non-Volatile SRAM, 512KX8, 150ns, CMOS;
| 型号： | DS1647P-150 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Non-Volatile SRAM, 512KX8, 150ns, CMOS 时钟 双倍数据速率 静态存储器 外围集成电路 |
| 文件： | 总11页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1647/DS1647P
Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
§ Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
§ Clock registers are accessed identical to the
static RAM. These registers are resident in
the eight top RAM locations
§ Totally nonvolatile with over 10 years of
operation in the absence of power
§ Access time of 120 ns and 150 ns
§ BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
A18
A16
A14
A12
A7
1
32
31
VCC
A15
A17
WE
A13
A8
2
3
4
30
29
5
6
28
27
A6
A5
A9
7
8
26
25
A11
OE
A10
CE
A4
A3
A2
A1
9
10
24
23
11
12
22
21
DQ7
DQ6
A0
13
14
15
16
20
19
18
17
DQ0
DQ1
DQ2
DQ5
DQ4
DQ3
§ Power-fail write protection allows for ±10%
VCC power supply tolerance
GND
§ DS1647 only (DIP Module)
512K X 8
32-PIN ENCAPSULATED PACKAGE
-
Upward compatible with the DS1646
Timekeeping RAM
-
Standard JEDEC Byte-wide 512k x 8
static RAM pinout
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
1
2
3
NC
A15
A16
§ DS1647P only (PowerCap Module Board)
-
Surface mountable package for direct
connection to PowerCap containing
battery and crystal
A13
A12
A11
4
5
6
PFO
VCC
WE
A10
7
OE
A9
8
CE
A8
9
DQ7
-
-
Replaceable battery (PowerCap)
Power-fail output
A7
A6
A5
A4
A3
A2
A1
A0
10
11
12
13
14
15
16
17
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
- Pin-for-pin compatible with other
densities of DS164XP Timekeeping
RAM
VBAT X2
X1 GND
34-PIN POWERCAP MODULE BOARD
(USES DS9034PCX POWERCAP)
ORDERING INFORMATION
DS1647-XXX
(28-pin DIP module)
-120
-150
120 ns access
150 ns access
*DS1647P-XXX
(34-pin PowerCap Module
Board)
-120
-150
120 ns access
150 ns access
*DS9034PCX
(Power Cap) Required;
must be ordered separately
1 of 11
080299
DS1647/DS1647P
PIN DESCRIPTION
A0-A18
- Address Input
DQ0-DQ7
NC
- Data Input/Output
- No Connection
- Chip Enable
CE
- Power-fail Output
(DS1647P only)
- Crystal Connection
- Battery Connection
PFO
- Output Enable
- Write Enable
- +5 Volts
OE
WE
X1, X2
VBAT
VCC
GND
- Ground
DESCRIPTION
The DS1647 is a 512k x 8 nonvolatile static RAM with a full function real time clock which are both
accessible in a Byte-wide format. The nonvolatile time keeping RAM is function equivalent to any
JEDEC standard 512k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double buffered to avoid access
of incorrect data that can occur during clock update cycles. The double buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1647
also contains its own power-fail circuitry which deselects the device when the VCC supply is in an out of
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low VCC as errant access and update cycles are avoided.
PACKAGES
The DS1647 is available in two packages (32-pin DIP module and 34-pin PowerCap module). The 32-pin
Dip style module integrated the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. The design allows the PowerCap to be mounted on top of the
DS1647P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCK
While the double buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1647 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, the seventh most significant bit in the control
register. As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was issued.
However, the internal clock registers of the double buffered system continue to update so that the clock
accuracy is not affected by the access of data. All of the DS1647 registers are updated simultaneously
after the clock status is reset. Updating is within a second after the read bit is written to zero.
2 of 11
DS1647/DS1647P
BLOCK DIAGRAM DS1647 Figure 1
TRUTH TABLE DS1647 Table 1
VCC
MODE
DQ
POWER
CE
VIH
X
OE
WE
X
X
VIL
VIH
VIH
X
X
X
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
VIL
VIL
VIL
X
X
5 VOLTS ± 10%
VIL
VIH
X
<4.5 VOLTS >VBAT
<VBAT
HIGH-Z
HIGH-Z
CMOS STANDBY
DATA RETENTION
MODE
X
X
X
SETTING THE CLOCK
The eighth bit of the control register is the write bit. Setting the write bit to a one, like the read bit, halts
updates to the DS1647 registers. The user can then load them with the correct day, date and time data in
24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
a one stops the oscillator.
bit is the MSB for the seconds registers. Setting it to
OSC
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic “1” and the
oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid
(i.e.,
low,
low, and address for seconds register remain valid and stable).
OE
CE
3 of 11
DS1647/DS1647P
CLOCK ACCURACY (DIP MODULE)
The DS1647 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The clock is
calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements.
The DS1647does not require additional calibration and temperature deviations will have a negligible
effect in most applications. For this reason, methods of field clock calibration are not available and not
necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1647P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.
DS1647 REGISTER MAP - BANK1 Table 2
DATA
ADDRESS
FUNCTION
B7
-
B6
-
B5
-
X
-
X
-
-
B4
-
-
-
X
-
B3
-
-
-
X
-
B2
-
-
-
-
-
-
-
B1
-
-
-
-
-
-
-
B0
-
-
-
-
-
-
-
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
YEAR
MONTH
DATE
00-99
X
X
X
X
X
X
X
FT
X
-
01-12
01-31
01-07
00-23
00-59
00-59
A
DAY
HOUR
-
-
-
-
MINUTES
SECONDS
CONTROL
-
-
OSC
7FFF8
W
R
X
X
X
X
X
X
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
= STOP BIT
= WRITE BIT
OSC
W
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
4 of 11
DS1647/DS1647P
RETRIEVING DATA FROM RAM OR CLOCK
The DS1647 is in the read mode whenever WE (write enable) is high,
(chip enable) is low. The
CE
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the
CE
and
access times and states are satisfied. If
or
access times are not met, valid data will be
OE
OE
CE
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by and . If the outputs are activated before t , the data
CE
OE
AA
lines are driven to an intermediate state until tAA. If the address inputs are changed while
and
OE
CE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1647 is in the write mode whenever WE and
are in their active state. The start of a write is
CE
referenced to the latter occurring high to low transition of WE and
. The addresses must be held valid
CE
throughout the cycle.
or WE must return inactive for a minimum of tWR prior to the initiation of
CE
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the signal will be high during a write cycle. However, can be
OE
OE
active provided that care is taken with the data bus to avoid bus contention. If
is low prior to WE
OE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCCI is within nominal limits (VCC > 4.5 volts) the DS1647 can be accessed as described above
with read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished
internally by inhibiting access via the
signal. At this time the power-fail output signal (PFO ) will be
CE
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.
5 of 11
DS1647/DS1647P
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.3V to +7.0V
0°C to 70°C
Storage Temperature
-20°C to +70°C
Soldering Temperature
260°C for 10 seconds (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to +70°C)
UNITS NOTES
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
5.5
VCC+0.3
0.8
Supply Voltage
Logic 1 Voltage All Inputs
Logic 0 Voltage All Inputs
VCC
VIH
VIL
4.5
2.2
-0.3
V
V
V
1
DC ELECTRICAL CHARACTERISTICS
(0°C £ tA £ +70°C; VCC =5.0V ± 10%)
PARAMETER
SYMBOL MIN
TYP
MAX
95
UNITS NOTES
Average VCC Power Supply Current
ICC1
ICC2
mA
mA
2, 3
2, 3
3
2
6
TTL Standby Current ( =V )
CE
IH
CMOS Standby Current
ICC3
4.0
mA
2, 3
(
=V -0.2V)
CE
CC
Input Leakage Current (any input)
Output Leakage Current
Output Logic 1 Voltage
(IOUT = -1.0 mA)
IIL
IOL
VOH
-1
-1
2.4
+1
+1
mA
mA
V
Output Logic 0 Voltage
(IOUT = +2.1 mA)
Write Protection Voltage
VOL
VPF
0.4
4.5
V
V
4.0
4.25
6 of 11
DS1647/DS1647P
AC ELECTRICAL CHARACTERISTICS
(0°C to +70°C; VCC = 5.0V + 10%)
DS1647-120
DS1647-150
PARAMETER
SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time
Address Access Time
tRC
tAA
tCEA
120
150
ns
ns
ns
120
120
150
150
Access Time
CE
tCEZ
40
50
ns
Data Off Time
CE
Output Enable Access Time
Output Enable Data Off Time
Output Enable to DQ Low-Z
tOEA
tOEZ
tOEL
tCEL
100
40
120
50
ns
ns
ns
ns
5
5
5
5
to DQ Low-Z
CE
Output Hold from Address
Write Cycle Time
Address Setup Time
tOH
tWC
tAS
5
120
0
5
150
0
ns
ns
ns
ns
tCEW
100
120
Pulse Width
CE
Address Hold from End of Write
tAH1
tAH2
tWEW
tWEZ
5
30
75
5
30
90
ns
ns
ns
ns
5
6
Write Pulse Width
40
50
Data Off Time
WE
WE
tWR
10
10
ns
or
Inactive Time
CE
Data Setup Time
Data Hold Time High
tDS
tDH1
tDH2
85
0
25
110
0
25
ns
ns
ns
5
6
AC TEST CONDITIONS
Input Levels:
Transition Times:
0V to 3V
5 ns
CAPACITANCE
PARAMETER
Capacitance on all pins (except DQ)
Capacitance on DQ pins
(tA = 25°C)
UNITS NOTES
SYMBOL MIN
TYP
MAX
7
10
CI
CDQ
pF
pF
AC ELECTRICAL CHARACTERISTICS
(POWER-UP/DOWN TIMING)
(0°C to +70°C)
UNITS NOTES
ms
PARAMETER
SYMBOL MIN
TYP
MAX
tPD
0
or at VIH before Power Down
CE
WE
VPF (Max) to VPF (Min) VCC Fall Time
VPF (Min) to VSO VCC Fall Time
VSO to VPF (Min) VCC Rise Time
VPF (Min) to VPF (Max) VCC Rise Time
Power-Up
tF
tFB
tRB
tR
tREC
tDR
300
10
1
0
15
10
ms
ms
ms
ms
ms
25
35
Expected Data Retention Time
(Oscillator On)
years
4
7 of 11
DS1647/DS1647P
DS1647 READ CYCLE TIMING
DS1647 WRITE CYCLE TIMING
8 of 11
DS1647/DS1647P
POWER-DOWN/POWER-UP TIMING
NOTES:
1. All voltages are referenced to ground.
OUTPUT LOAD
2. Typical values are at 25°C and nominal
supplies.
3. Outputs are open.
4. Data retention time is at 25°C and is
calculated from the date code on the device
package. The date code XXYY is the year
followed by the week of the year in which
the device was manufactured. For example,
9225, would mean the 25th week of 1992.
5. tAH1, tDH1 are measured from
6. tAH2, tDH2 are measured from
going high.
going high.
WE
CE
7. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live - bug”).
b. Hand Soldering and touch - up: Do not touch or apply the soldering iron to leads for more than 3
(three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
9 of 11
DS1647/DS1647P
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick
to remove solder.
DS1647 32-PIN PACKAGE
PKG
DIM
32-PIN
MIN
MAX
A IN.
MM
B IN.
MM
C IN.
MM
1.670
38.42
0.715
18.16
0.335
8.51
1.690
38.93
0.740
18.80
0.365
9.27
D IN.
MM
0.075
1.91
0.105
0.67
E IN.
MM
0.015
0.38
0.030
0.76
F IN.
MM
0.140
3.56
0.180
4.57
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
J IN.
MM
0.590
14.99
0.010
0.25
0.630
16.00
0.018
0.45
K IN.
MM
0.015
0.38
0.025
0.64
DS1647P
PKG
DIM
A
B
C
D
E
F
G
INCHES
MIN
NOM
0.925
0.985
-
0.055
0.050
0.020
0.027
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
0.920
0.980
-
0.052
0.048
0.015
0.025
NOTE: For the PowerCap version:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live - bug”).
b. Hand Soldering and touch - up: Do not touch or apply the soldering iron to leads for more than 3
(three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick
to remove solder.
10 of 11
DS1647/DS1647P
DS1647P WITH DS9034PCX ATTACHED
PKG
DIM
A
B
C
D
E
F
G
INCHES
NOM
MIN
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
0.920
0.955
0.240
0.052
0.048
0.015
0.020
0.925
0.960
0.245
0.055
0.050
0.020
0.025
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
INCHES
NOM
MIN
MAX
A
B
C
D
E
-
-
-
-
-
1.050
0.826
0.050
0.030
0.112
-
-
-
-
-
11 of 11
相关型号：
©2020 ICPDF网 联系我们和版权申明