DS1340-3 [MAXIM]
I2C RTC with Trickle Charger; I²C RTC ，带有涓流充电器
| 型号： | DS1340-3 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | I2C RTC with Trickle Charger |
| 文件： | 总14页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 4; 3/06
2
I C RTC with Trickle Charger
General Description
Features
♦ Enhanced Second Source for the ST M41T00
The DS1340 is a real-time clock (RTC)/calendar that is
pin compatible and functionally equivalent to the ST
M41T00, including the software clock calibration. The
device additionally provides trickle-charge capability
♦ Available in a Surface-Mount Package with an
Integrated Crystal (DS1340C)
2
♦ Fast (400kHz) I C Interface
on the V
pin, a lower timekeeping voltage, and
BACKUP
♦ Software Clock Calibration
an oscillator STOP flag. Block access of the register
map is identical to the ST device. Two additional regis-
ters, which are accessed individually, are required for
the trickle charger and flag. The clock/calendar pro-
vides seconds, minutes, hours, day, date, month, and
year information. A built-in power-sense circuit detects
power failures and automatically switches to the back-
up supply. Reads and writes are inhibited while the
clock continues to run. The device is programmed seri-
♦ RTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and Year
♦ Automatic Power-Fail Detect and Switch Circuitry
♦ Trickle-Charge Capability
♦ Low Timekeeping Voltage Down to 1.3V
♦ Three Operating Voltage Ranges (1.8V, 3V, and 3.3V)
♦ Oscillator Stop Flag
ally through an I C* bidirectional bus.
2
♦ Available in 8-Pin µSOP or SO Packages
♦ Underwriters Laboratory (UL) Recognized
Applications
Ordering Information
Portable Instruments
Point-of-Sale Equipment
Medical Equipment
Telecommunications
TOP
MARK
PART
TEMP RANGE PIN-PACKAGE
†
DS1340Z-18
DS1340Z-3
DS1340Z-33
DS1340U-18
DS1340U-3
DS1340U-33
DS1340C-18
DS1340C-3
DS1340C-33
-40°C to +85°C 8 SO (0.150in) D1340-18
-40°C to +85°C 8 SO (0.150in) DS1340-3
-40°C to +85°C 8 SO (0.150in) D1340-33
-40°C to +85°C 8 µSOP
-40°C to +85°C 8 µSOP
-40°C to +85°C 8 µSOP
-40°C to +85°C 16 SO
-40°C to +85°C 16 SO
-40°C to +85°C 16 SO
1340A1-18
1340A1-3
1340A1-33
1340C-18
1340C-3
Typical Operating Circuit
V
V
CC
CC
CRYSTAL
1340C-33
V
CC
C1
R
PU
R
PU
1
2
8
DS1340Z-18+ -40°C to +85°C 8 SO (0.150in) D1340-18
DS1340Z-3+ -40°C to +85°C 8 SO (0.150in) DS1340-3
DS1340Z-33+ -40°C to +85°C 8 SO (0.150in) D1340-33
X1
X2
V
CC
7
3
6
5
SCL
FT/OUT
CPU
DS1340U-18+ -40°C to +85°C 8 µSOP
DS1340U-3+ -40°C to +85°C 8 µSOP
1340A1-18
1340A1-3
1340A1-33
1340C-18
1340C-3
DS1340
SDA
V
BACKUP
DS1340U-33+ -40°C to +85°C 8 µSOP
DS1340C-18# -40°C to +85°C 16 SO
GND
4
R
PU
= t / C
R B
DS1340C-3#
-40°C to +85°C 16 SO
DS1340C-33# -40°C to +85°C 16 SO
1340C-33
+ Denotes a lead-free/RoHS-compliant device.
# Denotes a RoHS-compliant device that may include lead that
is exempt under RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-based and lead-
free soldering processes.
† A "+" anywhere on the top mark denotes a lead-free device.
A "#" denotes a RoHS-compliant device.
2
*Purchase of I C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
2
a license under the Philips I C Patent Rights to use these com-
2
ponents in an I C system, provided that the system conforms to
2
the I C Standard Specification as defined by Philips.
Pin Configurations appear at end of data sheet.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2
I C RTC with Trickle Charger
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
Voltage Range on SDA, SCL, and FT/OUT
Relative to Ground..................................-0.3V to (V
Pin Relative to Ground .....-0.3V to +6.0V
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature Range............................See IPC/JEDEC
J-STD-020 Specification
CC
+ 0.3V)
CC
Operating Temperature Range ...........................-40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AC ELECTRICAL CHARACTERISTICS
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1)
CC MAX A
CC
CC MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Standard mode
Fast mode
0
100
SCL Clock Frequency
f
kHz
SCL
100
4.7
400
Standard mode
Fast mode
Bus Free Time Between STOP
and START Conditions
t
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs
BUF
1.3
Standard mode
Fast mode
4.0
Hold Time (Repeated) START
Condition (Note 2)
t
HD:STA
0.6
Standard mode
Fast mode
4.7
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 3, 4)
Data Setup Time (Note 5)
START Setup Time
t
LOW
1.3
Standard mode
Fast mode
4.0
t
HIGH
0.6
Standard mode
Fast mode
0
0.9
0.9
t
HD:DAT
0
Standard mode
Fast mode
250
t
SU:DAT
100
Standard mode
Fast mode
4.7
t
SU:STA
0.6
Standard mode
Fast mode
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
4.7
1000
300
300
300
B
Rise Time of SDA and SCL
Signals (Note 6)
t
R
B
B
B
Standard mode
Fast mode
Fall Time of SDA and SCL Signals
(Note 6)
t
F
Standard mode
Fast mode
Setup Time for STOP Condition
t
SU:STO
0.6
Capacitive Load for Each Bus
Line
C
(Note 6)
400
pF
pF
ns
B
I/O Capacitance (SCL, SDA)
C
10
30
I/O
SP
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
t
Fast mode
(Note 7)
Oscillator Stop Flag (OSF) Delay
t
100
ms
OSF
2
_____________________________________________________________________
2
I C RTC with Trickle Charger
RECOMMENDED DC OPERATING CONDITIONS
(V
= V
to V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 3.3V, T = +25°C, unless
CC A
CC MIN
CC MAX
CC
A
otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DS1340-18
DS1340-3
DS1340-33
(Note 8)
1.71
2.7
1.8
1.89
Supply Voltage (Note 8)
V
V
3.0
3.3
3.3
5.5
CC
2.97
0.7 x V
-0.3
Input Logic 1 (SDA, SCL)
Input Logic 0 (SDA, SCL)
V
V + 0.3
CC
V
V
IH
CC
V
(Note 8)
+0.3 x V
CC
IL
Supply Voltage, Pullup
(FT/OUT, SDA, SCL), V
V
(Note 8)
5.5
V
PU
= 0V
CC
DS1340-18
DS1340-3
DS1340-33
(Notes 9, 10)
(Note 11)
1.3
1.3
1.3
3.7
3.7
5.5
Backup Supply Voltage (Note 8)
V
BACKUP
V
R1
R2
R3
250
2000
4000
1.6
Trickle-Charge Current-Limiting
Resistors
Ω
(Note 12)
DS1340-18
DS1340-3
DS1340-33
1.51
2.45
2.70
-1
1.71
2.7
Power-Fail Voltage (Note 8)
V
V
2.6
PF
2.88
2.97
+1
Input Leakage (SCL, CLK)
I/O Leakage (SDA, FT/OUT)
I
µA
µA
LI
I
-1
+1
LO
V
> 2V; V = 0.4V
3.0
CC
OL
SDA Logic 0 Output
I
mA
OLSDA
1.7V < V
< 2V; V = 0.2 x V
3.0
CC
OL
CC
V
> 2V; V = 0.4V
3.0
CC
OL
mA
µA
FT/OUT Logic 0 Output
I
1.7V < V
1.3V < V
< 2V; V = 0.2 x V
3.0
OLSQW
CC
CC
OL
CC
< 1.7V; V = 0.2x V
250
150
200
300
100
125
150
100
OL
CC
DS1340-18
DS1340-3
DS1340-33
DS1340-18
DS1340-3
DS1340-33
72
108
192
60
Active Supply Current (Note 13)
Standby Current (Note 14)
I
µA
CCA
I
µA
nA
81
CCS
100
V
Leakage Current
I
V
= 3.7V
BACKUP
BACKUP
BACKUPLKG
DC ELECTRICAL CHARACTERISTICS
(V
= 0V, V
= 3.7V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
BACKUP A
CC
PARAMETER
SYMBOL
CONDITIONS
OSC ON, FT = 0 (Note 15)
OSC ON, FT = 1 (Note 15)
MIN
TYP
800
850
MAX
1150
1250
UNITS
nA
I
BACKUP1
BACKUP2
I
V
V
Current
BACKUP
BACKUP
OSC ON, FT = 0, V
= 3.0V,
BACKUP
I
800
1000
100
BACKUP3
T
A
= +25°C (Notes 15, 16)
Data-Retention Current
I
OSC OFF
25.0
nA
BACKUPDR
_____________________________________________________________________
3
2
I C RTC with Trickle Charger
POWER-UP/POWER-DOWN CHARACTERISTICS
(T = -40°C to +85°C) (Figure 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Recovery at Power-Up
t
(Note 17)
2
ms
REC
V
V
Fall Time; V
PF(MIN)
to
to
CC
PF(MAX)
t
300
0
µs
µs
VCCF
V
V
Rise Time; V
PF(MIN)
PF(MAX)
CC
t
VCCR
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
Note 1:
Note 2:
Note 3:
Limits at -40°C are guaranteed by design and not production tested.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
signal) to bridge the undefined region of the falling edge of SCL.
of the SCL
IH(MIN)
Note 4:
Note 5:
The maximum t
only has to be met if the device does not stretch the low period (t
) of the SCL signal.
≥ to 250ns must be met. This
HD:DAT
LOW
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
+ t
= 1000 + 250 = 1250ns
R MAX
SU:DAT
Note 6:
Note 7:
C —total capacitance of one bus line in pF.
B
The parameter t
is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V ≤ V
≤
CC
OSF
V
and 1.3V ≤ V
≤ 3.7V range.
CCMAX
BAT
Note 8:
Note 9:
All voltages are referenced to ground.
Measured at V = typ, V = 0V, register 08h = A5h.
CC
BACKUP
Note 10: The use of the 250Ω trickle-charge resistor is not allowed at V
> 3.63V and should not be enabled.
CC
Note 11: Measured at V
Note 12: Measured at V
= typ, V
= typ, V
= 0V, register 08h = A6h.
= 0V, register 08h = A7h.
CC
CC
BACKUP
BACKUP
Note 13:
I
—SCL clocking at max frequency = 400kHz.
CCA
2
Note 14: Specified with I C bus inactive.
Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 16: Limits at +25°C are guaranteed by design and not production tested.
Note 17: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay
occurs.
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
R
t
F
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
SU:STO
t
REPEATED
START
SU:DAT
STOP
START
t
HD:DAT
2
Figure 1. Data Transfer on I C Serial Bus
4
_____________________________________________________________________
2
I C RTC with Trickle Charger
V
CC
PF(MAX)
V
V
V
PF
PF
V
PF(MIN)
t
t
F
R
t
RPU
t
RST
RST
RECOGNIZED
VALID
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
Figure 2. Power-Up/Power-Down Timing
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
A
CC
I
vs. V FT = 0
I
vs. V FT = 0
CC
I (FT = 0) vs. V
BACKUP1 BACKUP
CCSA
CC
CCS
250
150
125
100
75
850
800
750
700
650
600
550
500
450
400
200
150
100
50
-3.3V
-3.0V
-1.8V
50
25
0
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
V
V
BACKUP
(V)
CC
CC
I
(FT = 1) vs. V
BACKUP
FT vs. V
I
vs. TEMPERATURE
BACKUP2
BACKUP
BACKUP3
850
800
750
700
650
600
550
500
450
400
512.0000
511.9995
511.9990
511.9985
511.9980
511.9975
511.9970
511.9965
511.9960
850
800
750
700
650
600
550
500
V
= 3.0V
BACKUP
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
-40
-20
0
20
40
60
80
V
V
TEMPERATURE (°C)
BACKUP
BACKUP
_____________________________________________________________________
5
2
I C RTC with Trickle Charger
Pin Description
PIN
NAME
X1
FUNCTION
Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for
8
16
1
—
operation with a crystal having a specified load capacitance (C ) of 12.5pF. X1 is the input to the oscillator
L
and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator,
X2, is floated if an external oscillator is connected to X1.
2
3
—
X2
Connection for a Secondary Power Supply. For the 1.8V and 3V devices, V
must be held between
BACKUP
1.3V and 3.7V for proper operation. Diodes placed in series between the supply and the input pin may
result in improper operation. V can be as high as 5.5V on the 3.3V device.
BACKUP
14
V
BACKUP
This pin can be connected to a primary cell such as a lithium coin cell. Additionally, this pin can be
connected to a rechargeable cell or a super cap when used with the trickle-charge feature. UL recognized
to ensure against reverse charging when used with a lithium battery (www.maxim-ic.com/qa/info/ul).
4
5
15
16
GND
SDA
Ground
2
Serial Data Input/Output. SDA is the data input/output for the I C serial interface. The SDA pin is open drain
and requires an external pullup resistor.
2
Serial Clock Input. SCL is the clock input for the I C interface and is used to synchronize data movement on
the serial interface.
6
7
1
2
SCL
Frequency Test/Output. This pin is used to output either a 512Hz signal or the value of the OUT bit. When
the FT bit is logic 1, the FT/OUT pin toggles at a 512Hz rate. When the FT bit is logic 0, the FT/OUT pin
reflects the value of the OUT bit. This open-drain pin requires an external pullup resistor, and operates with
FT/OUT
either V
or V
applied.
BACKUP
CC
Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data
can be written and read. When a backup supply is connected to the device and V is below V , reads and
CC
TP
8
3
V
CC
writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage.
—
4–13
N.C.
No Connection. Must be connected to ground.
V
drops below V . If V is greater than V
,
CC
PF
PF
BACKUP
to V
BACKUP
Detailed Description
the device power is switched from V
CC
The DS1340 is a low-power clock/calendar with a trickle
charger. Address and data are transferred serially
when VCC drops below V
maintained from the V
returned to nominal levels (Table 1). After V
above V , read and write access is allowed t
. The registers are
BACKUP
source until V
is
CC
returns
BACKUP
2
through a I C bidirectional bus. The clock/calendar pro-
CC
vides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The DS1340
has a built-in power-sense circuit that detects power fail-
ures and automatically switches to the backup supply.
.
PF
REC
Table 1. Power Control
READ/WRITE
SUPPLY CONDITION
POWERED
BY
ACCESS
Power Control
V
CC
< V
,
CC
PF
< V
BACKUP
No
No
V
BAT
V
V
V
V
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
V
CC
< V
,
CC
PF
BACKUP
V
CC
CC
CC
comparator circuit that monitors the V
level. The
CC
> V
device is fully accessible and data can be written and
V
CC
> V
,
CC
PF
BACKUP
read when V is greater than V . However, when V
CC
PF
PF
CC
Yes
Yes
V
< V
falls below V , the internal clock registers are blocked
from any access. If V
is less than V
, the
BACKUP
PF
V
CC
> V
,
CC
PF
BACKUP
V
device power is switched from V
to V
when
CC
BACKUP
> V
6
_____________________________________________________________________
2
I C RTC with Trickle Charger
Oscillator Circuit
Operation
The DS1340 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 2 specifies several crys-
tal parameters for the external crystal. Figure 3 shows a
functional schematic of the oscillator circuit. If using a
crystal with the specified characteristics, the startup
time is usually less than one second.
The DS1340 operates as a slave device on the serial
bus. Access is obtained by implementing a START
condition and providing a device identification code fol-
lowed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The
device is fully accessible and data can be written and
read when V
CC
is greater than V . However, when
PF
falls below V , the internal clock registers are
CC
V
PF
Clock Accuracy
blocked from any access. If V is less than V
,
BACKUP
PF
The initial clock accuracy depends on the accuracy of
the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capaci-
tive load for which the crystal was trimmed. Additional
error is added by crystal frequency drift caused by
temperature shifts. External circuit noise coupled into
the oscillator circuit can result in the clock running fast.
Figure 4 shows a typical PC board layout for isolating
the crystal and oscillator from noise. Refer to
Application Note 58: Crystal Considerations with Dallas
Real-Time Clocks (www.maxim-ic.com/RTCapps) for
detailed information.
the device power is switched from V
to V
BACKUP
CC
when V
drops below V . If V
is greater than
CC
PF
PF
V
V
, the device power is switched from V
to
CC
BACKUP
BACKUP
ters are maintained from the V
when V
drops below V
. The regis-
CC
BACKUP
source until V
CC
BACKUP
is returned to nominal levels. The functional diagram
(Figure 5) shows the main elements of the serial RTC.
LOCAL GROUND PLANE (LAYER 2)
X1
DS1340C Only
The DS1340C integrates a standard 32,768Hz crystal
CRYSTAL
into the package. Typical accuracy with nominal V
CC
X2
and +25°C is approximately +15ppm. Refer to
Application Note 58 for information about crystal accu-
racy vs. temperature.
Table 2. Crystal Specifications*
PARAMETER
Nominal
Frequency
SYMBOL MIN
TYP
MAX UNITS
GND
f
32.768
kHz
O
Series Resistance
Load Capacitance
ESR
45,60**
kΩ
pF
Figure 4. Layout Example
C
12.5
L
*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocks for addi-
tional specifications.
X1
X2
FT/OUT
32,768Hz
512Hz
MUX/BUFFER
**A crystal with up to 60kΩ ESR can be used if the minimum
OSCILLATOR
operating voltages on both V
and V
are at least 2.0V.
CC
BACKUP
DIVIDER AND
CALIBRATION
CIRCUIT
"C" VERSION ONLY
RTC
V
CC
POWER
CONTROL
CLOCK AND
CALENDAR
REGISTERS
1Hz
V
BACKUP
COUNTDOWN
CHAIN
CONTROL
LOGIC
SCL
SDA
SERIAL BUS
INTERFACE
AND ADDRESS
REGISTER
USER BUFFER
(7 BYTES)
RTC
REGISTERS
C 1
L
C 2
L
DS1340
X2
X1
CRYSTAL
Figure 5. Functional Diagram
_____________________________________________________________________
Figure 3. Oscillator Circuit Showing Internal Bias Network
7
2
I C RTC with Trickle Charger
enable oscillator (EOSC) bit. When this bit is set to 1, the
Address Map
oscillator is disabled. When cleared to 0, the oscillator is
Table 3 shows the DS1340 address map. The RTC reg-
isters are located in address locations 00h to 06h, and
the control register is located at 07h. The trickle-charge
and flag registers are located in address locations 08h
to 09h. During a multibyte access of the timekeeping
registers, when the address pointer reaches 07h—the
end of the clock and control register space—it wraps
around to location 00h. Writing the address pointer to
the corresponding location accesses address locations
08h and 09h. After accessing location 09h, the address
enabled. The initial power-up value of EOSC is 0.
Location 02h is the century/hours register. Bit 7 and bit
6 of the century/hours register are the century-enable
bit (CEB) and the century bit (CB). Setting CEB to logic
1 causes the CB bit to toggle, either from a logic 0 to a
logic 1, or from a logic 1 to a logic 0, when the years
register rolls over from 99 to 00. If CEB is set to logic 0,
CB does not toggle.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the
time and date registers, the user buffers are synchro-
nized to the internal registers on any START or STOP
and when the register pointer rolls over to zero. The
time information is read from these secondary registers
while the clock continues to run. This eliminates the
need to reread the registers in case the internal regis-
ters update during a read.
2
pointer wraps around to location 00h. On a I C START,
STOP, or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Table 3 shows the
RTC registers. The time and calendar data are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The day-of-week
register increments at midnight. Values that correspond
to the day of week are user-defined but must be
sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries
result in undefined operation. Bit 7 of register 0 is the
The divider chain is reset whenever the seconds regis-
ter is written. Write transfers occur on the acknowledge
from the DS1340. Once the divider chain is reset, to
avoid rollover issues, the remaining time and date reg-
isters must be written within one second.
Special-Purpose Registers
The DS1340 has three additional registers (control,
trickle charger, and flag) that control the RTC, trickle
charger, and oscillator flag output.
Table 3. Address Map
ADDRESS
00H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
Seconds
Minutes
Century/Hours
Day
RANGE
00–59
00–59
0–1; 00–23
01–07
01–31
01–12
00–99
—
EOSC
10 Seconds
10 Minutes
Seconds
01H
X
CEB
X
Minutes
Hours
02H
CB
X
10 Hours
03H
X
X
X
X
Day
04H
X
X
10 Date
Date
Month
Year
Date
05H
X
X
10 Month
Month
06H
10 Year
Year
07H
OUT
TCS3
OSF
FT
TCS2
0
S
TCS1
0
CAL4
TCS0
0
CAL3
DS1
0
CAL2
DS0
0
CAL1
CAL0
Control
08H
ROUT1
0
ROUT0 Trickle Charger
Flag
—
09H
0
—
X = Read/Write bit
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
8
_____________________________________________________________________
2
I C RTC with Trickle Charger
is disabled when power is first applied. The diode-
select (DS) bits (bits 2, 3) select whether or not a diode
Control Register (07h)
Bit 7: Output Control (OUT). This bit controls the out-
put level of the FT/OUT pin when the FT bit is set to 0. If
FT = 0, the logic level on the FT/OUT pin is 1 if OUT = 1
and 0 if OUT = 0. The initial power-up OUT value is 1.
is connected between V
and V
. If DS is 01,
BACKUP
CC
no diode is selected; if DS is 10, a diode is selected.
The ROUT bits (bits 0, 1) select the value of the resistor
connected between V
and V
. Table 3 shows
BACKUP
CC
Bit 6: Frequency Test (FT). When this bit is 1, the
FT/OUT pin toggles at a 512Hz rate. When FT is written
to 0, the OUT bit controls the state of the FT/OUT pin.
The initial power-up value of FT is 0.
the resistor selected by the resistor select (ROUT) bits
and the diode selected by the diode select (DS) bits.
Warning: The ROUT value of 250Ω must not be select-
ed whenever V
is greater than 3.63V.
CC
Bit 5: Calibration Sign Bit (S). A logic 1 in this bit indi-
cates positive calibration for the RTC. A 0 indicates
negative calibration for the clock. See the Clock
Calibration section for a detailed description of the bit
operation. The initial power-up value of S is 0.
The user determines diode and resistor selection
according to the maximum current desired for battery
or super cap charging (Table 4). The maximum charg-
ing current can be calculated as illustrated in the fol-
lowing example.
Bits 4 to 0: Calibration Bits (CAL4 to CAL0). These
bits can be set to any value between 0 and 31 in binary
form. See the Clock Calibration section for a detailed
description of the bit operation. The initial power-up
value of CAL0–CAL4 is 0.
Assume that a 3.3V system power supply is applied to
V
and a super cap is connected to V
. Also
CC
BACKUP
assume that the trickle charger has been enabled with
a diode and resistor R2 between V and V
.
BACKUP
CC
The maximum current I
ed as follows:
would therefore be calculat-
MAX
Trickle-Charger Register (08h)
The simplified schematic in Figure 6 shows the basic
components of the trickle charger. The trickle-charge
select (TCS) bits (bits 4–7) control the selection of the
trickle charger. To prevent accidental enabling, only a
pattern on 1010 enables the trickle charger. All other
patterns disable the trickle charger. The trickle charger
I
= (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) /
2kΩ ≈ 1.3mA
MAX
As the super cap charges, the voltage drop between
and V decreases and therefore the charge
V
CC
BACKUP
current decreases.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
DS1
BIT 2
BIT 1
BIT 0
TCS3 TCS2 TCS1 TCS0
DS0 ROUT1 ROUT0
TCS = TRICKLE-CHARGER SELECT
0-3
DS = DIODE SELECT
0-1
TOUT = RESISTOR SELECT
0-1
1 OF 16 SELECT
NOTE: ONLY 1010b
ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
R1
250Ω
R2
2kΩ
V
V
BACKUP
CC
R3
4kΩ
Figure 6. Trickle Charger Functional Diagram
_____________________________________________________________________
9
2
I C RTC with Trickle Charger
Table 4. Trickle-Charge Register
TCS3
TCS2
TCS1
TCS0
DS1
0
DS0
0
ROUT1
ROUT0
FUNCTION
X
X
X
1
1
1
1
1
1
0
X
X
X
0
0
0
0
0
0
0
X
X
X
1
1
1
1
1
1
0
X
X
X
0
0
0
0
0
0
0
X
X
0
0
0
1
1
1
1
0
X
X
0
1
1
0
0
1
1
0
Disabled
Disabled
Disabled
1
1
X
X
0
1
No diode, 250Ω resistor
One diode, 250Ω resistor
No diode, 2kΩ resistor
One diode, 2kΩ resistor
No diode, 4kΩ resistor
One diode, 4kΩ resistor
Power-on reset value
1
0
0
1
1
0
0
1
1
0
0
0
ister. Adding counts speeds the clock up and subtract-
ing counts slows the clock down.
Flag Register (09h)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator has stopped or was
stopped for some time period and may be used to
judge the validity of the clock and calendar data. This
bit is edge triggered and is set to logic 1 when the
internal circuitry senses that the oscillator has transi-
tioned from a normal run state to a STOP condition. The
following are examples of conditions that can cause the
OSF bit to be set:
The calibration bits can be set to any value between 0
and 31 in binary form. Bit 5 of the control register, S, is
the sign bit. A value of 1 for the S bit indicates positive
calibration, while a value of 0 represents negative cali-
bration. Calibration occurs within a 64-minute cycle.
The first 62 minutes in the cycle can, once per minute,
have a one-second interval where the calibration is per-
formed. Negative calibration blanks 128 cycles of the
32,768Hz oscillator, slowing the clock down. Positive
calibration inserts 256 cycles of the 32,768Hz oscillator,
speeding the clock up. If a binary 1 is loaded into the
calibration bits, only the first two minutes in the 64-
minute cycle are modified. If a binary 6 is loaded, the
first 12 minutes are affected, and so on. Therefore,
each calibration step either adds 512 or subtracts 256
oscillator cycles for every 125,829,120 actual 32,678Hz
oscillator cycles (64 minutes). This equates to
+4.068ppm or -2.034ppm of adjustment per calibration
step. If the oscillator runs at exactly 32,768Hz, each of
the 31 increments of the calibration bits would repre-
sent +10.7 or -5.35 seconds per month, corresponding
to +5.5 or -2.75 minutes per month.
1) The first time power is applied.
2) The voltages present on V
and V
BACKUP
CC
are insufficient to support oscillation.
3) The EOSC bit is set to 1, disabling the
oscillator.
4) External influences on the crystal (e.g., noise,
leakage).
The OSF bit remains at logic 1 until written to logic 0. It
can only be written to logic 0. Attempting to write OSF
to logic 1 leaves the value unchanged.
Bits 6 to 0: All other bits in the flag register read as 0
and cannot be written.
For example, if using the FT function, a reading of
512.01024Hz would indicate a +20ppm oscillator fre-
quency error, requiring a -10(00 1010) value to be
loaded in the S bit and the five calibration bits.
Clock Calibration
The DS1340 provides a digital clock calibration feature
to allow compensation for crystal and temperature vari-
ations. The calibration circuit adds or subtracts counts
from the oscillator divider chain at the divide-by-256
stage. The number of pulses blanked (subtracted for
negative calibration) or inserted (added for positive cal-
ibration) depends upon the value loaded into the five
calibration bits (CAL4–CAL0) located in the control reg-
Note: Setting the calibration bits does not affect the fre-
quency test output frequency. Also note that writing to
the control register resets the divider chain.
10
____________________________________________________________________
2
I C RTC with Trickle Charger
2
STOP data transfer: A change in the data line’s
state from low to high, while the clock line is high,
defines a STOP condition.
I C Serial Data Bus
2
The DS1340 supports a bidirectional I C bus and data
transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiv-
ing data as a receiver. The device that controls the
message is called a master. The devices that are con-
trolled by the master are slaves. A master device that
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions must control the bus. The DS1340 operates as a
Data valid: The data line’s state represents valid
data when, after a START condition, the data line is
stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condi-
tion and terminated with a STOP condition. The
number of data bytes transferred between the
START and STOP conditions is not limited, and is
determined by the master device. The information
is transferred byte-wise and each receiver
acknowledges with a ninth bit.
2
slave on the I C bus. Connections to the bus are made
through the open-drain I/O lines SDA and SCL. Within
the bus specifications a standard mode (100kHz max
clock rate) and a fast mode (400kHz max clock rate)
are defined. The DS1340 works in both modes.
The following bus protocol has been defined (Figure 7):
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowl-
edge after the reception of each byte. The master
device must generate an extra clock pulse that is
associated with this acknowledge bit.
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high are inter-
preted as control signals.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable low during
the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into
account. A master must signal an end of data to
the slave by not generating an acknowledge bit on
the last byte that has been clocked out of the
slave. In this case, the slave must leave the data
line high to enable the master to generate the
STOP condition.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
START data transfer: A change in the data line’s
state from high to low, while the clock line is high,
defines a START condition.
SDA
MSB
SLAVE ADDRESS
R/W
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERED
CONDITION
2
Figure 7. I C Data Transfer Overview
____________________________________________________________________ 11
2
I C RTC with Trickle Charger
Figures 8 and 9 detail how data transfer is accom-
and decoding the slave address byte, the DS1340
2
plished on the I C bus. Depending upon the state of
outputs an acknowledge on SDA. After the
DS1340 acknowledges the slave address + write
bit, the master transmits a word address to the
DS1340. This sets the register pointer on the
DS1340, with the DS1340 acknowledging the
transfer. The master can then transmit zero or
more bytes of data, with the DS1340 acknowledg-
ing each byte received. The register pointer incre-
ments after each data byte is transferred. The
master generates a STOP condition to terminate
the data write.
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a num-
ber of data bytes. The slave returns an acknowl-
edge bit after each received byte.
Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte (the
slave address). The slave then returns an acknowl-
edge bit. Next follows a number of data bytes trans-
mitted by the slave to the master. The master
returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
Slave Transmitter Mode (Read Mode): The first
byte is received and handled as in the slave
receiver mode. However, in this mode, the direc-
tion bit indicates that the transfer direction is
reversed. The DS1340 transmits serial data on
SDA while the serial clock is input on SCL. Start
and STOP conditions are recognized as the begin-
ning and end of a serial transfer. Hardware per-
forms address recognition after reception of the
slave address and direction bit. The slave address
byte is the first byte received after the master gen-
erates the START condition. The slave address
byte contains the 7-bit DS1340 address, which is
1101000, followed by the direction bit (R/W),
which is 1 for a read. After receiving and decoding
the slave address byte, the DS1340 outputs an
acknowledge on SDA. The DS1340 then begins to
transmit data starting with the register address
pointed to by the register pointer. If the register
pointer is not written to before the initiation of a
read mode, the first address that is read is the last
one stored in the register pointer. The DS1340
must receive a not acknowledge to end a read.
The master device generates all the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated
START condition is also the beginning of the next
serial transfer, the bus is not released.
The DS1340 can operate in the following two modes:
Slave Receiver Mode (Write Mode): Serial data
and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. Start and STOP conditions are recog-
nized as the beginning and end of a serial trans-
fer. Hardware performs address recognition after
reception of the slave address and direction bit.
The slave address byte is the first byte received
after the master generates the START condition.
The slave address byte contains the 7-bit DS1340
address, which is 1101000, followed by the direc-
tion bit (R/W), which is 0 for a write. After receiving
<SLAVE
ADDRESS>
S 1101000
<SLAVE
ADDRESS>
S 1101000
<WORD
<DATA (n)>
<DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)>
XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
1
A
XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
0
A
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY
A NOT ACKNOWLEDGE (A) SIGNAL
S — START
A — ACKNOWLEDGE
P — STOP
S — START
A — ACKNOWLEDGE
P — STOP
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H
A — NOT ACKNOWLEDGE
R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H
Figure 8. Slave Receiver Mode (Write Mode)
Figure 9. Slave Transmitter Mode (Read Mode
12
____________________________________________________________________
2
I C RTC with Trickle Charger
The leaded 16-pin SO package may be reflowed as
Handling, PC Board
Layout, and Assembly
The DS1340C package contains a quartz tuning-fork
crystal. Pick-and-place equipment may be used, but
precautions should be taken to ensure that excessive
shocks are avoided. Exposure to reflow is limited to 2
times maximum. Ultrasonic cleaning should be avoided
to prevent damage to the crystal.
long as the peak temperature does not exceed 240°C.
Peak reflow temperature (≥ 230°C) duration should not
exceed 10 seconds, and the total time above 200°C
should not exceed 40 seconds (30 seconds nominal).
The RoHS and lead-free/RoHS packages may be
reflowed using a reflow profile that complies with
JEDEC J-STD-020.
Moisture-sensitive packages are shipped from the facto-
ry dry-packed.Handling instructions listed on the pack-
age label must be followed to prevent damage during
reflow. Refer to the IPC/JEDEC J-STD-020 standard for
moisture-sensitive device (MSD) classifications.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connect-
ed to ground.
Pin Configurations
TOP VIEW
SCL
1
2
3
4
5
6
7
8
16 SDA
15 GND
FT/OUT
X1
X2
1
2
3
4
8
7
6
5
V
CC
V
CC
14 V
BACKUP
FT/OUT
SCL
N.C.
N.C.
N.C.
N.C.
N.C.
13 N.C.
12 N.C.
11 N.C.
10 N.C.
DS1340
DS1340C
V
BACKUP
GND
SDA
SO, µSOP
9
N.C.
SO (300 mils)
____________________________________________________________________ 13
2
I C RTC with Trickle Charger
Package Information
Chip Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
TRANSISTOR COUNT: 10,930
PROCESS: CMOS
SUBSTRATE CONNECTED TO GROUND
PACKAGE
8-pin SO (150 mils)
8-pin µSOP
DOCUMENT NUMBER
56-G2008-001
56-G2018-001
56-G4009-001
Thermal Information
16-pin SO (300 mils)
Theta-JA: +170°C/W (0.150in SO)
Theta-JC: +40°C/W (0.150in SO)
Theta-JA: +221°C/W (µSOP)
Theta-JC: +39°C/W (µSOP)
Theta-JA: +89.6°C/W (0.300in SO)
Theta-JC: +24.8°C/W (0.300in SO)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
相关型号：
DS1340C-33#T&R
Real Time Clock, Non-Volatile, CMOS, PDSO16, 0.300 INCH, ROHS COMPLIANT, SOP-16
MAXIM
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