DS1258Y-70IND [MAXIM]
128k x 16 Nonvolatile SRAM;型号: | DS1258Y-70IND |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | 128k x 16 Nonvolatile SRAM 静态存储器 内存集成电路 |
文件: | 总8页 (文件大小:207K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS1258Y/AB
128k x 16 Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
Cꢀ10-Year Minimum Data Retention in the
Absence of External Power
CEU
CEL
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
V
WE
A16
A15
A14
A13
A12
A11
A10
A9
CꢀData is Automatically Protected During a
Power Loss
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
CꢀSeparate Upper Byte and Lower Byte Chip-
Select Inputs
CꢀUnlimited Write Cycles
9
32
31
30
CꢀLow-Power CMOS
DQ8
GND
10
11
12
CꢀRead and Write Access Times as Fast as 70ns
CꢀLithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
CꢀFull M10% Operating Range (DS1258Y)
CꢀOptional M5% Operating Range (DS1258AB)
CꢀOptional Industrial Temperature Range of
-40LC to +85LC, Designated IND
GND
29
28
27
26
25
A8
A7
A6
A5
A4
DQ7
DQ6
DQ5
DQ4
DQ3
13
14
15
16
17
18
19
20
24
23
22
21
A3
A2
A1
A0
DQ2
DQ1
DQ0
OE
40-Pin Encapsulated Package
740mil Extended
PIN DESCRIPTION
A0 to A16
DQ0 to DQ15
CEU
CEL
WE
- Address Inputs
- Data In/Data Out
- Chip Enable Upper Byte
- Chip Enable Lower Byte
- Write Enable
OE
- Output Enable
VCC
- Power (+5V)
GND
- Ground
DESCRIPTION
The DS1258 128k x 16 nonvolatile (NV) SRAMs are 2,097,152-bit fully static, NV SRAMs, organized as
131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry that constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1258 devices can be used in place of solutions that build NV
128k x 16 memory by utilizing a variety of discrete components. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
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083006
DS1258Y/AB
READ MODE
The DS1258 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and either/both
of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable) is active (low). The unique
address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is
accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If
CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is
inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU
and CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to
the 16 data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that CEU , CEL and OE access times are also satisfied. If CEU , CEL , and OE access times are not
satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is
either tCO for CEU , CEL , or tOE for OE rather than address access.
WRITE MODE
The DS1258 devices execute a write cycle whenever WE and either/both of CEU or CEL are active (low)
after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines
which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or
part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of
the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the
addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word
is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE . All
address inputs must be kept valid throughout the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled
(CEU and/or CEL , and OE active) then WE will disable the outputs in tODW from its falling edge.
READ/WRITE FUNCTION Table 1
VCC
CYCLE
OE
H
L
L
L
X
X
X
X
WE
H
H
H
H
L
CEL
X
L
L
H
L
CEU
X
L
H
L
CURRENT
DQ0-DQ7
High-Z
Output
Output
High-Z
Input
Input
High-Z
High-Z
DQ8-DQ15 PERFORMED
ICCO
High-Z
Output
High-Z
Output
Input
High-Z
Input
High-Z
Output Disabled
ICCO
Read Cycle
L
ICCO
ICCS
Write Cycle
L
L
X
L
H
H
H
L
H
Output Disabled
DATA RETENTION MODE
The DS1258AB provides full functional capability for VCC greater than 4.75V, and write protects by
4.5V. The DS1258Y provides full functional capability for VCC greater than 4.5V and write protects by
4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The NV static
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write
protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls
below approximately 3.0V, a power switching circuit connects the lithium energy source to RAM to
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DS1258Y/AB
retain data. During power-up, when VCC rises above approximately 3.0V, the power switching circuit
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resume after VCC exceeds 4.75V for the DS1258AB and 4.5V for the DS1258Y.
FRESHNESS SEAL
The DS1258 devices are shipped from Dallas Semiconductor with the lithium energy sources
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the
lithium energy source is enabled for battery backup operation.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Storage Temperature Range
Soldering Temperature
-0.3V to +6.0V
0°C to +70°C, -40LC to +85LC for Industrial Parts
-40°C to +70°C, -40LC to +85LC for Industrial Parts
+260°C for 10 seconds
Caution: Do Not Reflow
(Wave or Hand Solder Only)
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(tA: See Note 10)
PARAMETER
DS1258AB Power Supply Voltage
DS1258Y Power Supply Voltage
Logic 1
SYMBOL MIN
TYP
5.0
5.0
MAX
5.25
5.5
VCC
+0.8
UNITS NOTES
VCC
VCC
VIH
VIL
4.75
4.5
2.2
0.0
V
V
V
V
Logic 0
DC ELECTRICAL
CHARACTERISTICS
PARAMETER
(VCC = 5V Mꢀ5% for DS1258AB)
(tA: See Note 10) (VCC = 5V Mꢀ10% for DS1258Y)
SYMBOL MIN
TYP
MAX
UNITS NOTES
Input Leakage Current
IIL
-2.0
+2.0
ꢀA
I/O Leakage Current CEU = CEL O VIH
? VCC
IIO
-1.0
+1.0
ꢀA
Output Current @ 2.4V
Output Current @ 0.4V
IOH
IOL
ICCS1
ICCS2
ICCO1
VTP
-1.0
2.0
mA
mA
mA
0.7
150
1.5
300
170
4.75
4.5
Standby Current CEU , CEL =2.2V
Standby Current CEU , CEL =VCC - 0.5V
Operating Current
Write Protection Voltage (DS1258AB)
Write Protection Voltage (DS1258Y)
ꢀA
mA
V
4.50
4.25
4.62
4.37
VTP
V
3 of 8
DS1258Y/AB
(tA = +25LC)
UNITS NOTES
pF
CAPACITANCE
PARAMETER
SYMBOL MIN
TYP
20
MAX
25
Input Capacitance
CIN
Input/Output Capacitance
CI/O
5
10
pF
AC ELECTRICAL
(VCC = 5V Mꢀ5% for DS1258AB)
CHARACTERISTICS
(tA: See Note 10) (VCC = 5V Mꢀ10% for DS1258Y)
DS1258AB-70 DS1258AB-100
DS1258Y-70
DS1258Y-100
PARAMETER
Read Cycle Time
Access Time
SYMBOL
tRC
UNITS NOTES
MIN MAX MIN MAX
70
100
ns
ns
ns
ns
tACC
tOE
tCO
tCOE
tOD
tOH
tWC
tWP
tAW
70
35
70
100
50
100
OE to Output Valid
CEU or CEL to Output Valid
OE or CEU or CEL to Output Valid
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
5
5
ns
ns
ns
ns
ns
ns
5
5
25
25
35
5
70
55
0
5
100
75
0
3
tWR1
5
5
ns
12
13
tWR2
15
15
ns
tODW
tOEW
tDS
35
ns
ns
ns
5
5
4
Output High Z from WE
Output Active from WE
Data Setup Time
5
5
30
40
Data Hold Time
tDH1
0
0
ns
12
tDH2
10
10
ns
13
READ CYCLE
SEE NOTE 1
4 of 8
DS1258Y/AB
WRITE CYCLE 1
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
5 of 8
DS1258Y/AB
POWER-DOWN/POWER-UP CONDITION
POWER-DOWN/POWER-UP TIMING
(tA: See Note 10)
PARAMETER
CEU , CEL at VIH before Power-Down
VCC slew from VTP to 0V
SYMBOL MIN
TYP
TYP
MAX
UNITS NOTES
tPD
tF
0
11
ꢀs
ꢀs
ꢀs
ms
300
300
2
VCC slew from 0V to VTP
tR
tREC
125
CEU , CEL at VIH after Power-Up
(tA =+25LC)
PARAMETER
Expected Data Retention Time
SYMBOL MIN
tDR 10
MAX
UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1) WE is high for a Read Cycle.
2) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3) tWP is specified as the logical AND of CEU or CEL and WE . tWP is measured from the latter of CEU ,
CEL or WE going low to the earlier of CEU , CEL or WE going high.
4) tDS is measured from the earlier of CEU or CEL or WE going high.
5) These parameters are sampled with a 5pF load and are not 100% tested.
6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in
the output buffers remain in a high impedance state during this period.
7) If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the
output buffers remain in high impedance state during this period.
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DS1258Y/AB
8) If WE is low or the WE low transition occurs prior to or simultaneously with the CEU or CEL low
transition, the output buffers remain in a high impedance state during this period.
9) Each DS1258 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10) All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0LC to +70LC. For industrial products, this range is -40LC to
+85LC.
11) In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12) tWR1, tDH1 are measured from WE going high.
13) tWR2, tDH2 are measured from CEU OR CEL going high.
14) DS1258 DIP modules are recognized by Underwriters Laboratory (U.L.®) under file E99151.
DC TEST CONDITIONS
Outputs Open
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels:
Cycle = 200ns
All voltages are referenced to ground
0.0V to 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
Supply
Tolerance
5V M 5%
5V M 5%
5V M 5%
5V M 5%
5V M 5%
5V M 5%
5V M 10%
5V M 10%
5V M 10%
5V M 10%
5V M 10%
5V M 10%
Part Number
DS1258AB-70
Temperature Range
Pin/Package
Speed Grade
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
40 / 740 EMOD
70ns
70ns
70ns
70ns
100ns
100ns
70ns
70ns
70ns
70ns
100ns
100ns
DS1258AB-70#
DS1258AB-70IND
DS1258AB-70IND#
DS1258AB-100
DS1258AB-100#
DS1258Y-70
DS1258Y-70#
DS1258Y-70IND
DS1258Y-70IND#
DS1258Y-100
DS1258Y-100#
# Denotes RoHS-compliant product.
* DS9034PC or DS9034PCI (PowerCap) required. Must be ordered separately.
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DS1258Y/AB
DS1258Y/AB NONVOLATILE SRAM 40-PIN, 740-MIL EXTENDED MODULE
PKG
DIM
40-PIN
MIN
MAX
A IN.
MM
2.080
52.83
2.100
53.34
B IN.
MM
0.715
18.16
0.740
18.80
C IN.
MM
0.345
8.76
0.365
9.27
D IN.
MM
0.085
2.16
0.115
2.92
E IN.
MM
0.015
0.38
0.030
0.76
F IN.
MM
0.120
3.05
0.160
4.06
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.590
14.99
0.630
16.00
J IN.
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.43
0.025
0.58
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