DS1216F-3 [MAXIM]
Real Time Clock, Non-Volatile, 0 Timer(s), CMOS, PDIP32, 0.600 INCH, SOCKET TYPE, DIP-32;
| 型号： | DS1216F-3 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Real Time Clock, Non-Volatile, 0 Timer(s), CMOS, PDIP32, 0.600 INCH, SOCKET TYPE, DIP-32 光电二极管 外围集成电路 |
| 文件： | 总15页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6075; Rev 11/11
DS1216
SmartWatch RAM (DS1216B/C/D/H);
SmartWatch ROM (DS1216E/F)
GENERAL DESCRIPTION
FEATURES
The DS1216 SmartWatch RAM and SmartWatch
ROM sockets are 600-mil-wide DIP sockets with a
built-in CMOS watch function, an NV RAM
controller circuit, and an embedded lithium energy
source. The sockets provide an NV RAM solution
for memory sized from 2K x 8 to 512K x 8 with
package sizes from 26 pins to 32 pins. When a
socket is mated with a CMOS SRAM, it provides a
complete solution to problems associated with
memory volatility and uses a common energy
source to maintain time and date. The SmartWatch
ROM sockets use the embedded lithium source to
maintain the time and date only. A key feature of
the SmartWatch is that the watch function remains
transparent to the RAM. The SmartWatch monitors
VCC for an out-of-tolerance condition. When such a
condition occurs, an internal lithium energy source
is automatically switched on and write protection
is unconditionally enabled to prevent loss of watch
and RAM data.
.
Keeps Track of Hundredths of Seconds,
Seconds, Minutes, Hours, Days, Date of the
Month, Months, and Years
.
.
.
.
.
Converts Standard 2K x 8 Up to 512K x 8
CMOS Static RAMs into Nonvolatile Memory
Embedded Lithium Energy Cell Maintains
Watch Information and Retains RAM Data
Watch Function is Transparent to RAM
Operation
Automatic Leap Year Compensation Valid Up
to 2100
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power
is Applied for the First Time
.
.
.
Proven Gas-Tight Socket Contacts
Full ±10% Operating Range
Accuracy Better Than ±1 Minute/Month
at +25°C
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS1216B
DS1216C
DS1216D
DS1216E
DS1216F
DS1216H
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
28 SmartWatch Socket
28 SmartWatch Socket
32 SmartWatch Socket
28 SmartWatch Socket
32 SmartWatch Socket
32 SmartWatch Socket
(See Figure 2 for letter suffix marking identification.)
Selector Guide appears on page 2.
1 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
PIN DESCRIPTION
RST
- Reset, Active Low
OE
- Output Enable, Active Low
- Write Enable, Active Low
DQ0 - Data Input/Output 0 (RAM)
WE
VCC
A2
A0
- Address Bit 2 (Read/Write [ROM])
- Address Bit 0 (Data Input [ROM])
- Switched VCC for 28-/32-Pin RAM
VCCB - Switched VCC for 24-Pin RAM
VCCD - Switched VCC for 28-Pin RAM
GND - Ground
CE
- Conditioned Chip Enable, Active Low
PIN CONFIGURATIONS
TOP VIEW
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RST
VCC
RST 1
28 VCC
2
3
4
27 WE
VCCD
WE
26 VCC
B
25
5
6
24
23
7
22 OE
[A2] 8
21
OE
CE
[A2] 10
11
[A0] 12
9
20 CE
[A0] 10
19
DQ0 11
18
13
14
15
DQ0
12
13
17
16
GND 14
15
GND 16
DS1216B/C/E
28-Pin Intelligent Socket
DS1216D/F/H
32-Pin Intelligent Socket
SELECTOR GUIDE
PC BOARD MODIFICATION
PART
RAM/ROM
RAM DENSITY
REQUIRED FOR DENSITY
UPGRADE?
No/Yes
No
DS1216B
DS1216C
DS1216D
DS1216E
DS1216F
DS1216H
RAM
RAM
RAM
ROM
ROM
RAM
16K/64K
64K/256K
256K/1M
No/Yes
No
64K/256K
64K/256K/1M
1M/4M
No
No
2 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
DETAILED DESCRIPTION
The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600-mil-wide DIP sockets with a
built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source.
The sockets provide an NV RAM solution for memory sized from 2K x 8 to 512K x 8 with package sizes
from 26 pins to 32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to
problems associated with memory volatility and uses a common energy source to maintain time and date.
The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A
key feature of the SmartWatch is that the watch function remains transparent to the RAM. The
SmartWatch monitors VCC for an out-of-tolerance condition. When such a condition occurs, an internal
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent loss of watch and RAM data.
Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM
take up no more area than the memory alone. The SmartWatch uses the VCC, data I/O 0, CE, OE, and WE
for RAM and watch control. All other pins are passed straight through to the socket receptacle.
The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,
hours, days, date, months, and years. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either
24-hour or 12-hour format with an AM/PM indicator.
OPERATION
Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of
64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and
either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is
disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC
registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC
registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low
during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match
sequence.
PATTERN MATCH—RAM
Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control
of chip enable (CE), output enable (OE), and write enable (WE). Initially, a read cycle to any memory
location using the CE and OE control of the SmartWatch starts the pattern recognition sequence by
moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are
executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain
access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However,
the write cycles generated to gain access to the SmartWatch are also writing data to a location in the
mated RAM. The preferred way to manage this requirement is to set aside just one address location in
RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the
64-bit comparison register. If a match is found, the pointer increments to the next location of the
3 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for 64 write cycles as described above until all the bits in the comparison register have been matched (this
bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data
transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch
to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to
other locations outside the memory block can be interleaved with CE cycles without interrupting the
pattern recognition sequence or data transfer sequence to the SmartWatch.
PATTERN MATCH—ROM
Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits
that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the
proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior
to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read
cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition
starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of
the 64-bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above, until all the bits in the comparison register have been
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is
enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause
the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on
the level of /WRITE READ (A2).
After power-up, the controller could be in the 64-bit clock register read/write sequence (from an
incomplete access prior to power-down). Therefore, it is recommended that a 64-bit read be performed
upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to
the RAM would otherwise be expected.
4 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
Figure 1. SmartWatch Comparison Register Definition
HEX
VALUE
7
0
C5
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
BYTE 0
BYTE 1
3A
A3
BYTE 2
5C
C5
BYTE 3
BYTE 4
3A
A3
5C
BYTE 5
BYTE 6
BYTE 7
0
1
0
1
1
1
0
0
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN
ACCIDENTALLY DUPLICATING AND CAUSING INADVERTENT ENTRY TO THE SMARTWATCH ARE LESS
THAN 1 IN 1019. THIS PATTERN IS SENT TO THE SMARTWATCH LSB TO MSB.
NONVOLATILE CONTROLLER OPERATION
The DS1216 SmartWatch performs circuit functions required to make a CMOS RAM nonvolatile. First, a
switch is provided to direct power from the battery or VCC supply, depending on which voltage is greater.
This switch has a voltage drop of less than 0.2V. The second function that the SmartWatch provides is
power-fail detection, which occurs at VTP. The DS1216 constantly monitors the VCC supply. When VCC
goes out of tolerance, a comparator outputs a power-fail signal to the chip-enable logic. The third function
accomplishes write protection by holding the chip-enable signal to the memory within 0.2V of VCC or
battery. During nominal power-supply conditions, the memory chip-enable signal will track the chip-
enable signal sent to the socket with a maximum propagation delay of 6ns.
FRESHNESS SEAL
Each DS1216 is shipped from Maxim with its lithium energy source disconnected, ensuring full energy
capacity. When VCC is first applied at a level greater than the lithium energy source is enabled for battery-
backup operation.
5 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
SMARTWATCH REGISTER INFORMATION
The SmartWatch information is contained in eight registers of 8 bits, each of which is sequentially
accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When
updating the SmartWatch registers, each must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 3.
Data contained in the SmartWatch registers is in binary-coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
AM-PM/12-/24-MODE
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the 20-hour bit (20 to 23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the RST and oscillator functions. Bit 4 controls the
RST (pin 1). When the RST bit is set to logic 1, the RST input pin is ignored. When the RST bit is set to
logic 0, a low input on the RST pin will cause the SmartWatch to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set
to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the
factory set to logic 1.
ZERO BITS
Registers 1 to 6 contain one or more bits that always read logic 0. When writing these locations, a logic 1
or 0 is acceptable.
ADDITIONAL INFORMATION
Refer to Application Note 52: Using the Dallas Phantom Real-Time Clocks (available on our website at
www.maxim-ic.com/RTCapps) for information about using regarding optional modifications and the
phantom clock contained within the SmartWatch.
6 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
Figure 2. Reset and Memory Density Options
NOTE: THE LETTER SUFFIX OF THE SMARTWATCH IS LOCATED ON THE PC BOARD.
The RST pin on the controller has an internal pullup resistor. To disable the RST function, the trace
between pin 1 on the socket and pin 13 on the controller can be cut. In this case, the socket will ignore the
RST input, preventing address transitions from resetting the pattern match, even if the RST bit is enabled.
On the DS1216B and DS1216D, the two VCC pins are connected together on the PC board. The switched
VCC from the controller is connected to the two VCC pins that connect to the inserted RAM. No
modifications are required if the lower density RAM is used. To use the higher density RAM, the trace by
the lower density RAM VCC pin, identified by a hash mark labeled “U,” must be cut. The two square-
metal pads, labeled “G,” must be shorted together. This disconnects switched VCC from the pin going to
the inserted RAM, and connects it to the corresponding address input pin for the higher density RAM.
7 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
Figure 3. SmartWatch Register Definition
REGISTER
7
RANGE (BCD)
0
0.1 SEC
0.01 SEC
00-99
00-59
00-59
0
7
0
0
0
0
10 SEC
10 MIN
SECONDS
MINUTES
1
2
7
7
7
0
0
12/24
0
10
A/P
HR
HOUR
01-12
3
01-07
00-23
0
0
0
0
OSC
RST
0
DAY
4
7
7
7
0
0
0
0
0
10
0
DATE
DATE
MONTH
YEAR
01-31
01-12
00-99
5
6
7
10 MONTH
10 YEAR
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DS1216 SmartWatch RAM/SmartWatch ROM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on any Pin Relative to Ground………………………………….…………-0.3V to +6.0V
Operating Temperature Range…………………………………………………………..…...0°C to +70°C
Storage Temperature Range…………………………………………………………..…...-40°C to +85°C
Lead Temperature (soldering, 10s) ………................................................................................…...+260°C
Note: Wave or hand-solder only.
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = 0°C to +70°C)
PARAMETER
VCC Pin, 5V Supply
SYMBOL
VCC
MIN
4.5
TYP
MAX
5.5
UNITS
NOTES
5.0
V
V
1
8
Logic 1
Logic 0
VIH
2.2
VCC + 0.3
VIL
-0.3
+0.8
V
8
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 0°C to +70°C.)
PARAMETER
VCC Supply
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
ICCI
5
mA
1, 2, 3
VCC Supply Voltage
(ICCO = 80mA)
VCCO1(U)
IIL
VCC - 0.2
-1.0
V
µA
V
1, 6
Input Leakage
+1.0
2, 8, 13
Output Logic 1 Voltage
(IOUT = -1.0mA)
VOH
2.4
Output Logic 1 Voltage
(IOUT = -1.0mA)
VOL
VTP
0.4
4.5
V
V
Write-Protection Voltage
4.25
BACKUP POWER CHARACTERISTICS
(VCC < VTP; TA = 0°C to +70°C.)
PARAMETER
CE Output
SYMBOL
MIN
TYP
MAX
UNITS NOTES
VOH(L)
VBAT - 0.2
VBAT - 0.2
2
V
V
1
VCC Supply Voltage
(ICCO = 10µA)
VCCO2(U)
1, 6, 14
1, 15
RAM VCC (Battery) Voltage
VBAT
tREC
3
3.6
2
V
Recovery at Power-Up
ms
VCC Slew Rate Power-Down
tF
300
10
µs
V
PF(MAX) to VPF(MIN)
VCC Slew Rate Power-Down
PF(MIN) to VBAT(MIN)
CE Pulse Width
tFB
tCE
µs
µs
V
1.5
5
9 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
CIN
MIN
TYP
MAX
UNITS
pF
NOTES
Input Capacitance
5
7
Output Capacitance
Expected Data Retention
COUT
pF
tDR
10
years
14
AC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V, TA = 0°C to +70°C.)
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
TYP
MAX
UNITS
ns
NOTES
75
CE Access Time
tCO
65
65
ns
OE Access Time
tOE
ns
CE to Output Low-Z
OE to Output Low-Z
CE to Output High-Z
OE to Output High-Z
Address Setup Time (ROM)
Address Hold Time (ROM)
Read Recovery
tCOE
tOEE
tOD
6
6
ns
ns
30
30
ns
tODO
tAS
ns
20
11
12
tAH
10
tRR
15
75
75
15
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Write Pulse Width
Write Recovery
tWC
tWP
tWR
tDS
9
Data Setup Time
10
10
Data Hold Time
tDH
CE Pulse Width
tCW
tRST
tPD
65
75
RST Pulse Width
CE Propagation Delay
CE High to Power-Fail
6
0
7
tPF
10 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
Timing Diagram: Read Cycle to SmartWatch
Timing Diagram: Write Cycle to SmartWatch
11 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
Timing Diagram: Reset for SmartWatch
Timing Diagram: Power-Down
tCE
CE (L)*
VIL
tPD
VBAT -0.2V
tCE
VIH
CE (U)
VIL
tF
VPF(max)
VPF(min)
VBAT(min)
V
CC (L)
tFB
*Note 1
Timing Diagram: Power-Up
12 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
WARNING:
Under no circumstances should negative undershoots of any amplitude be allowed when the device is in
battery-backup mode. Water washing for flux removal will discharge internal lithium source because
exposed voltage pins are present.
NOTES:
1) Pin locations are designated “U” when a parameter definition refers to the socket receptacle and “L”
when a parameter definition refers to the socket pin.
2) No memory inserted in the socket.
3) Pin 26L can be connected to VCC or left disconnected at the PC board.
4) SmartWatch sockets can be successfully processed through some conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. However, post-solder cleaning with water-washing techniques is not permissible.
Discharge to the lithium energy source can result, even if deionized water is used. It is equally
imperative that ultrasonic vibration is not used in order to avert damage to the quartz crystal resonator
employed by the oscillator circuit.
5) tCE max must be met to ensure data integrity on power loss.
6) VCCO1 is the maximum voltage drop from VCC(L) to VCC(U) while Vcc(L) is supplying power. VCCO
is the maximum voltage drop from VBAT to VCC(U) while the part is in battery backup.
2
7) Input pulse rise and fall times equal 10ns.
8) Applies to pins RST L, A2 L, A0 L, CE L, OE L, and WE L.
9) tWR is a functions of the latter occurring edge of WE or CE.
10) tDH and tDS are a function of the first occurring edge of WE or CE.
11) tAS is a function of the first occurring edge of OE or CE.
12) tAH is a function of the latter occurring edge of OE or CE.
13) RST (Pin 1) has an internal pullup resistor.
14) Expected data retention is based on using an external SRAM with a data retention current of less than
0.5µA at +25°C. Expected data-retention time (time while on battery) for a given RAM battery
current can be calculated using the following formula:
0.045 / (current in amps) = data-retention time in hours
15) The DS1216 products are shipped with the battery-backup power off. First power-up switches backup
battery on to clock and RAM VCC pin upon power-down.
13 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PKG
28-PIN
32-PIN
DIM MIN MAX MIN MAX
A IN. 1.390 1.420 1.580 1.620
MM
B IN. 0.690 0.720 0.690 0.720
MM 17.53 18.29 17.53 18.29
C IN. 0.420 0.470 0.400 0.470
MM 10.67 11.94 10.16 11.94
D IN. 0.035 0.065 0.035 0.065
MM 0.89 1.65 0.89 1.65
E IN. 0.055 0.075 0.055 0.075
MM 1.39 1.90 1.39 1.90
F IN. 0.120 0.160 0.120 0.160
MM 3.04 4.06 3.04 4.06
G IN. 0.090 0.110 0.090 0.110
MM 2.29 2.79 2.29 2.79
H IN. 0.590 0.630 0.590 0.630
MM 14.99 16.00 14.99 16.00
J IN. 0.008 0.012 0.008 0.012
MM 0.20 0.30 0.20 0.30
K IN. 0.015 0.021 0.015 0.021
MM 0.38 0.53 0.38 0.53
L IN. 0.380 0.420 0.380 0.420
MM 9.65 10.67 9.65 10.67
35.31 36.07 40.13 41.14
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DS1216 SmartWatch RAM/SmartWatch ROM
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Updated the Features, Nonvolatile Controller Operation,
AM-PM/12-/24-MODE, and Absolute Maximum Ratings sections
11/11
1, 5, 6, 9
15 of 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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