DS1010S-50+ [MAXIM]
Silicon Delay Line, 1-Func, 10-Tap, True Output, CMOS, PDSO16, 0.300 INCH, LEAD FREE, SOIC-16;型号: | DS1010S-50+ |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Silicon Delay Line, 1-Func, 10-Tap, True Output, CMOS, PDSO16, 0.300 INCH, LEAD FREE, SOIC-16 光电二极管 逻辑集成电路 延迟线 |
文件: | 总6页 (文件大小:66K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DS1010
10-Tap Silicon Delay Line
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ All-silicon time delay
IN1
NC
1
2
14
13
12
11
10
9
VCC
ꢀ 10 taps equally spaced
ꢀ Delays are stable and precise
ꢀ Leading and trailing edge accuracy
ꢀ Delay tolerance ±5% or ±2 ns, whichever is
greater
TAP 1
IN1
1
2
3
4
5
6
7
8
VCC
NC
16
15
14
TAP 2
TAP 4
TAP 6
3
4
5
6
7
TAP 3
TAP 5
TAP 7
TAP 9
TAP 10
NC
NC
TAP 1
TAP 2
TAP 4
13
12
11
10
TAP 3
TAP 5
ꢀ Economical
TAP 7
TAP 9
TAP 10
TAP 6
TAP 8
TAP 8
GND
ꢀ Auto-insertable, low profile
ꢀ Standard 14-pin DIP or 16-pin SOIC
ꢀ Low-power CMOS
ꢀ TTL/CMOS-compatible
ꢀ Vapor phase, IR and wave solderable
ꢀ Custom delays available
ꢀ Fast turn prototypes
8
GND
9
DS1010S 16-Pin SOIC
(300-mil)
DS1010 14-Pin DIP (300-mil)
See Mech. Drawings Section
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1 - TAP 10 - TAP Output Number
VCC
GND
NC
- 5 Volts
- Ground
- No Connection
- Input
IN
DESCRIPTION
The DS1010 series delay line has ten equally spaced taps providing delays from 5 ns to 500 ns. The
devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines.
Alternatively, a 16-pin SOIC is available for surface mount technology which reduces PC board area.
Since the DS1010 is an all-silicon solution, better economy is achieved when compared to older methods
using hybrid techniques. The DS1010 series delay lines provide a nominal accuracy of ±5% or ±2 ns,
whichever is greater. The DS1010 reproduces the input logic state at the TAP 10 output after a fixed
delay as specified by the dash number extension of the part number. The DS1010 is designed to produce
both leading and trailing edge with equal precision. Each tap is capable of driving up to 10 74LS type
loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests
and rapid delivery, call (972) 371-4348.
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111799
DS1010
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1
CATALOG P/N
DS1010-50
TOTAL DELAY
DELAY/TAP (ns)
50
5
6
DS1010-60
60
DS1010-75
DS1010-80
75
80
7.5
8
DS1010-100
DS1010-125
DS1010-150
DS1010-175
DS1010-200
DS1010-250
DS1010-300
DS1010-350
DS1010-400
DS1010-450
DS1010-500
Custom delays available.
100
125
150
175
200
250
300
350
400
450
500
10
12.5
15
17.5
20
25
30
35
40
45
50
2 of 6
DS1010
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-1.0V to +7.0V
0°C to 70°C
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER
SYM
TEST
MIN TYP
MAX
UNITS NOTES
CONDITION
Supply Voltage
High Level Input
Voltage
VCC
VIH
4.75
2.2
5.00
5.25
VCC + 0.5
V
V
1
1
Low Level Input
Voltage
Input Leakage
Current
VIL
II
-0.5
-1.0
0.8
1.0
V
1
µA
mA
mA
mA
0.0V ≤ VI ≤ VCC
Active Current
ICC
IOH
IOL
VCC=Max;
Period=Min.
VCC=Min.
VOH=4
VCC=Min.
VOL=0.5
40
150
-1.0
2
High Level Output
Current
Low Level Output
Current
12
AC ELECTRICAL CHARACTERISTICS
(TA = 25°C; VCC = 5V ± 5%)
PARAMETER
Input Pulse Width
Input to Tap Delay
(leading edge)
SYMBOL
tWI
MIN
TYP
MAX UNITS
NOTES
8
3, 4, 5, 6,
7, 9
40% of TAP 10 tPLH
ns
ns
tPLH
Table 1
Table 1
Input to Tap Delay
(trailing edge)
tPHL
ns
3, 4, 5, 6,
7, 9
Power-up Time
tPU
Period
100
ms
ns
4 (tWI)
8
CAPACITANCE
PARAMETER
Input Capacitance
(TA = 25°C)
MAX UNITS
10 pF
SYMBOL
MIN
TYP
5
NOTES
CIN
3 of 6
DS1010
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Input-to-tap delays accurate on both rising and falling edges within ±2 ns or ±5%
whichever is greater.
4. See “Test Conditions” section.
5. For DS1010 delay lines with a TAP 10 delay of 100 ns or greater, temperature variations from 25°C
to 0°C or 70°C may produce an additional input-to-tap delay shift of ±2ns or ±3%, whichever is
greater.
6. For DS1010 delay lines with a TAP 10 delay less than 100 ns, temperature variations from 25°C to
0°C or 70°C may produce an additional input-to-tap delay shift of ±1 ns or ±9%, whichever is greater.
7. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP
1 slows down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
8. Pulse width and period specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
9. Certain high-frequency applications not recommended for -50 in 16-pin package. Consult factory.
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
4 of 6
DS1010
TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
5 of 6
DS1010
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1010.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (VCC):
Input Pulse:
25°C ± 3°C
5.0V ± 0.1V
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
50 ohm max.
3.0 ns max.
500 ns (1 µs for -500)
1 µs ( 2 µs for -500)
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
OUTPUT:
Each output is loaded with the equivalent of one 74FO4 input gate. Delay is measured at the 1.5V level
on the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
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