DG421CJ [MAXIM]
Improved Low-Power, CMOS Analog Switches with Latches; 改进的低功耗， CMOS模拟开关与门锁
| 型号： | DG421CJ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Improved Low-Power, CMOS Analog Switches with Latches |
| 文件： | 总12页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0137; Rev 1; 3/94
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
13/DG425
_______________Ge n e ra l De s c rip t io n
______________________Ne w Fe a t u re s
♦ Plug-In Upgrades for Industry-Standard
DG421/DG423/DG425
Maxim’s redesigned DG421/DG423/DG425 monolithic
analog switches now feature guaranteed on-resistance
matching (3Ω max) between switches and on-resistance
flatness over the signal range (4Ω max). These low on-
resistance switches (20Ω typ) conduct equally well in both
directions. They guarantee a low charge injection of 15pC
maximum and an ESD tolerance of 2000V minimum per
Method 3015.7. Off leakage current over temperature has
also been reduced (less than 5nA at +85°C).
♦ Improved r
Match Between Channels (3Ω max)
(DS)ON
♦ Guaranteed r
Over Signal Range (4Ω max)
FLAT(ON)
♦ Improved Charge Injection (15pC max)
♦ Improved Off Leakage Current Over Temperature
(<5nA at +85°C)
♦ Withstands Electrostatic Discharge (2000V min)
per Method 3015.7
The DG421/DG423/DG425 are precision, dual CMOS
switches with latchable logic inputs that simplify inter-
facing with microprocessors (µPs). The single-pole/single-
throw DG421 and double-pole/single-throw DG425 are
norma lly op e n d ua l s witc he s . The d ua l, s ing le -
pole/double-throw DG423 has two normally open and
two normally closed switches. Fast switching times
__________________Ex is t in g Fe a t u re s
♦ Low r
(35Ω max)
DS(ON)
♦ Single-Supply Operation +10V to +30V
Bipolar-Supply Operation ±4.5V to ±20V
♦ Low Power Consumption (35µW max)
♦ Rail-to-Rail Signal Handling Capability
♦ TTL/CMOS-Logic Compatible
(175ns for t
a nd 145ns for t
) a nd low p owe r
ON
OFF
consumption (35µW max) make these parts ideal for
battery-powered applications requiring µP-compatible
switches. Operation is from a single +10V to +30V supply,
______________Ord e rin g In fo rm a t io n
±
or bipolar 4.5V to ±20V supplies. Fabricated with the
same 44V silicon-gate process, these switches have
rail-to-rail signal handling capabilities.
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 SO
DG421CJ
DG421CY
DG421C/D
DG421DJ
DG421DY
DG421DK
DG421AK
0°C to +70°C
_______________________Ap p lic a t io n s
0°C to +70°C
Dice*
Sample-and-Hold Circuits
Fax Machines
Battery-Operated Systems
Guidance and Control Systems
Audio Signal Routing
Modems
Test Equipment
PBX, PABX
Military Radios
Communication Systems
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 SO
16 CERDIP
16 CERDIP**
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
**Contact factory for availability and processing to MIL-STD-883B.
__Func tiona l Dia gra m s /Truth Ta ble s
_________________P in Co n fig u ra t io n s
TOP VIEW
D1
WR
S1
1
2
3
4
5
6
7
8
S1
16
15
14
13
12
11
10
9
D1
IN1
V-
WR
DG421 TRUTH TABLE
N.C.
N.C.
CK
R
IN1
D
Q
GND
WR RS IN SWITCH
DG421
0
1
Off
On
N.C.
N.C.
RS
V
L
DG421
CK
R
IN2
0
1
D
Q
V+
IN2
S2
RS
S2
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
D2
D2
SWITCHES SHOWN FOR
LOGIC "1" INPUT
TWO SPST SWITCHES
PER PACKAGE
DIP
N.C. = No Internal Connection
Pin Configurations continued at end of data sheet.
Functional Diagrams/Truth Tables continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to V-
Continuous Power Dissipation (TA = +70°C)
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) . . .842mW
20-Pin PLCC (derate 10.00mW/°C above +70°C) . . . . . 800mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) . . . 800mW
Operating Temperature Ranges
DG42_C_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
DG42_D_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
DG42_A_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature Ranges
V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+ + 0.3V)
Digital Inputs, VS, VD (Note 1). . . . . . . . . . . . . . (V- - 2V) to (V+ + 2V)
Current (any terminal, except S or D) .................................30mA
Continuous Current, S or D.................................................20mA
Peak Current, S or D (pulsed at 1ms, 10% duty cycle max)...100mA
DG42_C_/DG42_D_ . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
DG42_A_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (soldering, 10sec). . . . . . . . . . . . . . . . . . . . +300°C
Note 1: Signals on S, D, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward current to maximum current ratings.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 15V, V- = -15V, V = +5V, GND = 0V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted.)
L
13/DG425
DG42_C, DG42_D
MIN TYP MAX
(Note 2)
DG42_A
MIN TYP MAX UNITS
(Note 2)
PARAMETER
SWITCH
SYMBOL
CONDITIONS
Analog Signal Range
V
(Note 3)
-15
15
45
-15
15
35
V
ANALOG
V+ = 13.5V,
V- = -13.5V,
I = -10mA,
S
T
= +25°C
20
20
A
Drain-Source
On-Resistance
r
Ω
DS(ON)
T
A
= T
MIN to TMAX
45
3
45
3
V
D
= ±10V
V+ = 16.5V,
V- = -16.5V,
T
A
= +25°C
On-Resistance Match
Between Channels
(Note 4)
∆r
Ω
DS(ON)
I
S
= -10mA,
T
A
= T
MIN to TMAX
4
4
V
D
= ±10V
V+ = 15V,
V- = -15V,
I = -10mA,
S
T
= +25°C
4
4
A
On-Resistance
Flatness (Note 4)
r
Ω
FLAT(ON)
T
A
= T
MIN to TMAX
5
5
V
D
= ±5V
V+ = 16.5V,
V- = -16.5V,
T
= +25°C
-0.50 -0.01 0.50
-5
-0.50 -0.01 0.50
-5
-1.0 -0.04 1.0
-10 10
-0.25 -0.01 0.25
-10 10
-0.25 -0.01 0.25
-10 10
-0.40 -0.04 0.40
-20 20
A
Source-Off
Leakage Current
(Note 5)
I
nA
nA
nA
S(OFF)
V
D
= ±15.5V,
T
A
= T
MIN to TMAX
5
V
S
= m15.5V
V+ = 16.5V,
V- = -16.5V,
T
A
= +25°C
Drain-Off
Leakage Current
(Note 5)
I
D(OFF)
V
D
= ±15.5V,
T
A
= T
MIN to TMAX
5
V
S
= m15.5V
V+ = 16.5V,
V- = -16.5V,
T
A
= +25°C
Drain-On
Leakage Current
(Note 5)
I
D(ON)
V
V
S
= ±15.5V,
= ±15.5V
D
T
A
= T
MIN to TMAX
2
_______________________________________________________________________________________
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
13/DG425
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, V- = -15V, V = +5V, GND = 0V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted.)
L
MIN TYP MAX
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
UNITS
INPUT
Input Current with Input Voltage High
Input Current with Input Voltage Low
SUPPLY
I
IN = 2.4V, all others = 0.8V
-0.50 0.005 0.50
-0.50 0.005 0.50
µA
µA
INH
I
IN = 0.8V, all others = 2.4V
INL
Power Supply Range
V+, V-
I+
(Note 3)
±4.5
-1.0
±20
1.0
V
All channels on or off,
V+ = 16.5V, V- = -16.5V,
T
= +25°C
0.01
A
Positive Supply Current
Negative Supply Current
Logic Supply Current
Ground Current
µA
T
A
= T
MIN to TMAX
-5.0
5.0
V
IN
= 0V or 5V
All channels on or off,
V+ = 16.5V, V- = -16.5V,
T
A
= +25°C
-1.0 -0.01 1.0
-5.0 5.0
-1.0 -0.01 1.0
-5.0 5.0
-1.0 -0.01 1.0
I-
µA
µA
µA
T
A
= T
MIN to TMAX
V
IN
= 0V or 5V
All channels on or off,
V+ = 16.5V, V- = -16.5V,
T
A
= +25°C
I
L
T
A
= T
MIN to TMAX
V
IN
= 0V or 5V
All channels on or off,
V+ = 16.5V, V- = -16.5V,
T
A
= +25°C
I
GND
T
A
= T
MIN to TMAX
-5.0
5.0
V
IN
= 0V or 5V
DYNAMIC
T
= +25°C
150
250
300
200
A
Turn-On Time
Turn-Off Time
t
Figure 2
Figure 2
ns
ns
ON
T
A
= T
MIN to TMAX
t
OFF
T
= +25°C
200
200
100
100
60
A
t
WW
T
A
= -55°C to +125°C
= +25°C
V
= ±10V,
= 300Ω,
= 35pF,
S
T
A
R
L
C
L
Latch Timing
t
ns
DW
T
A
= -55°C to +125°C
= +25°C
Figure 3
T
A
t
WD
T
= -55°C to +125°C
= +25°C
A
100
5
A
Break-Before-Make Interval (Note 3)
Charge Injection (Note 3)
t
DG423, Figure 4
T
25
10
ns
D
C
R
= 10nF, V = 0V,
G
= 0Ω, Figure 5
L
Q
T
= +25°C
= +25°C
= +25°C
15
pC
A
G
Off-Isolation Rejection Ratio
(Note 6)
R
= 100Ω, C = 5pF,
L
L
OIRR
T
A
72
90
dB
dB
f = 1MHz, Figure 6
R
= 50Ω, C = 5pF,
L
L
Crosstalk (Note 7)
T
A
f = 1MHz, Figure 7
f = 1MHz, Figure 8
f = 1MHz, Figure 8
f = 1MHz, Figure 9
f = 1MHz, Figure 9
Drain-Off Capacitance
Source-Off Capacitance
Drain-On Capacitance
Source-On Capacitance
C
T
A
= +25°C
= +25°C
= +25°C
= +25°C
12
12
39
39
pF
pF
pF
pF
D(OFF)
S(OFF)
C
T
A
C
C
T
A
D(ON)
S(ON)
T
A
Note 2: Typical values are for design aid only, are not guaranteed, and are not subject to production testing. The algebraic convention,
where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet.
Note 3: Guaranteed by design.
Note 4: On-resistance match between channels and flatness are guaranteed only with bipolar-supply operation. Flatness is defined as the dif-
ference between the maximum and minimum value of on-resistance as measured at the extremes of the specified analog signal range.
Note 5: Leakage parameters I
, I
, and I are 100% tested at the maximum rated hot temperature and guaranteed by
D(ON)
S(OFF) D(OFF)
correlation at +25°C.
Note 6: Off-Isolation Rejection Ratio = 20log (VD/VS), VD = output, VS = input to off switch.
Note 7: Between any two switches.
_______________________________________________________________________________________
3
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
D
ON-RESISTANCE vs. V AND
D
D
(SINGLE SUPPLY)
(DUAL-SUPPLIES)
TEMPERATURE (DUAL SUPPLIES)
140
120
55
35
30
A: V+ = 5V, V- = -5V
B: V+ = 10V, V- = -10V
C: V+ = 15V, V- = -15V
D: V+ = 20V, V- = -20V
V- = 0V
50
A
T = +125°C
A
45
40
35
30
25
20
15
10
T = +85°C
A
T = +25°C
A
100
80
60
40
20
25
20
15
10
5
V+ = 5V
B
C
T = -55°C
A
D
V+ = 10V
V+ = 15V
V+ = 15V, V- = -15V
V+ = 20V
5
0
5
10
(V)
15
20
-20
-10
0
10
20
-20
-10
0
10
20
V
V
D
(V)
V
D
(V)
D
13/DG425
ON-RESISTANCE vs. V AND
TEMPERATURE (SINGLE SUPPLY)
OFF LEAKAGE CURRENTS vs.
TEMPERATURE
ON LEAKAGE CURRENTS vs.
TEMPERATURE
D
70
60
100
10
100
10
V+ = 16.5V
V- = -16.5V
V+ = 16.5V
V- = -16.5V
V = ±15V
= ±15V
S
V
= ±15V
= ±15V
D
D
T = +125°C
A
V
V
S
50
40
30
20
10
1
0.1
1
0.1
T = +85°C
A
T = +25°C
A
0.01
0.01
0.001
0.0001
0.001
0.0001
V+ = 12V, V- = 0V
5
0
10
(V)
15
20
-75
25
125
-75
25
TEMPERATURE (°C)
125
V
TEMPERATURE (°C)
D
CHARGE INJECTION vs.
ANALOG VOLTAGE
SUPPLY CURRENT vs.
TEMPERATURE
60
40
100
10
1
20
0
I+ at V+ = 16.5V
I- at V- = -16.5V
0.1
-20
-40
-60
0.01
0.001
0.0001
I
at V = 5V
L
L
V+ = 15V, V- = -15V
-10
-20
0
10
20
-75
25
TEMPERATURE (°C)
125
V
(V)
D
4
_______________________________________________________________________________________
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
13/DG425
__________Ap p lic a t io n s In fo rm a t io n
___________________P in De s c rip t io n s
Op e ra t io n w it h S u p p ly Vo lt a g e s
Ot h e r Th a n ±1 5 V
DG421
The DG421/DG423/DG425 switches operate with ±4.5V
to ±20V bipolar supplies or with a +10V to +30V single
supply. In either case, analog signals ranging from V+
to V- c a n b e s witc he d . The Typ ic a l Op e ra ting
Characteristics graphs illustrate typical analog-signal
and supply-voltage on-resistance variations. The usual
on-resistance temperature coefficient is 0.5%/°C (typ).
PIN
1, 8
2
NAME
FUNCTION
Drain Terminals
D1, D2
–—–––
WR
Write Select
No Internal Connection
Reset Select
3, 4, 5, 6
7
N.C.
–—–––
RS
9, 16
10, 15
11
S1, S2
IN1, IN2
V+
Source Terminals
Input Control
Lo g ic In p u t s
These devices operate with a single positive supply or
with bipolar supplies. They maintain TTL compatibility
with supplies anywhere in the ±4.5V to ±20V range as
long as V = +5V. If V is connected to V+ or another
Positive Supply
Logic Supply
12
V
L
L
L
supply at voltages other than +5V, the devices will
operate at CMOS-logic-level inputs.
13
GND
V-
Ground
14
Negative Supply
DG423/DG425
Ove rvo lt a g e P ro t e c t io n
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings because stresses beyond the listed rat-
ings may cause permanent damage to the devices.
DIP
PLCC
NAME
FUNCTION
1, 8, 3, 6 2, 10, 4, 8
D1-D4
Drain Terminals
Write Select
–—–––
2
3
WR
Always sequence V+ on first, followed by V , V-, and
L
logic inputs. If power-supply sequencing is not possi-
ble, add two small, external signal diodes in series with
s up p ly p ins for ove rvolta g e p rote c tion (Fig ure 1).
Adding diodes reduces the analog signal range to 1V
below V+ and 1V above V-, without affecting low switch
resistance and low leakage characteristics. Device
operation is unchanged, and the difference between V+
and V- should not exceed +44V.
16, 9, 4, 5 20, 12, 5, 7
S1-S4
Source Terminals
Resets Select
Input Control
–—–––
7
15, 10
11
9
RS
19, 13
IN1, IN2
V+
14
Positive Supply
Logic Supply
12
15
1, 6, 11, 16
18
V
L
—
N.C.
V-
No Internal Connection
Negative Supply
Ground
14
13
17
GND
V+
S
D
V
g
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
_______________________________________________________________________________________
5
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
______________________________________________Tim in g Dia g ra m s /Te s t Circ u it s
V
OUT
is the steady-state output with the switch on. Feedthrough via switch capacitance may result in spikes at the
leading and trailing edge of the output waveform.
t
t
F
< 20ns
< 20ns
R
DG421
DG423
DG425
+5V
+15V
LOGIC
INPUT
3V
0V
V
L
V+
S
50%
SWITCH OUTPUT
V = 10V for t
V = -10V for t
D
D
D
ON
V
OUT
t
OFF
OFF
R
L
C
L
V
OUT
IN
0.9 x V
OUT
GND
V-
LOGIC
INPUT
SWITCH
OUTPUT
0V
t
ON
0.9 x V
OUT
-V
OUT
R
-15V
L
V
OUT
= V
D
(
)
R + r
L
DS(ON)
*V = 10V for t , V = -10V for t
OFF
D
ON
D
REPEAT TEST FOR IN2 AND S2.
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
13/DG425
NOTE: LOGIC INPUT WAVEFORM IS INVERTED FOR
SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.
L
Figure 2. Switching Time
3V
0
WR
1.5V
t
WW
t
DW
t
WD
3V
0
2.0V
IN
0.8V
3V
0
RS
1.5V
t
RS
t
OFF(RS)
V
0.8 x V
OUT
SWITCH OUT
0
OUTPUT
Figure 3. Latch Timing
6
_______________________________________________________________________________________
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
13/DG425
_________________________________Tim in g Dia g ra m s /Te s t Circ u it s (c o n t in u e d )
3V
+5V
+15V
50%
DG423
LOGIC
INPUT
0V
0V
V+
S
RS
V
L
D
D
V
OUT1
V = 10V
D
V = 10V
D
V
OUT2
S
V
OUT1
C
L1
R
L1
0.9 x V
OUT
IN
35pF
300Ω
SWITCH
OUTPUT 1
R
300Ω
C
L2
L2
35pF
WR GND
V-
LOGIC
INPUT
0.9 x V
OUT
V
OUT2
-15V
R = 1000Ω
C = 35pF
L
L
SWITCH
OUTPUT 2
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
0V
t
D
t
D
Figure 4. DG423 Break-Before-Make Interval
+5V
+15V
V+
DG421
DG423
DG425
∆V
OUT
RS
V
L
R
g
V
OUT
S
D
V
OUT
C
L
10nF
V
g
IN
0FF
0N
0FF
GND WR
IN
V-
-15V
Q = ∆V x C
OUT
L
IN DEPENDENT ON SWITCH CONFIGURATION.
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
V
IN
= 3V
Figure 5. Charge Injection
10nF
+15V
V+
+5V
DG421
DG423
DG425
SIGNAL GENERATOR
V
L
RS
D
V
S
IN
0V or 2.4V
V
D
S
NETWORK
ANALYZER
V-
GND
WR
R
L
-15V
10nF
Figure 6 . Off-Isolation Rejection Ratio
_______________________________________________________________________________________
7
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
_________________________________Tim in g Dia g ra m s /Te s t Circ u it s (c o n t in u e d )
+15V
10nF
+5V
DG421
DG423
DG425
V+
RS
V
L
50Ω
SIGNAL GENERATOR
D
S
IN
0V or 2.4V
IN
D
0V or 2.4V
N.C.
S
NETWORK
ANALYZER
GND WR
V-
R
L
10nF
-15V
Figure 7. Crosstalk
13/DG425
+15V
+5V
+15V
V+
+5V
10nF
D
10nF
D
DG421
DG423
DG425
DG421
DG423
DG425
V+
RS
V
L
RS
V
L
CAPACITANCE
METER
IN
CAPACITANCE
METER
IN
0V or 2.4V
0V or 2.4V
S
S
GND WR
V-
GND WR
V-
10nF
10nF
-15V
-15V
Figure 8. Drain/Source-Off Capacitance
Figure 9. Drain/Source-On Capacitance
8
_______________________________________________________________________________________
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
13/DG425
_____________________________________________P in Co n fig u ra t io n s (c o n t in u e d )
TOP VIEW
3
2
1
20
19
D1
WR
D3
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D3
4
18 V-
IN1
V-
S3
N.C.
S4
5
6
7
8
17 GND
16 N.C.
S3
GND
DG423
DG425
DG423
DG425
S4
D4
RS
D2
V
L
V+
IN2
S2
15
V
L
D4
14 V+
9
10
11
12
13
DIP
PLCC
N.C. = No Internal Connection
_____________________________Fu n c t io n a l Dia g ra m s /Tru t h Ta b le s (c o n t in u e d )
D1
D3
D1
D3
S1
S3
S1
S3
WR
WR
CK
D
Q
CK
D
Q
Q
IN1
RS
IN1
RS
R
Q
R
DG423
DG425
IN2
IN2
D
R
Q
D R
CK
Q
CK
S2
S4
S2
S4
D2
D4
D2
D4
TWO DPST SWITCHES PER PACKAGE
DG425 TRUTH TABLE
TWO SPDT SWITCHES PER PACKAGE
DG423 TRUTH TABLE
WR RS IN SWITCH 1, 2 SWITCH 3, 4
WR RS IN SWITCH
0
1
0
1
Off
On
Off
On
On
Off
1
0
0
1
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
LOGIC "O" ≤ 0.8V
LOGIC "1" ≥ 2.4V
LATCH OPERATION TRUTH TABLE
IN
RS WR
LATCH/SWITCH X
X
X
1
1
0
Latch operation transparent.
Control data latched in.
Switches on or off as selected by last IN.
X
X
0
X
X
All latches reset. Switches on or off as
when IN = 0, WR = 0, RS = 1.
_______________________________________________________________________________________
9
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
_Ord e rin g In fo rm a t io n (c o n t in u e d )
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 SO
DG423CJ
DG423CY
DG423C/D
DG423DJ
DG423DY
DG423DN
DG423DK
DG423AK
DG425CJ
DG425CY
DG425C/D
DG425DJ
DG425DY
DG425DN
DG425DK
DG425AK
0°C to +70°C
0°C to +70°C
Dice*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
16 Plastic DIP
16 SO
20 PLCC
16 CERDIP
16 CERDIP**
16 Plastic DIP
16 SO
0°C to +70°C
0°C to +70°C
Dice*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 SO
20 PLCC
13/DG425
16 CERDIP
16 CERDIP**
* Contact factory for dice specifications.
**Contact factory for availability and processing to MIL-STD-883B.
___________________________________________________________Ch ip To p o g ra p h ie s
DG421
DG423/DG425
WR
D1
S1
IN1
WR
D1
S1
IN1
N.C.
D3
V-
V-
GND
0.105"
GND
0.105"
N.C.
N.C.
S3
S4
V
L
V
L
(2.66mm)
(2.66mm)
V+
V+
N.C.
RS
D4
RS
D2
S2
IN2
D2
S2
IN2
0.082"
(2.08mm)
0.082"
(2.08mm)
TRANSISTOR COUNT: 100
TRANSISTOR COUNT: 100
SUBSTRATE CONNECTED TO V+
SUBSTRATE CONNECTED TO V+
10 ______________________________________________________________________________________
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
13/DG425
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
D1
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
A
–
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.27
0.20
18.92
0.13
7.62
6.10
0.150
0.080
0.022
0.065
0.012
0.765
0.030
0.325
0.280
3.81
2.03
0.56
1.65
0.30
19.43
0.76
8.26
7.11
B
0.016
B1 0.050
C
D
0.008
0.745
E
D1 0.005
0.300
E1 0.240
E
E1
D
e
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
A3
e
A
B
A2
A1
A
L
e
–
0.115
0˚
0.400
0.150
15˚
–
10.16
3.81
L
2.92
0˚
α
15˚
21-587A
α
16-PIN PLASTIC
DUAL-IN-LINE
PACKAGE
C
e
B1
e
e
A
B
B
INCHES
MIN
MILLIMETERS
DIM
MAX
0.200
0.023
0.065
0.015
0.840
0.310
0.320
MIN
–
MAX
5.08
0.58
1.65
0.38
21.34
7.87
8.13
A
B
–
S1
S
0.014
0.36
0.97
0.20
–
B1 0.038
C
D
E
0.008
–
0.220
5.59
7.37
E1 0.290
e
L
0.100 BSC
2.54 BSC
0.125
0.150
0.015
–
0.200
–
3.18
3.81
0.38
–
5.08
–
E1
E
L1
Q
S
0.060
0.080
–
1.52
2.03
–
D
A
S1 0.005
0˚
0.13
0˚
α
15˚
15˚
21-590B
α
Q
L
L1
C
16-PIN CERAMIC
DUAL-IN-LINE
PACKAGE
e
B1
B
______________________________________________________________________________________ 11
Im p ro ve d Lo w -P o w e r,
CMOS An a lo g S w it c h e s w it h La t c h e s
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
INCHES
MILLIMETERS
DIM
MIN
0.165
MAX
0.180
0.110
0.156
–
MIN
4.19
2.54
3.68
0.51
0.33
0.66
0.23
9.78
8.89
7.37
MAX
4.57
2.79
3.96
–
A
A1 0.100
A2 0.145
A3 0.020
A2
B
0.013
0.021
0.032
0.011
0.395
0.355
0.330
0.53
0.81
0.28
10.03
9.02
8.38
B1 0.026
C
C
D
0.009
0.385
e
D1 0.350
D2 0.290
B1
B
D1
D
D2
D3
e
0.200 REF
0.050 REF
5.08 REF
1.27 REF
21-981A
A3
D3
D1
D
A1
13/DG425
A
20-PIN PLASTIC
LEADED CHIP
CARRIER
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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