78P2241B-IGT/F [MAXIM]

PCM Transceiver, 1-Func, BICMOS, PQFP48, LEAD FREE, TQFP-48;
78P2241B-IGT/F
元器件型号: 78P2241B-IGT/F
生产厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述和应用:

PCM Transceiver, 1-Func, BICMOS, PQFP48, LEAD FREE, TQFP-48

PC信息通信管理
PDF文件: 总23页 (文件大小:386K)
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型号参数:78P2241B-IGT/F参数
生命周期Obsolete
IHS 制造商MAXIM INTEGRATED PRODUCTS INC
零件包装代码QFP
针数48
Reach Compliance Codecompliant
HTS代码8542.39.00.01
风险等级5.63
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
78P2241B
E3/DS3/STS-1
Line Interface Unit
DATA SHEET
JULY 2005
DESCRIPTION
The 78P2241B is a line interface transceiver IC for
E3, DS3, STS-1, NA T3 and ATM applications. It
includes clock recovery and transmitter pulse
shaping functions for applications using 75-ohm
coaxial cable at distances up to 1100 feet. These
applications include DSLAMs, digital multiplexers,
SONET Add/Drop multiplexers, PDH equipment,
DS3 to Fiber optic and microwave modems and
ATM WAN access for routers and switches.
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements.
The 28-pin PLCC 78P2241B is pin and functionally
compatible to the 78P7200L and the 78P2241 (28
PLCC version). The 78P2241B in the 48-pin TQFP
is pin compatible with the 78P2241 in the same
package. To the 78P7200L functionality, it adds a
B3ZS/HDB3 ENDEC, line code violation detector,
loop-back and clock polarity selection as well as
ability to receive a DSX3 monitor signal. The line
code violation detector has been added to the
78P2241 functionality.
The 78P2241B is manufactured in an advanced
BICMOS process and operates at both 5V and
3.3 V power supply voltages. It consumes less than
110 mA of supply current.
LPBK
FEATURES
Single chip transmit and receive interface for
E3, DS3 and STS-1 applications.
Interface to 75 ohm coaxial cable over 1100
feet at speeds up to 51.84 Mbps.
Compliant with ANSI T1.102-1993, Telcordia
GR-499-CORE and GR-253-CORE, ITU-T
G.703, G.823 for jitter tolerance, and G.775
for loss of signal.
Compliant with ATM FORUM af-phy-0034 (E3
public UNI) and af-phy-0054 (DS3 public UNI).
Easily Interfaced to ATM framer ICs such as
PMC 7345 , 7346 QJET and 7321.
Unique clock recovery requires no reference
clock or crystal oscillator.
Receive DS3-high and DSX3 monitor signals
Includes diagnostic loop-back for AMI and
digital signals.
Includes a selectable B3ZS/HDB3 ENDEC.
Pin compatible to 78P7200 (28-lead PLCC)
and 78P2241.
28-lead PLCC and 48-lead TQFP packages
3.3 or 5 V operation, ICC<110mA
Input circuit works either Transformer or
Capacitor coupled
Line-code violation detector
TPOS
TNEG
TCLK
B3ZS /
HDB3
Encoder
TXEN
LBO
BLOCK DIAGRAM
PULSE
SHAPER
LOUTP
LOUTN
RPOS
RNEG
B3ZS /
HDB3
Decoder
Data
Slicer
Adaptive
Equalizer
Clock
Recovery
LINP
LINN
RCLK
Biasing
Signal
Detector
LF
LPBK
Page: 1 of 23
MON
RFO
LOS
©
2005 Teridian Semiconductor Corporation
Rev 5.0
78P2241B
E3/DS3/STS-1
Transceiver
FUNCTIONAL DESCRIPTION
The 78P2241B is a single chip line interface IC
designed to work with a 51.84 Mbit/s STS-1, 44.736
Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver
recovers clock, positive data and negative data from
an Alternate Mark Inversion (AMI) signal. The AMI
line input signal should be B3ZS or HDB3 coded.
The transmitter accepts clock, positive, and negative
data and converts them into an AMI signal to drive a
75
coaxial cable. The shape of the transmitted
signal though any cable length of 0 to 450 feet
complies with the published templates of ANSI
T1.102-1993, Telcordia TR-NWT-000499 and GR-
253-CORE, ITU-T G.703. The 78P2241B is designed
to work with B3ZS or HDB3 coded signals. The
B3ZS or HDB3 encoding and decoding functions are
normally included in the framer ICs; however, a
selectable B3ZS/HDB3 ENDEC is included in the
78P2241B for interface to binary NRZ data. The
78P2241B is designed to easily connect to popular
ATM framer ICs such as PMC 7345 (SUNI-PDH),
PMC 7346 (QJET) and 7321.
OPERATION SPEED
Internal bias generators that are adjusted by the
value of the RFO set the 78P2241B PLL center
frequency and Transmitter amplitude for the different
standards. The
E#
pin controls the equalizer
response and the transmitter pulse shape and
amplitude. The following table shows the proper
settings.
Standard
E3
DS3
STS-1
RECEIVER
The receiver input can be either transformer-coupled
or capacitor coupled to the AMI signal.
In
applications where the highest performance and
isolation is required, a 1:1 transformer is used on the
receiver path. In the applications, where isolation is
provided elsewhere in the circuit, an AC coupling can
be used.
The inputs to the IC are internally
referenced to Vcc. Since the input impedance of the
78P2241B is high, the AMI line must be terminated to
75
. The input signal of the 78P2241B must be
limited to a maximum of three consecutive zeros
using a coding scheme such as B3ZS or HDB3.
RFO Value, k
6.81
5.23
4.53
E#
pin setting
Low
High
Float
The AMI signal first enters a selectable fixed 20 dB
amplifier stage that compensates for very low
amplitude DSX3 monitor signal when MON pin is
held high. The signal then enters an equalizer and
AGC gain stage. The equalizer is designed to
overcome intersymbol interference caused by long
cable lengths. Because the equalizer is adaptive,
the circuit will work with all square shaped signals
such as DS3 high or 34 Mbit/s E3. The variable gain
differential amplifier maintains a constant voltage
level output regardless of the input voltage level.
The gain of the amplifier is adjusted by detecting the
peak of the signal and comparing it to a fixed
reference.
Outputs of the data comparators are connected to
the clock recovery circuits. The clock recovery
system employs a phase locked loop with an
auxiliary frequency-sensitive acquisition loop. This
system permits the loop to independently lock to the
frequency and phase of the incoming data stream
without the need for an external, high precision
tuned circuits or reference clock signal.
The jitter tolerance of the 78P2241B meets the
requirements of Telcordia GR-499-CORE for
Category I equipment for DS3 rates and exceeds the
requirements of ITU-T G.823 for E3 rates.
Pin 21
MON
Low
High
Low
High
Receive
Range
mVpk
90-850
25-80
104-1200
25-80
Mode
DS3/STS-1 normal
DS3 monitor
E3 normal
E3 monitor
B3ZS/HDB3 DECODER
The 78P2241B includes a selectable B3ZS/HDB3
Encoder/Decoder (ENDEC). When the
ENDEC
pin
is low, the ENDEC is selected and the receiver
generates a composite NRZ logic data following the
B3ZS (for DS3/STS-1) or HDB3 (for E3) substitution
codes via the RPOS/RNRZ pin as shown below.
Pin 20
ENDEC
High
Low
RPOS/RNRZ
Positive AMI
NRZ data
RNEG
Negative AMI
No Connect
Page: 2 of 23
©
2005 Teridian Semiconductor Corporation
Rev 5.0
78P2241B
E3/DS3/STS-1
Transceiver
FUNCTIONAL DESCRIPTION
(continued)
The decoder also detects Receive Line Code
Violations (RLCV) and outputs a pulse via the
RNEG/RLCV pin. Three different classes of line code
violations are detected.
1)
2)
Too many zeros: More than two (three)
consecutive zeros in B3ZS (HDB3) mode.
Not enough zeros between bipolar pulse (B) and
bipolar violation pulse (V): (B,V) for B3ZS, (B,V)
or (B,0,V) for HDB3.
Code violation: Even number of bipolar pulses
(B) detected between bipolar violation pulses (V).
RCLK/TCLK polarity reversal:
To simplify the interface with framer circuitry, RCLK
and TCLK can be inverted with the ICKP pin.
Pin 10
ICKP
Low
Float
High
RCLK
Normal
Invert
Normal
TCLK
Normal
Invert
Invert
3)
Loop-back modes:
The following loop-back modes allow for the
diagnostic test of the PC board. This function is
controlled by the
LPBK
pin.
Pin 28
LPBK
LPBK
Low
Float
High
Loop-back
Local loop-back (LLB)
Remote loop-back (RLB)
Normal Operation
On the transmit side, NRZ input data is internally
converted to Positive and Negative logic data
following the B3ZS (for DS3/STS-1) or HDB3 (for E3)
substitution codes. The NRZ data is input to the
TPOS/TNRZ pin as shown below.
Pin 20
ENDEC
High
Low
TPOS/TNRZ
Positive AMI
NRZ data
TNEG
Negative AMI
LCV
Local loop-back:
When
LPBK
is low, the 78P2241B enters Local
loopback. In this mode, the LOUT+/- transmit signals
are internally routed to the receiver input circuit. The
incoming line receiver AMI signal on LIN+/- is
ignored. With the transmitter still tied to the cable,
this test mode can indicate a short circuit on the
transmitter external components or other problem in
the transmit path.
Remote loop-back:
When
LPBK pin
is allowed to float, the 78P2241B
enters remote loopback mode. The RPOS/RNEG
and RCLK pins are internally tied to the
TPOS/TNEG and TCLK so the same AMI signal that
is received by the framer is transmitted back to the
far end where a bit continuity test can be performed.
Line Build-Out:
The Line Build-Out function controls the amplitude in
DS3 and STS-1 mode. The selection of LBO
depends on the amount of cable the transmitter is
connected to. When used with less than 225 ft of
cable the LBO pin should be pulled high. With 225ft
or more cable the LBO pin should be low.
LOSS OF SIGNAL
Should the input signal fall below a minimum value for
175 +/- 75 cycles of the receive clock RCLK, the loss
of signal indication,
LOS
goes low.
LOS
goes high
when a valid signal is received at the input for at least
175 +/- 75 cycles of the receive clock.
TRANSMITTER
The transmitter accepts logic level clock (TCLK),
positive data (TPOS) and negative data (TNEG)
signals and generates current pulses on the LOUT+
and LOUT- pins. When properly connected to a
center-tapped 1:2 transformer, an AMI pulse is
generated which can drive a 75
coaxial cable.
When the recommended transformer is used and the
E#
pin is set high, the transmitted pulse shape at the
end of the 75
terminated cable of 0 to 450 feet will
fit the DS3 template in ANSI T1.102-1993 and
Telcordia GR-499-CORE standard documents.
For STS-1 applications, the transmitted pulse for a
short cable meets the requirements of Telcordia
GR-253-CORE. The
E#
pin should be allowed to
float.
For E3 applications, the transmitted pulse for a short
cable meets the requirements of ITU-T G.703. The
E#
pin is to be pulled low.
Page: 3 of 23
©
2005 Teridian Semiconductor Corporation
Rev 5.0
78P2241B
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION
:
(The 28-pin PLCC is compatible with 78P7200)
NAME
LIN+
LIN-
RCLK
RPOS/
RNRZ
RNEG/
LCV
PIN
TQFP
42
44
33
35
PIN
PLCC
1
3
23
25
TYPE
I
O
O
DESCRIPTION
Line Input: Differential AMI inputs to the chip. Should be
transformer coupled and terminated at 75-ohm resistor.
Receive Clock: Recovered receive clock.
Receive Positive Data / NRZ Data: When
ENDEC
is high, this
pin indicates reception of a positive AMI pulse on the coax
cable. When
ENDEC
is low, it outputs NRZ data.
Receive Negative Data/LCV: When
ENDEC
is high, this pin
indicates reception of a negative AMI pulse on the coax. When
ENDEC
is low this pin indicates the occurrence of a line
code violation.
Loss of Signal: logic low indicates that receiver signal (LIN±)
is below the threshold level for 175±75 periods. RPOS and
RNEG are forced low when
LOS=0.
Line Out: Differential AMI Output. Requires a 2:1 center
tapped transformer and 301
resistor.
Transmitter Clock Input: This signal is used to latch the
TPOS/TNRZ and TNEG signals into the 78P2241.
Transmit Positive Data / Transmit NRZ: When
ENDEC
is
high, a logic one on this pin generates a positive AMI pulse
on the coax. This pin should not be high at the same time
that TNEG is high.
When
ENDEC
is low, NRZ data received on this pin is encoded
into positive and negative AMI pulses.
Transmit Negative Data: When
ENDEC
is high, a logic one on
this pin generates a negative AMI pulse on the coax. This pin
should not be high at the same time that TPOS/TNRZ is high.
When
ENDEC
is low, this pin is ignored.
Line Build-Out, Transmitter: Logic low used with 225ft or
more of cable is used on transmit path. Logic high used with
less than 225ft of cable.
DS3, E3 and STS-1 Select: Set low for
E#
applications. Set
high for DS3, allow to float for STS-1 operation. Formerly
OPT!
On the 78P7200.
Transmitter Enable: When high, enables transmitter. When
low, tri-states transmitter drivers, LOUT±. This pin was
called
OPT@
on 78P7200.
DSX3 / E3 Monitor Select: When set high, an additional 20-
dB gain stage is added to the receiver gain. This pin was
tied to GND on the 78P7200.
Invert Clock Polarity: When low, the polarities of RCLK and
TCLK are the same as those on the 78P7200. When set high,
the polarity of TCLK is inverted. When allowed to float, the
polarities of both RCLK and TCLK are inverted.
Loop-back Select: When high, neither loop-back is activated.
When allowed to float RPOS, RNEG and RCLK are looped
back onto TPOS, TNEG and TCLK. When low, LOUT± is
looped back onto LIN±.
Power Supply.
34
24
O
LOS
39
27
O
LOUT+
LOUT-
TCLK
TPOS/
TNRZ
9
11
18
16
9
11
16
14
O
I
I
TNEG
17
15
I
LBO
13
12
I
E#
15
13
I3
TXEN
22
18
I
MON
28
21
I
ICKP
10
10
I3
LPBK
40
28
I3
VCC
5,6,20,
21,37,38
7,17,26
P
Page: 4 of 23
©
2005 Teridian Semiconductor Corporation
Rev 5.0
78P2241B
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION:
The 28-pin PLCC is compatible with 78P7200 (continued)
NAME
GND
PIN
TQFP
1, 3, 4, 7, 8,
12, 14, 19, 23,
24, 25, 29, 30,
31, 32, 36, 41,
43, 45, 46, 47,
48
2
PIN
PLCC
2,4,6,8,22
TYPE
P
DESCRIPTION
Ground. Connecting all ground pins to a common ground
plane is recommended.
RFO
5
-
LF1
ENDEC
26
27
19
20
-
I
A resistor to GND sets the operational speed of the chip.
RFO= 5.23K for DS3, RFO=6.81K for E3 and RFO=4.53K
for STS-1.
Receiver PLL filter capacitor.
Encoder/Decoder: When set low, activates B3ZS/HDB3
ENDEC on receiver and transmitter logic signals.
Note 1: Pin type: I-input; I3-three level logic input; O-output; P-power supply. Advanced Data sheet pin
assignment and functions are subject to change.
Page: 5 of 23
©
2005 Teridian Semiconductor Corporation
Rev 5.0
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