73S1210F-44IMR/F/P_技术文档

73S1210F

Self-Contained Smart Card Reader

with PINpad and Power Management

Simplifying System Integration™

DATA SHEET

May 2009

In addition, the circuit features an ON/OFF mode which

operates directly with an ON/OFF system switch: Any

activity on the ON/OFF button is debounced internally

and controls the power generation circuit accordingly,

under the supervision of the firmware (OFF request /

OFF acknowledgement at firmware level). The OFF

mode can be alternatively initiated from the controller

(firmware action instead of ON/OFF switch).

GENERAL DESCRIPTION

The 73S1210F is a versatile and economical CMOS

System-on-Chip device intended for smart card reader

applications. The circuit is built around an 80515 high-

performance core; it features primarily an ISO-7816 / EMV

interface and a generic asynchronous serial interface.

Delivered with turnkey Teridian embedded firmware, it

forms a ready-to-use smart card reader solution that can be

seamlessly incorporated into any microprocessor-based

system where a serial line is available.

In OFF mode, the circuit typically draws less than 1µA,

which makes it ideal for applications where battery life

must be maximized.

The solution is scalable, thanks to a built-in I²C interface

that allows to drive external electrical smart card interfaces

such as Teridian 73S8010 ICs. This makes the solution

immediately able to support multi-card slots or multi-SAM

architectures.

Embedded Flash memory is in-system programmable

and lockable by means of on-silicon fuses. This makes

the 73S1210F suitable for both development and

production phases.

In addition, the 73S1210 features a 5x6 PINpad interface, 8

user I/Os, multiple interrupt options and an analog voltage

input (for DC voltage monitoring such as battery level

detection) that make it suitable for low-cost PINpad reader

devices.

Teridian Semiconductor Corporation offers with its

73S1210F a very comprehensive set of software

libraries for EMV. Refer to the 73S12xxF Software

User’s Guide for a complete description of the

Application Programming Interface (API Libraries) and

related software modules.

The 80515 CPU core instruction set is compatible with the

industry standard 8051, while offering one clock-cycle per

instruction processing power (most instructions). With a

CPU clock running up to 24MHz, it results in up to 24MIPS

available that meets the requirements of various encryption

needs such as AES, DES / 3-DES and even RSA (for PIN

encryption for instance).

A complete array of development and programming

tools, libraries and demonstration boards enable rapid

development and certification of readers that meet

most demanding smart card standards.

APPLICATIONS

The circuit requires a single 6MHz to 12MHz crystal.

•

PINpad smart card readers:

o

With serial connectivity

Ideal for low-cost POS Terminals and Digital

Identification (Secure Login, Gov’t ID, ...)

The respective 73S1210F embedded memories are 32KB

Flash program memory, 2KB user XRAM memory, and

256B IRAM memory. Dedicated FIFOs for the ISO 7816

UART are independent from the user XRAM and IRAM.

•

SIM Readers in Personal Wireless devices

Payphones & Vending machines

General purpose smart card readers

Alternatively to the turnkey firmware offered by Teridian,

customers can develop their own embedded firmware

directly within their application or using Teridian 73S1210F

Evaluation Board through a JTAG-like interface.

ADVANTAGES

•

Reduced BOM

Versatile power supply options

o

2.7V to 6.5V ranges

The chip incorporates an inductor-based DC-DC converter

that generates all the necessary voltages to the various

73S1210F function blocks (smart card interface, digital

core, etc.) from any of two distinct power supply sources:

•

Higher performance CPU core (up to 24MIPS)

Built-in EMV/ISO slot, expandable to multi-slots

Flexible power supply options

o

On-chip DC-DC converter

CMOS switches between supply inputs

the +5V bus (V_BUS, 4.4 to 6.5V), or a main battery (V_BAT

,

4.0V to 6.5V). The chip automatically powers-up the DC-

DC converter with V_BUSif it is present, or uses V_BATas the

supply input if V_BUSis not present. Alternatively, the pin V_PC

can support a wider power supply input range (2.7V to

6.5V), when using a single system supply source.

•

Sub-µA Power Down mode with ON/OFF switch

Powerful In-Circuit Emulation and Programming

A complete set of EMV4.1 / ISO7816 libraries

Turnkey PC/SC firmware and host drivers

o

Multiple OS supported

Rev. 1.4

1

73S1210F Data Sheet

DS_1210F_001

FEATURES

80515 Core:

Communication Interfaces:

•

1 clock cycle per instruction (most instructions)

CPU clocked up to 24MHz

•

Full-duplex serial interface (1200 to 115kbps

UART)

I²C Master Interface (400kbps)

•

32KB Flash memory (lockable)

2kB XRAM (User Data Memory)

256 byte IRAM

Man-Machine Interface and I/Os:

6x5 Keyboard (hardware scanning, debouncing

and scrambling)

Hardware watchdog timer

•

(8) User I/Os

Oscillators:

Single programmable current output (LED)

Operating Voltage:

•

Single low-cost 6MHz to 12MHz crystal

An Internal PLL provides all the necessary clocks to

each block of the system

Single supply 2.7V to 6.5V operation (VPC)

5V supply (VBUS 4.4V to 5.5V) with or without

battery back up operation (VBAT 4.0V to 6.5V)

Interrupts:

•

Standard 80C515 4-priority level structure

9 different sources of interrupt to the core

•

Automated detection of voltage presence - Priority

on VBUS over VBAT

Power Down Modes:

DC-DC Converter:

•

2 standard 80C515 Power Down and IDLE modes

Sub-µA OFF mode

•

Requires a single 10µH Inductor

3.3V / 20mA supply available for external circuits

ON/OFF Main System Power Switch:

Input for an SPST momentary switch to ground

Operating Temperature:

•

-40°C to 85°C

Timers:

Package:

•

(2) Standard 80C52 timers T0 and T1

(1) 16-bit timer

•

68-pin QFN, 44 pin QFN

Turnkey Firmware:

Built-in ISO-7816 Card Interface:

•

Compliant with PC/SC, ISO7816 and EMV4.1

specifications

•

Linear regulator produces VCC for the card

(1.8V, 3V or 5V)

•

Features a Power Down mode accessible from the

host

•

Full compliance with EMV 4.1

•

Supports Plug & Play over serial interface

Windows^®XP driver available (*)

Windows CE / Mobile driver available (*)

Linux and other OS: Upon request

Or for custom developments:

Activation/Deactivation sequencers

Auxiliary I/O lines (C4 and C8 signals)

7kV ESD protection on all interface pins

Communication with Smart Cards:

•

ISO 7816 UART 9600 to 115kbps for T=0, T=1

(2) 2-Byte FIFOs for transmit and receive

o

A complete set of ISO-7816, EMV4.1 and

low-level libraries are available for T=0 / T=1

Configured to drive multiple external Teridian

73S8010x interfaces (for multi-SAM architectures)

o

Two-level Application Programming Interface

(ANSI C-language libraries)

Voltage Detection:

•

Analog Input (detection range: 1.0V to 2.5V)

(*) Contact Teridian Semiconductor for conditions and

availability.

2

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Table of Contents

1

Hardware Description.........................................................................................................................8

1.1 Pin Description.............................................................................................................................8

1.2 Hardware Overview ...................................................................................................................11

1.3 80515 MPU Core .......................................................................................................................11

1.3.1 80515 Overview.............................................................................................................11

1.3.2 Memory Organization ....................................................................................................11

1.4 Program Security .......................................................................................................................16

1.5 Special Function Registers (SFRs) ...........................................................................................18

1.5.1 Internal Data Special Function Registers (SFRs)..........................................................18

1.5.2 IRAM Special Function Registers (Generic 80515 SFRs) ............................................19

1.5.3 External Data Special Function Registers (SFRs) ........................................................20

1.6 Instruction Set............................................................................................................................22

1.7 Peripheral Descriptions..............................................................................................................22

1.7.1 Oscillator and Clock Generation....................................................................................22

1.7.2 Power Supply Management ..........................................................................................25

1.7.3 Power ON/OFF..............................................................................................................26

1.7.4 Power Control Modes ....................................................................................................27

1.7.5 Interrupts........................................................................................................................33

1.7.6 UART .............................................................................................................................40

1.7.7 Timers and Counters .....................................................................................................45

1.7.8 WD Timer (Software Watchdog Timer) .........................................................................47

1.7.9 User (USR) Ports...........................................................................................................49

1.7.10 Analog Voltage Comparator ..........................................................................................51

1.7.11 LED Driver .....................................................................................................................53

1.7.12 I²C Master Interface.......................................................................................................54

1.7.13 Keypad Interface............................................................................................................61

1.7.14 Emulator Port.................................................................................................................68

1.7.15 Smart Card Interface Function ......................................................................................69

1.7.16 VDD Fault Detect Function..........................................................................................103

2

3

Typical Application Schematic......................................................................................................104

Electrical Specification...................................................................................................................105

3.1 Absolute Maximum Ratings.....................................................................................................105

3.2 Recommended Operating Conditions .....................................................................................105

3.3 Digital IO Characteristics .........................................................................................................106

3.4 Oscillator Interface Requirements ...........................................................................................107

3.5 DC Characteristics: Analog Input.............................................................................................107

3.6 Smart Card Interface Requirements........................................................................................108

3.7 DC Characteristics...................................................................................................................110

3.8 Current Fault Detection Circuits...............................................................................................111

4

5

Equivalent Circuits .........................................................................................................................112

Package Pin Designation ...............................................................................................................120

5.1 68-pin QFN Pinout ...................................................................................................................120

5.2 44-pin QFN Pinout ...................................................................................................................121

6

Packaging Information ...................................................................................................................122

6.1 68-Pin QFN Package Outline ..................................................................................................122

6.2 44-Pin QFN Package Outline ..................................................................................................123

7

8

9

Ordering Information......................................................................................................................124

Related Documentation..................................................................................................................124

Contact Information........................................................................................................................124

Revision History......................................................................................................................................125

Rev. 1.4

3

73S1210F Data Sheet

DS_1210F_001

Figures

Figure 1: IC Functional Block Diagram......................................................................................................... 7

Figure 2: Memory Map................................................................................................................................ 15

Figure 3: Clock Generation and Control Circuits ........................................................................................ 22

Figure 4: Oscillator Circuit........................................................................................................................... 24

Figure 5: Detailed Power Management Logic Block Diagram.................................................................... 25

Figure 6: Power Down Control.................................................................................................................... 27

Figure 7: Detail of Power Down Interrupt Logic.......................................................................................... 28

Figure 8: Power Down Sequencing ............................................................................................................ 29

Figure 9: External Interrupt Configuration................................................................................................... 33

Figure 10: I²C Write Mode Operation.......................................................................................................... 55

Figure 11: I²C Read Operation ................................................................................................................... 56

Figure 12: Simplified Keypad Block Diagram ............................................................................................. 61

Figure 13: Keypad Interface Flow Chart..................................................................................................... 63

Figure 14: Smart Card Interface Block Diagram......................................................................................... 69

Figure 15: External Smart Card Interface Block Diagram .......................................................................... 70

Figure 16: Asynchronous Activation Sequence Timing.............................................................................. 73

Figure 17: Deactivation Sequence.............................................................................................................. 73

Figure 18: Smart Card CLK and ETU Generation ...................................................................................... 74

Figure 19: Guard, Block, Wait and ATR Time Definitions .......................................................................... 75

Figure 20: Synchronous Activation ............................................................................................................. 77

Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 77

Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode................................. 78

Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 78

Figure 24: Operation of 9-bit Mode in Sync Mode...................................................................................... 79

Figure 25: 73S1210F Typical Application Schematic............................................................................... 104

Figure 26: 12 MHz Oscillator Circuit......................................................................................................... 112

Figure 27: 32KHz Oscillator Circuit........................................................................................................... 112

Figure 28: Digital I/O Circuit...................................................................................................................... 113

Figure 29: Digital Output Circuit................................................................................................................ 113

Figure 30: Digital I/O with Pull Up Circuit.................................................................................................. 114

Figure 31: Digital I/O with Pull Down Circuit............................................................................................. 114

Figure 32: Digital Input Circuit................................................................................................................... 115

Figure 33: OFF_REQ Interface Circuit ..................................................................................................... 115

Figure 34: Keypad Row Circuit ................................................................................................................. 115

Figure 35: Keypad Column Circuit............................................................................................................ 116

Figure 36: LED Circuit............................................................................................................................... 116

Figure 37: Test and Security Pin Circuit ................................................................................................... 117

Figure 38: Analog Input Circuit ................................................................................................................. 117

Figure 39: Smart Card Output Circuit ....................................................................................................... 117

Figure 40: Smart Card I/O Circuit ............................................................................................................. 118

Figure 41: PRES Input Circuit................................................................................................................... 118

Figure 42: PRESB Input Circuit ................................................................................................................ 118

Figure 43: ON_OFF Input Circuit.............................................................................................................. 119

Figure 44: 73S1210F 68 QFN Pinout ....................................................................................................... 120

Figure 45: 73S1210F 44 QFN Pinout ....................................................................................................... 121

Figure 46: 73S1210F 68 QFN Mechanical Drawing................................................................................. 122

Figure 47: 73S1210F 44 QFN Package Drawing..................................................................................... 123

4

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Tables

Table 1: 73S1210 Pinout Description ........................................................................................................... 8

Table 2: MPU Data Memory Map ............................................................................................................... 11

Table 3: Flash Special Function Registers ................................................................................................. 13

Table 4: Internal Data Memory Map ........................................................................................................... 14

Table 5: Program Security Registers.......................................................................................................... 17

Table 6: IRAM Special Function Registers Locations ................................................................................ 18

Table 7: IRAM Special Function Registers Reset Values .......................................................................... 19

Table 8: XRAM Special Function Registers Reset Values......................................................................... 20

Table 9: PSW Register................................................................................................................................ 21

Table 10: Port Registers ............................................................................................................................. 21

Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 23

Table 12: The MCLKCtl Register................................................................................................................ 23

Table 13: The TCON Register .................................................................................................................... 24

Table 14: The INT5Ctl Register .................................................................................................................. 30

Table 15: The MISCtl0 Register.................................................................................................................. 30

Table 16: The MISCtl1 Register.................................................................................................................. 31

Table 17: The MCLKCtl Register................................................................................................................ 31

Table 18: The PCON Register.................................................................................................................... 32

Table 19: The IEN0 Register ...................................................................................................................... 34

Table 20: The IEN1 Register ...................................................................................................................... 35

Table 21: The IEN2 Register ...................................................................................................................... 35

Table 22: The TCON Register .................................................................................................................... 36

Table 23: The T2CON Register .................................................................................................................. 36

Table 24: The IRCON Register................................................................................................................... 37

Table 25: External MPU Interrupts.............................................................................................................. 37

Table 26: Control Bits for External Interrupts.............................................................................................. 38

Table 27: Priority Level Groups .................................................................................................................. 38

Table 28: The IP0 Register......................................................................................................................... 38

Table 29: The IP1 Register......................................................................................................................... 39

Table 30: Priority Levels.............................................................................................................................. 39

Table 31: Interrupt Polling Sequence.......................................................................................................... 39

Table 32: Interrupt Vectors ......................................................................................................................... 39

Table 33: UART Modes .............................................................................................................................. 40

Table 34: Baud Rate Generation ................................................................................................................ 40

Table 35: The PCON Register.................................................................................................................... 41

Table 36: The BRCON Register ................................................................................................................. 41

Table 37: The MISCtl0 Register.................................................................................................................. 42

Table 38: The S0CON Register.................................................................................................................. 43

Table 39: The S1CON Register.................................................................................................................. 44

Table 40: The TMOD Register.................................................................................................................... 45

Table 41: Timers/Counters Mode Description ............................................................................................ 45

Table 42: The TCON Register .................................................................................................................... 46

Table 43: The IEN0 Register ...................................................................................................................... 47

Table 44: The IEN1 Register ...................................................................................................................... 48

Table 45: The IP0 Register......................................................................................................................... 48

Table 46: The WDTREL Register ............................................................................................................... 48

Table 47: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49

Table 48: UDIR Control Bit ......................................................................................................................... 49

Table 49: Selectable Controls Using the UxIS Bits..................................................................................... 49

Table 50: The USRIntCtl1 Register ............................................................................................................ 50

Table 51: The USRIntCtl2 Register ............................................................................................................ 50

Table 52: The USRIntCtl3 Register ............................................................................................................ 50

Table 53: The USRIntCtl4 Register ............................................................................................................ 50

Table 54: The ACOMP Register ................................................................................................................. 51

Table 55: The INT6Ctl Register .................................................................................................................. 52

Table 56: The LEDCtl Register................................................................................................................... 53

Rev. 1.4

5

73S1210F Data Sheet

DS_1210F_001

Table 57: The DAR Register....................................................................................................................... 57

Table 58: The WDR Register...................................................................................................................... 57

Table 59: The SWDR Register ................................................................................................................... 58

Table 60: The RDR Register....................................................................................................................... 58

Table 61: The SRDR Register .................................................................................................................... 59

Table 62: The CSR Register....................................................................................................................... 59

Table 63: The INT6Ctl Register .................................................................................................................. 60

Table 64: The KCOL Register..................................................................................................................... 64

Table 65: The KROW Register ................................................................................................................... 64

Table 66: The KSCAN Register.................................................................................................................. 65

Table 67: The KSTAT Register................................................................................................................... 65

Table 68: The KSIZE Register.................................................................................................................... 66

Table 69: The KORDERL Register............................................................................................................. 67

Table 70: The KORDERH Register ............................................................................................................ 67

Table 71: The INT5Ctl Register .................................................................................................................. 68

Table 72: The SCSel Register .................................................................................................................... 80

Table 73: The SCInt Register ..................................................................................................................... 81

Table 74: The SCIE Register...................................................................................................................... 82

Table 75: The VccCtl Register.................................................................................................................... 83

Table 76: The VccTmr Register.................................................................................................................. 84

Table 77: The CRDCtl Register .................................................................................................................. 85

Table 78: The STXCtl Register................................................................................................................... 86

Table 79: The STXData Register................................................................................................................ 87

Table 80: The SRXCtl Register................................................................................................................... 87

Table 81: The SRXData Register ............................................................................................................... 88

Table 82: The SCCtl Register..................................................................................................................... 89

Table 83: The SCECtl Register................................................................................................................... 90

Table 84: The SCDIR Register ................................................................................................................... 91

Table 85: The SPrtcol Register................................................................................................................... 92

Table 86: The SCCLK Register .................................................................................................................. 93

Table 87: The SCECLK Register................................................................................................................ 93

Table 88: The SParCtl Register.................................................................................................................. 94

Table 89: The SByteCtl Register ................................................................................................................ 95

Table 90: The FDReg Register................................................................................................................... 96

Table 91: The FDReg Bit Functions............................................................................................................ 96

Table 92: Divider Ratios Provided by the ETU Counter ............................................................................. 96

Table 93: Divider Values for the ETU Clock ............................................................................................... 97

Table 94: The CRCMsB Register ............................................................................................................... 98

Table 95: The BGT Register....................................................................................................................... 99

Table 96: The EGT Register....................................................................................................................... 99

Table 97: The BWTB0 Register................................................................................................................ 100

Table 98: The BWTB1 Register................................................................................................................ 100

Table 99: The BWTB2 Register................................................................................................................ 100

Table 100: The BWTB3 Register.............................................................................................................. 100

Table 101: The CWTB0 Register.............................................................................................................. 100

Table 102: The CWTB1 Register.............................................................................................................. 100

Table 103: The ATRLsB Register............................................................................................................. 101

Table 104: The ATRMsB Register............................................................................................................ 101

Table 105: The STSTO Register .............................................................................................................. 101

Table 106: The RLength Register............................................................................................................. 101

Table 107: Smart Card SFR Table ........................................................................................................... 102

Table 108: The VDDFCtl Register ............................................................................................................ 103

Table 109: Order Numbers and Packaging Marks ................................................................................... 124

6

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

ON_OFF

ICE INTERFACE

OFF_REQ

POWER

VDD

PLL

and

TIMEBASES

REGULATION

AND VCC

CONTROL

LOGIC

VDD

VCC

VOLTAGE REFERENCE

AND FUSE TRIM

CIRCUITRY

VPD REGULATOR

GND

X12IN

12MHz

OSCILLATOR

X12OUT

RST

CLK

VDD

OCDSI

SMART

CARD

ISO

I/O

FLASH/ROM

INTERFACE

AUX1

PROGRAM

MEMORY

32KB

MEMORY_

CONTROL

UNIT

CONTROL

GND

AUX2

RAM_

SFR_

CONTROL

ROW0

ROW1

ROW2

ROW3

TIMER_0_1

CORE

PRES

SCRATCH

IRAM

256B

FLASH

INTERFACE

ROW4

ROW5

COL0

COL1

COL2

COL3

COL4

KEYPAD

INTERFACE

EXTERNAL

SMART

CARD

SCLK

SIO

ALU

INTERFACE

WATCH-

DOG

TIMER

PMU

DATA

XRAM

2KB

INT2

INT3

PORTS

ISR

SERIAL

SCL

SDA

I²

C

USR0

USR1

USR2

MASTER

INT.

USR3

USR4

USR5

USR6

USR7

PERIPHERAL

INTERFACE

and SFR LOGIC

LED

DRIVER

Pins available on both 68 and 44-pin packages.

Pins only available on 68-pin package.

Figure 1: IC Functional Block Diagram

Rev. 1.4

7

73S1210F Data Sheet

DS_1210F_001

1 Hardware Description

1.1 Pin Description

Table 1: 73S1210 Pinout Description

Pin Name

Description

X12IN

10

11

9

I

Figure 26 MPU clock crystal oscillator input pin. A 1MΩ resistor is

required between pins X12IN and X12OUT.

X12OUT

10

O

I

Figure 26 MPU clock crystal oscillator output pin.

Figure 34 Keypad row input sense.

ROW(5:0)

0

1

2

3

4

5

21

22

24

33

36

37

COL(4:0)

O

Figure 35 Keypad column output scan pins.

0

1

2

3

4

12

13

14

16

19

USR(7:0)

IO

Figure 30 General-purpose user pins, individually configurable as

inputs or outputs or as external input interrupt ports.

0

1

2

3

4

5

6

7

35

34

32

31

30

29

23

20

22

21

20

19

18

17

14

13

SCL

5

6

O

Figure 29 I²C (master mode) compatible Clock signal. Note: the pin

is configured as an open drain output. When the I2C

interface is being used, an external pull up resistor is

required. A value of 3K is recommended.

SDA

6

7

IO

Figure 28 I²C (master mode) compatible data I/O. Note: this pin is bi-

directional. When the pin is configured as output, it is an

open drain output. When the I2C interface is being used,

an external pull up resistor is required. A value of 3K is

recommended.

RXD

TXD

INT3

INT2

SIO

17

18

48

49

47

11

12

30

31

29

I

O

I

Figure 32 Serial UART Receive data pin.

Figure 29 Serial UART Transmit data pin.

Figure 32 General purpose interrupt input.

I

IO

Figure 28 IO data signal for use with external Smart Card interface

circuit such as 73S8010.

SCLK

45

28

O

Figure 29 Clock signal for use with external Smart Card interface

circuit.

8

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Pin Name

Description

PRES

53

34

I

Figure 41 Smart Card presence. Active high. Note: the pin has a

very weak pull down resistor. In noisy environments, an

external pull down may be desired to insure against a

false card event.

CLK

RST

IO

55

57

61

60

59

58

36

38

42

41

40

39

O

Figure 39 Smart Card clock signal.

Figure 39 Smart Card reset signal.

IO

Figure 40 Smart Card Data IO signal.

Figure 40 Auxiliary Smart Card IO signal (C4).

Figure 40 Auxiliary Smart Card IO signal (C8).

AUX1

AUX2

VCC

IO

PSO

Smart Card VCC supply voltage output. A 0.47µF

capacitor is required and should be located at the smart

card connector. The capacitor should be a ceramic type

with low ESR.

GND

VPC

56

65

37 GND

Smart Card Ground.

44

PSI

Power supply source for main voltage converter circuit. A

10µF and a 0.1µF capacitor are required at the VPC input.

The 10µF capacitor should be a ceramic type with low

ESR.

VBUS

VBAT

62

64

PSI

Alternate power source input from external power supply.

Alternate power source input, typically from two series

cells, V > 4V.

VP

54

66

35

1

PSO

PSI

Intermediate output of main converter circuit. Requires an

external 4.7µF low ESR filter capacitor to GND.

LIN

Connection to 10µH inductor for internal step up

converter. Note: inductor must be rated for 400 mA

maximum peak current.

ON_OFF

63

43

33

I

Figure 43 Power control pin. Connected to normally open SPST

switch to ground. Closing switch for duration greater than

debounce period will turn 73S1210F on. If 73S1210F is

on, closing switch will flag the 73S1210F to go to the off

state. Firmware will control when the power is shut down.

OFF_REQ 52

O

Figure 33 Digital output. If ON_OFF switch is closed (to ground) for

debounce duration and circuit is “on,” OFF_REQ will go

high (Request to turn OFF). This output should be

connected to an interrupt pin to signal the CPU core that a

request to shut down power has been initiated. The

firmware can then perform all of its shut down

housekeeping duties before shutting down V_DD.

TBUS(3:0)

IO

Trace bus signals for ICE.

0

1

2

3

50

46

44

41

Rev. 1.4

9

73S1210F Data Sheet

DS_1210F_001

Pin Name

Description

RXTX

ERST

ISBR

43

38

3

27

23

IO

I

ICE control.

TCLK

ANA_IN

39

15

24

AI

Figure 38 Analog input pin. This signal goes to a programmable

comparator and is used to sense the value of an external

voltage.

SEC

2

I

Figure 37 Input pin for use in programming security fuse. It should be

connected to ground when not in use.

TEST

LED0

51

4

32

5

DI

IO

Figure 37 Test pin, should be connected to ground

Figure 36 Special output driver, programmable pull-down current to

drive LED. May also be used as an input.

VDD

N/C

68

28

40

3

16

25

PSO

V_DDsupply output pin. A 0.1µF capacitor is recommended

at each VDD pin.

7

8

No connect.

26

27

GND

9

2

8

15

26

GND

General ground supply pins for all IO and logic circuits.

25

42

67

RESET

1

4

I

Figure 32 Reset input, positive assertion. Resets logic and registers

to default condition. Note: to insure proper reset operation

after V_DDis turned on by application of V_BUSpower or

activation of the ON/OFF switch, external reset circuitry

must generate a proper reset signal to the 73S1210F. This

can be accomplished via a simple RC network.

* See the figures in the Equivalent Circuits section.

10

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.2 Hardware Overview

The 73S1210F single smart card controller integrates all primary functional blocks required to implement

a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up

to one instruction per clock cycle (80515), a fully integrated IS0 7816 compliant smart card interface,

expansion smart card interface, serial interface, I2C interface, 6 x 5 keypad interface, RAM, FLASH

memory, and a variety of I/O pins.

The power management circuitry provides a 3.3V voltage output (VDD, pin #68) that must be connected

to the power supply inputs of the digital core of the circuit, pins # 28 and 40 (these are not internally

connected). Should external circuitry require a 3.3V digital power supply, the VDD output is capable of

supplying additional current.

Figure 1 shows a functional block diagram of the 73S1210F.

1.3 80515 MPU Core

1.3.1 80515 Overview

The 73S1210F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one

clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution

of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most

of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)

improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.

Actual processor clocking speed can be adjusted to the total processing demand of the application

(cryptographic calculations, key management, memory management, and I/O management) using the

XRAM special function register MPUCKCtl.

Typical smart card, serial, keyboard and I2C management functions are available for the MPU as part of

the Teridian standard library. A standard ANSI “C” 80515-application programming interface library is

available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.

1.3.2 Memory Organization

The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.

Memory organization in the 80515 is similar to that of the industry standard 8051. There are three

memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory

(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2

Table 2: MPU Data Memory Map

Address

(hex)

Memory

Technology

Memory Size

(bytes)

Memory Type

Typical Usage

0000-7FFF

0000-07FF

FC00-FFFF

Flash Memory

Static RAM

Non-volatile

Volatile

Program and non-volatile data

MPU data XRAM

32KB

2KB

1KB

External SFR

Volatile

Peripheral control

Note: The IRAM is part of the core and is addressed differently.

Program Memory: The 80515 can address up to 32KB of program memory space from 0x0000 to

0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.

After reset, the MPU starts program execution from location 0x0000. The lower part of the program

memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting

from 0x0003. Reset is located at 0x0000.

Flash Memory: The program memory consists of flash memory. The flash memory is intended to

primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to

Rev. 1.4

11

73S1210F Data Sheet

DS_1210F_001

specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent

inadvertent erasure of the flash memory.

The mass erase sequence is:

1. Write 1 to the FLSH_MEEN bit in the FLSHCTL register (SFR address 0xB2[1]).

2. Write pattern 0xAA to ERASE (SFR address 0x94).

Note: The mass erase cycle can only be initiated when the ICE port is enabled.

The page erase sequence is:

1. Write the page address to PGADDR (SFR address 0xB7[7:1]).

2. Write pattern 0x55 to ERASE (SFR address 0x94).

The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and

there are 128 pages within the flash memory. The PGADDR denotes the upper seven bits of the flash

memory address such that bit 7:1 of the PGADDR corresponds to bit 15:9 of the flash memory address.

Bit 0 of the PGADDR is not used and is ignored. The MPU may write to the flash memory. This is one of

the non-volatile storage options available to the user. The FLSHCTL SFR bit FLSH_PWE (flash program

write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM

writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows

the location and description of the 73S1210 flash-specific SFRs.

Any flash modifications must set the CPUCLK to operate at 3.6923 MHz (MPUCLKCtl = 0x0C)

before any flash memory operations are executed to insure the proper timing when modifying the

flash memory.

12

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Table 3: Flash Special Function Registers

Description

Register

SFR

R/W

Address

ERASE

0x94

W

This register is used to initiate either the Flash Mass Erase cycle or the

Flash Page Erase cycle. Specific patterns are expected for ERASE in

order to initiate the appropriate Erase cycle (default = 0x00).

0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write

to PGADDR @ SFR 0xB7.

0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write

to FLSH_MEEN @ SFR 0xB2 and the debug port must be

enabled.

Any other pattern written to ERASE will have no effect.

PGADDR

FLSHCTL

0xB7

0xB2

R/W Flash Page Erase Address register containing the flash memory page

address (page 0 through 127) that will be erased during the Page Erase

cycle (default = 0x00). Note: the page address is shifted left by one bit

(see detailed description above).

Must be re-written for each new Page Erase cycle.

R/W Bit 0 (FLSH_PWE): Program Write Enable:

0 – MOVX commands refer to XRAM Space, normal operation (default).

1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.

This bit is automatically reset after each byte written to flash. Writes to

this bit are inhibited when interrupts are enabled.

W

Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default).

1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash

memory and CE program RAM. This bit is reset on chip reset and may

only be set. Attempts to write zero are ignored.

Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory.

The internal data memory address is always one byte wide and can be accessed by either direct or

indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is

available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal

RAM.

The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form

four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which

bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addresses 0x00-

0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 4

shows the internal data memory map.

Rev. 1.4

13

73S1210F Data Sheet

DS_1210F_001

Table 4: Internal Data Memory Map

Address

Direct Addressing

Indirect Addressing

RAM

0xFF

0x80

0x7F

0x30

0x2F

0x20

0x1F

0x00

Special Function

Registers (SFRs)

Byte-addressable area

Byte or bit-addressable area

Register banks R0…R7 (x4)

External Data Memory: While the 80515 can address up to 64KB of external data memory in the space

from 0x0000 to 0xFFFF, only the memory ranges shown in Figure 2 contain physical memory. The

80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A

instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR

instruction.

There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect

address to the external data RAM.

In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight

lower-ordered bits of address. This method allows the user access to the first 256 bytes of the 2KB of

external data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer

generates a sixteen-bit address.

14

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Address

0xFFFF

0XFF80

0xFF7F

0XFE00

0xFBFF

Use

Peripheral Control

Registers (128b)

Smart Card Control

(384b)

Address

0x7FFF

Use

–

0x0800

0x07FF

Use

Address

Indirect Access Direct Access

0xFF

0x80

0x7F

0x48

0x47

0x20

0x1F

0x18

0x17

0x10

0x0F

0x08

0x07

0x00

Byte RAM

SFRs

Byte RAM

Flash

Program

Memory

32K

Bit/Byte RAM

XRAM

Bytes

Register bank 3

Register bank 2

Register bank 1

Register bank 0

0x0000

Program Memory

0x0000

External Data Memory

Figure 2: Memory Map

Internal Data Memory

Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a

16-bit register that is used to address external memory. In the 80515 core, the standard data pointer is

called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active

pointer. The data pointer select bit is located at the LSB of the DPS IRAM special function register

(DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1.

The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related

instructions use the currently selected DPTR for any activity.

The second data pointer may not be supported by certain compilers.

Rev. 1.4

15

73S1210F Data Sheet

DS_1210F_001

1.4 Program Security

Two levels of program and data security are available. Each level requires a specific fuse to be blown in

order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE bit

(bit 6 of SFR register FLSHCTL 0xB2). Mode 0 limits the ICE interface to only allow bulk erase of the

flash program memory. All other ICE operations are blocked. This guarantees the security of the user’s

MPU program code. Security (Mode 0) is enabled by MPU code that sets the SECURE bit. The MPU

code must execute the setting of the SECURE bit immediately after a reset to properly enable Mode 0.

This should be the first instruction after the reset vector jump has been executed. If the “startup.a51”

assembly file is used in an application, then it must be modified to set the SECURE bit after the reset

vector jump. If not using “startup.a51”, then this should be the first instruction in main(). Once security

Mode 0 is enabled, the only way to disable it is to perform a global erase of the flash followed by a full

circuit reset. Once the flash has been erased and the reset has been executed, security Mode 0 is

disabled and the ICE has full control of the core. The flash can be reprogrammed after the bulk erase

operation is completed. Global erase of the flash will also clear the data XRAM memory.

The security enable bit (SECURE) is reset whenever the MPU is reset. Hardware associated with the bit

only allows it to be set. As a result, the code may set the SECURE bit to enable the security Mode 0

feature but may not reset it. Once the SECURE bit is set, the code is protected and no external read of

program code in flash or data (in XRAM) is possible. In order to invoke the security Mode 0, the

SECSET0 (bit 1 of the XRAM SFR register SECReg 0xFFD7) fuse must be blown beforehand or the

security mode 0 will not be enabled. The SECSET0 and SECSET1 fuses once blown, cannot be

overridden.

Specifically, when SECURE is set:

•

The ICE is limited to bulk flash erase only.

Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-

erased by either MPU or ICE. Page zero may only be erased with global flash erase. Note that

global flash erase erases XRAM whether the SECURE bit is set or not.

•

Writes to page zero, whether by MPU or ICE, are inhibited.

Security mode 1 is in effect when the SECSET1 fuse has been programmed (blown open). In security

mode 1, the ICE is completely and permanently disabled. The Flash program memory and the MPU are

not available for alteration, observation, nor control. As soon as the fuse has been blown, the ICE is

disabled. The testing of the SECSET1 fuse will occur during the reset and before the start of pre-boot

and boot cycles. This mode is not reversible, nor recoverable. In order to blow the SECSET1 fuse, the

SEC pin must be held high for the fuse burning sequence to be executed properly. The firmware can

check to see if this pin is held high by reading the SECPIN bit (bit 5 of XRAM SFR register SECReg

0xFFD7). If this bit is set and the firmware desires, it can blow the SECSET1 fuse. The burning of the

SECSET0 does not require the SEC pin to be held high.

In order to blow the fuse for SECSET1 and SECSET0, a particular set of register writes in a specific order

need to be followed. There are two additional registers that need to have a specific value written to them

in order for the desired fuse to be blown. These registers are FUSECtl (0xFFD2) and TRIMPCtl

(0xFFD1). The sequence for blowing the fuse is as follows:

1. Write 0x54H to FUSECtl.

2. Write 0x81H for security mode 0.

Write 0x82H for security mode 1.

3. Write 0xA6 to TRIMPCtl.

Note: only program one security mode at a time.

Note: SEC pin must be high for security mode 1.

4. Delay about 500 µs.

5. Write 0x00 to TRIMPCtl and FUSECtl.

16

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Table 5: Program Security Registers

Description

Register

SFR

R/W

Address

FLSHCTL

0xB2

R/W Bit 0 (FLSH_PWE): Program Write Enable:

0 – MOVX commands refer to XRAM Space, normal operation (default).

1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.

This bit is automatically reset after each byte written to flash. Writes to

this bit are inhibited when interrupts are enabled.

W

Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default).

1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash

memory and CE program RAM. This bit is reset on chip reset and may

only be set. Attempts to write zero are ignored.

TRIMPCtl

FUSECtl

SECReg

0xFFD1

0xFFD2

0xFFD7

W

0x54 value will set up for security fuse control. All other values are

reserved and should not be used.

0xA6 value will cause the selected fuse to be blown. All other values

will stop the burning process.

Bit 7 (PARAMSEC):

0 – Normal operation.

1 – Enable permanent programming of the security fuses.

R

Bit 5 (SECPIN):

Indicates the state of the SEC pin. The SEC pin is held low by a

pull-down resistor. The user can force this pin high during boot

sequence time to indicate to firmware that sec mode 1 is desired.

R/W Bit 1 (SECSET1):

See the Program Security section.

R/W Bit 0 (SECSET0):

See the Program Security section.

Rev. 1.4

17

73S1210F Data Sheet

DS_1210F_001

1.5 Special Function Registers (SFRs)

The 73S1210F utilizes numerous SFRs to communicate with the 73S1210Fs many peripherals. This

results in the need for more SFR locations outside the direct address IRAM space (0x80 to 0xFF). While

some peripherals are mapped to unused IRAM SFR locations, additional SFRs for the smart card and

other peripheral functions are mapped to the top of the XRAM data space (0xFC00 to 0xFFFF).

1.5.1 Internal Data Special Function Registers (SFRs)

A map of the Special Function Registers is shown in Table 6.

Table 6: IRAM Special Function Registers Locations

Bin/

Hex

Hex\Bin

X000

X001

X010

X011

X100

X101

X110

X111

F8

F0

E8

E0

D8

D0

C8

C0

B8

B0

A8

A0

98

90

88

80

FF

F7

EF

E7

DF

D7

CF

C7

BF

B7

AF

A7

9F

97

B

A

BRCON

PSW

KCOL

KROW

KSCAN KSTAT KSIZE KORDERL KORDERH

T2CON

IRCON

IEN1

IP1

IP0

S0RELH S1RELH

FLSHCTL

PGADDR

IEN0

S0RELL

S0CON S0BUF

IEN2

DPS

TL0

S1CON S1BUF S1RELL

USR70 UDIR70

ERASE

TH0

TCON

TMOD

SP

TL1

TH1

8F

87

MCLKCtl

DPL

DPH

DPL1

DPH1

WDTREL

PCON

Only a few addresses are used, the others are not implemented. SFRs specific to the 73S1210F are

shown in bold print (gray background). Any read access to unimplemented addresses will return

undefined data, while most write access will have no effect. However, a few locations are reserved and

not user configurable in the 73S1210F. Writes to the unused SFR locations can affect the operation

of the core and therefore must not be written to. This applies to all the SFR areas in both the

IRAM and XRAM spaces. In addition, all unused bit locations within valid SFR registers must be

left in their default (power on default) states.

18

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.5.2 IRAM Special Function Registers (Generic 80515 SFRs)

Table 7 shows the location of the SFRs and the value they assume at reset or power-up.

Table 7: IRAM Special Function Registers Reset Values

Name

SP

Location Reset Value Description

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8F

0x90

0x91

0x92

0x94

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0xA8

0xA9

0xAA

0xB2

0xB7

0xB8

0xB9

0xBA

0xBB

0xC0

0xC8

0xD0

0XD1

0x07

0x00

0x0A

0xFF

0x00

0xD9

0x00

0x03

0x00

0x1F

Stack Pointer

DPL

Data Pointer Low 0

DPH

Data Pointer High 0

DPL1

Data Pointer Low 1

DPH1

WDTREL

PCON

TCON

TMOD

TL0

Data Pointer High 1

Watchdog Timer Reload register

Power Control

Timer/Counter Control

Timer Mode Control

Timer 0, low byte

TL1

Timer 1, high byte

TH0

Timer 0, low byte

TH1

Timer 1, high byte

MCLKCtl

USR70

UDIR70

DPS

Master Clock Control

User Port Data (7:0)

User Port Direction (7:0)

Data Pointer Select Register

Flash Erase

ERASE

S0CON

S0BUF

IEN2

Serial Port 0, Control Register

Serial Port 0, Data Buffer

Interrupt Enable Register 2

Serial Port 1, Control Register

Serial Port 1, Data Buffer

Serial Port 1, Reload Register, low byte

Interrupt Enable Register 0

Interrupt Priority Register 0

Serial Port 0, Reload Register, low byte

Flash Control

S1CON

S1BUF

S1RELL

IEN0

IP0

S0RELL

FLSHCTL

PGADDR

IEN1

Flash Page Address

Interrupt Enable Register 1

Interrupt Priority Register 1

Serial Port 0, Reload Register, high byte

Serial Port 1, Reload Register, high byte

Interrupt Request Control Register

Timer 2 Control

IP1

S0RELH

S1RELH

IRCON

T2CON

PSW

Program Status Word

Keypad Column

KCOL

Rev. 1.4

19

73S1210F Data Sheet

DS_1210F_001

Name

Location Reset Value Description

KROW

KSCAN

KSTAT

KSIZE

0XD2

0XD3

0XD4

0XD5

0x3F

0x00

Keypad Row

Keypad Scan Time

Keypad Control/Status

Keypad Size

KORDERL 0XD6

KORDERH 0XD7

Keypad Column LS Scan Order

Keypad Column MS Scan Order

BRCON

0xD8

0xE0

0xF0

Baud Rate Control Register (only BRCON.7 bit used)

A

B

Accumulator

B Register

1.5.3 External Data Special Function Registers (SFRs)

A map of the XRAM Special Function Registers is shown in Table 8. The smart card registers are listed

separately in Table 107.

Table 8: XRAM Special Function Registers Reset Values

Name

DAR

Location Reset Value Description

0x FF80 0x00

0x FF81 0x00

0x FF82 0x00

0x FF83 0x00

0x FF84 0x00

0x FF85 0x00

Device Address Register (I²C)

WDR

SWDR

RDR

Write Data Register (I²C)

Secondary Write Data Register (I²C)

Read Data Register (I²C)

Secondary Read Data Register (I²C)

Control and Status Register (I²C)

External Interrupt Control 1

External Interrupt Control 2

External Interrupt Control 3

External Interrupt Control 4

External Interrupt Control 5

External Interrupt Control 6

MPU Clock Control

SRDR

CSR

USRIntCtl1 0x FF90 0x00

USRIntCtl2 0x FF91 0x00

USRIntCtl3 0x FF92 0x00

USRIntCtl4 0x FF93 0x00

INT5Ctl

INT6Ctl

0x FF94 0x00

0x FF95 0x00

MPUCKCtl 0x FFA1 0x0C

ACOMP

TRIMPCtl

FUSECtl

VDDFCtl

SECReg

MISCtl0

MISCtl1

LEDCtl

0x FFD0 0x00

0x FFD1 0x00

0x FFD2 0x00

0x FFD4 0x00

0x FFD7 0x00

0x FFF1 0x00

0x FFF2 0x10

0x FFF3 0xFF

Analog Compare Register

TRIM Pulse Control

FUSE Control

VDDFault Control

Security Register

Miscellaneous Control Register 0

Miscellaneous Control Register 1

LED Control Register

Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold

the operand. The mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC.

B Register: The B register is used during multiply and divide instructions. It can also be used as a

scratch-pad register to hold temporary data.

20

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Program Status Word (PSW):

Table 9: PSW Register

MSB

LSB

P

CV

AC

F0

RS1

RS

OV

–

Bit

Symbol

Function

PSW.7

PSW.6

PSW.5

PSW.4

CV

AC

Carry flag.

Auxiliary Carry flag for BCD operations.

General purpose Flag 0 available for user.

F0

RS1

Register bank select control bits. The contents of RS1 and RS0 select the

working register bank:

RS1/RS0

Bank Selected

Bank 0

Location

00

01

10

11

(0x00 – 0x07)

(0x08 – 0x0F)

(0x10 – 0x17)

(0x18 – 0x1F)

PSW.3

RS0

Bank 1

Bank 2

Bank 3

PSW.2

PSW.1

PSW.0

OV

F1

P

Overflow flag.

General purpose Flag 1 available for user.

Parity flag, affected by hardware to indicate odd / even number of “one” bits

in the Accumulator, i.e. even parity.

Stack Pointer: The stack pointer (SP) is a 1-byte register initialized to 0x07 after reset. This register is

incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08.

Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH.

It can be loaded as a 2-byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It

is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR

respectively).

Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This

register is incremented during the fetching operation code or when operating on data from program

memory. Note: The program counter is not mapped to the SFR area.

Port Registers: The I/O ports are controlled by Special Function Register USR70. The contents of the

SFR can be observed on corresponding pins on the chip. Writing a 1 to any of the ports (see Table 10)

causes the corresponding pin to be at high level (3.3V), and writing a 0 causes the corresponding pin to

be held at low level (GND). The data direction register UDIR70 define individual pins as input or output

pins (see the User (USR) Ports section for details).

Table 10: Port Registers

SFR

Register

R/W

Description

Address

USR70

0x90

R/W Register for User port bit 7:0 read and write operations (pins USR0…

USR7).

UDIR70

Rev. 1.4

0x91

R/W Data direction register for User port bits 0:7. Setting a bit to 0 means

that the corresponding pin is an output.

21

73S1210F Data Sheet

DS_1210F_001

All ports on the chip are bi-directional. Each consists of a Latch (SFR ‘USR70’), an output driver, and an

input buffer, therefore the MPU can output or read data through any of these ports if they are not used for

alternate purposes.

1.6 Instruction Set

All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set

and of the associated op-codes is contained in the 73S12xxF Software User’s Guide.

1.7 Peripheral Descriptions

1.7.1 Oscillator and Clock Generation

The 73S1210F has one oscillator circuit for the main CPU clock. The main oscillator circuit is designed to

operate with various crystal or external clock frequencies. An internal divider working in conjunction with a

PLL and VCO provides a 96MHz internal clock within the 73S1210F. 96 MHz is the recommended

frequency for proper operation of specific peripheral blocks such as the specific timers, ISO 7816 UART

and interfaces, Step-up converter, and keypad. The clock generation and control circuits are shown in

Figure 3.

MCount(2:0)

M DIVIDER

12.00MHz

/(2*N + 4)

KEYCLK

1kHz

DIVIDER

/93760

HOSCen

MCLK

96MHz

X12IN

Phase

Freq

DET

HIGH

XTAL

OSC

VCO

HCLK

12.00MHz

X12OUT

CPU CLOCK

DIVIDER

6 bits

1.5-48MHz

7.386MHz

ICLK

7.386MHz

CPUCKDiv

MPU CLOCK - CPCLK

3.6923MHz

I2CCLK

DIVIDE

by 120

400kHz

I2C_2x

800kHz

CLK1M

DIVIDE

by 96

1MHz

SMART CARD LOGIC

BLOCK CLOCK

SCCLK

SC/SCE

CLOCK

Prescaler 6bits

SEL

ETU CLOCK

ETUCLK

SCECLK

SCLK

CLOCK

Prescaler 6bits

DIVIDER

12 bits

SELSC

See SC Clock descriptions for more accurate diagram

SCCKenb

Figure 3: Clock Generation and Control Circuits

22

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

The master clock control register enables different sections of the clock circuitry and specifies the value

of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper

operation of some of the peripheral blocks according to the following formula:

MCLK = (Mcount * 2 + 4) * F_XTAL= 96MHz

Mcount is configured in the MCLKCtl register must be bound between a value of 1 to 10. The possible

crystal or external clock frequencies for getting MCLK = 96MHz are shown in Table 11.

Table 11: Frequencies and Mcount Values for MCLK = 96MHz

F

_XTAL(MHz)

12.00

9.60

Mcount (N)

2

3

4

5

6

8.00

6.86

6.00

Master Clock Control Register (MCLKCtl): 0x8F  0x0A

The MPU clock that drives the CPU core defaults to 3.6923MHz after reset. The MPU clock is scalable

by configuring the MPU Clock Control register.

Table 12: The MCLKCtl Register

MSB

LSB

MCT.2 MCT.1 MCT.0

HSOEN KBEN SCEN

–

Bit

Symbol

Function

High-speed oscillator disable. When set = 1, disables the high-speed

crystal oscillator and VCO/PLL system. Do not set this bit = 1.

MCLKCtl.7

HSOEN

MCLKCtl.6

MCLKCtl.5

MCLKCtl.4

MCLKCtl.3

MCLKCtl.2

MCLKCtl.1

KBEN

SCEN

–

1 = Disable the keypad logic clock.

1 = Disable the smart card logic clock.

–

MCT.2

MCT.1

This value determines the ratio of the VCO frequency (MCLK) to the

high-speed crystal oscillator frequency such that:

MCLK = (MCount*2 + 4)* F_XTAL. The default value is MCount = 2h such

that MCLK = (2*2 + 4)*12.00MHz = 96MHz.

MCLKCtl.0

MCT.0

Rev. 1.4

23

73S1210F Data Sheet

DS_1210F_001

MPU Clock Control Register (MPUCKCtl): 0xFFA1  0x0C

Table 13: The TCON Register

MSB

LSB

–

MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0

Bit

Symbol

Function

MPUCKCtl.7

–

MPUCKCtl.6

MPUCKCtl.5

MPUCKCtl.4

MPUCKCtl.3

MPUCKCtl.2

MPUCKCtl.1

MPUCKCtl.0

–

MDIV.5

MDIV.4

MDIV.3

MDIV.2

MDIV.1

MDIV.0

This value determines the ratio of the MPU master clock frequency to the

VCO frequency (MCLK) such that

MPUClk = MCLK/(2 * (MPUCKDiv(5:0) + 1)).

Do not use values of 0 or 1 for MPUCKDiv(n).

Default is 0Ch to set CPCLK = 3.6923MHz.

The oscillator circuits are designed to connect directly to standard parallel resonant crystal in a Pierce

oscillator configuration. Each side of the crystal should include a 22pF capacitor to ground for both

oscillator circuits and a 1MΩ resistor is required across the 12MHz crystal.

73S1210F

1MΩ

12MHz

22pF

Note: The crystal should be placed as close as possible to the IC, and vias should be avoided.

Figure 4: Oscillator Circuit

24

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.2 Power Supply Management

The detailed power supply management logic block diagram is shown in Figure 5.

V_BUS

+

-

V_BUSTH

NO

NC

VPC

V_BAT

DC-DC

Converter

SET

CLR

EN

/ Pass

S

R

Q

Through*

LIN

VP

*Pass Through -> VP = VPC

SET

CLR

D

Q

ON_OFF

Debounce

Circuit

OFF_REQ

INT

INT3

VP

Delay

Circuit

(POR)

MPU

PWRDN*

*PWRDN bit in MISCtl0

Pass Through

Mode Enable

VCC Voltage

Select

Smart

Card

Power

VCC

VDD

VCC

Regulator

VCC Enable

Power

Control

To optional

external

VDD

circuits

Regulator

20mA max.

VDD to

Internal

Circuits

Figure 5: Detailed Power Management Logic Block Diagram

The 73S1210F contains a power supply and converter circuit that takes power from any one of three

sources; V_PC, V_BUS, or V_BAT

.

V_PCis specified to range from 2.7 to 6.5 volts. It can typically be supplied by a single cell battery with a

voltage range of 2.7 to approximately 3.1 volts or by a standard supply of 3.3 or 5 volts.

V_BUSis typically supplied by an external power supply and ranges in value from 4.4 to 5.5 volts (6.5V maximum).

Rev. 1.4

25

73S1210F Data Sheet

DS_1210F_001

V_BATis expected to be supplied from a battery of three to four series connected cells with a voltage value

of 4.0 to 6.5 volts.

V_BATand V_BUSare internally switched to V_PCby two separate FET switches configured as a SPDT switch

(break-before-make). They will not be enabled at the same time. V_BUSis automatically selected in lieu of

V_BATwhen V_BUSis present (i.e. V_BUSalways has the priority).

If V_PCis provided and either V_BATor V_BUSis also used, the source of V_PCmust be diode isolated from the

V_PCpin to prevent current flow from V_BATor V_BUSinto the V_PCsource.

The power that is supplied to the V_PCpin (externally or internally, i.e. through V_BATor V_BUS– see above) is

up-converted to the intermediate voltage V_Putilizing an inductive, step-up converter. A series power

inductor (nominal value = 10 µH) must be connected from V_PCto the pin LIN, and a 10µF low ESR filter

capacitor must be connected to V_PC.

V_Prequires a 4.7µF filter capacitor and will have a nominal value of 5.5 volts during normal operation. V_P

is used internally by the smart card electrical interface circuit and is regulated to the desired smart card

supply V_CCvoltage (can be programmed for values of 5V, 3V, or 1.8V).

V_Pis also used internally to generate a 3.3V nominal, regulated power supply V_DD. V_DDis output on pin

68 and must be directly tied to all other V_DDpins on the 73S1210F (pins 28 and 40). V_DDpowers all the

digital logic, input/output buffering, and analog functions. It can also be used for external circuitry: up to

20mA current can be supplied to external devices simultaneously to the 73S1210F’s digital core

maximum consumption.

1.7.3 Power ON/OFF

The 73S1210F features an ON_OFF input pin for a momentary contact, main-system ON/OFF switch. The

purpose of this switch is to place the circuit in a very low-power mode – the “OFF” mode – where all circuits

are no longer powered, therefore allowing the lowest possible current consumption.

When in “OFF” mode, an action on the ON/OFF switch will turn-on the power supply of the digital core

(V_DD) and apply a power-on-reset condition. Alternatively, entering the “OFF” mode from the “ON” mode

requires firmware action.

When in “ON” mode, an action on the ON/OFF switch will send a request to the controller that will have to

be acknowledged (firmware action required) in order to enter the “OFF” state.

When placed into the “OFF” state, the 73S1210F will consume minimum current from V_PCand V_BAT; V_P

and V_DDwill be unavailable (V_DDout = 0V and V_P= 0V).

When in “ON” mode, the 73S1210F will operate normally, with all the features described in this document

available. V_Pand V_DDwill be available (V_DDout = 3.3V and V_P= 5.5V nominal).

Whenever V_BUSpower is supplied, the circuit will be automatically in the “ON” state. The functions of the

ON/OFF switch and circuitry are overridden and the 73S1210F is in the “ON” state with V_Pand V_DDavailable.

Without V_BUSapplied, the circuit is by default in the “OFF” state, and will respond only to the ON_OFF pin.

The ON_OFF pin should be connected to an SPST switch to ground. If the circuit is OFF and the switch

is closed for a debounce period of 50-100ms, the circuit will go into the “ON” state wherein all functions

are operating in normal fashion. If the circuit is in the “ON” state and the ON/OFF pin is connected to

ground for a period greater than the debounce period, OFF_REQ will be asserted high and held

regardless of the state of ON/OFF. The OFF_REQ signal should be connected to one of the interrupt

pins to signal the CPU core that a request to shutdown has been initiated. The firmware will

acknowledge this request by setting the SCPWRDN bit in the Smart Card V_CCControl/Status Register

(VccCtl) high after it has completed all shutdown activities. When SCPWRDN is set high, the circuit will

deactivate the smart card interface if required and turn off all analog functions and the V_DDsupply for the

logic and companion circuits. The default state upon application of power is the “OFF” state unless

power is supplied to the V_BUSsupply. Note that at any time, the firmware may assert SCPWRDN and the

26

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

73S1210F will go into the “OFF” state (when V_BUSis not present). If the ON/OFF switch function is not

desired and the application does not need to shut down power on VDD, the ON_OFF input can be

permanently grounded which will automatically turn on VDD when power is supplied on any of the VPC,

VBAT or VBUS power supply inputs.

If power is applied to both V_BATand V_BUS, the circuit will automatically consume power from only the V_BUS

source. The 73S1210F will be unconditionally “ON” when V_BUSis applied. If the V_BUSsource is removed,

the 73S1210F will switchover to the VBAT input supply and remain in the “ON” state. The firmware

should assert SCPWRDN based on no activity or V_BUSremoval to reduce battery power consumption.

When operating from V_BUS, and not calling for V_CC, the step-up converter becomes a simple switch

connecting V_BUSto V_Pin order to save power.

Note: When the ON_OFF switch function is not needed, i.e. when the 73S1210F must be in an always-ON

state when using another supply than VBUS (V_PCor V_BAT), some external discrete components are needed.

1.7.4 Power Control Modes

The 73S1210F contains circuitry to disable portions of the device and place it into a lower power standby

mode or power down the 73S1210F into its “OFF” mode. The standby mode will stop the core, clock

subsystem and the peripherals connected to it. This is accomplished by either shutting off the power or

disabling the clock going to the block. The Miscellaneous Control registers MISCtl0, MISCtl1 and the

Master Clock Control register (MCLKCtl) provide control over the power modes. The PWRDN bit in

MISCtl0 will setup the 73S1210F for standby or “OFF” modes. Depending on the state of the ON/OFF

circuitry and power applied to the VBUS input, the 73S1210F will go into either standby mode or power

“OFF” mode. If system power is provided by, VBUS or the ON/OFF circuitry is in the “ON” state, the MPU

core will placed into standby mode. If the VBUS input is not sourcing power and the ON/OFF circuitry is

in the “OFF” state, setting the PWRDN bit will shut down the converter and VP will turn off. The power

down mode should only be initiated by setting the PWRDN bit in the MISCtl0 register and not by

manipulating individual control bits in various registers. Figure 6 shows how the PWRDN bit controls the

various functions that comprise power down state.

Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the PWRDN

bit to the assertion of the PWRDN Signal (32 MPU clocks). Refer to the Power Down sequence diagram.

PWRDN Signal

MISCtl0 - PWRDN

Analog functions

(VCO, PLL,

reference and bias

circuits, etc.)

VDDFCtl - VDDFEN

VDDFAULT

+

ANALOG

COMPARE

ACOMP - CMPEN

+

High Speed OSC

+

MCLCKCtl - HOSEN

Smart Card Power

+

SCVCCCtl - SCPRDN

Flash Read Pulse

one-shot circuit

+

MISCtl1 - FRPEN

These are the block

references.

These are the registers and

the names of the control bits.

Figure 6: Power Down Control

Rev. 1.4

27

73S1210F Data Sheet

DS_1210F_001

When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the

program to set the STOP bit in the PCON register. This delay will enable the program to properly halt the

core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias

circuitry, etc.). The PDMUX bit in SFR INT5Ctl should be set prior to setting the PWRDN bit in order to

configure the wake up interrupt logic. The power down mode is de-asserted by any of the interrupts

connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Keypad). These interrupt

sources are OR’ed together and routed through some delay logic into INT0 to provide this functionality.

The interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After

the clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When

the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 7

shows the detailed logic for waking up the 73S1210F from a power down state using these specific

interrupt sources. Figure 8 shows the timing associated with the power down mode.

PDMUX

(FF94h:bit7)

USR0

USR1

USR[7:0] Control

MPU

INT0

USR2

USR3

USR4

USR5

USR6

USR7

0

1

USRxINTSrc set to

4(ext INT0 high)

or

6(ext INT0 low)

INT4

INT5

CE

TC

9 BIT CNTR

CLR

RESETB

PWRDN

(FFF1h:bit7)

D

Q

PWRDN_analog

CLR

TC

CE

RESETB

5 BIT CNTR

Notes:

CLR

1. The counters are clocked by the MPUCLK

2. TC - Terminal count (high at overflow)

3. CE - Count enable

RESETB

Figure 7: Detail of Power Down Interrupt Logic

28

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

text

t0

PWRDN BIT

t1

PWRDN SIG

EXT. EVENT

t4

t6

INT0 to MPU

MPU STOP

t7

t2

ANALOG Enable

t3

t5

PLL CLOCKS

t0: MPU sets PWRDN bit.

t1: 32 MPU clock cycles after t0, the PWRDN SIG is asserted, turning all analog functions OFF.

t2: MPU executes STOP instruction, must be done prior to t1.

t3: Analog functions go to OFF condition. No Vref, PLL/VCO, Ibias, etc.

text: An external event (RTC, Keypad, Card event, USB) occurs.

t4: PWRDN bit and PWRDN signal are cleared by external event.

t5: High-speed oscillator/PLL/VCO operating.

t6: After 512 MPU clock cycles, INT0 to MPU is asserted.

t7: INT0 causes MPU to exit STOP condition.

Figure 8: Power Down Sequencing

Rev. 1.4

29

73S1210F Data Sheet

DS_1210F_001

External Interrupt Control Register (INT5Ctl): 0xFF94  0x00

Table 14: The INT5Ctl Register

MSB

LSB

KPIEN KPINT

PDMUX

–

Bit

Symbol

Function

When set = 1, enables interrupts from Keypad (normally going to int5),

Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to

cause interrupt on int0. The assertion of the interrupt to int0 is delayed by

512 MPU clocks to allow the analog circuits, including the clock system, to

stabilize. This bit must be set prior to asserting the PWRDN bit in order to

properly configure the interrupts that will wake up the circuit. This bit is

reset = 0 when this register is read.

INT5Ctl.7

PDMUX

INT5Ctl.6

INT5Ctl.5

INT5Ctl.4

INT5Ctl.3

INT5Ctl.2

INT5Ctl.1

INT5Ctl.0

–

KPIEN

KPINT

Keypad interrupt enable.

Keypad interrupt flag.

Miscellaneous Control Register 0 (MISCtl0): 0xFFF1  0x00

Table 15: The MISCtl0 Register

MSB

LSB

SLPBK SSEL

PWRDN

–

Bit

Symbol

Function

This bit sets the circuit into a low-power condition. All analog (high-speed

oscillator and VCO/PLL) functions are disabled 32 MPU clock cycles after

this bit is set = 1. This allows time for the next instruction to set the STOP

bit in the PCON register to stop the CPU core. The MPU is not operative in

this mode. When set, this bit overrides the individual control bits that

otherwise control power consumption.

MISCtl0.7

PWRDN

MISCtl0.6

MISCtl0.5

MISCtl0.4

MISCtl0.3

MISCtl0.2

MISCtl0.1

MISCtl0.0

–

SLPBK

SSEL

UART loop back testing mode.

Serial port pins select.

30

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Miscellaneous Control Register 1 (MISCtl1): 0xFFF2  0x10

Table 16: The MISCtl1 Register

MSB

LSB

–

FRPEN FLSH66

–

Bit

Symbol

Function

MISCtl1.7

MISCtl1.6

–

Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is

passed through with no change. When FRPEN = 0 a one-shot circuit that

shortens the Flash Read signal is enabled to save power. The Flash Read

pulse will shorten to 40 or 66ns (approximate based on the setting of the

FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock

frequencies greater than 10MHz, this bit should be set high.

MISCtl1.5

FRPEN

When high, creates a 66ns Flash read pulse, otherwise creates a 40ns

read pulse when FRPEN is set.

MISCtl1.4

FLSH66

MISCtl1.3

MISCtl1.2

MISCtl1.1

MISCtl1.0

–

Master Clock Control Register (MCLKCtl): 0x8F  0x0A

Table 17: The MCLKCtl Register

MSB

LSB

MCT.2 MCT.1 MCT.0

HSOEN KBEN

SCEN

–

Bit

Symbol

Function

High-speed oscillator enable. When set = 1, disables the high-speed

crystal oscillator and VCO/PLL system. This bit is not changed when the

PWRDN bit is set but the oscillator/VCO/PLL is disabled.

MCLKCtl.7

MCLKCtl.6

MCLKCtl.5

HSOEN*

KBEN

1 = Disable the keypad logic clock. This bit is not changed in PWRDN

mode but the function is disabled.

1 = Disable the smart card logic clock. This bit is not changed in PWRDN

mode but the function is disabled. Interrupt logic for card insertion/removal

remains operable even with smart card clock disabled.

SCEN

MCLKCtl.4

MCLKCtl.3

MCLKCtl.2

MCLKCtl.1

–

MCT.2

MCT.1

This value determines the ratio of the VCO frequency (MCLK) to the

high-speed crystal oscillator frequency such that:

MCLK = (MCount*2 + 4)*Fxtal. The default value is MCount = 2h such

that MCLK = (2*2 + 4)*12.00MHz = 96MHz.

MCLKCtl.0

MCT.0

*Note: The HSOEN bit should never be set under normal circumstances. Power down control should

only be initiated via use of the PWRDN bit in MISCtl0.

Rev. 1.4

31

73S1210F Data Sheet

DS_1210F_001

Power Control Register 0 (PCON): 0x87  0x00

The SMOD bit used for the baud rate generator is set up via this register.

Table 18: The PCON Register

MSB

LSB

IDLE

SMOD

–

GF1

GF0

STOP

Bit

Symbol

Function

PCON.7

PCON.6

PCON.5

PCON.4

PCON.3

PCON.2

PCON.1

PCON.0

SMOD

–

If SM0D = 1, the baud rate is doubled.

–

GF1

GF0

STOP

IDLE

General purpose flag 1.

Sets CPU to Stop mode.

Sets CPU to Idle mode.

32

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.5 Interrupts

The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request

flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the

corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and

IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.

These are described in more detail in the respective sections.

External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of

the 73S1210F, for example the USR I/O, smart card interface, analog comparators, etc. The external

interrupt configuration is shown in Figure 9.

PDMUXCtl

Clear PWRDN bit

USR0

USR1

t0

USR2

USR

0

1

int0

USR

Int

USR3

USR4

USR5

USR6

USR7

USR

Pads

USR

Int

Ctl

Int

Ctl

t1

Ctl

int1

+

Delay

int2

int3

INT2

INT3

INT

Pads

Card_Det

VCC_OK

CRDCtl

Wait Timeout

Card Event

VCC_TMR

RxData

+

SCInt

SCIE

int4

TX_Event

Tx_Sent

TX_Error

RX_Error

MPU

CORE

VccCTL

During STOP, IDLE

when PWRDN bit is set

INT5

Ctl

KeyPad

int5

int6

2

I C

INT6

Ctl

VDD_Fault

Analog

Comp

Serial

Ch 0

SerChan 0 int

SerChan 1 int

Serial

Ch 1

Figure 9: External Interrupt Configuration

Rev. 1.4

33

73S1210F Data Sheet

1.7.5.1 Interrupt Overview

DS_1210F_001

When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 32. Once

the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt

service is terminated by a return from the RETI instruction. When a RETI is performed, the processor will

return to the instruction that would have been next when the interrupt occurred.

When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is

set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per

machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt

when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the

interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address.

Interrupt response will require a varying amount of time depending on the state of the MPU when the

interrupt occurs. If the MPU is performing an interrupt service with equal or greater priority, the new

interrupt will not be invoked. In other cases, the response time depends on the current instruction. The

fastest possible response to an interrupt is 7 machine cycles. This includes one machine cycle for

detecting the interrupt and six cycles to perform the LCALL.

1.7.5.2

Interrupt Enable 0 Register (IEN0): 0xA8  0x00

Table 19: The IEN0 Register

Special Function Registers for Interrupts

MSB

EAL

LSB

EX0

WDT

–

ES0

ET1

EX1

ET0

Bit

Symbol

EAL

WDT

–

Function

IEN0.7

IEN0.6

IEN0.5

IEN0.4

IEN0.3

IEN0.2

IEN0.1

IEN0.0

EAL = 0 – disable all interrupts.

Not used for interrupt control.

ES0

ET1

EX1

ET0

EX0

ES0 = 0 – disable serial channel 0 interrupt.

ET1 = 0 – disable timer 1 overflow interrupt.

EX1 = 0 – disable external interrupt 1.

ET0 = 0 – disable timer 0 overflow interrupt.

EX0 = 0 – disable external interrupt 0.

34

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Interrupt Enable 1 Register (IEN1): 0xB8  0x00

Table 20: The IEN1 Register

MSB

LSB

–

SWDT

EX6

EX5

EX4

EX3

EX2

Bit

Symbol

Function

IEN1.7

IEN1.6

IEN1.5

IEN1.4

IEN1.3

IEN1.2

IEN1.1

IEN1.0

–

SWDT Not used for interrupt control.

EX6

EX5

EX4

EX3

EX2

–

EX6 = 0 – disable external interrupt 6.

EX5 = 0 – disable external interrupt 5.

EX4 = 0 – disable external interrupt 4.

EX3 = 0 – disable external interrupt 3.

EX2 = 0 – disable external interrupt 2.

Interrupt Enable 2 Register (IEN2): 0x9A  0x00

Table 21: The IEN2 Register

MSB

LSB

ES1

–

Bit

Symbol

Function

IEN2.0

ES1

ES1 = 0 – disable serial channel interrupt.

Rev. 1.4

35

73S1210F Data Sheet

DS_1210F_001

Timer/Counter Control Register (TCON): 0x88  0x00

Table 22: The TCON Register

MSB

TF1

LSB

IT0

TR1

TF0

TR0

IE1

IT1

IE0

Bit

Symbol

Function

TCON.7

TCON.6

TCON.5

TCON.4

TCON.3

TF1

TR1

TF0

TR0

IE1

Timer 1 overflow flag.

Not used for interrupt control.

Timer 0 overflow flag.

Not used for interrupt control.

Interrupt 1 edge flag is set by hardware when the falling edge on external

interrupt int1 is observed. Cleared when an interrupt is processed.

TCON.2

TCON.1

TCON.0

IT1

IE0

IT0

Interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for

input pin to cause an interrupt.

Interrupt 0 edge flag is set by hardware when the falling edge on external

interrupt int0 is observed. Cleared when an interrupt is processed.

Interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for input

pin to cause interrupt.

Timer/Interrupt 2 Control Register (T2CON): 0xC8  0x00

Table 23: The T2CON Register

MSB

LSB

–

I3FR

I2FR

–

Bit

Symbol

Function

T2CON.7

–

External interrupt 3 failing/rising edge flag.

T2CON.6

T2CON.5

I3FR

I3FR = 0 external interrupt 3 negative transition active.

I3FR = 1 external interrupt 3 positive transition active.

External interrupt 3 failing/rising edge flag.

I2FR

I2FR = 0 external interrupt 3 negative transition active.

I2FR = 1 external interrupt 3 positive transition active.

T2CON.4

T2CON.3

T2CON.2

T2CON.1

T2CON.0

–

36

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Interrupt Request Register (IRCON): 0xC0  0x00

Table 24: The IRCON Register

MSB

LSB

–

EX6

IEX5

IEX4

IEX3

IEX2

Bit

Symbol

–

Function

IRCON.7

IRCON.6

IRCON.5

IRCON.4

IRCON.3

IRCON.2

IRCON.1

IRCON.0

–

IEX6

IEX5

IEX4

IEX3

IEX2

–

External interrupt 6 flag.

External interrupt 5 flag.

External interrupt 4 flag.

External interrupt 3 flag.

External interrupt 2 flag.

1.7.5.3

External Interrupts

The external interrupts (external to the CPU core) are connected as shown in Table 25. Interrupts with

multiple sources are OR’ed together and individual interrupt source control is provided in XRAM SFRs to

mask the individual interrupt sources and provide the corresponding interrupt flags. Multifunction USR

[7:0] pins control Interrupts 0 and 1. Dedicated external interrupt pins INT2 and INT3 control interrupts 2

and 3. The polarity of interrupts 2 and 3 is programmable in the MPU. Interrupts 4, 5 and 6 have multiple

peripheral sources and are multiplexed to one of these three interrupts. The peripheral functions will be

described in subsequent sections. Generic 80515 MPU literature states that interrupts 4 through 6 are

defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 4, 5 and 6 are

converted to rising edge level by the hardware.

SFR (special function register) enable bits must be set to permit any of these interrupts to occur.

Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically

by the MPU interrupt handler.

Table 25: External MPU Interrupts

External

Connection

Polarity

Flag Reset

Interrupt

0

1

2

3

4

5

6

USR I/O High Priority

USR I/O Low Priority

External Interrupt Pin INT2

External Interrupt Pin INT3

Smart Card Interrupts

Keypad

see USRIntCtlx

Edge selectable

N/A

Automatic

N/A

I²C, V_DD_Fault, Analog Comp

N/A

Note: Interrupts 4, 5 and 6 have multiple interrupt sources and the flag bits are cleared upon reading of

the corresponding register. To prevent any interrupts from being ignored, the register containing multiple

interrupt flags should be stored temporary to allow each interrupt flag to be tested separately to see which

interrupt(s) is/are pending.

Rev. 1.4

37

73S1210F Data Sheet

DS_1210F_001

Table 26: Control Bits for External Interrupts

Enable Bit

EX0

Description

Flag Bit

IE0

Description

External interrupt 0 flag

Enable external interrupt 0

Enable external interrupt 1

Enable external interrupt 2

Enable external interrupt 3

Enable external interrupt 4

Enable external interrupt 5

Enable external interrupt 6

EX1

IE1

External interrupt 1 flag

External interrupt 2 flag

External interrupt 3 flag

External interrupt 4 flag

External interrupt 5 flag

External interrupt 6 flag

EX2

IEX2

IEX3

IEX4

IEX5

IEX6

EX3

EX4

EX5

EX6

1.7.5.4

Power Down Interrupt Logic

The 73S1210F contains special interrupt logic to allow INT0 to wake up the CPU from a power down

(CPU STOP) state. See the Power Control Modes section for details.

1.7.5.5

Interrupt Priority Level Structure

All interrupt sources are combined in groups, as shown in Table 27.

Table 27: Priority Level Groups

Group

0

1

2

3

4

5

External interrupt 0

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

Serial channel 0 interrupt

–

Serial channel 1 interrupt

–

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

Each group of interrupt sources can be programmed individually to one of four priority levels by setting or

clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level

are received simultaneously, an internal polling sequence as per Table 31 determines which request is

serviced first.

IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its

own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler.

Interrupt Priority 0 Register (IP0): 0xA9  0x00

Table 28: The IP0 Register

MSB

LSB

IP0.0

–

WDTS

IP0.5

IP0.4

IP0.3

IP0.2

IP0.1

Note: WDTS is not used for interrupt controls.

38

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Interrupt Priority 1 Register (IP1): 0xB9  0x00

Table 29: The IP1 Register

MSB

LSB

–

IP1.5

IP1.4

IP1.3

IP1.2

IP1.1

IP1.0

Table 30: Priority Levels

IP1.x

IP0.x

Priority Level

0

1

0

1

0

1

Level0 (lowest)

Level1

Level2

Level3 (highest)

Table 31: Interrupt Polling Sequence

External interrupt 0

Serial channel 1 interrupt

Timer 0 interrupt

External interrupt 2

External interrupt 1

External interrupt 3

Timer 1 interrupt

Serial channel 0 interrupt

External interrupt 4

External interrupt 5

External interrupt 6

1.7.5.6

Interrupt Sources and Vectors

Table 32 shows the interrupts with their associated flags and vector addresses.

Table 32: Interrupt Vectors

Interrupt Request Flag Description

Interrupt Vector Address

0x0000

N/A

Chip Reset

IE0

External interrupt 0

Timer 0 interrupt

0x0003

0x000B

0x0013

0x001B

0x0023

0x0083

0x004B

0x0053

0x005B

0x0063

0x006B

TF0

IE1

External interrupt 1

Timer 1 interrupt

TF1

RI0/TI0

RI1/TI1

IEX2

IEX3

IEX4

IEX5

IEX6

Serial channel 0 interrupt

Serial channel 1 interrupt

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

Rev. 1.4

39

73S1210F Data Sheet

DS_1210F_001

1.7.6 UART

The 80515 core of the 73S1210F includes two separate UARTs that can be programmed to communicate

with a host. The 73S1210F can only connect one UART at a time since there is only one set of TX and

Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each

UART has a different set of operating modes that the user can select according to their needs. The

UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at

up to 115,200 bits/s. The TX and RX pins operate at the V_DDsupply voltage levels and should never

exceed 3.6V. The operation of each pin is as follows:

RX: Serial input data is applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first.

The voltage applied at RX must not exceed 3.6V.

TX: This pin is used to output the serial data. The bytes are output LSB first.

The 73S1210F has several UART-related read/write registers. All UART transfers are programmable for

parity enable, parity select, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud

rates from 300 to 115200 bps. Table 33 shows the selectable UART operation modes and Table 34

shows how the baud rates are calculated.

Table 33: UART Modes

UART 0

UART 1

Start bit, 8 data bits, parity, stop bit, variable

baud rate (internal baud rate generator).

Mode 0

Mode 1

Mode 2

Mode 3

N/A

Start bit, 8 data bits, stop bit, variable

baud rate (internal baud rate generator

or timer 1).

Start bit, 8 data bits, stop bit, variable baud

rate (internal baud rate generator).

Start bit, 8 data bits, parity, stop bit, fixed

baud rate 1/32 or 1/64 of f_CKMPU.

N/A

Start bit, 8 data bits, parity, stop bit,

variable baud rate (internal baud rate

generator or timer 1).

Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with

parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit

output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit

serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits

S0CON3 and S1CON3 in the S0COn and S1CON SFRs.

Table 34: Baud Rate Generation

Using Timer 1

2^smod* f_CKMPU/ (384 * (256-TH1))

N/A

Using Internal Baud Rate Generator

2^smod* f_CKMPU/(64 * (2¹⁰-S0REL))

f_CKMPU/(32 * (2¹⁰-S1REL))

Serial Interface 0

Serial Interface 1

Note: S0REL (9:0) and S1REL (9:0) are 10-bit values derived by combining bits from the respective timer

reload registers SxRELH (bits 1:0) and SxRELL (bits 7:0). TH1 is the high byte of timer 1. The SMOD bit

is located in the PCON SFR.

40

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Power Control Register 0 (PCON): 0x87  0x00

The SMOD bit used for the baud rate generator is set up via this register.

Table 35: The PCON Register

MSB

LSB

SMOD

–

GF1

GF0

STOP

IDLE

Bit

Symbol

SMOD

–

Function

PCON.7

PCON.6

PCON.5

PCON.4

PCON.3

PCON.2

PCON.1

PCON.0

If SM0D = 1, the baud rate is doubled.

–

GF1

GF0

STOP

IDLE

General purpose flag 1.

Sets CPU to Stop mode.

Sets CPU to Idle mode.

Baud Rate Control Register 0 (BRCON): 0xD8  0x00

The BSEL bit used to enable the baud rate generator is set up via this register.

Table 36: The BRCON Register

MSB

LSB

–

BSEL

–

Bit

Symbol

Function

If BSEL = 0, the baud rate is derived using timer 1. If BSEL = 1 the

baud rate generator circuit is used.

BRCON.7

BSEL

BRCON.6

BRCON.5

BRCON.4

BRCON.3

BRCON.2

BRCON.1

BRCON.0

–

.

Rev. 1.4

41

73S1210F Data Sheet

DS_1210F_001

Miscellaneous Control Register 0 (MISCtl0): 0xFFF1  0x00

Transmit and receive (TX and RX) pin selection and loop back test configuration are setup via this

register.

Table 37: The MISCtl0 Register

MSB

LSB

SLPBK SSEL

PWRDN

–

Bit

Symbol

Function

MISCtl0.7

MISCtl0.6

MISCtl0.5

MISCtl0.4

MISCtl0.3

MISCtl0.2

PWRDN

This bit places the 73S1210F into a power down state.

–

1 = UART loop back testing mode. The pins TXD and RXD are to be

connected together externally (with SLPBK =1) and therefore:

SLPBK SSEL

Mode

MISCtl0.1

SLPBK

0

1

0

1

0

1

normal using Serial_0

normal using Serial_1

Serial_0 TX feeds Serial_1 RX

Serial_1 TX feeds Serial_0 RX

Selects either Serial_1 if set =1 or Serial_0 if set = 0 to be connected to

RXD and TXD pins.

MISCtl0.0

SSEL

1.7.6.1

Serial Interface 0

The Serial Interface 0 can operate in 4 modes:

•

Mode 0

Pin RX serves as input and output. TX outputs the shift clock. 8 bits are transmitted with LSB first.

The baud rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting

the flags in S0CON as follows: RI0 = 0 and REN0 = 1. In other modes, a start bit when REN0 = 1

starts receiving serial data.

Mode 1

Pin RX serves as input, and TX serves as serial output. No external shift clock is used, 10 bits are

transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start

bit synchronizes the transmission, 8 data bits are available by reading S0BUF, and stop bit sets the

flag RB80 in the Special Function Register S0CON. In mode 1 either internal baud rate generator or

timer 1 can be use to specify baud rate.

•

Mode 2

This mode is similar to Mode 1, with two differences. The baud rate is fixed at 1/32 or 1/64 of

oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a

programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity of the serial

interface: at transmission, bit TB80 in S0CON is output as the 9th bit, and at receive, the 9th bit

affects RB80 in Special Function Register S0CON.

42

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

•

Mode 3

The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator

or timer 1 can be use to specify baud rate.

The S0BUF register is used to read/write data to/from the serial 0 interface.

Serial Interface 0 Control Register (S0CON): 0x9B  0x00

Transmit and receive data are transferred via this register.

Table 38: The S0CON Register

MSB

LSB

RI0

SM0

SM1

SM20

REN0

TB80

RB80

TI0

Bit

Symbol

Function

S0CON.7

SM0

SM1

These two bits set the UART0 mode:

Mode

Description

N/A

SM0

SM1

0

1

2

3

0

1

0

1

0

1

S0CON.6

8-bit UART

9-bit UART

S0CON.5

S0CON.4

S0CON.3

SM20

REN0

TB80

Enables the inter-processor communication feature.

If set, enables serial reception. Cleared by software to disable reception.

The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,

depending on the function it performs (parity check, multiprocessor

communication etc.).

S0CON.2

RB80

In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,

RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by

software.

S0CON.1

S0CON.0

TI0

RI0

Transmit interrupt flag, set by hardware after completion of a serial transfer.

Must be cleared by software.

Receive interrupt flag, set by hardware after completion of a serial

reception. Must be cleared by software.

Rev. 1.4

43

73S1210F Data Sheet

DS_1210F_001

1.7.6.2

Serial Interface 1

The Serial Interface 1 can operate in 2 modes:

•

Mode A

This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmitted or received: a start bit

(0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control

the parity of the serial interface: at transmission, bit TB81 in S1CON is outputted as the 9th bit, and at

receive, the 9th bit affects RB81 in Special Function Register S1CON. The only difference between

Mode 3 and A is that in Mode A only the internal baud rate generator can be use to specify baud rate.

•

Mode B

This mode is similar to Mode 1 of Serial interface 0. Pin RX serves as input, and TX serves as serial

output. No external shift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB

first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are

available by reading S1BUF, and stop bit sets the flag RB81 in the Special Function Register

S1CON. In mode 1, the internal baud rate generator is use to specify the baud rate.

The S1BUF register is used to read/write data to/from the serial 1 interface.

Serial Interface Control Register (S1CON): 0x9B  0x00

The function of the serial port depends on the setting of the Serial Port Control Register S1CON.

Table 39: The S1CON Register

MSB

SM

LSB

RI1

–

SM21

REN1

TB81

RB81

TI1

Bit

Symbol

Function

S1CON.7

SM

Sets the UART operation mode.

SM

0

Mode

Description

9-bit UART

8-bit UART

Baud Rate

variable

A

B

1

variable

S1CON.6

S1CON.5

S1CON.4

S1CON.3

–

SM21

REN1

TB81

Enables the inter-processor communication feature.

If set, enables serial reception. Cleared by software to disable reception.

The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending

on the function it performs (parity check, multiprocessor communication, etc.).

S1CON.2

S1CON.1

RB81

TI1

In Mode B, if sm21 is 0, rb81 is the stop bit. Must be cleared by software.

Transmit interrupt flag, set by hardware after completion of a serial transfer.

Must be cleared by software.

S1CON.0

RI1

Receive interrupt flag, set by hardware after completion of a serial reception.

Must be cleared by software.

Multiprocessor operation mode: The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 or in

Mode A of Serial Interface 1 can be used for multiprocessor communication. In this case, the slave

processors have bit SM20 in S0CON or SM21 in S1CON set to 1. When the master processor outputs

slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave

processors compare the received byte with their network address. If there is a match, the addressed slave

will clear SM20 or SM21 and receive the rest of the message, while other slaves will leave the SM20 or

SM21 bit unaffected and ignore this message. After addressing the slave, the host will output the rest of the

message with the 9th bit set to 0, so no serial port receive interrupt will be generated in unselected slaves.

44

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.7 Timers and Counters

The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be

configured for counter or timer operations.

In timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12

periods of the MPU clock signal.

In counter mode, the register is incremented when the falling edge is observed at the corresponding input

signal T0 or T1 (T0 and T1 are the timer gating inputs derived from USR[0:7] pins, see the User (USR)

Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count

rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure

proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.

Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD

and TCON) are used to select the appropriate mode.

The Timer 0 load registers are designated as TL0 and TH0 and the Timer 1 load registers are designated

as TL1 and TH1.

Timer/Counter Mode Control Register (TMOD): 0x89  0x00

Table 40: The TMOD Register

MSB

GATE

LSB

M0

C/T

M1

M0

GATE

C/T

M1

Timer 1

Timer 0

Bits TR1 and TR0 in the TCON register start their associated timers when set.

Bit

Symbol

Function

TMOD.7

TMOD.3

Gate

If set, enables external gate control (USR pin(s) connected to T0 or T1 for

Counter 0 or 1, respectively). When T0 or T1 is high, and TRx bit is set (see

the TCON register), a counter is incremented every falling edge on T0 or T1

input pin. If not set, the TRx bit controls the corresponding timer.

TMOD.6

TMOD.2

C/T

Selects Timer or Counter operation. When set to 1, the counter operation is

performed based on the falling edge of T0 or T1. When cleared to 0, the

corresponding register will function as a timer.

TMOD.5

TMOD.1

M1

M0

Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in the

TMOD description.

TMOD.4

TMOD.0

Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in the

TMOD description.

Table 41: Timers/Counters Mode Description

M1

0

M0

0

Mode

Mode 0

Function

13-bit Counter/Timer.

16-bit Counter/Timer.

0

1

Mode 1

Mode 2

Mode 3

1

0

8-bit auto-reload Counter/Timer.

1

If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1

and M0 bits are set to '1', Timer 0 acts as two independent 8-bit

Timer/Counters.

Rev. 1.4

45

73S1210F Data Sheet

DS_1210F_001

Mode 0

Putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a divide-by-32

prescaler. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from

all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an

interrupt. The counted input is enabled to the timer when TRx = 1 and either GATE = 0 or TX = 1 (setting

GATE = 1 allows the timer to be controlled by external input TX, to facilitate pulse width measurements).

TRx are control bits in the special function register TCON; GATE is in TMOD. The 13-bit register consists

of all 8 bits of TH1 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be

ignored. Setting the run flag (TRx) does not clear the registers. Mode 0 operation is the same for timer 0

as for timer 1.

Mode 1

Mode 1 is the same as mode 0, except that the timer register is run with all 16 bits.

Mode 2

Mode 2 configures the timer register as an 8-bit counter (TLx) with automatic reload. The overflow from

TLx not only sets TFx, but also reloads TLx with the contents of THx, which is preset by software. The

reload leaves THx unchanged.

Mode 3

Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect

is the same as setting TR1 = 0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters.

TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function

(counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls

the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When

timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or

can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring

an interrupt from timer 1 itself.

Timer/Counter Control Register (TCON): 0x88  0x00

Table 42: The TCON Register

MSB

TF1

LSB

IT0

TR1

TF0

TR0

IE1

IT1

IE0

Bit

Symbol

Function

TCON.7

TCON.6

TCON.5

TCON.4

TF1

TR1

TF0

TR0

Timer 1 overflow flag.

Not used for interrupt control.

Timer 0 overflow flag.

Not used for interrupt control.

Interrupt 1 edge flag is set by hardware when the falling edge on external

interrupt int1 is observed. Cleared when an interrupt is processed.

TCON.3

TCON.2

TCON.1

TCON.0

IE1

IT1

IE0

IT0

Interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for

input pin to cause an interrupt.

Interrupt 0 edge flag is set by hardware when the falling edge on external

interrupt int0 is observed. Cleared when an interrupt is processed.

Interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for

input pin to cause interrupt.

46

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.8 WD Timer (Software Watchdog Timer)

The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.

After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a

16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once

the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.

WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register

enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6

in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing

the state of the WDT timer.

Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request

signal from becoming active. This requirement imposes an obligation on the programmer to issue two

instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay

allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has

not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of

the WDTREL register and WDT is automatically reset.

Interrupt Enable 0 Register (IEN0): 0xA8  0x00

Table 43: The IEN0 Register

MSB

EAL

LSB

EX0

WDT

ET2

ES0

ET1

EX1

ET0

Bit

Symbol

Function

IEN0.7

IEN0.6

EAL

EAL = 0 – disable all interrupts.

Watchdog timer refresh flag.

WDT

Set to initiate a refresh of the watchdog timer. Must be set directly before

SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT

is reset by hardware 12 clock cycles after it has been set.

IEN0.5

IEN0.4

IEN0.3

IEN0.2

IEN0.1

IEN0.0

–

ES0

ET1

EX1

ET0

EX0

ES0 = 0 – disable serial channel 0 interrupt.

ET1 = 0 – disable timer 1 overflow interrupt.

EX1 = 0 – disable external interrupt 1.

ET0 = 0 – disable timer 0 overflow interrupt.

EX0 = 0 – disable external interrupt 0.

Rev. 1.4

47

73S1210F Data Sheet

DS_1210F_001

Interrupt Enable 1 Register (IEN1): 0xB8  0x00

Table 44: The IEN1 Register

MSB

LSB

–

SWDT

EX6

EX5

EX4

EX3

EX2

–

Bit

Symbol

Function

IEN1.7

IEN1.6

–

SWDT Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer.

When directly set after setting WDT, a watchdog timer refresh is performed. Bit

SWDT is reset by the hardware 12 clock cycles after it has been set.

IEN1.5

IEN1.4

IEN1.3

IEN1.2

IEN1.1

IEN1.0

EX6

EX5

EX4

EX3

EX2

–

EX6 = 0 – disable external interrupt 6.

EX5 = 0 – disable external interrupt 5.

EX4 = 0 – disable external interrupt 4.

EX3 = 0 – disable external interrupt 3.

EX2 = 0 – disable external interrupt 2.

Interrupt Priority 0 Register (IP0): 0xA9  0x00

Table 45: The IP0 Register

MSB

–

LSB

IP0.0

WDTS

IP0.5

IP0.4

IP0.3

IP0.2

IP0.1

Bit

Symbol

WDTS

Function

IP0.6

Watchdog timer status flag. Set when the watchdog timer has expired. The

internal reset will be generated, but this bit will not be cleared by the reset.

This allows the user program to determine if the watchdog timer caused the

reset to occur and respond accordingly. Can be read and cleared by software.

Note: The remaining bits in the IP0 register are not used for watchdog control.

Watchdog Timer Reload Register (WDTREL): 0x86  0x00

Table 46: The WDTREL Register

MSB

LSB

WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0

Bit

Symbol

Function

Prescaler select bit. When set, the watchdog is clocked through an

additional divide-by-16 prescaler.

WDTREL.7

WDPSEL

WDTREL.6

to

WDTREL.0

Seven bit reload value for the high-byte of the watchdog timer. This value is

WDREL6-0 loaded to the WDT when a refresh is triggered by a consecutive setting of

bits WDT and SWDT.

48

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.9 User (USR) Ports

The 73S1210F includes 8 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins

are inputs until they are configured for the desired direction. The pins are configured and controlled by

the USR70 and UDIR70 SFRs. Each pin declared as USR can be configured independently as an input

or output with the bits of the UDIR70 register. Table 47 lists the direction registers and configurability

associated with each group of USR pins. USR pins 0 to 7 are multiple use pins that can be used for

general purpose I/O, external interrupts and timer control. Table 48 shows the configuration for a USR

pin through its associated bit in its UDIR register. Values read from and written into the GPIO ports use

the data registers USR70. Note: After reset, all USR pins are defaulted as inputs and pulled up to VDD

until any write to the corresponding UDIR register is performed. This insures all USR pins are set to a

known value until set by the firmware. Unused USR pins can be set for output if unused and

unconnected to prevent them from floating. Alternatively, unused USR pins can be set for input and tied

to ground or V_DD.

Table 47: Direction Registers and Internal Resources for DIO Pin Groups

Direction

Register

(SFR)

Data

Register

(SFR)

Direction

Register

Name

Data

Register

Name

USR Pin Group

Type

Location

USR_0…USR_7

Multi-use

UDIR70

0x91 [7:0]

USR70

0x90 [7:0]

Table 48: UDIR Control Bit

UDIR Bit

0

1

output

input

USR Pin Function

Four XRAM SFR registers (USRIntTCtl0, USRIntTCtl1, USRIntTCtl2, and USRIntTCtl3) control the use of

the USR [7:0] pins. Each of the USR [7:0] pins can be configured as GPIO or individually be assigned an

internal resource such as an interrupt or a timer/counter control. Each of the four registers contains two

3-bit configuration words named UxIS (where x corresponds to the USR pin). The control resources

selectable for the USR pins are listed in Table 50 through Table 53. If more than one input is connected

to the same resource, the resources are combined using a logical OR.

Table 49: Selectable Controls Using the UxIS Bits

UxIS Value

Resource Selected for USRx Pin

None

0

1

2

3

4

5

6

7

None

T0 (counter0 gate/clock)

T1 (counter1 gate/clock)

Interrupt 0 rising edge/high level on USRx

Interrupt 1 rising edge/high level on USRx

Interrupt 0 falling edge/low level on USRx

Interrupt 1 falling edge/low level on USRx

Note: x denotes the corresponding USR pin. Interrupt edge or level control is assigned in the IT0 and IT1

bits in the TCON register.

Rev. 1.4

49

73S1210F Data Sheet

DS_1210F_001

External Interrupt Control Register (USRIntCtl1) : 0xFF90  0x00

Table 50: The USRIntCtl1 Register

MSB

LSB

U0IS.2 U0IS.1 U0IS.0

–

U1IS.6 U1IS.5 U1IS.4

–

External Interrupt Control Register (USRIntCtl2) : 0xFF91  0x00

Table 51: The USRIntCtl2 Register

MSB

LSB

–

U3IS.6 U3IS.5 U3IS.4

–

U2IS.2 U2IS.1 U2IS.0

External Interrupt Control Register (USRIntCtl3) : 0xFF92  0x00

Table 52: The USRIntCtl3 Register

MSB

LSB

–

U5IS.6 U5IS.5 U5IS.4

–

U4IS.2 U4IS.1 U4IS.0

External Interrupt Control Register (USRIntCtl4) : 0xFF93  0x00

Table 53: The USRIntCtl4 Register

MSB

LSB

–

U7IS.6 U7IS.5 U7IS.4

–

U6IS.2 U6IS.1 U6IS.0

50

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.10 Analog Voltage Comparator

The 73S1210F includes a programmable comparator that is connected to the ANA_IN pin. The

comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a

selectable threshold voltage. The comparator control register should not be modified when the analog

interrupt (ANAIEN bit in the INT6Ctl register) is enabled to guard against any false interrupt that might be

generated when modifying the threshold. The comparator has a built-in hysteresis to prevent the

comparator from repeatedly responding to low-amplitude noise. This hysteresis is approximately 20mV.

Interrupt control is handled in the INT6Ctl register.

Analog Compare Control Register (ACOMP): 0xFFD0  0x00

Table 54: The ACOMP Register

MSB

ANALVL

LSB

ONCHG CPOL CMPEN TSEL.2 TSEL.1 TSEL.0

–

Bit

Symbol

Function

When read, indicates whether the input level is above or below the

threshold. This is a real time value and is not latched, so it may change

from the time of the interrupt trigger until read.

ACOMP.7

ANALVL

ACOMP.6

ACOMP.5

–

If set, the Ana_interrupt is invoked on any change above or below the

threshold, bit 4 is ignored.

ONCHG

If set = 1, Ana_interrupt is invoked when signal rises above selected

threshold. If set = 0, Ana_interrupt is invoked when signal goes below

selected threshold (default).

ACOMP.4

ACOMP.3

ACOMP.2

CPOL

CMPEN

TSEL.2

Enables power to the analog comparator. 1 = Enabled. 0 = Disabled

(default).

Sets the voltage threshold for comparison to the voltage on pin ANA_IN.

Thresholds are as follows:

TSEL.2

TSEL.1

TSEL.0 Voltage Threshold

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.00V

1.24V

1.40V

1.50V

1.75V

2.00V

2.30V

2.50V

ACOMP.1

ACOMP.0

TSEL.1

TSEL.0

Rev. 1.4

51

73S1210F Data Sheet

DS_1210F_001

External Interrupt Control Register (INT6Ctl): 0xFF95  0x00

Table 55: The INT6Ctl Register

MSB

LSB

VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT

–

Bit

Symbol

Function

INT6Ctl.7

INT6Ctl.6

INT6Ctl.5

INT6Ctl.4

INT6Ctl.3

INT6Ctl.2

–

VFTIEN

VFTINT

I2CIEN

I2CINT

VDD fault interrupt enable.

VDD fault interrupt flag.

I²C interrupt enabled.

I²C interrupt flag.

If ANIEN = 1 Analog Compare event interrupt is enabled. When masked

(ANIEN = 0), ANINT (bit 0) may be set, but no interrupt is generated.

INT6Ctl.1

ANIEN

(Read Only) Set when the selected ANA_IN signal changes with respect to

the selected threshold if Compare_Enable is asserted. Cleared on read of

register.

INT6Ctl.0

ANINT

52

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.11 LED Driver

The 73S1210F provides a single dedicated output pin for driving an LED. The LED driver pin can be

configured as a current source that will pull to ground to drive an LED that is connected to VDD without

the need for an external current limiting resistor. This pin may be used as general purpose output with

the programmed pull-down current and a strong (CMOS) pull-up, if enabled. The analog block must be

enabled when this output is being used to drive the selected output current.

This pin may be used as an input with consideration of the programmed output current and level. The

register bit when read, indicates the state of the pin.

LED Control Register (LEDCtl): 0xFFF3  0xFF

Table 56: The LEDCtl Register

MSB

LSB

–

LPUEN ISET.1 ISET.0

–

LEDD0

Bit

Symbol

Function

LEDCtl.7

LEDCtl.6

–

LPUEN 0 = Pull-ups are enabled for all of the LED pins.

These two bits control the drive current (to ground) for the LED driver pin.

Current levels are:

LEDCtl.5

LEDCtl.4

ISET.1

ISET.0

00 = 0ma(off)

01 = 2ma

10 = 4ma

11 = 10ma

LEDCtl.3

LEDCtl.2

LEDCtl.1

LEDCtl.0

–

LEDD0 Write data controls output level of pin LED0. Read will report level of pin LED0.

Rev. 1.4

53

73S1210F Data Sheet

DS_1210F_001

1.7.12 I²C Master Interface

The 73S1210F includes a dedicated fast mode, 400kHz I²C Master interface. The I²C interface can read

or write 1 or 2 bytes of data per data transfer frame. The MPU communicates with the interface through

six dedicated SFR registers:

•

Device Address (DAR)

Write Data (WDR)

Secondary Write Data (SWDR)

Read Data (RDR)

Secondary Read Data (SRDR)

Control and Status (CSR)

The DAR register is used to set up the slave address and specify if the transaction is a read or write

operation. The CSR register sets up, starts the transaction and reports any errors that may occur. When

the I²C transaction is complete, the I²C interrupt is reported via external interrupt 6. The I²C interrupt is

automatically de-asserted when a subsequent I²C transaction is started. The I²C interface uses a 400kHz

clock from the time-base circuits.

1.7.12.1 I²C Write Sequence

To write data on the I²C Master Bus, the 80515 has to program the following registers according to the

following sequence:

1. Write slave device address to Device Address register (DAR). The data contains 7 bits for the slave

device address and 1 bit of op-code. The op-code bit should be written with a 0 to indicate a write

operation.

2. Write data to Write Data register (WDR). This data will be transferred to the slave device.

3. If writing 2 bytes, set bit 0 of the Control and Status register (CSR) and load the second data byte to

Secondary Write Data register (SWDR).

4. Set bit 1 of the CSR register to start I²C Master Bus.

5. Wait for I²C interrupt to be asserted. It indicates that the write on I²C Master Bus is done. Refer to

information about the INT6Ctl, IEN1 and IRCON register for masking and flag operation.

Figure 10 shows the timing of the I²C write mode:

54

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Transfer length

(CSR bit0)

Start I2C

(CSR bit1)

I2C_Interrupt

SDA

Device Address

[7:0]

Write Data [7:0

MSB LSB

MSB

LSB

SCL

1-7

8

9

10-17

18

ACK bit

START

STOP

condition

Transfer length

(CSR bit0)

Start I2C

(CSR bit1)

I2C_Interrupt

SDA

Device Address

[7:0]

Secondary Write

Data [7:0]

Write Data [7:0]

MSB

LSB

MSB

LSB

MSB

LSB

SCL

1-7

8

9

10-17

18

19-26

27

ACK bit

STOP

START

condition

Figure 10: I²C Write Mode Operation

1.7.12.2 I²C Read Sequence

To read data on the I²C Master Bus from a slave device, the 80515 has to program the following registers

in this sequence:

1. Write slave device address to Device Address register (DAR). The data contains 7 bits device

address and 1 bit of op-code. The op-code bit should be written with a 1.

2. Write control data to Control and Status register. Write a 1 to bit 1 to start I²C Master Bus. Also write

a 1 to bit 0 if the Secondary Read Data register (SRDR) is to be captured from the I²C Slave device.

3. Wait for I²C interrupt to be asserted. It indicates that the read operation on the I²C bus is done.

Refer to information about the INT6Ctl, IEN1 and IRCON registers for masking and flag operation.

4. Read data from the Read Data register (RDR).

5. Read data from Secondary Read Data register (SRDR) if bit 0 of Control and Status register (CSR) is

written with a 1.

Rev. 1.4

55

73S1210F Data Sheet

DS_1210F_001

Figure 11 shows the timing of the I²C read mode:

Transfer length

(CSR bit0)

Start I2C

(CSR bit1)

I2c_Interrupt

SDA

Device Address

Read Data [7:0

MSB LSB

[7:0]

MSB

LSB

SCL

1-7

8

9

10-17

18

ACK bit

No ACK bit

START

STOP

condition

Transfer length

(CSR bit0)

Start I2C

(CSR bit1)

I2c_Interrupt

SDA

Device Address

[7:0]

Secondary Read

Data[7:0]

Read Data [7:0]

MSB

LSB

MSB

LSB

SCL

1-7

8

9

10-17

18

19-26

27

ACK bit

No ACK bit

START

STOP

condition

Figure 11: I²C Read Operation

56

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Device Address Register (DAR): 0xFF80  0x00

Table 57: The DAR Register

MSB

LSB

DVADR.6 DVADR.5 DVADR.4 DVADR.3 DVADR.2 DVADR.1 DVADR.0 I2CRW

Bit

Symbol

Function

DAR.7

DAR.6

DAR.5

DAR.4

DAR.3

DAR.2

DAR.1

DAR.0

DVADR

[0:6]

Slave device address.

I2CRW

If set = 0, the transaction is a write operation. If set=1, read.

I2C Write Data Register (WDR): 0XFF81  0x00

Table 58: The WDR Register

MSB

WDR.7

LSB

WDR.0

WDR.6

WDR.5

WDR.4

WDR.3

WDR.2

WDR.1

Bit

Function

WDR.7

WDR.6

WDR.5

WDR.4

WDR.3

WDR.2

WDR.1

WDR.0

Data to be written to the I²C slave device.

Rev. 1.4

57

73S1210F Data Sheet

DS_1210F_001

I2C Secondary Write Data Register (SWDR): 0XFF82  0x00

Table 59: The SWDR Register

MSB

LSB

SWDR.7 SWDR.6 SWDR.5 SWDR.4 SWDR.3 SWDR.2 SWDR.1 SWDR.0

Bit

Function

SWDR.7

SWDR.6

SWDR.5

SWDR.4

SWDR.3

SWDR.2

SWDR.1

SWDR.0

Second Data byte to be written to the I²C slave device if bit 0 (I2CLEN) of the

Control and Status register (CSR) is set = 1.

I2C Read Data Register (RDR): 0XFF83  0x00

Table 60: The RDR Register

MSB

RDR.7

LSB

RDR.0

RDR.6

RDR.5

RDR.4

RDR.3

RDR.2

RDR.1

Bit

Function

RDR.7

RDR.6

RDR.5

RDR.4

RDR.3

RDR.2

RDR.1

RDR.0

Data read from the I²C slave device.

58

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

I2C Secondary Read Data Register (SRDR): 0XFF84  0x00

Table 61: The SRDR Register

MSB

LSB

SRDR.0

SRDR.7

SRDR.6

SRDR.5

SRDR.4

SRDR.3

SRDR.2

SRDR.1

Bit

Function

SRDR.7

SRDR.6

SRDR.5

SRDR.4

SRDR.3

SRDR.2

SRDR.1

SRDR.0

Second Data byte to be read from the I²C slave device if bit 0 (I2CLEN) of the Control

and Status register (CSR) is set = 1.

I2C Control and Status Register (CSR): 0xFF85  0x00

Table 62: The CSR Register

MSB

LSB

I2CLEN

–

AKERR

I2CST

Bit

Symbol

Function

CSR.7

CSR.6

CSR.5

CSR.4

CSR.3

–

Set to 1 if acknowledge bit from Slave Device is not 0. Automatically reset

when the new bus transaction is started.

CSR.2

AKERR

Write a 1 to start I²C transaction. Automatically reset to 0 when the bus

transaction is done. This bit should be treated as a “busy” indicator on

reading. If it is high, the serial read/write operations are not completed and

no new address or data should be written.

CSR.1

CSR.0

I2CST

I2CLEN

Set to 1 for 2 byte read or write operations. Set to 0 for 1-byte operations.

Rev. 1.4

59

73S1210F Data Sheet

DS_1210F_001

External Interrupt Control Register (INT6Ctl): 0xFF95  0x00

Table 63: The INT6Ctl Register

MSB

LSB

VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT

–

Bit

Symbol

Function

INT6Ctl.7

INT6Ctl.6

INT6Ctl.5

INT6Ctl.4

INT6Ctl.3

–

VFTIEN

VFTINT

I2CIEN

VDD fault interrupt enable.

VDD fault interrupt flag.

When set = 1, the I²C interrupt is enabled.

When set = 1, the I²C transaction has completed. Cleared upon the start

INT6Ctl.2

I2CINT

of a subsequent I²C transaction.

INT6Ctl.1

INT6Ctl.0

ANIEN

ANINT

Analog compare interrupt enable.

Analog compare interrupt flag.

60

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.13 Keypad Interface

The 73S1210F supports a 30-button (6 rows x 5 columns) keypad (SPST Mechanical Contact Switches)

interface using 11 dedicated I/O pins. Figure 12 shows a simplified block diagram of the keypad

interface.

KORDERL / H Registers

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

VDD

COL4:0

Keypad Clock

Column Value

Scan

5

7

6

5

4

3

2

1

0

KCOL Register⁽¹⁾

VDD

KSIZE Register

7

6

5

4

3

2

1

0

Keypad Clock

Row Value

6

Debouncing

7

6

5

4

3

2

1

0

KROW Register

Hardware Scan Enable

If smaller keypad than 6 x 5 is to be

implemented, unused row inputs

should be connected to VDD. Unused

column outputs should be left

unconnected.

7

6

5

4

3

2

1

0

6

KSTAT Register

0

1

2

3

4

5

6

7

(1) KCOL is normally used as Read only

register. When hardware keyscan mode

is disabled, this register is to be used by

firmware to write the column data to

handle firmware scanning.

KSCAN Register

1kHz

Dividers

73S1210F

Figure 12: Simplified Keypad Block Diagram

There are five drive lines (outputs) corresponding to columns and 6 sense lines (inputs) corresponding to

rows. Hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external

resistors in the keypad. Key scanning happens by asserting one of the 5 column lines low and looking for

a low on a sense line indicating that a key is pressed (switch closed) at the intersection of the drive/sense

(column/row) line in the keypad. Key detection is performed by hardware with an incorporated debounce

timer. Debouncing time is adjustable through the KSCAN register. Internal hardware circuitry performs

column scanning at an adjustable scanning rate and column scanning order through registers KSCAN

and KORDERL / KORDERH. Key scanning is disabled at reset and must be enabled by firmware. When

a valid key is detected, an interrupt is generated and the valid value of the pressed key is automatically

Rev. 1.4

61

73S1210F Data Sheet

DS_1210F_001

written into the KCOL and KROW registers. The keypad interface uses a 1kHz clock derived from the

12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the MCLKCtl register (see the Oscillator

and Clock Generation section) to carry out scanning and debouncing. The keypad size can be adjusted

within the KSIZE register.

Normal scanning is performed by hardware when the SCNEN bit is set at 1 in the KSTAT register. Figure

13 shows the flowchart of how the hardware scanning operates. In order to minimize power, scanning

does not occur until a key-press is detected. Once hardware key scanning is enabled, the hardware

drives all column outputs low and waits for a low to be detected on one of the inputs. When a low is

detected on any row, and before key scanning starts, the hardware checks that the low level is still

detected after a debounce time. The debounce time is defined by firmware in the KSCAN register (bits

7:0, DBTIME). Debounce times from 4ms to 256ms in 4ms increments are supported. If a key is not

pressed after the debounce time, the hardware will go back to looking for any input to be low. If a key is

confirmed to be pressed, key scanning begins.

Key scanning asserts one of the 5 drive lines (COL 4:0) low and looks for a low on a sense line indicating

that a key is pressed at the intersection of the drive/sense line in the keypad. After all sense lines have

been checked without a key-press being detected, the next column line is asserted. The time between

checking each sense line is the scan time and is defined by firmware in the KSCAN register (bits 0:1 –

SCTIME). Scan times from 1ms to 4ms are supported. Scanning order does not affect the scan time.

This scanning continues until the entire keypad is scanned. If only one key is pressed, a valid key is

detected. Simultaneous key presses are not considered as valid (If two keys are pressed, no key is

reported to firmware).

Possible scrambling of the column scan order is provided by means of the KORDERL and KORDERH

registers that define the order of column scanning. Values in these registers must be updated every time

a new keyboard scan order is desired. It is not possible to change the order of scanning the sense lines.

The column and row intersection for the detected valid key are stored in the KCOL and KROW registers.

When a valid key is detected, an interrupt is generated. Firmware can then read those registers to

determine which key had been pressed. After reading the KCOL and KROW registers, the firmware can

update the KORDERL / KORDERH registers if a new scan order is needed. When the SCNEN bit is

enabled in the KSTAT register, the KCOL and KROW registers are only updated after a valid key has

been identified. The hardware does not wait for the firmware to service the interrupt in order to proceed

with the key scanning process. Once the valid key (or invalid key – e.g. two keys pressed) is detected,

the hardware waits for the key to be released. Once the key is released, the debounce timer is started. If

the key is not still released after the debounce time, the debounce counter starts again. After a key

release, all columns will be driven low as before and the process will repeat waiting for any key to be

pressed. When the SCNEN bit is disabled, all drive outputs are set to the value in the KCOL register. If

firmware clears the SCNEN bit in the middle of a key scan, the KCOL register contains the last value

stored in there which will then be reflected on the output pins. A bypass mode is provided so that the

firmware can do the key scanning manually (SCNEN bit must be cleared). In bypass mode, the firmware

writes/reads the Column and Row registers to perform the key scanning.

62

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

KSTAT Register:

Enable HW Scanning

Enable Keypad Interrupt

Keypad

Initialization

All Column

Outputs = 0

Any

Row

Input = 0 ?

No

Yes

No

Deboucing

Timer

KSCAN Register:

Debouncing Time

Any Row

Input still = 0 ?

KSIZE Register:

Keypad Size Definition

KORDERL / H Registers:

Column Scan Order

Keypad Scanning

KSCAN Register:

Scanning Rate

How Many

keys have been

detected?

0 key

More

than

1 key

KCOL Register:

Value of the valid key column

Download of the key row and

column values in KROW and

KCOL registers

KROW Register:

Value of the valid key row

Keypad Interrupt

generation

KSTAT Register:

Key Detect Interrupt

No

Is (are)

the key(s)

released ?

(*)

Deboucing

Timer

Yes

No

KSCAN Register:

Debouncing Time

Is (are)

the key(s)

still released ?

(*)

Register Used to Control the

hardware keypad interface

Register written by the

Yes

hardware keypad interface

(*) Key release is cheked by looking for a low level on any row.

Figure 13: Keypad Interface Flow Chart

Rev. 1.4

63

73S1210F Data Sheet

DS_1210F_001

Keypad Column Register (KCOL): 0xD1  0x1F

This register contains the value of the column of a key detected as valid by the hardware. In bypass

mode, this register firmware writes directly this register to carry out manual scanning.

Table 64: The KCOL Register

MSB

LSB

COL.0

–

COL.4

COL.3

COL.2

COL.1

Bit

Symbol

Function

KCOL.7

KCOL.6

KCOL.5

KCOL.4

KCOL.3

KCOL.2

KCOL.1

KCOL.0

–

COL.4

COL.3

COL.2

COL.1

COL.0

Drive lines bit mapped to corresponding with pins COL(4:0). When a key

is detected, firmware reads this register to determine column. In bypass

(S/W keyscan) mode, Firmware writes this register directly. 0x1E =

COL(0) low, all others high. 0x0F = COL(4) low, all others high. 0x1F =

COL(4:0) all high.

Keypad Row Register (KROW): 0xD2  0x3F

This register contains the value of the row of a key detected as valid by the hardware. In bypass mode,

this register firmware reads directly this register to carry out manual detection.

Table 65: The KROW Register

MSB

LSB

ROW.5 ROW.4 ROW.3 ROW.2 ROW.1 ROW.0

–

Bit

Symbol

Function

KROW.7

KROW.6

KROW.5

KROW.4

KROW.3

KROW.2

KROW.1

KROW.0

–

ROW.6

ROW.4

ROW.3

ROW.2

ROW.1

ROW.0

Sense lines bit mapped to correspond with pins ROW(5:0). When key

detected, firmware reads this register to determine row. In bypass mode,

firmware reads rows and has to determine if there was a key press or not.

0x3E = ROW(0) low, all others high. 0x1F = ROW(5) low, all others high.

0x3F = ROW(5:0) all high.

64

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Keypad Scan Time Register (KSCAN): 0xD3  0x00

This register contains the values of scanning time and debouncing time.

Table 66: The KSCAN Register

MSB

LSB

DBTIME.5 DBTIME.4 DBTIME.3 DBTIME.2 DBTIME.1 DBTIME.0 SCTIME.1 SCTIME.0

Bit

Symbol

Function

KSCAN.7

KSCAN.6

KSCAN.5

KSCAN.4

KSCAN.3

KSCAN.2

KSCAN.1

KSCAN.0

DBTIME.5

DBTIME.4

DBTIME.3

DBTIME.2

DBTIME.1

DBTIME.0

SCTIME.1

SCTIME.0

Debounce time in 4ms increments. 1 = 4ms de-bounce time, 0x3F =

252ms, 0x00 = 256ms. Key presses and key releases are debounced by

this amount of time.

Scan time in ms. 01 = 1ms, 02 = 2ms, 00 = 3ms, 00 = 4ms. Time between

checking each key during keypad scanning.

Keypad Control/Status Register (KSTAT): 0xD4  0x00

This register is used to control the hardware keypad scanning and detection capabilities, as well as the

keypad interrupt control and status.

Table 67: The KSTAT Register

MSB

LSB

KEYCLK HWSCEN KEYDET KYDTEN

–

Bit

Symbol

Function

KSTAT.7

KSTAT.6

KSTAT.5

KSTAT.4

KSTAT.3

–

KEYCLK

The current state of the keyboard clock can be read from this bit.

Hardware Scan Enable – When set, the hardware will perform automatic

KSTAT.2

KSTAT.1

KSTAT.0

HWSCEN key scanning. When cleared, the firmware must perform the key scanning

manually (bypass mode).

Key Detect – When HWSCEN = 1, this bit is set causing an interrupt that

indicates a valid key press was detected and the key location can be read

from the Keypad Column and Row registers. When HWSCEN = 0, this bit

is an interrupt which indicates a falling edge on any Row input if all Row

inputs had been high previously (note: multiple Key Detect interrupts may

KEYDET

occur in this case due to the keypad switch bouncing). In all cases, this bit

is cleared when read. When HWSCEN = 0 and the keypad interface 1kHz

clock is disabled, a key press will still set this bit and cause an interrupt.

Key Detect Enable – When set, the KEYDET bit can cause an interrupt and

KYDTEN

when cleared the KEYDET cannot cause an interrupt. KEYDET can still

get set even if the interrupt is not enabled.

Rev. 1.4

65

73S1210F Data Sheet

DS_1210F_001

Keypad Scan Time Register (KSIZE): 0xD5  0x00

This register is not applicable when HWSCEN is not set. Unused row inputs should be connected to

VDD.

Table 68: The KSIZE Register

MSB

LSB

ROWSIZ.2 ROWSIZ.1 ROWSIZ.0 COLSIZ.2 COLSIZ.1 COLSIZ.0

–

Bit

Symbol

Function

KSIZE.7

KSIZE.6

KSIZE.5

KSIZE.4

KSIZE.3

KSIZE.2

KSIZE.1

KSIZE.0

–

ROWSIZ.2

Defines the number of rows in the keypad. Maximum number is 6 given

ROWSIZ.1 the number of row pins on the package. Allows for a reduced keypad size

for scanning.

ROWSIZ.0

COLSIZ.2

Defines the number of columns in the keypad. Maximum number is 5

COLSIZ.1 given the number of column pins on the package. Allows for a reduced

keypad size for scanning.

COLSIZ.0

66

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Keypad Column LS Scan Order Register (KORDERL): 0xD6  0x00

In the KORDERL and KORDERH registers, Column Scan Order(14:0) is grouped into 5 sets of 3 bits

each. Each set determines which column (COL(4:0) pin) to activate by loading the column number into

the 3 bits. When in HW_Scan_Enable mode, the hardware will step through the sets from 1Col to 5Col

(up to the number of columns in Colsize) and scan the column defined in the 3 bits. To scan in sequential

order, set a counting pattern with 0 in set 0, and 1 in set 1,and 2 in set 2, and 3 in set 3, and 4 in set 4.

The firmware should update this as part of the interrupt service routine so that the new scan order is

loaded prior to the next key being pressed. For example, to scan COL(0) first, 1Col(2:0) should be

loaded with 000’b. To scan COL(4) fifth, 5Col(2:0) should be loaded with 100’b.

Table 69: The KORDERL Register

MSB

LSB

3COL.1 3COL.0 2COL.2 2COL.1 2COL.0 1COL.2 1COL.1 1COL.0

Bit

Symbol

3COL.1

3COL.0

2COL.2

2COL.1

2COL.0

1COL.2

1COL.1

1COL.0

Function

KORDERL.7

KORDERL.6

KORDERL.5

KORDERL.4

KORDERL.3

KORDERL.2

KORDERL.1

KORDERL.0

Column to scan 3^rd(lsb’s).

Column to scan 2^nd.

Column to scan 1^st.

Keypad Column MS Scan Order Register (KORDERH): 0xD7  0x00

Table 70: The KORDERH Register

MSB

LSB

5COL.2 5COL.1 5COL.0 4COL.2 4COL.1 4COL.0 3COL.2

–

Bit

Symbol

–

Function

KORDERH.7

KORDERH.6

KORDERH.5

KORDERH.4

KORDERH.3

KORDERH.2

KORDERH.1

KORDERH.0

5COL.2

5COL.1

5COL.0

4COL.2

4COL.1

4COL.0

3COL.2

Column to scan 5^th.

Column to scan 4^th.

Column to scan 3^rd(msb).

Rev. 1.4

67

73S1210F Data Sheet

DS_1210F_001

External Interrupt Control Register (INT5Ctl): 0xFF94  0x00

Table 71: The INT5Ctl Register

MSB

LSB

KPINT

PDMUX

–

KPIEN

Bit

Symbol

Function

INT5Ctl.7

INT5Ctl.6

INT5Ctl.5

INT5Ctl.4

INT5Ctl.3

INT5Ctl.2

INT5Ctl.1

PDMUX

Power down multiplexer control.

–

KPIEN

Enables Keypad interrupt when set = 1.

This bit indicates the Keypad logic has set Key_Detect bit and a key

location may be read. Cleared on read of register.

INT5Ctl.0

KPINT

1.7.14 Emulator Port

The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX, provides control of the MPU

through an external in-circuit emulator. The E_TBUS[3:0] pins, together with the E_ISYNC/BRKRQ, add

trace capability to the emulator. The emulator port is compatible with the ADM51 emulators

manufactured by Signum Systems™.

The signals of the emulator port have weak pull-ups. Adding resistor footprints for signals E_RST,

E_TCLK and E_RXTX on the PCB is recommended. If necessary, adding 10kΩ pull-up resistors on

E_TCLK and E_RXTX and a 3kΩ on E_RST will help the emulator operate normally if a problem arises.

If code trace capability is needed on this interface, 20pF capacitors ( (to ground) need to be added to

allow the trace function capability to run properly. These capacitors should be attached to the TBUS0:3

and ISBR signals.

68

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.15 Smart Card Interface Function

The 73S1210F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well

as an external smart card interface to allow multiple smart cards to be connected using the Teridian 8010

family of interface devices. Figure 14 shows the simplified block diagram of the card circuitry (UART +

interfaces), with detail of dedicated XRAM registers.

ICC Event

SCInt

Card Interrupt

ICC Pwr_event

Management

SCIE

Card

Insertion

PRES

SParCtl

Serial

UART

VccCtl/

VccTMR

TX

RX

SByteCtl

FDReg

Activation /

Deactivation

Sequencer

UART

T=0 T=1

VCC Card

Generation

SCCtl

Direct

Mode

VCC

I/O

SCECtl

SCPrtcol

Buffer / Level

Shifter

I/O ICC#1

Card and

Mode

Selection

2-Byte

Tx FIFO

STXCtl

STXData

SRXCtl

Buffer / Level

Shifter

RST

CLK

2-Byte

Rx FIFO

SCSel

SRXData

Buffer / Level

Shifter

SCCLK/SCSCLK

BGT/EGT

BGT0/1/2/3/

CWT0/1

Buffer / Level

Shifter

Timers

C4

ATRMsB/LsB

STSTO

Buffer / Level

Shifter

RLength

C8

SCDir

SCCLK

CLK ICC

Internal ICC Interface

Card Clock

Management

7.2MHz

CLKExt. ICC

SIO

SCLK

SCSCLK

XRAM Registers

SCCLK/

SCSCLK

External ICC Interface

Figure 14: Smart Card Interface Block Diagram

Card interrupts are managed through two dedicated registers: SCIE (Interrupt Enable to define which

interrupt is enabled) and SCInt (Interrupt status). They allow the firmware to determine the source of an

interrupt, that can be a card insertion / removal, card power fault, or a transmission (TX) or reception (RX)

event / fault. It should be noted that even when card clock is disabled, an ICC interrupt can be generated

Rev. 1.4

69

73S1210F Data Sheet

DS_1210F_001

on a card insertion / removal to allow power saving modes. Card insertion / removal is generated from

the respective card switch detection inputs (whose polarity is programmable).

The built-in ICC Interface has a linear regulator (V_CCgenerator) capable of driving 1.8, 3.0 and 5.0V smart

cards in accordance with the ISO 7816-3 and EMV4.1 standards. This converter uses the V_P(5.5V

nominal) input supply source. See the power supply management section above for more detail.

Auxiliary I/O lines C4 and C8 are only provided for the built-in interface. If support for the auxiliary lines is

necessary for the external smart card interface, they need to be handled manually through the USR GPIO

pins. The external 73S8010x devices directly connect the I/O (SIO) and clock (SCLK) signals and control

is handled via the I²C interface.

Figure 15 shows how multiple 8010 devices can be connected to the 73S1210F.

VPC

PRES

VCC

RST

CLK

SC1

C4

C8

I/O

GND

SIO

SCLK

INT

PRES

73S1210F

SCL

SDA

IOUC

SC(n)

73S8010

XTALIN

SAD(0:2)

INT

PRES

SCL

SDA

SC3

73S8010

IOUC

XTALIN

SAD(0:2)

INT

PRES

INT3

SCL

SDA

SCL

SC2

73S8010

IOUC

XTALIN

SAD(0:2)

Figure 15: External Smart Card Interface Block Diagram

70

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.15.1 ISO 7816 UART

An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card

and the 73S1210F MPU. The UART can be shared between the one built-in ICC interface and the

external ICC interface. Selection of the desired interface is made by register SCSel. Control of the

external interface is handled by the I²C interface for any external 73S8010x device. The following is a list

of features for the ISO 7816 UART:

•

Two-byte FIFO for temporary data storage on both TX and Rx data.

Parity checking in T=0. This feature can be enabled/disabled by firmware. Parity error reporting to

firmware and Break generation to ICC can be controlled independently.

•

Parity error generation for test purposes.

Retransmission of last byte if ICC indicates T=0 parity error. This feature can be enabled/disabled by

firmware.

•

Deletion of last byte received if ICC indicates T=0 parity error. This feature can be enabled/disabled

by firmware.

CRC/LRC generation and checking. CRC/LRC is automatically inserted into T=1 data stream by the

hardware. This feature can be enabled/disabled by firmware.

Support baud rates: 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware control

(assuming 12MHz crystal) with various F/D settings.

Firmware manages F/D. All F/D combinations are supported in which F/D is directly divisible by 31 or

32 (i.e. F/D is a multiple of either 31 or 32).

•

Flexible ETU clock generation and control.

Detection of convention (direct or indirect) character TS. This affects both polarity and order of bits in

byte. Convention can be overridden by firmware.

•

Supports WTX Timeout with an expanded Wait Time Counter (28 bits).

A Bypass Mode is provided to bypass the hardware UART in order for the software to emulate the

UART (for non-standard operating modes). In such a case, the I/O line value is reflected in SFR

SCCtl or SCECtl respectively for the built-in or external interfaces. This mode is appropriate for some

synchronous and non T=0 / T=1 cards.

The single integrated smart card UART is capable of supporting T=0 and T=1 cards in hardware

therefore offloading the bit manipulation tasks from the firmware. The embedded firmware instructs the

hardware which smart card it should communicate with at any point in time. Firmware reconfigures the

UART as required when switching between smart cards. When the 73S1210F has transmitted a

message with an expected response, the firmware should not switch the UART to another smart card

until the first smart card has responded. If the smart card responds while another smart card is selected,

that first smart card’s response will be ignored.

Rev. 1.4

71

73S1210F Data Sheet

DS_1210F_001

1.7.15.2 Answer to Reset Processing

A card insertion event generates an interrupt to the firmware, which is then responsible for the

configuration of the electrical interface, the UART and activation of the card. The activation sequencer

goes through the power up sequence as defined in the ISO 7816-3 specification. An asynchronous

activation timing diagram is shown in

Figure 16. After the card reset is de-asserted, the firmware instructs the hardware to look for a TS byte

that begins the ATR response. If a response is not provided within the pre-programmed timeout period,

an interrupt is generated and the firmware can then take appropriate action, including instructing the

73S1210F to begin a deactivation sequence. Once commanded, the deactivation sequencer goes

through the power down sequence as defined in the ISO 7816-3 specification. If an ATR response is

received, the hardware looks for a TS byte that determines direct/inverse convention. The hardware

handles the indirect convention conversion such that the embedded firmware only receives direct

convention. This feature can be disabled by firmware within SByteCtl register. Parity checking and

break generation is performed on the TS byte unless disabled by firmware. If during the card session, a

card removal, over-current or other error event is detected, the hardware will automatically perform the

deactivation sequence and then generate an interrupt to the firmware. The firmware can then perform

any other error handling required for proper system operation. Smart card RST, I/O and CLK, C4, C8

shall be low before the end of the deactivation sequence. Figure 17 shows the timing for a deactivation

sequence.

SELSC

bits

VCCSEL

bits

VCC

t4

VCCOK bit

RSTCRD bit

See Note

RST

CLK

ATR starts

IO

t1

t5

t4

t2

t3

tto

t1: SELSC.1 bit set (selects internal ICC interface) and a non-zero value in VCCSEL bits (calling for a

value of Vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence. t1 is the time for Vcc to rise

to acceptable level, declared as Vcc OK (bit VCCOK gets set). This time depends on filter capacitor

value and card Icc load.

tto: The time allowed for Vcc to rise to Vcc OK status after setting of the VCCSEL bits. This time is

generated by the VCCTMR counter. If Vcc OK is not set, (bit VCCOK) at this time, a deactivation will

be initiated. VCCSEL bits are not automatically cleared. The firmware must clear the VCCSEL bits

before starting a new activation.

t2: Time from VccTmr timeout and VCC OK to IO reception (high), typically 2-3 CLK cycles if RDYST

= 0. If RDYST = 1, t2 starts when VCCOK = 1.

t3: Time from IO = high to CLK start, typically 2-3 CLK cycles.

t4: Time allowed for start of CLK to de-assertion of RST. Programmable by the RLength register.

t5: Time allowed for ATR timeout, set by the STSTO register.

Note: If the RSTCRD bit is set, RST is asserted (low). Upon clearing RSTCRD bit, RST will be

de-asserted after t4.

72

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Figure 16: Asynchronous Activation Sequence Timing

Firmware sets

VCCSEL to 00

t5

t5 delay or

Card Event

IO

RST

CLK

CMDVCCnB

VCC

t3

t1

t2

t4

t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0

(see t5, VCCOff_tmr) occurs until RST is asserted low.

t2: Time after RST goes low until CLK stops.

t3: Time after CLK stops until IO goes low.

t4: Time after IO goes low until VCC is powered down.

t5: Delayed VCC off time (in ETUs per VCCOff_tmr bits). Only in effect due to firmware

deactivation.

Figure 17: Deactivation Sequence

1.7.15.3 Data Reception/Transmission

When a 12Mhz crystal is used, the smart card UART will generate a 3.69Mhz (default) clock to both

smart card interfaces. This will allow approximately 9600bps (1/ETU) communication during ATR (ISO

7816 default). As part of the PPS negotiation between the smart card and the reader, the firmware may

determine that the smart card parameters F & D may be changed. After this negotiation, the firmware

may change the ETU by writing to the SFR FDReg to adjust the ETU and CLK. The firmware may also

change the smart card clock frequency by writing to the SFR SCCLK (SCECLK for external interface).

Independent clock frequency control is provided to each smart card interface. Clock stop high or Clock

stop low is supported in asynchronous mode. Figure 18 shows the ETU and CLK control circuits. The

firmware determines when clock stop is supported by the smart card and when it is appropriate to go into

that mode (and when to come out of it). The smart card UART is clocked by the same clock that is

provided to the selected smart card. The transition between smart card clocks is handled in hardware to

eliminate any glitches for the UART during switchover. The external smart card clock is not affected

when switching the UART to communicate with the internal smart card.

Rev. 1.4

73

73S1210F Data Sheet

DS_1210F_001

FDReg(3:0)

FDReg(7:4)

FI Decoder

F/D Register

ETUCLK

EDGE

Pre-Scaler

6 bits

7.38M

ETU Divider

12 bits

9926

1/13

CENTER

1/744

SCSel(3:2)

SYNC

SCCLK(5:0)

DIV

by

2

MSCLK

7.38M

3.69M

SCSCLK(5:0)

CLK

MCLK =

96MHz

DIV

by

2

MSCLKE

Pre-Scaler

6 bits

PLL

3.69M

7.38M

1/13

SCLK

Defaults

in Italics

Figure 18: Smart Card CLK and ETU Generation

There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing,

if a parity error is detected by the 73S1210F during message reception, an error signal (BREAK) will be

generated to the smart card. The byte received will be discarded and the firmware notified of the error.

Break generation and receive byte dropping can be disabled under firmware control. During the

transmission of a byte, if an error signal (BREAK) is detected, the last byte is retransmitted again and the

firmware notified. Retransmission can be disabled by firmware. When a correct byte is received, an

interrupt is generated to the firmware, which then reads the byte from the receive FIFO. Receive overruns

are detected by the hardware and reported via an interrupt. During transmission of a message, the

firmware will write bytes into the transmit FIFO. The hardware will send them to the smart card. When the

last byte of a message has been written, the firmware will need to set the LASTTX bit in the STXCtl SFR.

This will cause the hardware to insert the CRC/LRC if in a T=1 protocol mode. CRC/LRC

generation/checking is only provided during T=1 processing. Firmware will need to instruct the smart

function to go into receive mode after this last transmit data byte if it expects a response from the smart

card. At the end of the smart card response, the firmware will put the interface back into transmit mode if

appropriate.

The hardware can check for the following card-related timeouts:

•

Character Waiting Time (CWT)

Block Waiting Time (BWT)

Initial Waiting Time (IWT)

The firmware will load the Wait Time with the appropriate value for the operating mode at the appropriate

time. Figure 19 shows the guard, block, wait and ATR time definitions. If a timeout occurs, an interrupt

will be generated and the firmware can take appropriate recovery steps. Support is provided for adding

additional guard times between characters using the Extra Guard Time register (EGT), and between the

last byte received by the 73S1210F and the first byte transmitted by the 73S1210F using the Block Guard

Time register (BGT). Other than the protocol checks described above, the firmware is responsible for all

protocol checking and error recovery.

74

Rev. 1.4

DS_1210F_001

T = 0 Mode

73S1210F Data Sheet

> EGT

CHAR 1

CHAR 2

< WWT

WWT is set by the value in the BWT registers.

T = 1 Mode

TRANSMISSION

RECEPTION

BLOCK2

(By seting Last_TXByte and

TX/RXB=0 during CHAR N,

RX mode will start after last

TX byte)

BGT(4:0)

BLOCK1

CHAR

N+1

CHAR

N+2

CHAR

N+3

CHAR 1

CHAR 2

CHAR N

TX

> BWT

< CWT

EGT

ATR Timing Parameters

CHAR 1

CHAR 2

CHAR N

IO

TSTO(7:0)

ATRTO(15:0)

RST

IWT(15:0)

RLen(7:0)

VCC_OK

Figure 19: Guard, Block, Wait and ATR Time Definitions

1.7.15.4 Bypass Mode

It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart

cards. This is called Bypass mode. In this mode the embedded firmware will communicate directly with

the selected smart card and drive I/O during transmit and read I/O during receive in order to communicate

with the smart card. In this mode, ATR processing is under firmware control. The firmware must

sequence the interface signals as required. Firmware must perform TS processing, parity checking,

break generation and CRC/LRC calculation (if required).

1.7.15.5 Synchronous Operation Mode

The 73S1210F supports synchronous operation. When sync mode is selected for either interface, the

CLK signal is generated by the ETU counter. The values in c, SCCLK, and SCECLK must be set to

obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the

interface must be selected to obtain a smart card clock signal. In sync mode, input data is sampled on

the rise of CLK, and output data is changed on the fall of CLK.

Rev. 1.4

75

73S1210F Data Sheet

DS_1210F_001

Special Notes Regarding Synchronous Mode Operation

When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card

interface operates in synchronous mode and there are changes in the definition and behavior of pertinent

register bits and associated circuitry. The following requirements are to be noted:

1. The source for the smart card clock (CLK or SCLK) is the ETU counter. Only the actively selected

interface can have a running synchronous clock. In contrast, an unselected interface may have a

running clock in the asynchronous mode of operation.

2. The control bits CLKLVL, SCLKLVL, CLKOFF, and SCLKOFF are functional in synchronous mode.

When the CLKOFF bit is set, it will not truncate either the logic low or logic high period when the (stop

at) level is of opposite polarity. The CLK/SCLK signal will complete a correct logic low or logic high

duty cycle before stopping at the selected level. The CLK “start” is a result of the falling edge of the

CLKOFF bit. Setting clock to run when it is stopped low will result in a half period of low before going

high. Setting clock to run when it is stopped high will result in the clock going low immediately and

then running at the selected rate with 50% duty cycle (within the limitations of the ETU divisor value).

3. The Rlen(7:0) is configured to count the falling edges of the ETU clock (CLK or SCLK) after it has

been loaded with a value from 1 to 255. A value of 0 disables the counting function and RLen

functions such as I/O source selection (I/O signal bypasses the FIFOs and is controlled by the

SCCLK/SCECLK SFRs). When the RLen counter reaches the “max” (loaded) value, it sets the

WAITTO interrupt (SCInt, bit 7), which is maskable via WTOIEN (SCIE, bit 7). It must be reloaded in

order to start the counting/clocking process again. This allows the processor to select the number of

CLK cycles and hence, the number of bits to be read or written to/from the card.

4. The FIFO is not clocked by the first CLK (falling) edge resulting from a CLKOFF de-assertion (a clock

start event) when the CLK was stopped in the high state and RLen has been loaded but not yet

clocked.

5. The state of the pin IO or SIO is sampled on the rising edge of CLK/SCLK and stored in bit 5 of the

SCCtl/SCECtl register.

6. When Rlen = max or 0 and I2CMODE= 1 (STXCtl, b7), the IO or SIO signal is directly controlled by the

data and direction bits in the respective SCCtl and SCECtl register. The state of the data in the TX

FIFO is bypassed.

7. In the SPrtcol register, bit 6 (MODE9/8B) becomes active. When set, the RXData FIFO will read

nine-bit words with the state of the ninth bit being readable in SRXCtl, bit 7 (B9DAT). The RXDAV

interrupt will occur when the ninth bit has been clocked in (rising edge of CLK or SCLK).

8. Care must be taken to clear the RX and TX FIFOs at the start of any transaction. The user shall read

the RX FIFO until it indicates empty status. Reading the TX FIFO twice will reset the input byte

pointer and the next write to the TX FIFO will load the byte to the “first out” position. Note that the bit

pointer (serializer/deserializer) is reset to bit 0 on any change of the TX/RXD bit.

Special bits that are only active for sync mode include: SRXCtl, b7 “BIT9DAT”, SPrtcol, b6 “MODE9/8B”,

STXCtl, b7 “I2CMODE”, and the definition of SCInt, b7, which was “WAITTO”, becomes RLenINT interrupt,

and SCIE, b7, which was “WTOIEN”, becomes RLenIEN.

76

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

VCCSEL

bits

VCC

VCCOK

RSTCRD

RST

t3

CLK

IO

t4

t1

t2

tto

t1: The time from setting VCCSEL bits until VCCOK = 1.

tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),

activation starts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when

sequence is starting.

t2: time from start of activation (no external indication) until IO goes into reception mode (= 1). This is approximately

4 SCCLK (or SCECLK) clock cycles.

t3: minimum one half of ETU period.

t4: ETU period.

Note that in Sync mode, IO as input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK,

either from the card or from the 73S1210F. The RST signal to the card is directly controlled by the RSTCRD bit

(non-inverted) via the MPU and is shown as an example of a possible RST pattern.

Figure 20: Synchronous Activation

IO reception on

5

2

RST

CLK

1

CLKOFF

CLKLVL

RLength Count

RLenght = 1

7

Count MAX

3

4

Rlength Interrupt

6

TX/RXB Mode bit

(TX = '1')

t1

t1. CLK wll start at least 1/2 ETU after CLKOFF is set low

when CLKLVL = 0

1. Clear CLKOFF after Card is in reception mode.

2. Set RST bit.

3. Interrupt is generated when Rlength counter is MAX.

4. Read and clear Interrupt.

5. Clear RST bit.

6. Toggle TX/RXB to reset bit counter.

7. Reload RLength Counter.

Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals

Rev. 1.4

77

73S1210F Data Sheet

DS_1210F_001

START Bit

CLK

IO

Data from Card -end of ATR

Data from TX FIFO

6

RLength

Count MAX

RLen=0

Rlen=1

RLength Count - was set for length of ATR

5

1

2

RLength Interrupt

CLK Stop

3

CLK Stop Level

IO Bit

7

IODir Bit

6

TX/RX Mode Bit

TX = '1'

4

1. Interrupt generated when Rlength counter is MAX.

2. Read and clear Interrupt.

3. Set CLK Stop and CLK Stop level high in Interrupt routine.

4. Set TX/RX Bit to TX mode.

5. Reload Rlength Counter.

6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.

7. Clear CLK Stop and CLK Stop level.

Note: Data in TX fifo should not be Empty here.

Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to

generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.

Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode

CLK

I2CMode = 1: Data to/from Card

I2CMode = 0: Data from TX fifo

I2CMode = 1:ACK Bit (to/from card)

I2CMode = 0: Data from TX fifo

IO

6

RLength Count MAX

2

RLength Count

(Rlength = 9)

STOP Bit

1

RLength Interrupt

CLK Stop

8

3

CLK Stop Level

IO Bit

7

4

IODir Bit

TX/RX Mode Bit

TX = '1'

5

TX/RX mode

1. Interrupt generated when Rlength counter is MAX.

2. Read and clear Interrupt.

3. Set CLK Stop and CLK Stop level high.

4. Set IO Bit low and IODir = Output.

5. Set TX/RX Bit to TX mode.

6. Reload Rlength Counter.

7. Set IO Bit High and IODir = Output.

8. Clear CLK Stop and CLK Stop level.

Note: Data in TX fifo should not be Empty here.

Synchronous Clock Start/Stop Mode Stop bit procedure. This procedure should be used to

generate the Stop bit in Synchronous Mode. SYCKST is bit 7 of STXCTL register.

Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode

78

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

CLK

IO

Data from Card

(Bit 8)

Protection Bit

(Bit 9)

Data from Card

(Bit 1)

RLength Count MAX

RLength Count

RLength = 9

Rlen=8

Rlen=0

Rlen =1

Rlen=9

RLength Interrupt

RX data

RX FIFO

(Data from Card is ready for CPU read)

Protection Bit Data

(Bit 9)

Protection Bit is ready for CPU read

TX/RX Mode Bit

TX = '1'

1._ Interrupt generated

when Rlength counter is

Max

3._ Reload RLength

counter

2._ Read and clear

Interrupt

Receive data in 9 bit mode

CLK

RLength Count

RLength = 9

RLength Count MAX

Rlen=9

Rlen=8

RLength Interrupt

CLK Stop

CLK Stop Level = 0

2._Stop CLK after the last

byte and protection bit

1._ Interrupt generated

when Rlength counter is Max

Stop CLK after receiving the last byte and protection bit.

Figure 24: Operation of 9-bit Mode in Sync Mode

Synchronous card operation is broken down into three primary types. These are commonly referred to as

2-wire, 3-wire and I2C synchronous cards. Each card type requires different control and timing and

therefore requires different algorithms to access. Teridian has created an application note to provide

detailed algorithms for each card type. Refer to the application note titled “73S12xxF Synchronous Card

Design Application Note”.

Rev. 1.4

79

73S1210F Data Sheet

DS_1210F_001

1.7.15.6 Smart Card SFRs

Smart Card Select Register (SCSel): 0xFE00  0x00

The Smart Card Select register is used to determine which smart card interface is using the ISO UART.

The internal Smart Card has integrated 7816-3 compliant sequencer circuitry to drive an external smart

card interface. The external smart card interface relies on 73S8010 parts to generate the ISO 7816-3

compatible signals and sequences. Multiple 73S8010 devices can be connected to the external smart

card interface.

Table 72: The SCSel Register

MSB

LSB

–

SELSC.1 SELSC.0 BYPASS

–

Bit

Symbol

Function

SCSel.7

SCSel.6

SCSel.5

SCSel.4

–

Select Smart Card Interface - These bits select the interface that is using

the IS0 UART. These bits do not activate the interface. Activation is

performed by the VccCtl register.

SCSel.3

SCSel.2

SELSC.1

SELSC.0

00 = No smart card interface selected.

01 = External Smart Card Interface selected (using SCLK, SIO).

1X = Internal Smart Card Interface selected.

1 = Enabled, 0 = Disabled. When enabled, ISO UART is bypassed and the

I/O line is controlled via the SCCtl and SCECtl registers.

SCSel.1

SCSel.0

BYPASS

–

80

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Smart Card Interrupt Register (SCInt): 0xFE01  0x00

When the smart card interrupt is asserted, the firmware can read this register to determine the actual

cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be disabled by

the Smart Card Interrupt Enable register. Error processing must be handled by the firmware. This

register relates to the interface that is active – see the SCSel register (above).

Table 73: The SCInt Register

MSB

LSB

WAITTO CRDEVT VCCTMRI RXDAV TXEVT TXSENT TXERR RXERR

Bit

Symbol

Function

Wait Timeout - An ATR or card wait timeout has occurred. In sync mode,

this interrupt is asserted when the RLen counter (it advances on falling

edges of CLK/ETU) reaches the loaded (max) value. This bit is cleared

when the SCInt register is read. When running in Synchronous Clock

Stop Mode, this bit becomes RLenINT interrupt (set when the Rlen

counter reaches the terminal count).

SCInt.7

WAITTO

Card Event - A card event is signaled via pin DETCARD either when the

Card was inserted or removed (read the CRDCtl register to determine

card presence) or there was a fault condition in the interface circuitry.

This bit is functional even if the smart card logic clock is disabled and

when the PWRDN bit is set. This bit is cleared when the SCInt register is

read.

SCInt.6

SCInt.5

SCInt.4

CRDEVT

VCCTMRI

RXDAV

VCC Timer - This bit is set when the VCCTMR times out. This bit is

cleared when the SCInt register is read.

Rx Data Available - Data was received from the smart card because the

Rx FIFO is not empty. In bypass mode, this interrupt is generated on a

falling edge of the smart card I/O line. After receiving this interrupt in

bypass mode, firmware should disable it until the firmware has received

the entire byte and is waiting for the next start delimiter. This bit is

cleared when there is no RX data available in the RX FIFO.

TX Event - Set whenever the TXEMTY or TXFULL bits are set in the

SRXCtl SFR. This bit is cleared when the STXCtl register is read.

SCInt.3

SCInt.2

TXEVNT

TXSENT

TX Sent - Set whenever the ISO UART has successfully transmitted a

byte to the smart card. Also set when a CRC/LRC byte is sent in T=1

mode. Will not be set in T=0 when a break is detected at the end of a

byte (when break detection is enabled). This bit is cleared when the

SCInt register is read.

TX Error - An error was detected during the transmission of data to the

smart card as indicated by either BREAKD or TXUNDR bit being set in

the STXCtl SFR. Additional information can be found in that register

description. This bit is cleared when the STXCtl register is read.

SCInt.1

SCInt.0

TXERR

RXERR

RX Error - An error was detected during the reception of data from the

smart card. Additional information can be found in the SRXCtl register.

This interrupt will be asserted for RXOVRR, or RX Parity error events.

This bit is cleared when the SRXCtl register is read.

Rev. 1.4

81

73S1210F Data Sheet

DS_1210F_001

Smart Card Interrupt Enable Register (SCIE): 0xFE02  0x00

When set to 1, the respective condition can cause a smart card interrupt. When set to a 0, the respective

condition cannot cause an interrupt. When disabled, the respective bit in the Smart Card Interrupt

register can still be set, but it will not interrupt the MPU.

Table 74: The SCIE Register

MSB

LSB

WTOIEN CDEVEN VTMREN RXDAEN TXEVEN TXSNTEN TXEREN RXEREN

Bit

Symbol

Function

Wait Timeout Interrupt Enable - Enable for ATR or Wait Timeout Interrupt.

In sync mode, function is RLIEN (RLen = max.) interrupt enable.

SCIE.7

WTOIEN

SCIE.6

SCIE.5

SCIE.4

SCIE.3

SCIE.2

SCIE.1

SCIE.0

CDEVEN Card Event Interrupt Enable.

VTMREN VCC Timer Interrupt Enable.

RXDAEN Rx Data Available Interrupt Enable.

TXEVEN

TXSNTEN TX Sent Interrupt Enable.

TXEREN TX Error Interrupt Enable.

RXEREN RX Error Interrupt Enable.

TX Event Interrupt Enable.

82

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Smart Card V_CCControl/Status Register (VccCtl): 0xFE03  0x00

This register is used to control the power up and power down of the integrated smart card interface. It is

used to determine whether to apply 5V, 3V, or 1.8 to the smart card. Perform the voltage selection with

one write operation, setting both VCCSEL.1 and VCCSEL.0 bits simultaneously. The VDDFLT bit (if

enabled) will provide an emergency deactivation of the internal smart card slot. See the VDD Fault

Detect Function section for more detail.

Table 75: The VccCtl Register

MSB

LSB

SCPWRDN

VCCSEL.1 VCCSEL.0 VDDFLT

RDYST

VCCOK

–

Bit

Symbol

Function

Setting non-zero value for bits 7,6 will begin activation sequence with target

Vcc as given below:

VccCtl.7

VCCSEL.1

State VCCSEL.1

VCCSEL.0

VCC

0V

1

2

3

4

0

1

0

1

0

1

1.8V

3.0V

5V

A card event or VCCOK going low will initiate a deactivation sequence.

When the deactivation sequence for RST, CLK and I/O is complete, V_CCwill

be turned off. When this type of deactivation occurs, the bits must be reset

before initiating another activation.

VccCtl.6

VCCSEL.0

When there is a VDD Fault event, this bit will be set = 0. This causes

VCCSEL.1 and VCCSEL.0 bits to be immediately set = 0 to begin

deactivation.

VccCtl.5

VccCtl.4

VDDFLT

RDYST

If this bit is set = 1, the activation sequence will start when bit VCCOK is set =

1. If not set, the deactivation sequence shall start when the VCCTMR times

out.

VccCtl.3

VccCtl.2

VccCtl.1

VCCOK

(Read only). Indicates that V_CCoutput voltage is stable.

–

This bit controls the power-off mode of the 73S1210F circuit.

1 = power off, 0 = normal operation. When in power down mode,

V_DD= 0V. V_DDcan only be turned on by pressing the ON/OFF switch or by

application of 5V to V_BUS. If V_BUSpower is available and SCPWRDN bit is set,

it has no effect until V_BUSis removed and V_DDwill shut off.

VccCtl.0 SCPWRDN

Rev. 1.4

83

73S1210F Data Sheet

DS_1210F_001

V_CCStable Timer Register (VccTmr): 0xFE04  0x0F

A programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and

VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of this

timers programmed interval (tto in Figure 16) in order for the activation sequence to continue. If VCC_OK

is not true and the end of the interval (tto), the Card Event interrupt will be set, and a deactivation

sequence shall begin including clearing of the VCCSEL bits.

Table 76: The VccTmr Register

MSB

LSB

OFFTMR.3 OFFTMR.2 OFFTMR.1 OFFTMR.0 VCCTMR.3 VCCTMR.2 VCCTMR.1 VCCTMR.0

Bit

Symbol

Function

VccTmr.7 OFFTMR.3 VCC Off Timer - The bits set the delay (in number of ETUs) for

deactivation after the VCCSEL.1 and VCC SEL.0 have been set

to 0. The time value is a count of the 32768Hz clock and is given

by tto = OFFTMR(7:4) * 30.5µs. This delay does not affect

emergency deactivations due to VDD Fault or card events. A

VccTmr.6 OFFTMR.2

VccTmr.5 OFFTMR.1

VccTmr.4 OFFTMR.0

value of 0000 results in no additional delay.

VccTmr.3 VCCTMR.3 VCC Timer - VCCOK must be true at the time set by the value in

these bits in order for the activation sequence to continue. If not,

the VCCSEL bits will be cleared. The time value is a count of the

32768Hz clock and is given by tto = VCCTMR(3:0) * 30.5µs. A

value of 0000 results in no timeout, not zero time, and activation

requires that RDYST is set and RDY goes high.

VccTmr.2 VCCTMR.2

VccTmr.1 VCCTMR.1

VccTmr.0 VCCTMR.0

84

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Card Status/Control Register (CRDCtl): 0xFE05  0x00

This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This

register must be written to properly configure Debounce, Detect_Polarity (= 0 or = 1), and the pull-

up/down enable before setting CDETEN. The card detect logic is functional even without smart card logic

clock. When the PWRDN bit is set = 1, no debounce is provided but card presence is operable.

Table 77: The CRDCtl Register

MSB

LSB

DEBOUN CDETEN

–

DETPOL PUENB

PDEN

CARDIN

Bit

Symbol

Function

Debounce - When set = 1, this will enable hardware debounce of

the card detect pin. The debounce function shall wait for 64ms of

stable card detect assertion before setting the CARDIN bit. This

counter/timer uses the keypad clock as a source of 1kHz signal.

De-assertion of the CARDIN bit is immediate upon de-assertion

of the card detect pin(s).

CRDCtl.7

DEBOUN

Card Detect Enable - When set = 1, activates card detection

input. Default upon power-on reset is 0.

CRDCtl.6

CDETEN

CRDCtl.5

CRDCtl.4

–

Detect Polarity - When set = 1, the DETCARD pin shall interpret

a logic 1 as card present.

CRDCtl.3

DETPOL

CRDCtl.2

CRDCtl.1

PUENB

PDEN

Enable pull-up current on DETCARD pin (active low).

Enable pull-down current on DETCARD pin.

Card Inserted - (Read only). 1 = card inserted, 0 = card not

inserted. A change in the value of this bit is a “card event.” A

read of this bit indicates whether smart card is inserted or not

inserted in conjunction with the DETPOL setting.

CRDCtl.0

CARDIN

Rev. 1.4

85

73S1210F Data Sheet

DS_1210F_001

TX Control/Status Register (STXCtl): 0xFE06  0x00

This register is used to control transmission of data to the smart card. Some control and some status bits

are in this register.

Table 78: The STXCtl Register

MSB

LSB

I2CMODE

–

TXFULL TXEMTY TXUNDR LASTTX TX/RXB BREAKD

Bit

Symbol

Function

I2C Mode - When in sync mode and this bit is set, and when the RLen count

value = max or 0, the source of the smart card data for IO pin (or SIO pin) will

be connected to the IO bit in SCCtl (or SCECtl) register rather than the TX

FIFO. See the description for the Protocol Mode Register for more detail.

STXCtl.7

I2CMODE

–

STXCtl.6

STXCtl.5

TX FIFO is full. Additional writes may corrupt the contents of the FIFO. This

TXFULL bit it will remain set as long as the TX FIFO is full. Generates a TX_Event

interrupt upon going full.

1 = TX FIFO is empty, 0 = TX FIFO is not empty. If there is data in the TX

FIFO, the circuit will transmit it to the smart card if in transmit mode. In T=1

mode, if the LASTTX bit is set and the hardware is configured to transmit the

TXEMTY CRC/LRC, the TXEMTY will not be set until the CRC/LRC is transmitted. In

T=0, if the LASTTX bit is set, TXEMTY will be set after the last word has

been successfully transmitted to the smart card. Generates a TXEVNT

interrupt upon going empty.

STXCtl.4

TX Underrrun - (Read only) Asserted when a transmit under-run condition

has occurred. An under-run condition is defined as an empty TX FIFO when

the last data word has been successfully transmitted to the smart card and

the LASTTX bit was not set. No special processing is performed by the

hardware if this condition occurs. Cleared when read by firmware. This bit

generates a TXERR interrupt.

STXCtl.3

STXCtl.2

TXUNDR

Last TX Byte - Set by firmware (in both T=0 and T=1) when the last byte in

the current message has been written into the transmit FIFO. In T=1 mode,

the CRC/LRC will be appended to the message. Should be set after the last

LASTTX

byte has been written into the transmit FIFO. Should be cleared by firmware

before writing first byte of next message into the transmit FIFO. Used in T=0

to determine when to set TXEMTY.

1 = Transmit mode, 0 = Receive mode. Configures the hardware to be

receiving from or transmitting to the smart card. Determines which counters

should be enabled. This bit should be set to receive mode prior to switching

TX/RXB to another interface. Setting and resetting this bit shall initialize the CRC

logic. If LASTTX is set, this bit can be reset to RX mode and UART logic will

automatically change mode to RX when TX operation is completed

(TX_Empty = 1).

STXCtl.1

STXCtl.0

Break Detected - (Read only) 1 = A break has been detected on the I/O line

BREAKD indicating that the smart card detected a parity error. Cleared when read.

This bit generates a TXERR interrupt.

86

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

STX Data Register (STXData): 0xFE07  0x00

Table 79: The STXData Register

MSB

LSB

STXDAT.7 STXDAT.6 STXDAT.5 STXDAT.4 STXDAT.3 STXDAT.2 STXDAT.1 STXDAT.0

Bit

Function

STXData.7

STXData.6

STXData.5

STXData.4

STXData.3

STXData.2

STXData.1

STXData.0

Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by

the hardware and sent to the selected smart card. When the MPU reads this register,

the byte pointer is changed to effectively “read out” the data. Thus, two reads will

always result in an “empty” FIFO condition. The contents of the FIFO registers are not

cleared, but will be overwritten by writes.

SRX Control/Status Register (SRXCtl): 0xFE08  0x00

This register is used to monitor reception of data from the smart card.

Table 80: The SRXCtl Register

MSB

LSB

BIT9DAT

–

LASTRX CRCERR RXFULL RXEMTY RXOVRR PARITYE

Bit

Symbol

Function

Bit 9 Data - When in sync mode and with MODE9/8B set, this bit will contain

SRXCtl.7

BIT9DAT the data on IO (or SIO) pin that was sampled on the ninth CLK (or SCLK)

rising edge. This is used to read data in synchronous 9-bit formats.

SRXCtl.6

SRXCtl.5

–

Last RX Byte - User sets this bit during the reception of the last byte. When

byte is received and this bit is set, logic checks CRC to match 0x1D0F (T=1

mode) or LRC to match 00h (T=1 mode), otherwise a CRC or LRC error is

LASTRX

asserted.

SRXCtl.4

SRXCtl.3

CRCERR (Read only) 1 = CRC (or LRC) error has been detected.

RXFULL

(Read only) RX FIFO is full. Status bit to indicate RX FIFO is full.

(Read only) RX FIFO is empty. This is only a status bit and does not generate

an RX interrupt.

SRXCtl.2

RXEMTY

RX Overrun - (Read Only) Asserted when a receive-over-run condition has

occurred. An over-run is defined as a byte was received from the smart card

when the RX FIFO was full. Invalid data may be in the receive FIFO.

Firmware should take appropriate action. Cleared when read. Additional

writes to the RX FIFO are discarded when a RXOVRR occurs until the overrun

condition is cleared. Will generate an RXERR interrupt.

SRXCtl.1

RXOVRR

Parity Error - (Read only) 1 = The logic detected a parity error on incoming

SRXCtl.0

PARITYE data from the smart card. Cleared when read. Will generate an RXERR

interrupt.

Rev. 1.4

87

73S1210F Data Sheet

DS_1210F_001

SRX Data Register (SRXData): 0xFE09  0x00

Table 81: The SRXData Register

MSB

LSB

SRXDAT.7 SRXDAT.6 SRXDAT.5 SRXDAT.4 SRXDAT.3 SRXDAT.2 SRXDAT.1 SRXDAT.0

Bit

Function

SRXData.7

SRXData.6

SRXData.5

SRXData.4

SRXData.3

SRXData.2

SRXData.1

SRXData.0

(Read only) Data received from the smart card. Data received from the smart

card gets stored in a FIFO that is read by the firmware.

88

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Smart Card Control Register (SCCtl): 0xFE0A  0x21

This register is used to monitor reception of data from the smart card.

Table 82: The SCCtl Register

MSB

LSB

CLKLVL CLKOFF

RSTCRD

–

IO

IOD

C8

C4

Bit

Symbol

Function

1 = Asserts the RST (set RST = 0) to the smart card interface, 0 = De-assert

the RST (set RST = 1) to the smart card interface. Can be used to extend

RST to the smart card. Refer to RLength register description. This bit is

operational in all modes and can be used to extend RST during activation or

perform a “Warm Reset” as required. In auto-sequence mode, this bit should

be set = 0 to allow the sequencer to de-assert RST per the RLength

parameters.

SCCtl.7

RSTCRD

In sync mode (see the SPrtcol register) the sense of this bit is non-inverted, if

set = 1, RST = 1, if set = 0, RST = 0. Rlen has no effect on Reset in sync

mode.

SCCtl.6

SCCtl.5

–

Smart Card I/O. Read is state of I/O signal (Caution, this signal is not

synchronized to the MPU clock). In Bypass mode, write value is state of

signal on I/O. In sync mode, this bit will contain the value of I/O pin on the

latest rising edge of CLK.

IO

Smart Card I/O Direction control Bypass mode or sync mode. 1 = input

(default), 0 = output.

SCCtl.4

SCCtl.3

IOD

C8

Smart Card C8. When C8 is an output, the value written to this bit will appear

on the C8 line. The value read when C8 is an output is the value stored in

the register. When C8 is an input, the value read is the value on the C8 pin

(Caution, this signal is not synchronized to the MPU clock). When C8 is an

input, the value written will be stored in the register but not presented to the

C8 pin.

Smart Card C4. When C4 is an output, the value written to this bit will appear

on the C4 line. The value read when C4 is an output is the value stored in

the register. When C4 is an input, the value read is the value on the C4 pin

(Caution, this signal is not synchronized to the MPU clock). When C4 is an

input, the value written will be stored in the register but not presented to the

C4 pin.

SCCtl.2

C4

1 = High, 0 = Low. If CLKOFF is set = 1, the CLK to smart card will be at the

logic level indicated by this bit. If in bypass mode, this bit directly controls the

state of CLK.

SCCtl.1

SCCtl.0

CLKLVL

CLKOFF

0 = CLK is enabled. 1 = CLK is not enabled. When asserted, the CLK will

stop at the level selected by CLKLVL. This bit has no effect if in bypass

mode.

Rev. 1.4

89

73S1210F Data Sheet

DS_1210F_001

External Smart Card Control Register (SCECtl): 0xFE0B  0x00

This register is used to directly set and sample signals of External Smart Card interface. There are three

modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per

the ISO 7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for

I²C clock stop and start. Control for Reset (to make RST signal), activation control, voltage select, etc.

should be handled via the I²C interface when using external 73S8010 devices. USR(n) pins shall be

used for C4, C8 functions if necessary.

Table 83: The SCECtl Register

MSB

LSB

SCLKLVL SCLKOFF

–

SIO

SIOD

–

Bit

Symbol

Function

SCECtl.7

SCECtl.6

–

External Smart Card I/O. Bit when read indicates state of pin SIO for SIOD

= 1 (Caution, this signal is not synchronized to the MPU clock), when

written, sets the state of pin SIO for SIOD = 0. Ignored if not in bypass or

sync modes. In sync mode, this bit will contain the value of IO pin on the

latest rising edge of SCLK.

SCECtl.5

SIO

1 = input, 0 = output. External Smart Card I/O Direction control. Ignored if

not in bypass or sync modes.

SCECtl.4

SIOD

SCECtl.3

SCECtl.2

–

Sets the state of SCLK when disabled by SCLKOFF bit. If in bypass mode,

this bit directly controls the state of SCLK.

SCECtl.1

SCECtl.0

SCLKLVL

SCLKOFF

0 = SCLK enabled, 1 = SCLK disabled. When disabled, SCLK level is

determined by SCLKLVL. This bit has no effect if in bypass mode.

90

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

C4/C8 Data Direction Register (SCDIR): 0xFE0C  0x00

This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are

tri-stated.

Table 84: The SCDIR Register

MSB

LSB

–

C8D

C4D

–

Bit

Symbol

Function

SCDIR.7

SCDIR.6

SCDIR.5

SCDIR.4

SCDIR.3

SCDIR.2

SCDIR.1

SCDIR.0

–

C8D

C4D

–

1 = input, 0 = output. Smart Card C8 direction.

1 = input, 0 = output. Smart Card C4 direction.

–

Rev. 1.4

91

73S1210F Data Sheet

DS_1210F_001

Protocol Mode Register (SPrtcol): 0xFE0D  0x03

This register determines the protocol to be use when communicating with the selected smart card. This

register should be updated as required when switching between smart card interfaces.

Table 85: The SPrtcol Register

MSB

SCISYN MOD9/8B SCESYN

LSB

0

TMODE CRCEN CRCMS RCVATR

Bit

Symbol

Function

Smart Card Internal Synchronous mode - Configures internal smart card

interface for synchronous mode. This mode routes the internal interface

buffers for RST, IO, C4, C8 to the SCCtl register bits for direct firmware

control. CLK is generated by the ETU counter.

SPrtcol.7

SCISYN

Synchronous 8/9 bit mode select - For sync mode, in protocols with 9-bit

SPrtcol.6

SPrtcol.5

MOD9/8B words, set this bit. The first eight bits read go into the RX FIFO and the

ninth bit read will be stored in the IO (or SIO) data bit of the SRXCtl register.

Smart Card External Synchronous mode - Configures External Smart Card

interface for synchronous mode. This mode routes the external smart card

interface buffers for SIO to SCECtl register bits for direct firmware control.

SCESYN

SCLK is generated by the ETU counter.

SPrtcol.4

SPrtcol.3

0

Reserved bit, must always be set to 0.

Protocol mode select - 0: T=0, 1: T=1. Determines which smart card

protocol is to be used during message processing.

TMODE

CRC Enable – 1 = Enabled, 0 = Disabled. Enables the checking/generation

of CRC/LRC while in T=1 mode. Has no effect in T=0 mode. If enabled and

a message is being transmitted to the smart card, the CRC/LRC will be

inserted into the message stream after the last TX byte is transmitted to the

smart card. If enabled, CRC/LRC will be checked on incoming messages

and the value made available to the firmware via the CRC LS/MS registers.

SPrtcol.2

CRCEN

CRCMS

CRC Mode Select – 1 = CRC, 0 = LRC. Determines type of checking

algorithm to be used.

SPrtcol.1

SPrtcol.0

Receive ATR – 1 = Enable ATR timeout, 0 = Disable ATR timeout. Set by

RCVATR firmware after the smart card has been turned on and the hardware is

expecting ATR.

92

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

SC Clock Configuration Register (SCCLK): 0xFE0F  0x0C

This register controls the internal smart card (CLK) clock generation.

Table 86: The SCCLK Register

MSB

LSB

ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0

–

Bit

Symbol

–

Function

SCCLK.7

SCCLK.6

SCCLK.5

SCCLK.4

SCCLK.3

SCCLK.2

SCCLK.1

SCCLK.0

–

ICLKFS.5

ICLKFS.4

ICLKFS.3

ICLKFS.2

ICLKFS.1

ICLKFS.0

Internal Smart Card CLK Frequency Select - Division factor to determine

internal smart card CLK frequency. MCLK clock is divided by (register

value + 1) to clock the ETU divider, and then by 2 to generate CLK.

Default ratio is 13. The programmed value in this register is applied to the

divider after this value is written, in such a manner as to produce a

glitch-free output, regardless of the selection of active interface. A

register value = 0 will default to the same effect as register value = 1.

External SC Clock Configuration Register (SCECLK): 0xFE10  0x0C

This register controls the external smart card (SCLK) clock generation.

Table 87: The SCECLK Register

MSB

LSB

–

ECLKFS.5 ECLKFS.4 ECLKFS.3 ECLKFS.2 ECLKFS.1

ECLKFS.0

Bit

Symbol

Function

SCECLK.7

SCECLK.6

–

SCECLK.5 ECLKFS.5

SCECLK.4 ECLKFS.4

SCECLK.3 ECLKFS.3

SCECLK.2 ECLKFS.2

SCECLK.1 ECLKFS.1

SCECLK.0 ECLKFS.0

External Smart Card CLK Frequency Select - Division factor to determine

external smart card CLK frequency. MCLK clock is divided by (register

value + 1) to clock the ETU divider, and then by 2 to generate SCLK.

Default ratio is 13. The programmed value in this register is applied to the

divider after this value is written, in such a manner as to produce a

glitch-free output, regardless of the selection of active interface. A

register value = 0 will default to the same effect as register value = 1.

Rev. 1.4

93

73S1210F Data Sheet

DS_1210F_001

Parity Control Register (SParCtl): 0xFE11  0x00

This register provides the ability to configure the parity circuitry on the smart card interface. The settings

apply to both integrated smart card interfaces.

Table 88: The SParCtl Register

MSB

LSB

–

DISPAR BRKGEN BRKDET RETRAN DISCRX

Symbol Function

INSPE FORCPE

Bit

SParCtl.7

–

Disable Parity Check – 1 = disabled, 0 = enabled. If enabled, the UART will

check for even parity (the number of 1’s including the parity bit is even) on

every character. This also applies to the TS during ATR.

SParCtl.6

DISPAR

Break Generation Disable – 1 = disabled, 0 = enabled. If enabled, and T=0

protocol, the UART will generate a Break to the smart card if a parity error is

detected on a receive character. No Break will be generated if parity

checking is disabled. This also applies to TS during ATR.

SParCtl.5

BRKGEN

BRKDET

Break Detection Disable – 1 = disabled, 0 = enabled. If enabled, and T=0

protocol, the UART will detect the generation of a Break by the smart card.

SParCtl.4

SParCtl.3

Retransmit Byte – 1 = enabled, 0 = disabled. If enabled and a Break is

RETRAN detected from the smart card (Break Detection must be enabled), the last

character will be transmitted again. This bit applies to T=0 protocol.

Discard Received Byte – 1 = enabled, 0 = disabled. If enabled and a parity

SParCtl.2

SParCtl.1

SParCtl.0

DISCRX

INSPE

error is detected (Parity checking must be enabled), the last character

received will be discarded. This bit applies to T=0 protocol.

Insert Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If

enabled, the UART will insert a parity error in every character transmitted by

generating odd parity instead of even parity for the character.

Force Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If

FORCPE enabled, the UART will generate a parity error on a character received from

the smart card.

94

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Byte Control Register (SByteCtl): 0xFE12  0x2C

This register controls the processing of characters and the detection of the TS byte. When receiving, a

Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is sampled at 11

ETU.

Table 89: The SByteCtl Register

MSB

LSB

–

DETTS

Symbol

DIRTS BRKDUR.1 BRKDUR.0

Function

–

Bit

SByteCtl.7

–

Detect TS Byte – 1 = Next Byte is TS, 0 = Next byte is not TS. When set, the

hardware will treat the next character received as the TS and determine if

direct or indirect convention is being used. Direct convention is the default

used if firmware does not set this bit prior to transmission of TS by the smart

card to the firmware. The hardware will check parity and generate a break as

defined by the DISPAR and BRKGEN bits in the parity control register. This

bit is cleared by hardware after TS is received. TS is decoded prior to the

FIFO and is stored in the receive FIFO.

SByteCtl.6

DETTS

Direct Mode TS Select – 1 = direct mode, 0 = indirect mode. Set/cleared by

hardware when TS is processed indicating either direct/indirect mode of

operation. When switching between smart cards, the firmware should write

the bit appropriately since this register is not unique to an individual smart

card (firmware should keep track of this bit).

SByteCtl.5

DIRTS

Break Duration Select – 00 = 1 ETU, 01 = 1.5 ETU, 10 = 2 ETU,

11 = reserved. Determines the length of a Break signal which is generated

when detecting a parity error on a character reception in T=0 mode.

SByteCtl.4 BRKDUR.1

SByteCtl.3 BRKDUR.0

SByteCtl.2

SByteCtl.1

SByteCtl.0

–

Rev. 1.4

95

73S1210F Data Sheet

DS_1210F_001

FD Control Register (FDReg): 0xFE13  0x11

This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register

are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is

created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created

by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and

DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to divide by 2 * 372 = 744. The

maximum supported F/D ratio is 4096.

Table 90: The FDReg Register

MSB

FVAL.3

LSB

DVAL.0

FVAL.2

FVAL.1

FVAL.0

DVAL.3

DVAL.2

DVAL.1

Table 91: The FDReg Bit Functions

Function

Bit

Symbol

FVAL.3

FVAL.2

FVAL.1

FVAL.0

DVAL.3

DVAL.2

DVAL.1

DVAL.0

FDReg.7

FDReg.6

FDReg.5

FDReg.4

FDReg.3

FDReg.2

FDReg.1

FDReg.0

Refer to the Table 93 above. This value is converted per the table to

set the divide ratio used to generate the baud rate (ETU). Default,

also used for ATR, is 0001 (Fi = 372). This value is used by the

selected interface.

Refer to Table 93 above. This value is used to set the divide ratio

used to generate the smart card CLK. Default, also used for ATR, is

0001 (Di = 1).

Table 92: Divider Ratios Provided by the ETU Counter

FI (code)

0000

372

4

0001

372

5

0010

558

6

0011

744

8

0100

1116

12

0101

1488

16

0110

1860

20

0111

1860⊕

20⊕

Fi (ratio)

FCLK max

FI(code)

Fi(ratio)

1000

512⊕

5⊕

1001

512

5

1010

768

7.5

1011

1024

10

1100

1536

15

1101

2048

20

1110

2048⊕

20⊕

1111

2048⊕

20⊕

FCLK max

DI(code)

Di(ratio)

0000

0001

1

0010

2

0011

4

0100

8

0101

16

0110

32

0111

1⊕

32⊕

DI(code)

Di(ratio)

1000

12

1001

20

1010

1011

1100

1101

1110

1111

16⊕

Note: values marked with ⊕ are not included in the ISO definition and arbitrary values have been

assigned.

The values given below are used by the ETU divider to create the ETU clock. The entries that are not

shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are

within 1% of the target value.

96

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Table 93: Divider Values for the ETU Clock

Fi code 0000

0001

372

0010

558

0011

744

0100

1116

0101

1488

Di

code

372

F→

D↓

1

0001

0010

0011

0100

1000

0101

1001

0110

744

372

186

93

744

372

186

93

1116

558

279

138

93

1488

744

372

186

124

93

2232

1116

558

279

186

140

112

70

2976

1488

744

372

248

186

149

93

2

4

8

12

16

20

32

62

47

70

37

56

74

23

35

47

Fi code 0110

1001

512

1010

768

1011

1024

1100

1536

1101

2048

Di

code

1860

F→

D↓

1

0001

0010

0011

0100

1000

0101

1001

0110

3720

1860

930

465

310

233

186

116

1024

512

256

128

85

1536

768

384

192

128

96

2048

1024

512

256

171

128

102

64

3072

1536

768

384

256

192

154

96

4096

2048

1024

512

2

4

8

12

16

20

32

341

64

256

51

32

77

48

205

128

Rev. 1.4

97

73S1210F Data Sheet

DS_1210F_001

CRC MS Value Registers (CRCMsB): 0xFE14  0xFF, (CRCLsB): 0xFE15  0xFF

Table 94: The CRCMsB Register

MSB

LSB

CRC.15 CRC.14 CRC.13 CRC.12 CRC.11 CRC.10

CRC.9

CRC.1

CRC.8

MSB

CRC.7

LSB

CRC.6

CRC.5

CRC.4

CRC.3

CRC.2

CRC.0

The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode

(read value). The initial value of CRC to be used when generating a CRC to be transmitted at the end of

a message (after the last TX byte is sent) when enabled in T=1 mode. Should be reloaded at the

beginning of every message to be transmitted. When using CRC, both CRC registers should be

initialized to FF. When using LRC, the CRCLsB value register should be loaded to 00. When receiving a

message, the firmware should load this with the initial value and then read this register to get the final

value at the end of the message. These registers need to be reloaded for each new message to be

received. When in LRC mode, bits (7:0) are used and bits (15:8) are undefined. During LRC/CRC

checking and generation, this register is updated with the current value and can be read to aid in

debugging. This information will be transmitted to the smart card using the timing specified by the Guard

Time register. When checking CRC/LRC on an incoming message (CRC/LRC is checked against the

data and CRC/LRC), the firmware reads the final value after the message has been received and

determines if an error occurred (= 0x1D0F (CRC) no error, else error; = 0 (LRC) no error, else error).

When a message is received, the CRC/LRC is stored in the FIFO. The polynomial used to generate and

check CRC is x¹⁶+ x¹²+ x⁵+1. When in indirect convention, the CRC is generated prior to the conversion

into indirect convention. When in indirect convention, the CRC is checked after the conversion out of

indirect convention. For a given message, the CRC generated (and readable from this register) will be

the same whether indirect or direct convention is used to transmit the data to the smart card. The

CRCLsB / CRCMsB registers will be updated with CRC/LRC whenever bits are being received or

transmitted from/to the smart card (even if CRCEN is not set and in mode T1). They are available to the

firmware to use if desired.

98

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Block Guard Time Register (BGT): 0xFE16  0x10

This register contains the Extra Guard Time Value (EGT) most-significant bit. The Extra Guard Time

indicates the minimum time between the leading edges of the start bit of consecutive characters. The

delay is depends on the T=0/T=1 mode. Used in transmit mode. This register also contains the Block

Guard Time (BGT) value. Block Guard Time is the minimum time between the leading edge of the start

bit of the last character received and the leading edge of the start bit of the first character transmitted.

This should not be set less than the character length. The transmission of the first character will be held

off until BGT has elapsed regardless of the TX data and TX/RX control bit timing.

Table 95: The BGT Register

MSB

EGT.8

LSB

BGT.0

–

BGT.4

BGT.3

BGT.1

BGT.2

Bit

Symbol

EGT.8

–

Function

BGT.7

BGT.6

BGT.5

BGT.4

BGT.3

BGT.2

BGT.1

BGT.0

Most-significant bit for 9-bit EGT timer. See the EGT register.

–

BGT.4

BGT.3

BGT.2

BGT.1

BGT.0

Time in ETUs between the start bit of the last received character to

start bit of the first character transmitted to the smart card. Default

value is 22.

Extra Guard Time Register (EGT): 0xFE17  0x0C

This register contains the Extra Guard Time Value (EGT) least-significant byte. The Extra Guard Time

indicates the minimum time between the leading edges of the start bit of consecutive characters. The

delay depends on the T=0/T=1 mode. Used in transmit mode.

Table 96: The EGT Register

MSB

EGT.7

LSB

EGT.0

EGT.6

EGT.5

EGT.4

EGT.3

EGT.1

EGT.2

Bit

Function

EGT.7

EGT.6

EGT.5

EGT.4

EGT.3

EGT.2

EGT.1

EGT.0

Time in ETUs between start bits of consecutive characters. In T=0

mode, the minimum is 1. In T=0, the leading edge of the next start bit

may be delayed if there is a break detected from the smart card.

Default value is 12. In T=0 mode, regardless of the value loaded, the

minimum value is 12, and for T=1 mode, the minimum value is 11.

Rev. 1.4

99

73S1210F Data Sheet

DS_1210F_001

Block Wait Time Registers (BWTB0): 0xFE1B  0x00, (BWTB1): 0xFE1A  0x00,

(BWTB2): 0xFE19  0x00, (BWTB3): 0xFE18  0x00

These registers are used to set the Block Waiting Time(27:0) (BWT). All of these parameters define the

maximum time the 73S1210F will have to wait for a character from the smart card. These registers serve

a dual purpose. When T=1, these registers are used to set up the block wait time. The block wait time

defines the time in ETUs between the beginning of the last character sent to smart card and the start bit

of the first character received from smart card. It can be used to detect an unresponsive card and should

be loaded by firmware prior to writing the last TX byte. When T=0, these registers are used to set up the

work wait time. The work wait time is defined as the time between the leading edge of two consecutive

characters being sent to or from the card. If a timeout occurs, an interrupt is generated to the firmware.

The firmware can then take appropriate action. A Wait Time Extension (WTX) is supported with the 28-

bit BWT.

Table 97: The BWTB0 Register

MSB

BWT.7

LSB

BWT.0

BWT.6

BWT.5

BWT.4

BWT.3

BWT.1

BWT.2

BWT.9

Table 98: The BWTB1 Register

MSB

LSB

BWT.8

BWT.15 BWT.14 BWT.13 BWT.12 BWT.11 BWT.10

Table 99: The BWTB2 Register

MSB

LSB

BWT.23 BWT.22 BWT.21 BWT.20 BWT.19 BWT.18 BWT.17 BWT.16

Table 100: The BWTB3 Register

MSB

LSB

BWT.27 BWT.26 BWT.25 BWT.24

–

Character Wait Time Registers (CWTB0): 0xFE1D  0x00, (CWTB1): 0xFE1C  0x00

These registers are used to hold the Character Wait Time(15:0) (CWT) or Initial Waiting Time(15:0) (IWT)

depending on the situation. Both the IWT and the CWT measure the time in ETUs between the leading

edge of the start of the current character received from the smart card and the leading edge of the start of

the next character received from the smart card. The only difference is the mode in which the card is

operating. When T=1 these registers are used to configure the CWT and these registers configure the IWT

when the ATR is being received. These registers should be loaded prior to receiving characters from the

smart card. Firmware must manage which time is stored in the register. If a timeout occurs, an interrupt is

generated to the firmware. The firmware can then take appropriate action.

Table 101: The CWTB0 Register

MSB

CWT.7

LSB

CWT.0

CWT.6

CWT.5

CWT.4

CWT.3

CWT.1

CWT.2

CWT.9

Table 102: The CWTB1 Register

MSB

CWT.15 CWT.14 CWT.13 CWT.12 CWT.11 CWT.10

LSB

CWT.8

100

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

ATR Timeout Registers (ATRLsB): 0xFE20  0x00, (ATRMsB): 0xFE1F  0x00

These registers form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU between the leading

edge of the first character and leading edge of the last character of the ATR response. Timer is enabled

when the RCVATR is set and starts when leading edge of the first start bit is received and disabled when

the RCVATR is cleared. An ATR timeout is generated if this time is exceeded.

Table 103: The ATRLsB Register

MSB

ATRTO.7

LSB

ATRTO.6

ATRTO.5

ATRTO.4

ATRTO.3

ATRTO.1 ATRTO.2 ATRTO.0

Table 104: The ATRMsB Register

MSB

LSB

ATRTO.15 ATRTO.14 ATRTO.13 ATRTO.12 ATRTO.11 ATRTO.10 ATRTO.9 ATRTO.8

TS Timeout Register (STSTO): 0xFE21  0x00

The TS timeout is the time in ETU between the de-assertion of smart card reset and the leading edge of

the TS character in the ATR (when DETTS is set). The timer is started when smart card reset is

de-asserted. An ATR timeout is generated if this time is exceeded (MUTE card).

Table 105: The STSTO Register

MSB

TST0.7

LSB

TST0.0

TST0.6

TST0.5

TST0.4

TST0.3

TST0.1

TST0.2

Reset Time Register (RLength): 0xFE22  0x70

Time in ETUs that the hardware delays the de-assertion of RST. If set to 0 and RSTCRD = 0, the hardware

adds no extra delay and the hardware will release RST after VCCOK is asserted during power-up. If set to 1,

it will delay the release of RST by the time in this register. When the firmware sets the RSTCRD bit, the

hardware will assert reset (RST = 0 on pin). When firmware clears the bit, the hardware will release RST

after the delay specified in Rlen. If firmware sets the RSTCRD bit prior to instructing the power to be applied

to the smart card, the hardware will not release RST after power-up until RLen after the firmware clears the

RSTCRD bit. This provides a means to power up the smart card and hold it in reset until the firmware wants

to release the RST to the selected smart card. Works with the selected smart card interface.

Table 106: The RLength Register

MSB

RLen.7

LSB

RLen.0

RLen.6

RLen.5

RLen.4

RLen.3

RLen.1

RLen.2

Rev. 1.4

101

73S1210F Data Sheet

DS_1210F_001

Shaded locations indicate functions that are not provided in the synchronous mode.

Table 107: Smart Card SFR Table

Name

SCSel

SCInt

Address

FE00

b7

b6

b5

b4

b3

b2

b1

b0

SelSC(1:0)

BYPASS

TXERR

FE01

WAITTO/ CRDEVT

RLIEN

VCCTMR

VTMREN

RXDAVl

TXEVNT

TXSENT

RXERR

SCIE

FE02

WTOI/

RLIEN

CDEVNT

RXDAEN TXEVEN TXSNTEN TXERR

VccCtl

FE03

FE04

FE05

FE06

FE07

FE08

VCCSEL.1 VCCSEL.0 VDDFLT

OFFTMR(3:0)

RDYST

VCCOK

SCPWRDN

VCCTmr

CRDCtl

STXCtl

STXData

SRXCtl

VCCTMR(3:0)

DEBOUN CDETEN

DETPOL

PUENB

PDEN

CARDIN

BREAKD

I2CMODE

BIT9DAT

RSTCRD

TXFULL

LASTRX

TXEMTY TXUNDR LASTTX

TXDATA(7:0)

TX/RXB

CRCERR RXFULL

RXDATA(7:0)

RXEMTY RXOVRR PARITYE

SRXData FE09

SCCtl

FE0A

FE0B

FE0C

FE0D

FE0F

FE10

FE11

FE12

FE13

IO

IOD

C8

C4

CLKLVL

CLKOFF

SCECtl

SCDIR

SPrtcol

SCCLK

SCECLK

SParCtl

SByteCtl

FDReg

SIO

SIOD

SCLKLVL SCLKOFF

C8D

C4D

SCISYN MOD9/8B

SCESYN

0

TMODE

CRCEN

CRCMS

INSPE

RCVATR

FORCPE

ICLKFS(5:0)

ECLKFS(5:0)

RTRAN DISCRX

DISPAR

DETTS

BRKGEN

DIRTS

BRKDET

BRKDUR (1:0)

FVAL(3:0)

DVAL (3:0)

CRCMsB FE14

CRC(15:8)

CRC(7:0)

CRCLsB

BGT

FE15

FE16

FE17

FE18

FE19

FE1A

FE1B

FE1C

FE1D

FE1F

FE20

FE21

FE22

EGT8

BGT(4:0)

EGT

EGT(7:0)

BWTB3

BWTB2

BWTB1

BWTB0

CWTB1

CWTB0

ATRMsB

ATRLsB

STSTO

RLength

BWT(27:24)

BWT(23:16)

BWT(15:8)

BWT(7:0)

CWT(15:8)

CWT(7:0)

ATRTO(15:8)

ATRTO(7:0)

TSTO(7:0)

RLen(7:0)

102

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

1.7.16 VDD Fault Detect Function

The 73S1210F contains a circuit to detect a low-voltage condition on the supply voltage V_DD. If enabled,

it will deactivate the active internal smart card interface when V_DDfalls below the V_DDFault threshold. The

register configures the V_DDFault threshold for the nominal default of 2.3V* or a user selectable threshold.

The user’s code may load a different value using the FOVRVDDF bit = 1 after the power-up cycle has

completed.

VDDFault Control Register (VDDFCtl): 0xFFD4  0x00

Table 108: The VDDFCtl Register

MSB

LSB

STXDAT.3 VDDFTH.2 VDDFTH.1 VDDFTH.0

–

FOVRVDDF VDDFLTEN

–

Bit

Symbol

Function

VDDFCtl.7

–

Setting this bit high will allow the VDDFLT(2:0) bits set in this register to control

VDDFCtl.6 FOVRVDDF the VDDFault threshold. When this bit is set low, the VDDFault threshold will

be set to the factory default setting of 2.3V*.

VDDFCtl.5 VDDFLTEN Set = 1 will disable VDD Fault operation.

VDDFCtl.4

VDDFCtl.3

–

VDD Fault Threshold.

VDDFCtl.2 VDDFTH.2

VDDFCtl.1 VDDFTH.1

Bit Value(2:0)

VDDFault Voltage

000

001

010

011

100

101

110

111

2.3 (nominal default)

2.4

2.5

2.6

2.7

2.8

2.9

3.0

VDDFCtl.0 VDDFTH.0

* Note: The V_DDFault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The

73S1210F has the capability to burn fuses at the factory to set the factory default to any of these

voltages. Contact Teridian for further details.

Rev. 1.4

103

DS_7310F_001

73S1210F Data Sheet

3 Electrical Specification

3.1 Absolute Maximum Ratings

Operation outside these rating limits may cause permanent damage to the device. The smart card

interface pins are protected against short circuits to V_CC, ground, and each other.

Parameter

Rating

DC Supply voltage, V_DD

Supply Voltage V_PC

-0.5 to 4.0 VDC

-0.5 to 6.6 VDC

-60 to 150°C

-0.3 to (V_DD+0.5) VDC

-0.3 to (V_CC+0.5) VDC

+/- 2KV

Supply Voltage V_BUS

Supply Voltage V_BAT

Storage Temperature

Pin Voltage (except card interface)

Pin Voltage (card interface)

ESD tolerance (except card interface)

ESD tolerance (card interface)

Pin Current

+/- 7KV

± 200 mA

Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.

Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins.

3.2 Recommended Operating Conditions

Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges:

Parameter

Rating

Supply Voltage V_PC

2.7 to 6.5 VDC

4.4 to 5.5 VDC

4.0 to 6.5 VDC

-40°C to +85°C

Supply Voltage V_BUS

Supply Voltage V_BAT

Ambient Operating Temperature (Ta)

Rev. 1.4

105

73S1210F Data Sheet

DS_1210F_001

3.3 Digital IO Characteristics

These requirements pertain to digital I/O pin types with consideration of the specific pin function and

configuration. The LED(1:0) pins have pull-ups that may be enabled. The Row pins have 100kΩ pull-

ups.

Symbol Parameter

Conditions

Ioh = -2mA

Min.

0.8 * V_DD

V_DD- 0.45

0

Typ.

Max.

Unit

V

Voh

Output level, high

V_DD

OFF_REQ pin - I_OH= -1mA

Iol = 2mA

V

Vol

Output level, low

0.3

0.45

V_DD+0.3

0.6

V

OFF_REQ pin - Iol = 2mA

2.7v < VDD <3.6v

RESET, ON_OFF,PRES pins

0 < Vin < VDD

V

Vih

Vil

Input voltage, high

Input voltage, low

1.8

-0.3

-5

V

0.8

V

Ileak

Leakage current

5

µA

All output modes disabled,

pull-up/downs disabled

Ipu

Ipd

Pull-up current

If provided and enabled,

Vout < 0.1v

-5

µA

Pull-down current

If provided and enabled,

Vout > VDD – 0.1v

5

Symbol Parameter

Conditions

Min.

Typ.

Max.

Unit

Iled

LED drive current

Vout = 1.3V,

2.7v < VDD < 3.6v

2

4

mA

10

Iolkrow

Iolkcol

Keypad row output

low current

0.0v < Voh < 0.1v

when pull-up R is enabled

40

100

3

µA

Keypad column

0.0v < Voh < 0.1v

1.5

mA

output high current

when col. is pulled low

106

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

3.4 Oscillator Interface Requirements

Symbol

Parameter

Condition

Min

Typ.

Max

Unit

High-Frequency Oscillator (Xin) Parameters. Xin Is Used As Input For External Clock For Test

Purposes Only. A Resistor Connecting x12in To x12out Is Required, Value = 1mΩ.

VILX12IN

Input Low Voltage –

X12IN

-0.3

1.5

1.6

0.3*VDD

V

Input High Voltage – X12IN

Input Current -X12IN

VIHX12IN

IILXTAL

Fxtal

0.7*VDD

-10

Vdd+.0.3

10

V

GND < Vin < Vdd

μA

Crystal resonant

frequency

Fundamental mode

6

12

MHz

3.5 DC Characteristics: Analog Input

Symbol

Parameter

Condition

Min

Typ.

Max

Unit

V_THTOL

Voltage Threshold

Tolerance

Selected Threshold

Value

-3%

+3%

V

Rev. 1.4

107

73S1210F Data Sheet

DS_1210F_001

3.6 Smart Card Interface Requirements

Symbol

Card Power Supply (V_CC) Regulator

General conditions, -40°C < T < 85°C, 4.75V < V_PC< 6.0V, 2.7V < V_DD< 3.6V

Parameter

Condition

Min

Typ.

Max

Unit

Inactive mode

-0.1

4.65

2.85

1.68

0.1

0.4

V

Inactive mode, I_CC= 1mA

Active mode; I_CC<65mA; 5V

Active mode; I_CC< 65mA; 3V

Active mode; I_CC< 40mA; 1.8V

5.25

3.15

1.92

Active mode; single pulse of

100mA for 2µs; 5V, fixed load =

25mA

4.6

2.76

4.6

5.25

3.15

5.25

3.15

1.92

V

Card supply Voltage

including ripple and

noise

Active mode; single pulse of

100mA for 2µs; 3V, fixed load =

25mA

V_CC

Active mode; current pulses of

40nAs with peak |I_CC| <200mA, t

<400ns; 5V

Active mode; current pulses of

40nAs with peak |I_CC| <200mA,t

<400ns; 3V

2.7

Active mode; current pulses of

20nAs with peak |I_CC| <100mA,t

<400ns; 1.8V

1.62

V_CCrip

I_CCmax

V_CCRipple

f_RIPPLE= 20kHz – 200MHz

350

40

mV

mA

Static load current, V_CC>1.65

Card supply output

current

Static load current, V_CC>4.6V or

2.7V as selected

65

mA

Class A, B (5V and 3V)

Class C (1.8V)

100

60

180

130

150

I_CCF

Isc

I_CCfault current

mA

Load current limit prior to Vcc

shut-down

80

mA.

Maximum current

prior to shut-down

Load current limit prior to Vcc

shut-down for Vcc = 1.8V

mA

60

130

V_SR

V_SF

Vcc slew rate, rise

Vcc slew rate, fall

0.12

0.15

4.6

.30

0.50

1.20

Rise rate on activate C = 0.47µF

Fall rate on deactivate, C = 0.47µF

5V operation, Vcc rising

V/µs

V

Vcc ready voltage

(VCCOK = 1)

V_rdy

3V operation, Vcc rising

2.75

1.65

V

1.8V operation, Vcc rising

V

108

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Symbol

Parameter

Condition

Min

Typ.

Max

Unit

Interface Requirements – Data Signals: I/O, AUX1 and AUX2

I_OH= 0

0.9 * V_CC

0.75 V_CC

V_CC+0.1

0.15 *V_CC

V_CC+0.30

0.2 * V_CC

0.1

V

V_OH

Output level, high

I_OH= -40µA

V_OL

V_IH

V_IL

Output level, low

Input level, high

Input level, low

I_OL= 1mA

V

0.6 * V_CC

-0.15

V

I_OL= 0

I_OL= 1mA

V_IH= V_CC

V_IL= 0

V

Output voltage when outside

of session

V_INACT

0.3

V

I_LEAK

I_IL

Input leakage

10

µA

mA

Input current, low

0.65

I_IL

V_IL= 0

0.7

For output low, shorted

to V_CCthrough 33Ω

I_SHORTL

Short circuit output current

15

mA

For output high,

shorted to ground

through 33Ω

I_SHORTH

Short circuit output current

15

mA

For I/O, AUX1, AUX2,

C_L= 80pF, 10% to

t_R, t_F

Output rise time, fall times

90%. For I/OUC,

100

ns

AUX1UC, AUX2UC, CL

= 50Pf, 10% to 90%.

t_IR, t_IF

R_PU

Input rise, fall times

Internal pull-up resistor

Maximum data rate

1

14

1

µs

kΩ

Output stable for

>200ns

8

11

FD_MAX

MHz

Reset and Clock for card interface, RST, CLK

V_OH

V_OL

Output level, high

Output level, low

0.9 * V_CC

0

V_CC

0.15 *V_CC

0.1

V

I_OH= -200µA

I_OL= 200µA

I_OL= 0

Output voltage when outside

of session

V_INACT

I_OL= 1mA

0.3

I_{RST_LIM}

I_{CLK_LIM}

Output current limit, RST

Output current limit, CLK

30

70

8

mA

ns

C_L= 35pF for CLK,

10% to 90%

t_R, t_F

Output rise time, fall time

Duty cycle for CLK

C_L= 200pF for RST,

10% to 90%

100

55

ns

%

C_L= 35pF, F_CLK

45

δ

≤ 20MHz, CLKIN duty

cycle is 48% to 52%.

Rev. 1.4

109

73S1210F Data Sheet

DS_1210F_001

3.7 DC Characteristics

Symbol Parameter

Condition

Min

44

31

23

20

34

24

18

16

20

14

11

9

Typ.

55

38

29

25

43

30

22

19

25

18

13

12

20

14

10

9

Max

66

46

35

30

51

36

27

23

30

21

16

14

24

17

13

11

23

17

13

11

23

17

13

11

41

28

21

19

31

21

16

14

24

17

13

11

3.6

Unit

Supply Current @ V_PC= 2.7V

(V_BUSand V_BATunconnected)

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

mA

V

Supply Current @ V_PC= 3.3V

(V_BUSand V_BATunconnected)

I_PC

Supply Current @ V_PC= 5.0V

(V_BUSand V_BATunconnected)

Supply Current @ V_VBUS= 4.4V

Supply Current @ V_VBUS= 5.0V

Supply Current @ V_VBUS= 5.5V

16

11

8

7

16

11

8

19

14

10

9

I_VBUS

7

16

11

8

20

14

11

9

7

Supply Current @ V_VBAT= 4.0V

(V_BUS= 0V)

28

19

14

12

20

14

11

9

34

24

18

15

26

18

13

12

20

14

10

9

Supply Current @ V_VBAT= 5.0V

(V_BUS= 0V)

I_VBAT

Supply Current @ V_VBAT= 6.5V

(V_BUS= 0V)

16

11

8

7

V_DD*

V_DDSupply Voltage

2.7V < VPC < 6.5V,

I_VDD< 40mA.

3.0

3.3

110

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

I_{DD_IN}

Supply Current – pins 28 + 40

(internal consumption – digital

core)

CPU clock @ 24MHz

CPU clock @ 12MHz

CPU clock @ 6MHz

CPU clock @ 3.69MHz

29

21

33.5

24

mA

15.5

13.5

18

15.5

Power down

(-40° to 85°C)

8

6

50

15

20

µA

Power down (25°C)

Supply Current – pin 68

(available to external circuitry)

I_{DD_OUT}

I_VBUS

Circuit ON

mA

V

_CCoff, I_DDINTERNAL<

Supply Current from V_BUS

0.2

0.4

1

mA

20µA

I_VBAT

I_VPC

Supply Current from V_BATor

V_PC

Circuit OFF

0.01

µA

VBUS_ONV_BUSdetection threshold

VBUS_IDISV_BUSdischarge current

3.5

50

V

μA

External Capacitor Values

C_VPC

C_VP

External filter capacitor for V_PC

External filter capacitor for V_P

External filter capacitors for V_DD

µF

8.0

2.0

0.2

10.0

4.7

12.0

10.0

1.0

C_VDD

*

C

_VCCshould be ceramic

with low ESR

C_VCC

External filter capacitor for V_CC

0.2

0.47

1.0

µF

(<100MΩ).

*Note: Recommend on 0.1µF for each V_DDpin.

3.8 Current Fault Detection Circuits

Symbol Parameter

Condition

Min

Typ.

Max

150

100

150

130

Unit

mA

IV_Pmax

I_DDmax

I_CCF

V_Pover current fault

VDD over-current limit

Card overcurrent fault

40

80

60

I_CCF1P8

V_CC= 1.8V

Rev. 1.4

111

73S1210F Data Sheet

DS_1210F_001

4 Equivalent Circuits

VDD

X12LIN

X12OUT

ESD

ENABLE

To

circuit

Figure 26: 12 MHz Oscillator Circuit

VDD

ENABLEb

X32OUT

>1MEG

X32LIN

ESD

To

circuit

Figure 27: 32KHz Oscillator Circuit

112

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

VDD

STRONG

PFET

Output

Disable

ESD

Data

From

circuit

STRONG

NFET

To

circuit

Figure 28: Digital I/O Circuit

VDD

STRONG

PFET

Output

Disable

ESD

Data

From

circuit

STRONG

NFET

Figure 29: Digital Output Circuit

Rev. 1.4

113

73S1210F Data Sheet

DS_1210F_001

VDD

VERY

WEAK

PFET

Pull-up

Disable

STRONG

PFET

Output

Disable

ESD

Data

From

circuit

STRONG

NFET

To

circuit

Figure 30: Digital I/O with Pull Up Circuit

VDD

STRONG

PFET

Output

Disable

ESD

Data

From

circuit

STRONG

NFET

To

circuit

VERY

WEAK

NFET

Pull-down

Enable

Figure 31: Digital I/O with Pull Down Circuit

114

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

To

circuit

ESD

Figure 32: Digital Input Circuit

VDD

VERY

WEAK

PFET

Pull-up

Disable

STRONG

PFET

ESD

Output

Disable

ESD

Data

From

circuit

STRONG

NFET

To

circuit

VERY

WEAK

NFET

Pull-down

Enable

Figure 33: OFF_REQ Interface Circuit

VDD

Pull-up

Disable

100k

OHM

STRONG

PFET

Output

Disable

ESD

Data

From

circuit

STRONG

NFET

To

circuit

Figure 34: Keypad Row Circuit

Rev. 1.4

115

73S1210F Data Sheet

DS_1210F_001

VDD

1200

OHMS

MEDIUM

PFET

Output

Disable

ESD

Data

From

circuit

STRONG

NFET

To

circuit

Figure 35: Keypad Column Circuit

VDD

STRONG

PFET

Pullup

Disable

ESD

Data

From

circuit

STRONG

NFET

To

circuit

Current Value

Control

0, 2, 4,

10mA

Figure 36: LED Circuit

116

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

This buffer has a

special input

threshold:

Vih>0.7*VDD

To Circuit

Logic

ESD

R= 20kΩ

Figure 37: Test and Security Pin Circuit

To

Comparator

Input

ESD

Figure 38: Analog Input Circuit

VCC

STRONG

ESD

PFET

From

circuit

ESD

STRONG

NFET

Figure 39: Smart Card Output Circuit

Rev. 1.4

117

73S1210F Data Sheet

DS_1210F_001

VCC

RL=11K

STRONG

PFET

ESD

125ns

DELAY

From

IO

circuit

STRONG

NFET

To

circuit

ESD

Figure 40: Smart Card I/O Circuit

VDD

ESD

To

circuit

VERY

WEAK

NFET

ESD

Pull-down

Enable

Figure 41: PRES Input Circuit

VDD

VERY

WEAK

PFET

Pull-up

Disable

ESD

To

circuit

Pull-down

Enable

ESD

Figure 42: PRESB Input Circuit

118

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

VPC

R= 24kΩ

To Circuit

Logic

ESD

Figure 43: ON_OFF Input Circuit

Rev. 1.4

119

73S1210F Data Sheet

DS_1210F_001

5 Package Pin Designation

5.1 68-pin QFN Pinout

CAUTION: Use handling procedures necessary

for a static sensitive component

68

18

VDD

TXD

67

19

GND

COL4

66

20

USR7

LIN

65

21

ROW0

VPC

64

22

VBAT

ROW1

63

23

ON_OFF

USR6

62

24

VBUS

ROW2

61

25

IO

GND

TERIDIAN

73S1210F

60

26

27

28

29

30

31

32

33

34

AUX1

N/C

59

AUX2

58

VCC

VDD

57

RST

USR5

USR4

USR3

56

GND

55

CLK

54

USR2

ROW3

USR1

VP

53

PRES

52

OFF_REQ

Figure 44: 73S1210F 68 QFN Pinout

120

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

5.2 44-pin QFN Pinout

CAUTION: Use handling procedures necessary

for a static sensitive component.

44

12

13

14

15

16

VPC

TXD

USR7

USR6

GND

43

ON_OFF

42

IO

41

AUX1

40

AUX2

VDD

TERIDIAN

73S1210F

39

38

37

36

35

34

17

18

USR5

USR4

USR3

USR2

USR1

USR0

VCC

RST

GND

CLK

VP

19

20

21

22

PRES

Figure 45: 73S1210F 44 QFN Pinout

Rev. 1.4

121

73S1210F Data Sheet

DS_1210F_001

6 Packaging Information

6.1 68-Pin QFN Package Outline

Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias).

Controlling dimensions are in mm.

0.65

0.85

8.00

0.2

7.75

0.00/0.05

68

1

2

3

7.75 8.00

TOP VIEW

12°

SEATING

PLANE

8.00

0.42

0.24/0.60

SIDE VIEW

PIN#1 ID

R0.20

6.30

6.15/6.45

68

0.00/0.05

1

2

3

0.45

0.20

0.15/0.25

0.42

0.24/0.60

SECTION "C-C"

SCALE: NONE

6.30

6.40 8.00

6.15/6.45

C

L

TERMINAL TIP

0.40

6.40

FOR ODD TERMINAL/SIDE

BOTTOM VIEW

Figure 46: 73S1210F 68 QFN Mechanical Drawing

122

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

6.2 44-Pin QFN Package Outline

Notes: 5.1mm x 5.1mm exposed pad area must remain UNCONNECTED (clear of PCB traces or

vias). Controlling dimensions are in mm.

0.65

0.85

7.00

0.2

6.75

0.00/0.05

44

1

2

3

6.75 7.00

TOP VIEW

12°

SEATING

PLANE

7.00

0.42

0.24/0.60

SIDE VIEW

PIN#1 ID

R0.20

5.10

4.95/5.25

44

0.00/0.05

1

2

3

0.45

0.23

0.18/0.30

0.42

0.24/0.60

SECTION "C-C"

SCALE: NONE

5.10

5.00 7.00

4.95/5.25

C

L

TERMINAL TIP

0.50

5.00

FOR ODD TERMINAL/SIDE

BOTTOM VIEW

Figure 47: 73S1210F 44 QFN Package Drawing

Rev. 1.4

123

73S1210F Data Sheet

DS_1210F_001

7 Ordering Information

Table 109 lists the order numbers and packaging marks used to identify 73S1210F products.

Table 109: Order Numbers and Packaging Marks

Part Description

Order Number

Packaging Mark

73S1210F 68-Pin QFN, Lead Free

73S1210F 68-Pin QFN, Lead Free with Programming

73S1210F-68IM/F

73S1210F-68IM/F/P

73S1210F68IM

73S1210F 68-Pin QFN, Lead Free, Tape and Reel

73S1210F-68IMR/F

73S1210F68IM

73S1210F 68-Pin QFN, Lead Free, Tape and Reel with Programming 73S1210F-68IMR/F/P 73S1210F68IM

73S1210F 44-Pin QFN, Lead Free

73S1210F 44-Pin QFN, Lead Free with Programming

73S1210F-44IM/F

73S1210F-44IM/F/P

73S1210F44IM

73S1210F 44-Pin QFN, Lead Free, Tape and Reel

73S1210F-44IMR/F

73S1210F44IM

73S1210F 44-Pin QFN, Lead Free, Tape and Reel with Programming 73S1210F-44IMR/F/P 73S1210F44IM

8 Related Documentation

The following 73S1210F documents are available from Teridian Semiconductor Corporation:

73S1210F Data Sheet (this document)

73S1210F Development Board Quick Start Guide

73S1210F Software Development Kit Quick Start Guide

73S1210F Evaluation Board User’s Guide

73S12xxF Software User’s Guide

73S12xxF Synchronous Card Design Application Note

9 Contact Information

For more information about Teridian Semiconductor products or to check the availability of the 73S1210F,

contact us at:

6440 Oak Canyon Road

Suite 100

Irvine, CA 92618-5201

Telephone: (714) 508-8800

FAX: (714) 508-8878

Email: scr.support@teridian.com

For a complete list of worldwide sales offices, go to http://www.teridian.com.

124

Rev. 1.4

DS_1210F_001

73S1210F Data Sheet

Revision History

Revision Date

Description

First publication.

1.0

1.1

5/10/2007

11/6/2007

In Table 1, added Equivalent Circuit references.

In Section 1.4, updated program security description to remove pre-boot

and 32-cycle references.

In Section 1.7.1, changed “Mcount is configured in the MCLKCtl register

must be bound between a value of 1 to 7. The possible crystal or external

clock are shown in Table 12.“ to “Mcount is configured in the MCLKCtl

register must be bound between a value of 1 to 7. The possible crystal or

external clock frequencies for getting MCLK = 96MHz are shown in Table

11.”

In the BRCON description, changed “If BSEL = 1, the baud rate is derived

using timer 1.” to “If BSEL = 0, the baud rate is derived using timer 1.”

In Section 1.7.14, removed the following from the emulator port

description: “The signals of the emulator port have weak pull-ups. Adding

resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is

recommended. If necessary, adding 10KΩ pull-up resistors on E_TCLK

and E_RXTX and a 3KΩ on E_RST will help the emulator operate

normally if a problem arises.”

In Ordering Information, removed the leaded part numbers.

In Table 1, added the “Pin (44 QFN)” column.

1.2

12/15/2008

In Table 1, added more description to the SCL, SDA, PRES, VCC, VPC,

SEC, TEST and VDD pins.

In Section 1.3.2, changed “FLSH_ERASE” to “ERASE” and

“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes

the page address for page erase. The page size is 512 (200h) bytes and

there are 128 pages within the flash memory. The PGADDR denotes the

upper seven bits of the flash memory address such that bit 7:1 of the

PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of

the PGADDR is not used and is ignored.” In the description of the

PGADDR register, added “Note: the page address is shifted left by one bit

(see detailed description above).”

In Table 5, changed “FLSHCRL” to “FLSHCTL”.

In Table 5, removed the PREBOOT bit description.

In Table 5, moved the TRIMPCtl bit description to FUSECtl and moved the

FUSECtl bit description to TRIMPCtl.

In Table 6, changed “PGADR” to “PGADDR”.

In Table 7, added PGADDR.

In Table 8, changed the reset value for RTCCtl from “0x81” to “0x00”.

Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,

LEDCal and LOCKCtl registers.

In Table 7, removed the Mcount 7 row.

In Table 50 through Table 53, changed the names of registers USRIntCtl0

through USRIntCtl3 to USRIntCtl1 through USRIntCtl4.

In TCON, corrected the descriptions for TCON.2 and TCON.0.

In Section 1.7.9, added a note about USR pins defaulting as inputs after

reset.

Changed the register address for ATRMsB from FE21 to FE1F.

Rev. 1.4

125

73S1210F Data Sheet

DS_1210F_001

In Section 1.7.15.5, deleted “The ETU clock is held in reset condition until

the activation sequence begins (either by VCCOK=1 or VCCTMR timeout)

and will go high ½ the ETU period thereafter.”

In Section 1.7.15.5, added “Synchronous card operation is broken down

into three primary types. These are commonly referred to as 2-wire,

3-wire and I2C synchronous cards. Each card type requires different

control and timing and therefore requires different algorithms to access.

Teridian has created an application note to provide detailed algorithms for

each card type. Refer to the application note titled 73S12xxF

Synchronous Card Design Application Note.”

In Table 78 and Table 107, changed the SYCKST bit to I2CMODE.

In Figure 25, replaced the schematic with a new schematic.

In Section 3.4, changed the Fxtal Min from 4 to 6.

Added 44-pin QFN package.

Added Section 8, Related Documentation.

Added Section 9, Contact Information.

Formatted the document per new standard. Added section numbering.

1.3

1.4

1/22/2009

5/12/2009

Changed the value for the I_{DD_IN}Power Down (25°C) parameter from 13

µA to 15 µA.

In Table 1, corrected the 44 QFN GND pin from 37 to 26.

Added the “with Programming” ordering numbers to Table 109.

Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.

Windows is a registered trademark of Microsoft Corporation.

Signum Systems is a trademark of Signum Systems Corporation.

All other trademarks are the property of their respective owners.

Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly

contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms

and Conditions. The company assumes no responsibility for any errors which may appear in this

document, reserves the right to change devices or specifications detailed herein at any time without

notice and does not make any commitment to update the information contained herein. Accordingly, the

reader is cautioned to verify that this document is current by comparing it to the latest version on

http://www.teridian.com or by checking with your sales representative.

Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618

TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com

126

Rev. 1.4


型号：	73S1210F-44IMR/F/P
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Power Supply Management Circuit, Fixed, 1 Channel, CMOS, LEAD FREE, QFN-44
文件：	总126页 (文件大小：1104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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