LTVQ_技术文档

LT1715

4ns, 150MHz

Dual Comparator with

Independent Input/Output Supplies

DESCRIPTION

FEATURES

TheLT^®1715isanUltraFast™dualcomparatoroptimizedfor

lowvoltageoperation.Separatesuppliesallowindependent

n

UltraFast: 4ns at 20mV Overdriven

150MHz Toggle Frequency

n

Separate Input and Output Power Supplies

Low Power: 4.6mA per Comparator at 3V

Pinout Optimized for High Speed Use

Output Optimized for 3V and 5V Supplies

TTL/CMOS Compatible Rail-to-Rail Output

Input Voltage Range Extends 100mV

Below Negative Rail

Internal Hysteresis with Speciﬁed Limits

Speciﬁed for –40°C to 125°C Temperature Range

Available in the 10-pin MSOP Package

analog input ranges and output logic levels with no loss of

performance.Theinputvoltagerangeextendsfrom100mV

n

belowV to1.2VbelowV .Internalhysteresismakesthe

EE

CC

LT1715 easy to use even with slow moving input signals.

The rail-to-rail outputs directly interface toTTL and CMOS.

The symmetric output drive results in similar rise and fall

times that can be harnessed for analog applications or for

easy translation to other single supply logic levels.

n

The LT1715 is available in the 10-pin MSOP package. The

pinoutoftheLT1715minimizesparasiticeffectsbyplacing

the most sensitive inputs away from the outputs, shielded

by the power rails.

APPLICATIONS

For a dual/quad single supply comparator with simi-

lar propagation delay, see the LT1720/LT1721. For a

single comparator with similar propagation delay, see

the LT1719.

n

High Speed Differential Line Receivers

n

Level Translators

n

Window Comparators

n

Crystal Oscillator Circuits

Threshold Detectors/Discriminators

High Speed Sampling Circuits

Delay Lines

n

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

UltraFast is a trademark of Linear Technology Corporation.

n

TYPICAL APPLICATION

100MHz Dual Differential Line Receiver

Line Receiver Response to 100MHz Clock,

50MHz Data Both with 25mV_P-PInputs

5V

3V

CLOCK OUT

+

–

1V/DIV

OUT A

OUT B

IN A

IN B

0V

3V

1V/DIV

+

–

DATA OUT

0V

5ns/DIV

FET PROBES

1715 TA02

1715 TA01

–5V

1715fa

1

LT1715

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Supply Voltage

+IN A

–IN A

–IN B

+IN B

1

2

3

4

5

10

9

V

CC

S

OUT A

OUT B

GND

+V to GND.............................................................7V

S

CC

A

+V

8

V

to V ..........................................................13.2V

EE

7

6

B

+V to V ..........................................................13.2V

S

EE

V

EE

V

to GND ......................................... –13.2V to 0.3V

MS PACKAGE

10-LEAD PLASTIC MSOP

Input Current (+IN, –IN)....................................... 10mA

Output Current (Continuous) ............................... 20mA

Operating Temperature Range (Note 2)

T

JMAX

= 150°C, θ = 120°C/W (NOTE 4)

JA

LT1715C...............................................–40°C to 85°C

LT1715I................................................–40°C to 85°C

LT1715H ............................................–40°C to 125°C

Speciﬁed Temperature Range (Note 3)

LT1715C................................................... 0°C to 70°C

LT1715I................................................ –40°C to 85°C

LT1715H ............................................ –40°C to 125°C

Junction Temperature ........................................... 150°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER INFORMATION

LEAD FREE FINISH

LT1715CMS#PBF

LT1715IMS#PBF

LT1715HMS#PBF

TAPE AND REEL

PART MARKING

LTVQ

PACKAGE DESCRIPTION

10-Lead Plastic MSOP

SPECIFIED TEMPERATURE RANGE

0°C to 70°C

LT1715CMS#TRPBF

LT1715IMS#TRPBF

LT1715HMS#TRPBF

LTVV

–40°C to 85°C

LTVV

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 5V, V_EE= –5V, +V_S= 5V, V_CM= 1V, C_OUT= 10pF, V_OVERDRIVE= 20mV,

unless otherwise speciﬁed.

SYMBOL

– V

PARAMETER

CONDITIONS

MIN

2.7

TYP

MAX

12

UNITS

l

V

Input Supply Voltage

Output Supply Voltage

Input Voltage Range

Input Trip Points

V

CC

EE

+V

2.7

6

S

V

(Note 5)

(Note 6)

V

– 0.1

V

– 1.2

CC

CMR

EE

+

l

V

TRIP

LT1715C, LT1715I

LT1715H

–1.5

–1.8

5.5

6

mV

–

l

V

TRIP

Input Trip Points

(Note 6)

LT1715C, LT1715I

LT1715H

–5.5

–6

1.5

1.8

mV

1715fa

2

LT1715

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 5V, V_EE= –5V, +V_S= 5V, V_CM= 1V, C_OUT= 10pF, V_OVERDRIVE= 20mV,

unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Offset Voltage

(Note 6)

0.4

2.5

3.5

4

mV

OS

l

LT1715C, LT1715I

LT1715H

l

V

Input Hysteresis Voltage

(Note 6)

(Note 7)

LT1715C, LT1715I

LT1715H

2

3.5

6

7

mV

HYST

l

/ΔT

Input Offset Voltage Drift

Input Bias Current

10

μV/°C

OS

l

I

B

LT1715C, LT1715I

LT1715H

–6

–7

–2.5

0

μA

l

I

Input Offset Current

LT1715C, LT1715I

LT1715H

0.2

70

0.6

1

μA

OS

l

CMRR

PSRR

Common Mode Rejection Ratio

LT1715C, LT1715I

LT1715H

60

55

dB

l

Power Supply Rejection Ratio

Voltage Gain

(Note 8)

(Note 9)

65

80

∞

dB

A

V

+

l

V

Output High Voltage

Output Low Voltage

Maximum Toggle Frequency

Propagation Delay

I

= 4mA, V = V

+ 20mV

+V – 0.4

V

OH

OL

SOURCE

IN

TRIP

–

S

= 10mA, V = V

– 20mV

0.4

SINK

IN

TRIP

f

(Note 10)

150

4

MHz

MAX

PD20

t

V

= 20mV (Note 11),

2.8

6

7

8

ns

OVERDRIVE

l

= 5V, V = –5V

LT1715C, LT1715I

LT1715H

CC

EE

V

= 20mV, V = 5V, V = 0V

4.4

4.8

ns

OVERDRIVE

CC

EE

= 20mV, V = 3V, V = 0V

3

6.5

7.5

8

ns

CC

EE

l

LT1715C, LT1715I

LT1715H

t

Propagation Delay

V

= 5mV, V = 0V (Notes 11, 12)

6

9

ns

PD5

OVERDRIVE

EE

l

12

+

–

Propagation Delay Skew

Differential Propagation Delay

Output Rise Time

(Note 13) Between t /t , V = 0V

0.5

0.3

2

1.5

1

ns

SKEW

PD PD

EE

Δt

(Note 14) Between Channels

PD

t

10% to 90%

90% to 10%

r

f

Output Fall Time

2

+

–

Output Timing Jitter

V

IN

= 1.2V (6dBm), Z = 50

t

PD

t

PD

15

11

ps

JITTER

P-P

IN

RMS

f = 20MHz (Note 15)

l

I

Positive Input Stage Supply Current

(per Comparator)

+V = V = 5V, V = –5V LT1715C, LT1715I

1

2

mA

CC

S

CC

EE

LT1715H

2.2

l

+V = V = 3V, V = 0V LT1715C, LT1715I

0.9

1.6

1.8

mA

S

CC

EE

LT1715H

l

Negative Input Stage Supply Current +V = V = 5V, V = –5V LT1715C, LT1715I

(per Comparator)

–4.8

–5.3

–2.9

–2.4

4.6

mA

EE

S

CC

EE

LT1715H

l

+V = V = 3V, V = 0V

LT1715C, LT1715I

LT1715H

–3.8

–4.3

mA

S

CC

EE

l

Positive Output Stage Supply Current +V = V = 5V, V = –5V LT1715C, LT1715I

(per Comparator)

7.5

8

mA

S

CC

EE

LT1715H

l

V = V = 3V, V = 0V

LT1715C, LT1715I

LT1715H

3.7

6

6.5

mA

S

CC

EE

1715fa

3

LT1715

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 8: The power supply rejection ratio is measured with V = 1V and is

CM

deﬁned as the worst of: the change in offset voltage from V = +V = 2.7V

CC

S

to V = +V = 6V (with V = 0V) divided by 3.3V or the change in offset

CC

S

EE

voltage from V = 0V to V = –6V (with V = +V = 6V) divided by 6V.

EE

CC

S

Note 2: The LT1715C is guaranteed functional over the operating range of

–40°C to 85°C.

Note 9: Because of internal hysteresis, there is no small-signal region in

which to measure gain. Proper operation of internal circuity is ensured by

measuring V and V with only 20mV of overdrive.

OH

OL

Note 3: The LT1715C is guaranteed to meet speciﬁed performance from

0°C to 70°C. The LT1715°C is designed, characterized and expected to

meet speciﬁed performance from –40°C to 85°C but is not tested or

QA sampled at these temperatures. The LT1715I is guaranteed to meet

speciﬁed performance from –40°C to 85°C. The LT1715H is guaranteed to

meet speciﬁed performance from –40°C to 125°C.

Note 10: Maximum toggle rate is deﬁned as the highest frequency at

which a 100mV sinusoidal input results in an error free output toggling to

greater than 4V when high and to less than 1V when low on a 5V output

supply.

Note 11: Propagation delay measurements made with 100mV steps.

Note 4: Thermal resistances vary depending upon the amount of PC board

Overdrive is measured relative to V

.

TRIP

2

metal attached to Pin 5 of the device. θ is speciﬁed for a 2500mm 3/32"

JA

Note 12: t cannot be measured in automatic handling equipment with

PD

2

FR-4 board covered with 2oz copper on both sides and with 100mm of

low values of overdrive. The LT1715 is 100% tested with a 100mV step

and 20mV overdrive. Correlation tests have shown that t limits can be

guaranteed with this test.

Note 13: Propagation Delay Skew is deﬁned as:

copper attached to Pin 5. Thermal performance can be improved beyond

the given speciﬁcation by using a 4-layer board or by attaching more metal

area to Pin 5.

Note 5: If one input is within these common mode limits, the other input

can go outside the common mode limits and the output will be valid.

PD

t

= |t

– t

|

SKEW

PDLH

PDHL

Note 14: Differential propagation delay is deﬁned as the larger of the two:

Note 6: The LT1715 comparator includes internal hysteresis. The trip

Δt

= |t

– t

|

PDLH

PDHL

PDLHA

PDHLA

PDLHB

PDHLB

points are the input voltage needed to change the output state in each

+

–

direction. The offset voltage is deﬁned as the average of V

while the hysteresis voltage is the difference of these two.

and V

,

TRIP

Note 15: Package inductances combined with asynchronous activity on

the other channel can increase the output jitter. See Channel Interactions

in Applications Information. Speciﬁcation above is with one channel active

only.

Note 7: The common mode rejection ratio is measured with V = 5V,

CC

V

= –5V and is deﬁned as the change in offset voltage measured from

EE

= –5.1V to V = 3.8V, divided by 8.9V.

CM

TYPICAL PERFORMANCE CHARACTERISTICS

Input Offset and Trip Voltages

vs Supply Voltage

Input Offset and Trip Voltages

vs Temperature

Input Common Mode Limits

vs Temperature

4.2

4.0

3

2

3

2

+

+V = V = 5V

S CC

= 1V

CM

= –5V

EE

S

EE

CC

= –5V

V

TRIP

V

+

–

V

TRIP

3.8

3.6

1

0

V

OS

V

OS

0

–4.8

–5.0

–5.2

–1

–2

–3

–1

–2

–3

–

V

TRIP

V

TRIP

T

V

= 25°C

A

= 1V

CM

= GND

EE

–5.4

50

TEMPERATURE (°C)

100 125

1715 G03

4.5

5.5

6.0

–50 –25

0

25

75

2.5 3.0

3.5 4.0

5.0

–60 –40 –20

0

20 40 60 80 100 120 140

SUPPLY VOLTAGE, V = +V (V)

TEMPERATURE (°C)

CC

S

1715 G01

1715 G02

1715fa

4

LT1715

TYPICAL PERFORMANCE CHARACTERISTICS

Input Current

Quiescent Supply Current

vs Temperature

Quiescent Supply Current

vs Supply Voltage

vs Differential Input Voltage

8

6

2

1

6

5

V

CC

V

EE

= +V = 5V

S

= –5V

T

= 25°C

= GND

T

V

= 25°C

A

EE

A

I , OUTPUT HIGH

S

V

= +V = 5V

CC

S

= –5V

EE

4

0

I

S

4

3

I , OUTPUT LOW

S

–1

–2

–3

–4

–5

–6

–7

2

I

CC

1

I

CC

0

–1

–2

–3

–4

–2

–4

–6

I

, OUTPUT LOW

EE

I

EE

I

, OUTPUT HIGH

EE

–25

0

50

75 100 125

–50

25

0

2

3

4

5

6

7

–5 –4 –3 –2 –1

0

5

1

2

3

4

TEMPERATURE (°C)

SUPPLY VOLTAGE, V = +V (V)

DIFFERENTIAL INPUT VOLTAGE (V)

CC

S

1715 G05

1715 G06

1715 G04

Output Low Voltage

vs Load Current

Output High Voltage

vs Load Current

Supply Current

vs Toggle Frequency

0.5

0.4

0.3

0.2

0.1

0

30

25

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

VALID

TOGGLING

INCOMPLETE

OUTPUT TOGGLING

V

= +V = 5V, UNLESS

S

V

= +V = 5V, UNLESS

S

CC

125°C

OTHERWISE NOTED

= 10mV

+V = 2.7V

S

V

= –10mV

V

IN

125°C

C

= 20pF

LOAD

C

= 10pF

LOAD

–55°C

20

–55°C

25°C

15

10

25°C

C

= 0pF

LOAD

125°C

T

= 25°C

IN

A

V

= 50mV SINUSOID

5

0

125°C

+V = 2.7V

+V = V = 5V

V

S

EE

CC

= GND

S

0

4

8

12

16

20

4

8

12

16

20

0

25 50 75 100 125 150 175 200 225

TOGGLE FREQUENCY (MHz)

0

OUTPUT SINK CURRENT (mA)

OUTPUT SOURCE CURRENT (mA)

1715 G07

1715 G09

1715 G08

Propagation Delay

vs Overdrive

Propagation Delay

vs Temperature

Propagation Delay

vs Supply Voltage

5.5

5.0

4.5

4.0

3.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

8

7

6

5

4

3

t

C

LOAD

= 10pF

T

V

= 25°C

STEP

T

V

C

= 25°C

PDLH

A

V = 100mV

STEP

= 100mV

= 10pF

STEP

LOAD

OVERDRIVE = 20mV

= 10pF

C

LOAD

V

= +V = 3V

S

= 0V

CC

EE

V

= +V = 3V

EE

OVERDRIVE = 5mV

CC

S

= 0V

t

PDLH

V

= GND

EE

t

PDHL

t

PDLH

t

PDLH

PDHL

t

PDLH

PDHL

V

= –5V

EE

V

= +V = 5V

EE

V

= +V = 5V

S

EE

CC

V

S

CC

OVERDRIVE = 20mV

= –5V

V

= –5V

t

PDHL

4.5

5.5

+

6.0

2.5 3.0

3.5 4.0

5.0

–25

0

50

75 100 125

–50

25

10

20

OVERDRIVE (mV)

40

0

50

30

SUPPLY VOLTAGE, +V = V OR V (V)

TEMPERATURE (°C)

S

CC

1715 G12

1715 G11

1715 G10

1715fa

5

LT1715

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Toggle Rate

vs Input Amplitude

Maximum Toggle Rate

vs Temperature

Maximum Toggle Rate

vs Supply Voltage

250

230

210

190

170

150

130

110

90

180

160

140

120

100

80

250

225

200

175

150

125

100

75

T

= 25°C

IN

T

= 25°C

A

V

A

TOGGLING FROM

= 50mV SINUSOID

+V = V = 5V

S

EE

CC

1V TO +V – 1V

+V = V = 5V

V

C

= GND

S

EE

LOAD

CC

V

C

R

= –5V

= 10pF

LOAD

= 10pF

= 500Ω

TOGGLING FROM

20% TO 80% OF +V

S

60

T

= 25°C

A

40

V

C

=

50mV SINUSOID

IN

EE

= GND

20

70

= 10pF

3

LOAD

50

0

50

–50

0

25

50

75 100 125

–25

1

10

INPUT SINUSOID AMPLITUDE (mV)

100

4

2

5

6

TEMPERATURE (°C)

+V = V SUPPLY VOLTAGE (V)

S

CC

1715 G13

1715 G14

1715 G15

Maximum Toggle Rate

vs Load Capacitance

Propagation Delay

Response to 150MHz 25mV_P-P

Sine Wave Driving 10pF

vs Load Capacitance

250

225

200

175

150

125

100

75

8

7

6

5

4

3

T

= 25°C

IN

NA

P-P

T

= 25°C

STEP

A

V

= 50mV SINUSOID

25mV

V

= 100mV

20mV/DIV

1V/DIV

+V = V = 5V

V

OVERDRIVE = 20mV

+V = V = 5V

S

EE

CC

= GND

5V

S

EE

CC

= –5V

V

OUT A

0V

RISING EDGE

(t

)

PDLH

FALLING EDGE

(t

)

PDHL

2.5ns/DIV

FET PROBES

1715 G18

V

= 5V

CC

EE

50

= –5V

10

20

40

0

50

30

0

5

10 15 20 25 30 35 40 45 50

OUTPUT CAPACITANCE (pF)

1715 G16

+V = 5V

S

OUTPUT LOAD CAPACITANCE (pF)

V

= 0V

CM

1715 G17

PIN FUNCTIONS

+IN A (Pin 1): Noninverting Input of Comparator A.

–IN A (Pin 2): Inverting Input of Comparator A.

–IN B (Pin 3): Inverting Input of Comparator B.

+IN B (Pin 4): Noninverting Input of Comparator B.

GND (Pin 6): Ground for Output Stage.

OUT B (Pin 7): Output of Comparator B.

OUT A (Pin 8): Output of Comparator A.

+V (Pin 9): Positive Supply Voltage for Output Stage.

S

V

(Pin 5): Negative Supply Voltage for Input Stage and

V

CC

(Pin 10): Positive Supply Voltage for Input Stage.

EE

Substrate.

1715fa

6

LT1715

TEST CIRCUITS

1715fa

7

LT1715

TEST CIRCUITS

Response Time Test Circuit

+V – V

s

CM

0V

0.01μF

V

– V

CM

CC

–100mV

25Ω

+

DUT

1/2 LT1715

10× SCOPE PROBE

25Ω

50k

(C ≈ 10pF)

IN

–

0.1μF

130Ω

50Ω

V1*

PULSE

IN

2N3866

750Ω

0V

V

– V

1N5711

EE

CM

–3V

–V

+

CM

50Ω

400Ω

*V1 = –1000 • (OVERDRIVE + V

)

TRIP

NOTE: RISING EDGE TEST SHOWN.

FOR FALLING EDGE, REVERSE LT1719 INPUTS

1715 TC02

–5V

1715fa

8

LT1715

APPLICATIONS INFORMATION

Power Supply Conﬁgurations

input stage is run from –5.2V and ground while the output

stage is run from 3V and ground. In this case the com-

mon mode input voltage range does not include ground,

The LT1715 has separate supply pins for the input and

outputstagesthatallowﬂexibleoperation,accommodating

separatevoltagerangesfortheanaloginputandtheoutput

logic. Of course, a single 3V/5V supply may be used by

so it may be helpful to tie V to 3V. Conversely, V may

CC

also be tied below ground, as long as the above rules are

not violated.

tying +V and V together as well as GND and V .

S

CC

EE

The minimum voltage requirement can be simply stated

as both the output and the input stages need at least 2.7V

Input Voltage Considerations

The LT1715 is speciﬁed for a common mode range of

–100mV to 3.8V when used with a single 5V supply. A

more general consideration is that the common mode

and the V pin must be equal to or less than ground.

EE

The following rules must be adhered to in any conﬁguration:

range is 100mV below V to 1.2V below V . The crite-

EE

CC

2.7V ≤ (V – V ≤ 12V

CC

EE)

rion for this common mode limit is that the output still

responds correctly to a small differential input signal. If

one input is within the common mode limit, the other

input signal can go outside the common mode limits, up

to the absolute maximum limits, and the output will retain

the correct polarity.

2.7V ≤ (+V – GND) ≤ 6V

S

(+V – V ) ≤ 12V

S

EE)

V

≤ Ground

EE

Althoughthegroundpinneednotbetiedtosystemground,

mostapplicationswilluseitthatway. Figure1showsthree

common conﬁgurations. The ﬁnal one is uncommon, but

it will work and may be useful as a level translator; the

When either input signal falls below the negative common

modelimit,theinternalPNdiodeformedwiththesubstrate

can turn on, resulting in signiﬁcant current ﬂow through

the die. An external Schottky clamp diode between the

input and the negative rail can speed uprecovery from

negative overdrive by preventing the substrate diode from

turning on.

2.7V TO 6V

5V

V

CC

3V

+V

+

–

+

–

+V

S

When both input signals are below the negative common

mode limit, phase reversal protection circuitry prevents

false output inversion to at least –400mV common mode.

However,theoffsetandhysteresisinthismodewillincrease

dramatically, to as much as 15mV each. The input bias

currents will also increase.

GND

V

EE

–5V

Single Supply

5V Input, 3V Output Supplies

12V

Whenoneinputsignalgoesabovethecommonmoderange

withoutexceedingadiodedropabovetheinputsupplyrail,

the input stage will remain biased and the comparator will

maintain correct output polarity. Above this voltage, the

input stage current source will saturate completely and

the ESD protection diode will forward conduct. Once the

aberrant input falls back into the common mode range,

thecomparatorwillrespondcorrectlytovalidinputsignals

within less than 10ns.

V

CC

5V

+V

3V

+V

+

–

+

–

S

GND

V

EE

–5.2V

1715 F01

12V Input, 5V Output Supplies Front End Entirely Negative

Figure 1. Variety of Power Supply Conﬁgurations

1715fa

9

LT1715

APPLICATIONS INFORMATION

When both input signals are above the positive common

modelimit,theinputstagewillgetdebiasedandtheoutput

polarity will be random. However, the internal hysteresis

will hold the output to a valid logic level. When at least one

of the inputs returns to within the common mode limits,

recovery from this state will take as long as 1μs.

High Speed Design Considerations

Applicationofhighspeedcomparatorsisoftenplaguedby

oscillations. The LT1715 has 4mV of internal hysteresis,

which will prevent oscillations as long as parasitic output

to input feedback is kept below 4mV. However, with the

2V/ns slew rate of the LT1715 outputs, a 4mV step can

be created at a 100Ω input source with only 0.02pF of

output to input coupling. The LT1715’s pinout has been

arranged to minimize problems by placing the sensitive

inputs away from the outputs, shielded by the power rails.

The input and output traces of the circuit board should

also be separated, and the requisite level of isolation is

readily achieved if a topside ground plane runs between

the output and the inputs. For multilayer boards where the

ground plane is internal, a topside ground or supply trace

should be run between the inputs and the output.

Thepropagationdelaydoesnotincreasesigniﬁcantlywhen

driven with large differential voltages, but with low levels

of overdrive, an apparent increase may be seen with large

source resistances due to an RC delay caused by the 2pF

typical input capacitance.

Input Protection

The input stage is protected against damage from large

differential signals, up to and beyond a differential voltage

equal to the supply voltage, limited only by the absolute

maximum currents noted. External input protection cir-

cuitry is only needed if currents would otherwise exceed

these absolute maximums. The internal catch diodes can

conduct current up to these rated maximums without

latchup, even when the supply voltages are at the absolute

maximum ratings.

ThegroundpinoftheLT1715candisturbthegroundplane

potential while toggling due to the extremely fast on and

off times of the output stage. Therefore, using a ground

for input termination or ﬁltering that is separate from the

LT1715Pin6groundcanbehighlybeneﬁcial.Forexample,

a ground plane tied to Pin 6 and directly adjacent to a 1"

longinputtracecancapacitivelycouple4mVofdisturbance

into the input. In this scenario, cutting the ground plane

betweentheGNDpinandtheinputswillcutthecapacitance

and the disturbance down substantially.

The LT1715 input stage has general purpose internal ESD

protection for the human body model. For use as a line

receiver, additional external protection may be required.

As with most integrated circuits, the level of immunity to

ESD is much greater when residing on a printed circuit

boardwherethepowersupplydecouplingcapacitancewill

limit the voltage rise caused by an ESD pulse.

Figure 2 shows a typical topside layout of the LT1715

on such a multilayer board. Shown is the topside metal

etch including traces, pin escape vias, and the land pads

for an MS10 LT1715 and its adjacent X7R 10nF bypass

capacitors in the 0805 case.

Input Bias Current

Input bias current is measured with both inputs held at

1V. As with any PNP differential input stage, the LT1715

bias current ﬂows out of the device. It will go to zero on

the higher of the two inputs and double on the lower

of the two inputs. With more than two diode drops of

differential input voltage, the LT1715’s input protection

circuitry activates, and current out of the lower input will

increase an additional 30% and there will be a small bias

current into the higher of the two input pins, of 4μA or

less. See the Typical Performance curve “Input Current

vs Differential Input Voltage.”

1715 F02

Figure 2. Typical Topside Metal for Multilayer PCB Layouts

1715fa

10

LT1715

APPLICATIONS INFORMATION

The ground trace from Pin 6 runs under the device up

to the bypass capacitor, shielding the inputs from the

outputs. Note the use of a common via for the LT1715

and the bypass capacitors, which minimizes interference

from high frequency energy running around the ground

plane or power distribution traces.

toggling at 100MHz with the other channel driven low

with the scope set to display inﬁnite persistence. Jitter is

almost nonexistent. Figure 4 displays the same channel

at 100MHz with inﬁnite persistence, but the other channel

ofthe comparator is toggling as well at frequencies swept

from 60MHz to 160MHz. Jitter will occur as rising and fall-

ing edges align for any non harmonic or non fundamental

frequency of the high frequency signal.

Thesupplybypassshouldincludeanadjacent10nFceramic

capacitor and a 2.2μF tantalum capacitor no farther than

5cm away; use more capacitance on +V if driving more

At frequencies well beyond 100MHz, the toggling of one

channel may be impaired by toggling on the other. This

is a rather complex interaction of supply bypassing and

bond inductance, and it cannot be entirely prevented.

However, good bypassing and board layout techniques

will effectively minimize it.

S

than 4mA loads. To prevent oscillations, it is helpful to

balance the impedance at the inverting and noninverting

inputs; source impedances should be kept low, preferably

1kΩ or less.

The outputs of the LT1715 are capable of very high slew

rates. To prevent overshoot, ringing and other problems

with transmission line effects, keep the output traces

shorter than 10cm, or be sure to terminate the lines

to maintain signal integrity. The LT1715 can drive DC

terminations of 200Ω or more, but lower characteristic

impedance traces can be used with series termination or

AC termination topologies.

Power Supply Sequencing

The LT1715 is designed to tolerate any power supply

sequencing at system turn-on and power down. In any

of the previously shown power supply conﬁgurations, the

various supplies can activate in any order without exces-

sive current drain by the LT1715.

As always, the Absolute Maximum Ratings must not be

exceeded, either on the power supply terminals or the

input terminals. Power supply sequencing problems can

occur when input signals are powered from supplies that

are independent of the LT1715’s supplies. No problems

should occur if the input signals are powered from the

Channel Interactions

The LT1715’s two channels are designed to be entirely

independent. However, at frequencies approaching and

exceeding 100MHz, bond wire inductance begins to

interfere with overlapping switching edges on the two

channels. Figure 3 shows one channel of the comparator

same V and V supplies as the LT1715.

CC

EE

–5V

1V/DIV

OUT A

1V/DIV

0V

OUT A

0V

5ns/DIV

1715 F04

1715 F03

Figure 3. Clean 100MHz Toggling

Figure 4. 100MHz Jitter with Both Channels Driven

1715fa

11

LT1715

APPLICATIONS INFORMATION

Unused Comparators

times better than prior generation comparators in these

regards. In fact, the CMRR and PSRR tests are performed

by checking for changes in either trip point to the limits

indicated in the speciﬁcations table. Because the offset

voltage is the average of the trip points, the CMRR and

PSRR of the offset voltage is therefore guaranteed to be

at least as good as those limits. This more stringent test

also puts a limit on the common mode and power supply

dependence of the hysteresis voltage.

If a comparator is unused, its output should be left ﬂoa-

tingto minimize load current. The unused inputs can be

tied off to the rails and power consumption can be further

minimized if the inputs are connected to the power rails

to induce an output low. Connecting the inverting input

to V and the noninverting input to V will likely be the

CC

EE

easiest method.

Hysteresis

Additional hysteresis may be added externally. The rail-

to-rail outputs of the LT1715 make this more predictable

than with TTL output comparators due to the LT1715’s

The LT1715 includes internal hysteresis, which makes it

easier to use than many other similar speed comparators.

The input-output transfer characteristic is illustrated in

small variability of V (output high voltage).

OH

Figure 5 showing the deﬁnitions of V and V

based

To add additional hysteresis, set up positive feedback

by adding additional external resistor R3 as shown in

Figure 6. Resistor R3 adds a portion of the output to the

threshold set by the resistor string. The LT1715 pulls the

OS

HYST

upon the two measurable trip points. The hysteresis band

makes the LT1715 well behaved, even with slowly moving

inputs.

outputs to +V and ground to within 200mV of the rails

S

The exact amount of hysteresis will vary from part to part

asindicatedinthespeciﬁcationstable.Thehysteresislevel

will also vary slightly with changes in supply voltage and

common mode voltage. A key advantage of the LT1715

is the signiﬁcant reduction in these effects, which is im-

portant whenever an LT1715 is used to detect a threshold

crossing in one direction only. In such a case, the relevant

trip point will be all that matters, and a stable offset volt-

age with an unpredictable level of hysteresis, as seen in

competing comparators, is useless. The LT1715 is many

with light loads, and to within 400mV with heavy loads.

For the load of most circuits, a good model for the volt-

age on the right side of R3 is 300mV or +V – 300mV,

S

for a total voltage swing of (+V – 300mV) – (300mV) =

S

+V – 600mV.

S

Withthisinmind, calculationoftheresistorvaluesneeded

isatwo-stepprocess.First,calculatethevalueofR3based

on the additional hysteresis desired, the output voltage

swing and the impedance of the primary bias string:

R3 = (R1||R2)(+V – 0.6V)/(additional hysteresis)

S

V

Additional hysteresis is the desired overall hysteresis less

the internal 4mV hysteresis.

OH

V

HYST

+

–

(= V

– V

)

TRIP

V

REF

R3

V

/2

HYST

R2

V

+

–

OL

+

ΔV = V – V

IN

1/2 LT1715

R1

0

–

+

V

TRIP

+

–

V

+ V

2

TRIP

V

=

OS

INPUT

1715 F06

1715 F05

Figure 5. Hysteresis I/O Characteristics

Figure 6. Additional External Hysteresis

1715fa

12

LT1715

APPLICATIONS INFORMATION

V

REF

power translator can be constructed with resistors as

shown in Figure 8.

R2´

V

TH

R3

+V

2

Figure 8a shows the standard TTL to Positive ECL (PECL)

resistive level translator. This translator cannot be used

forthe LT1715, or with CMOS logic, because it depends

S

V

=

AVERAGE

R1

+

on the 820Ω resistor to limit the output swing (V ) of

OH

1/2 LT1715

the all-NPNTTL gate with its so-called totem-pole output.

The LT1715is fabricated in a complementary bipolar

process and the output stage has a PNP driver that pulls

the output nearly all the way to the supply rail, even when

sourcing 10mA.

–

1715 F07

Figure 7. Model for Additional Hysteresis Calculations

The second step is to recalculate R2 to set the same av-

erage threshold as before. The average threshold before

Figure 8b shows a three resistor level translator for inter-

facing the LT1715 to ECL running off the same supply rail.

No pull-down on the output of the LT1715 is needed, but

was set at V = (V )(R1)/(R1 + R2). The new R2 is

TH

REF

calculatedbasedontheaverageoutputvoltage(+V /2)and

S

pull-down R3 limits the V seen by the PECL gate. This

IH

the simpliﬁed circuit model in Figure 7. To assure that the

is needed because ECL inputs have both a minimum and

comparator’s noninverting input is, on average, the same

maximum V speciﬁcation for proper operation. Resis-

IH

V

TH

as before:

tor values are given for both ECL interface types; in both

cases it is assumed that the LT1715 operates from the

same supply rail.

R2´ = (V – V )/(V /R1 + (V – V /2)/R3)

REF

TH

S

For additional hysteresis of 10mV or less, it is not uncom-

mon for R2´ to be the same as R2 within 1% resistor

tolerances.

Figure 8c shows the case of translating to PECL from

an LT1715 powered by a 3V supply rail. Again, resistor

values are given for both ECL interface types. This time

four resistors are needed, although with 10KH/E, R3 is not

needed. In that case, the circuit resembles the standard

TTL translator of Figure 8a, but the function of the new

resistor, R4, ismuchdifferent. R4loadstheLT1715output

when high so that the current ﬂowing through R1 doesn’t

forward bias the LT1715’s internal ESD clamp diode.

Although this diode can handle 20mA without damage,

normaloperationandperformanceoftheoutputstagecan

be impaired above 100μA of forward current. R4 prevents

this with the minimum additional power dissipation.

This method will work for additional hysteresis of up to

a few hundred millivolts. Beyond that, the impedance of

R3 is low enough to effect the bias string, and adjust-

ment of R1 may also be required. Note that the currents

through the R1/R2 bias string should be many times the

input currents of the LT1715. For 5% accuracy, the cur-

rent must be at least 20 times the input current, more for

higher accuracy.

Interfacing the LT1715 to ECL

The LT1715’s comparators can be used in high speed ap-

plicationswhereEmitter-CoupledLogic(ECL)isdeployed.

To interface the output of the LT1715 to ECL logic inputs,

standard TTL/CMOS to ECL level translators such as the

10H124, 10H424 and 100124 can be used. The secom-

ponents come at a cost of a few nanoseconds additional

delay as well as supply currents of 50mA or more, and

are only available in quads. A faster, simpler and lower

Finally, Figure 8d shows the case of driving standard,

negative-rail, ECL with the LT1715. Resistor values are

given for both ECL interface types and for both a 5V

and 3V LT1715 supply rail. Again, a fourth resistor, R4

is needed to prevent the low state current from ﬂowing

out of the LT1715, turning on the internal ESD/substrate

diodes. Resistor R4 again prevents this with the minimum

additional power dissipation.

1715fa

13

LT1715

APPLICATIONS INFORMATION

tors. Not only can they foul up the operation of the ECL

gate because of overshoots, they can damage the ECL

inputs, particularly during power-up of separate supply

conﬁgurations.

Of course, if the V of the LT1715 is the same as the

EE

ECL negative supply, the GND pin can be tied to it as well

and +V grounded. Then the output stage has the same

S

powerrails as the ECL and the circuits of Figure 8b can

be used.

Theleveltranslatordesignsassumeonegateload.Multiple

gates can have signiﬁcant I loading, and the transmis-

For all the dividers shown, the output impedance is about

110Ω. Thismakesthesefast, lessthanananosecond,with

mostlayouts.Avoidthetemptationtousespeedupcapaci-

IH

sion line routing and termination issues also make this

case difﬁcult.

5V

180Ω

270Ω

820Ω

DO NOT USE FOR LT1715

LEVEL TRANSLATION. SEE TEXT

LSTTL

10KH/E

(a) STANDARD TTL TO PECL TRANSLATOR

+V

S

V

CC

R2

R1

+V

R1

R2

R3

S

1/2 LT1715

10KH/E 5V OR 5.2V 510Ω 180Ω 750Ω

100K/E

4.5V

620Ω 180Ω 510Ω

R3

V

EE

(b) LT1715 OUTPUT TO PECL TRANSLATOR

V

ECL

V

3V

CC

R2

R1

R4

V

R1

R2

R3

R4

ECL

1/2 LT1715

10KH/E 5V OR 5.2V 300Ω 180Ω OMIT 560Ω

100K/E

4.5V

330Ω 180Ω 1500Ω 1000Ω

R3

V

EE

(c) 3V LT1715 OUTPUT TO PECL TRANSLATOR

+V

V

CC

S

R4

ECL FAMILY

V

+V

R1

R2

R3

R4

ECL

S

R1

5V

3V

5V

3V

560Ω 270Ω 330Ω 1200Ω

270Ω 510Ω 300Ω 330Ω

680Ω 270Ω 300Ω 1500Ω

330Ω 390Ω 270Ω 430Ω

1715 F08

1/2 LT1715

10KH/E

–5.2V

–4.5V

R2

R3

100K/E

V

EE

V

ECL

(d) LT1715 OUTPUT TO STANDARD ECL TRANSLATOR

Figure 8

1715fa

14

LT1715

APPLICATIONS INFORMATION

The input stage topology maximizes the input dynamic

range available without requiring the power, complexity

and die area of two complete input stages such as are

found in rail-to-rail input comparators. With a single

2.7V supply, the LT1715 still has a respectable 1.6V of

input common mode range. The differential input volt-

age rangeis rail-to-rail, without the large input currents

found incompeting devices. The input stage also features

phase reversal protection to prevent false outputs when

the inputs are driven below the –100mV common mode

voltage limit.

ECL,andparticularlyPECL,isvaluabletechnologyforhigh

speed system design, but it must be used with care. With

less than a volt of swing, the noise margins need to be

evaluated carefully. Note that there is some degradation of

noise margin due to the 5% resistor selections shown.

With 10KH/E, there is no temperature compensation of

the logic levels, whereas the LT1715 and the circuits

shown give levels that are stable with temperature. This

will lower the noise margin over temperature. In some

conﬁgurations it is possible to add compensation with

diode or transistor junctions in series with the resistors

of these networks.

Theinternalhysteresisisimplementedbypositive,nonlin-

ear feedback around a second gain stage. Until this point,

the signal path has been entirely differential. The signal

path is then split into two drive signals for the upper and

lower output transistors. The output transistors are con-

nected common emitter for rail-to-rail output operation.

The Schottky clamps limit the output voltages at about

300mVfromtherail, notquitethe50mVor15mVofLinear

Technology’srail-to-railampliﬁersandotherproducts.But

the output of a comparator is digital, and this output stage

can drive TTL or CMOS directly. It can also drive ECL, as

described earlier, or analog loads.

For more information on ECL design, refer to the ECLiPS

data book (DL140), the 10KH system design handbook

(HB205) and PECL design (AN1406), all from Motorola,

now ON Semiconductor.

Circuit Description

The block diagram of the LT1715 is shown in Figure 9.

The circuit topology consists of a differential input stage,

again stage with hysteresis and a complementary com-

mon-emitter output stage. All of the internal signal paths

utilize low voltage swings for high speed at low power.

+V

S

NONLINEAR STAGE

+

–

V

CC

+

Σ

+IN

–IN

+

–

+

–

A

V1

A

OUT

V2

+

Σ

+

–

V

EE

GND

1715 F09

Figure 9. LT1715 Block Diagram

1715fa

15

LT1715

APPLICATIONS INFORMATION

The bias conditions and signal swings in the output stage

are designed to turn their respective output transistors off

faster than on. This helps minimize the surge of current

base charge that requires one nanosecond or more of

active charging or discharging by the bias current of

the Darlington driver stage. When toggle rates are high

enough that insufﬁcient time is allowed for this turn-on

or turn-off, glitches may occur leading to dropout or runt

pulses. Furthermore, power consumption may increase

nonlinearly if devices are not turned off before the oppos-

ing cycle. However, once the toggle frequency increases

or decreases, the part will easily leave this undesired

operating mode no worse for the wear provided there

is adequate heat sinking toprevent thermal overload. At

frequencieswellbeyondthemaximumtogglerate,thepart

will toggle with limited output swing and well controlled

power consumption.

from +V to ground that occurs at transitions, to minimize

S

thefrequency-dependentincreaseinpowerconsumption.

The frequency dependence of the supply current is shown

in the Typical Performance Characteristics.

Speed Limits

The LT1715 comparator is intended for high speed ap-

plications, where it is important to understand a few

limitations. These limitations can roughly be divided into

three categories: input speed limits, output speed limits,

and internal speed limits.

The internal speed limits manifest themselves as disper-

sion. All comparators have some degree of dispersion,

deﬁned as a change in propagation delay versus input

overdrive. The propagation delay of the LT1715 will vary

with overdrive, from a typical of 4ns at 20mV overdrive

to 6ns at 5mV overdrive (typical). The LT1715’s primary

source of dispersion is the hysteresis stage. As a change

of polarity arrives at the gain stage, the positive feedback

of the hysteresis stage subtracts from the overdrive avail-

able. Only when enough time has elapsed for a signal to

propagate forward through the gain stage, backwards

through the hysteresis path and forward through the gain

stage again, will the output stage receive the same level

of overdrive that it would have received in the absence of

hysteresis.

Therearenosigniﬁcantinputspeedlimitsexcepttheshunt

capacitance of the input nodes. If the 2pF typical input

nodes are driven, the LT1715 will respond.

Theoutputspeedisconstrainedbythreemechanisms,the

ﬁrstofwhichistheslewcurrentsavailablefromtheoutput

transistors. To maintain low power quiescent operation,

the LT1715 output transistors are sized to deliver 35mA

to 60mA typical slew currents. This is sufﬁcient to drive

small capacitive loads and logic gate inputs at extremely

high speeds. But the slew rate will slow dramatically with

heavycapacitiveloads.Becausethepropagationdelay(t )

PD

deﬁnition ends at the time the output voltage is halfway

between the supplies, the ﬁxed slew current makes the

LT1715 faster at 3V than 5V with large capacitive loads

and sufﬁcient input overdrive.

The LT1715 is several hundred picoseconds faster when

Another manifestation of this output speed limit is skew,

V

= –5V, relative to single supply operation. This is due

EE

+

–

the difference between t

and t . The slew currents

PD

totheinternalspeedlimit;thegainstageoperatesbetween

EE

of the LT1715 vary with the process variations of the PNP

and NPN transistors, for rising edges and falling edges

respectively. The typical 0.5ns skew can have either polar-

ity, rising edge or falling edge faster. Again, the skew will

increase dramatically with heavy capacitive loads.

V

and +V , and it is faster with higher reverse voltage

S

bias due to reduced silicon junction capacitances.

Inmanyapplications, asshowninthefollowingexamples,

there is plenty of input overdrive. Even in applications pro-

viding low levels of overdrive, the LT1715 is fast enough

that the absolute dispersion of 2ns (= 6 – 4) is often small

enough to ignore.

A ﬁnal limit to output speed is the turn-on and turn-off

time of the output devices. Each device has substantial

1715fa

16

LT1715

APPLICATIONS INFORMATION

ThegainandhysteresisstageoftheLT1715issimple,short

and high speed to help prevent parasitic oscillations while

adding minimum dispersion. This internal “self-latch” can

beusefullyexploitedinmanyapplicationsbecauseitoccurs

early in the signal chain, in a low power, fully differential

stage. It is therefore highly immune to disturbances from

other parts of the circuit, such as the output, or on the

supplylines. Onceahighspeedsignaltripsthehysteresis,

the output will respond, after some propagation delay,

without regard to these external inﬂuences that can cause

trouble in nonhysteretic comparators.

V

Test Circuit

TRIP

The input trip points test circuit uses a 1kHz triangle wave

torepeatedlytripthecomparatorbeingtested.TheLT1715

output is used to trigger switched capacitor sampling of

the triangle wave, with a sampler for each direction.

Because the triangle wave is attenuated 1000:1 and fed to

the LT1715’s differential input, the sampled voltages are

therefore1000timestheinputtripvoltages.Thehysteresis

and offset are computed from the trip points as shown.

1715fa

17

LT1715

SIMPLIFIED SCHEMATIC

1715fa

18

LT1715

PACKAGE DESCRIPTION

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

0.889 ± 0.127

(.035 ± .005)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.497 ± 0.076

(.0196 ± .003)

REF

0.50

0.305 ± 0.038

(.0120 ± .0015)

TYP

(.0197)

10 9

8

7 6

BSC

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0° – 6° TYP

0.254

(.010)

GAUGE PLANE

1

2

3

4 5

0.53 ± 0.152

(.021 ± .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ± 0.0508

(.004 ± .002)

0.50

(.0197)

BSC

MSOP (MS) 0307 REV E

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1715fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LT1715

TYPICAL APPLICATION

High Performance Sine Wave

to Square Wave Converter

Similar delay performance is achieved with input fre-

quencies as high as 50MHz. There is, however, some

additional encroachment into the central ﬂat zone by both

the small amplitude and large amplitude variations. With

small input signals, the hysteresis and dispersion make

the LT1715 act like a comparator with a 12mV hysteresis

Propagationdelayofcomparatorsistypicallyspeciﬁedfora

100mV step with some fraction of that for overdrive. But

in many signal processing applications, such as in com-

munications, the goal is to convert a sine wave, such as

a carrier, to a square wave for use as a timing clock. The

desired behavior is for the output timing to be dependent

on the input timing only. No phase shift should occur as

a function of the input amplitude, which would result in

AM to FM conversion.

span. In other words, a 12mV sine wave at 10MHz will

P-P

barely toggle the LT1715, with 90° of phase lagor 25ns

additional delay.

Above5V at10MHz,theLT1715delaystartstodecrease

P-P

due to internal capacitive feed-forward in the input stage.

Unlike some comparators, the LT1715 will not falsely an-

ticipate a change in input polarity, but the feed-forward is

enoughtomakeatransitionpropagatethroughtheLT1715

faster once the input polarity does change.

The circuit of Figure 12a is a simple LT1715-based sine

wave to square wave converter. The 5V supplies on the

input allow very large swing inputs, while the 3V logic

supplykeepstheoutputswingsmalltominimizecrosstalk.

Figure 12b shows the time delay vs input amplitude with a

10MHz sine wave. The LT1715 delay changes just 0.65ns

overthe26dB amplitude range;2.33° at10MHz. The delay

isparticularlyﬂatyieldingexcellentAMrejectionfrom0dBm

to 15dBm. If a 2:1 transformer is used to drive the input

differentially, this exceptionally ﬂat zone spans –5dBm to

10dBm, a common range for RF signal levels.

5

4

25°C

V

= 5V

CC

EE

= –5V

3

2

+V = 3V

S

10MHz

5V

3V

SINE WAVE

INPUT

1

0

SQUARE WAVE

OUTPUT

+

632mV

0

2V

6.32V

P-P

50Ω

1/2 LT1715

–

–5

5

10

15

20

25

INPUT AMPLITUDE (dBm)

1715 F12b

–5V

1715 F12a

Figure 12a. LT1715-Based Sine Wave to Square Wave Converter

Figure 12b. Time Delay vs Sine Wave Input Amplitude

RELATED PARTS

PART NUMBER

LT1016

DESCRIPTION

COMMENTS

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LT1116

12ns Single Supply Ground-Sensing Comparator

7ns, UltraFast, Single Supply Comparator

4.5ns, 3V/5V/ 5V Single/Dual Rail-to-Rail Comparators

7ns, Low Power, 3V/5V/ 5V Single/Dual Rail-to-Rail Comparators

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LT1711/LT1712

LT1713/LT1714

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Dual/Quad 4.5ns, Single Supply 3V/5V Comparator

1715fa

LT 1008 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTVQ
厂家：	Linear
描述：	4ns, 150MHz Dual Comparator with Independent Input/Output Supplies 为4ns ， 150MHz的双通道比较器，带有独立的输入/输出电源比较器
文件：	总20页 (文件大小：244K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTVQ [Linear]

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