LTM4648IY#PBF_技术文档

LTM4648

Low V , 10A Step-Down

IN

µModule Regulator

FeaTures

DescripTion

The LTM^®4648 is a 10A low V

step-down

n

10A DC Output Current

IN

DC/DC µModule^®(micromodule) regulator. Included in

the package are the switching controller, power FETs,

inductor and all support components. Operating over

an input voltage range of 2.375V to 5.5V, the LTM4648

supports an output voltage range of 0.6V to 5V, set by a

singleexternalresistor.Thishighefficiencydesigndelivers

up to 10A continuous current. Only bulk input and output

capacitors are needed.

n

Input Voltage Range: 2.375V to 5.5V

n

Output Voltage Range: 0.6V to 5V

n

No Heat Sink or Current Derating Up to 85°C

Ambient Temperature

n

1.5ꢀ Maꢁimum Total DC Output Error

n

Multiphase Operation with Current Sharing

n

Remote Sense Amplifier

n

Built-In Temperature Monitor

Selectable Pulse-Skipping Mode/Burst Mode^®

n

Highswitchingfrequencyandacurrentmodearchitecture

enable a very fast transient response to line and load

changes without sacrificing stability. The device supports

frequency synchronization, programmable multiphase

operation and output voltage tracking for supply rail

sequencing.

Operation for High Efficiency at Light Load

n

Soft-Start/Voltage Tracking

n

Protection: Output Overvoltage and Overcurrent

Foldback

n

See LTM4649 for Up to 16V Operation

IN

n

9mm × 15mm × 4.92mm BGA Package

Fault protection features include overvoltage protec-

tion, overcurrent protection and thermal shutdown. The

LTM4648 is offered in a small 9mm × 15mm × 4.92mm

BGA package. The LTM4648 is RoHS compliant. For up

applicaTions

n

Telecom, Networking and Industrial Equipment

n

Point of Load Regulation

to 16V operation, see the LTM4649.

IN

L, LT, LTC, LTM, Burst Mode, µModule, PolyPhase, Linear Technology and the Linear logo are

registered trademarks of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620,

6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending.

Typical applicaTion

Efficiency and Power Loss

at 5V and 3.3V Input

Current Derating, 5V to 1.5V_OUT

with No Heat Sink

2.375V to 5.5V Input, 1.5V Output DC/DC

µModule Regulator

100

95

2.8

2.4

12

V

1.5V

10A

OUT

V

IN

V

IN

OUT

2.375V TO 5.5V

100µF

6.3V

×2

22µF

10V

×2

10

8

DIFFP

DIFFN

90

85

80

75

70

65

2.0

1.6

1.2

0.8

0.4

0

PINS NOT USED

IN THIS CIRCUIT:

LTM4648

INTV

SW

CC

MODE

V

OUT_LCL

6

DIFFOUT

RUN

PHMODE

TEMP

COMP

PGOOD

CLKIN

CLKOUT

TRACK/SS

V

FB

4

GND

0.1µF

6.65k

400LFM

200LFM

0LFM

2

4648 TA01a

V

= 3.3V

= 5V

IN

0

2

4

6

8

10

0

40

60

80

100

120

20

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

4648 TA01b

4648f

1

For more information www.linear.com/LTM4648

LTM4648

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

A

B

C

D

E

F

G

V ............................................................... –0.3V to 6V

IN

GND

V

IN

V

, INTV , PGOOD, RUN (Note 5) .......... –0.3V to 6V

1

2

3

4

5

6

7

8

9

OUT

CC

CLKOUT

MODE, CLKIN, TRACK/SS, DIFFP, DIFFN,

NC

FREQ

CLKIN

PHMODE

MODE

DIFFOUT, PHASMD...............................–0.3V to INTV

FB

CC

V ............................................................ –0.3V to 2.7V

TRACK/SS

DIFFN

COMP (Note 6).......................................... –0.3V to 2.7V

SW

INTV Peak Output Current (Note 6)..................100mA

COMP

FB

CC

TEMP

NC

Internal Operating Temperature Range

PGOOD

DIFFP

DIFFOUT

(Note 2).................................................. –55°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Solder Reflow Body Temperature................. 245°C

V

OUT_LCL

10

11

V

GND

OUT

BGA PACKAGE

68-LEAD (9mm × 15mm × 4.92mm)

T

JMAX

= 125°C, θ = 14°C/W, θ = 5°C/W, θ

= 20°C/W

JA

JCbottom

JCtop

WEIGHT = 1.0g

orDer inForMaTion

LEAD FREE FINISH

LTM4648EY#PBF

LTM4648IY#PBF

TRAY

PART MARKING*

LTM4648Y

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTM4648EY#TRPBF

LTM4648IY#TRPBF

68-Lead (9mm × 15mm × 4.92mm) BGA

LTM4648Y

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping

container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

4648f

2

For more information www.linear.com/LTM4648

LTM4648

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full internal

operating temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 5V per typical application.

SYMBOL

PARAMETER

CONDITIONS

MIN

2.375

0.6

TYP

MAX

5.5

UNITS

l

V

Input DC Voltage

Output Voltage Range

V

IN

5

OUT(RANGE)

OUT(DC)

Output Voltage, Total Variation with

Line and Load

1.477

1.50

1.523

C

= 10µF × 1,C

= 100µF Ceramic,

IN

OUT

FB

100µF POSCAP, R = 6.65k, MODE = GND,

V

= 2.375V to 5.5V, I

= 0A to 10A

OUT

IN

Input Specifications

V

RUN Pin On Threshold

RUN Pin On Hysteresis

Input Supply Bias Current

V

Rising

1.1

1.25

150

1.4

V

RUN

mV

RUN(HYS)

Q(VIN)

I

V

= 5V, V

= 1.5V, Burst Mode Operation

= 1.5V, Pulse-Skipping Mode

= 1.5V, Switching Continuous

5.5

25

100

2.5

mA

IN

OUT

Shutdown, RUN = 0, V = 5V

IN

I

Input Supply Current

V

= 5.5V, V

= 1.5V, I = 10A

OUT

3.3

A

S(VIN)

IN

OUT

Output Specifications

I

Output Continuous Current Range

Line Regulation Accuracy

V

= 5V, V = 1.5V (Note 4)

OUT

0

10

A

OUT(DC)

IN

l

ΔV

= 1.5V, V from 2.375V to 5.5V I = 0A

OUT

0.010

0.15

15

0.04

%/V

OUT(LINE)

OUT

IN

V

OUT

ΔV

Load Regulation Accuracy

Output Ripple Voltage

Turn-On Overshoot

V

= 1.5V, I

= 0A to 10A, V = 5V (Note 4)

0.5

%

mV

ms

mV

OUT(LOAD)

OUT

IN

V

OUT

V

I

= 0A, C

= 100µF Ceramic, 100µF POSCAP,

OUT

OUT(AC)

OUT

V

= 5V, V

= 1.5V

OUT

IN

ΔV

C

V

= 100µF Ceramic, 100µF POSCAP,

20

OUT(START)

OUTLS

OUT

= 1.5V, I

= 0A, V = 5V

IN

OUT

t

Turn-On Time

C

= 100µF Ceramic, 100µF POSCAP,

5

START

OUT

No Load, TRACK/SS = 0.01µF, V = 5V

IN

ΔV

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load,

C

V

60

= 100µF Ceramic, 100µF POSCAP,

OUT

= 5V, V

= 1.5V

OUT

IN

t

I

Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load,

20

µs

A

SETTLE

C

V

= 100µF Ceramic, 100µF POSCAP,

OUT

= 5V, V =1.5V

IN

OUT

Output Current Limit

V

= 5V, V

= 1.5V (Note 4)

OUT

11

OUTPK

IN

Control Specifications

l

V

Voltage at V Pin

I

= 0A, V = 1.5V

OUT

0.593

0.60

–12

0.66

1.2

90

0.607

–25

V

nA

V

FB

OUT

I

Current at V Pin

FB

V

Feedback Overvoltage Lockout

Track Pin Soft-Start Pull-Up Current

Minimum On-Time

0.64

1.0

0.68

1.4

OVL

I

t

TRACK/SS = 0V

(Note 3)

µA

ns

kΩ

TRACK/SS

ON(MIN)

R

Resistor Between V

Pins

and V

FB

9.90

0

10

10.10

3.6

FBHI

OUT_LCL

DIFFP, DIFFN CM Common Mode Input Range

RANGE

V

= 5V, Run > 1.4V

V

IN

V

A

Maximum DIFFOUT Voltage

Input Offset Voltage

Differential Gain

I

= 300µA

INTV – 1.4

V

mV

DIFFOUT(MAX)

DIFFOUT

CC

V

+ = V

= 1.5V, I = 100µA

DIFFOUT

4

OS

V

OSNS

DIFFOUT

1

2

V/V

SR

Slew Rate

V/µs

4648f

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For more information www.linear.com/LTM4648

LTM4648

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full internal

operating temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 5V per typical application.

SYMBOL

GBP

PARAMETER

CONDITIONS

MIN

TYP

3

MAX

UNITS

MHz

dB

Gain Bandwidth Product

Common Mode Rejection

DIFFOUT Current

CMRR

(Note 6)

Sourcing

60

I

2

mA

DIFFOUT

R

Input Resistance

V

+ to GND

OSNS

80

kΩ

IN

V

PGOOD Trip Level

With Respect to Set Output

PGOOD

FB

V

Ramping Negative

Ramping Positive

–10

10

%

FB

V

PGOOD Voltage Low

I

= 2mA

PGOOD

0.1

0.3

V

PGL

INTV Linear Regulator

CC

V

Internal V Voltage

2.375V ≤ V ≤ 5V

IN

4.8

5.15

5

5.25

5.2

5.35

V

INTVCC

CC

IN

V

= 5.5V

V

Load Reg INTV Load Regulation

I

= 0mA to 50mA

0.5

%

INTVCC

CC

Oscillator and Phase-Locked Loop

f

SYNC Capture Range

250

400

650

500

kHz

kΩ

V

SYNC

S

Nominal Switching Frequency

Mode Input Resistance

Clock Input Level High

Clock Input Level Low

450

250

R

MODE

V

2.0

IH_CLKIN

IL_CLKIN

0.8

V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime. Notes are automatically numbered when you apply

the note style.

Note 3: The minimum on-time condition is tested at wafer sort.

Note 4: See output current derating curves for different V , V

Note 5: Guaranteed by design.

and T .

IN OUT

A

Note 6: 100% tested at wafer level.

Note 2: The LTM4648 is tested under pulsed load conditions such that T ≈

J

T . The LTM4648E is guaranteed to meet performance specifications over

A

the 0°C to 125°C internal operating temperature range. Specifications over

the –40°C to 125°C internal operating temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTM4648I is guaranteed to meet specifications over the –40°C to

125°C internal operating temperature range. Note that the maximum

ambient temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal resistance and other environmental factors.

4648f

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For more information www.linear.com/LTM4648

LTM4648

Typical perForMance characTerisTics

2.5V_INEfficiency

3.3V_INEfficiency

5V_INEfficiency

100

95

100

95

100

95

90

85

80

75

70

65

90

85

80

75

70

65

90

85

80

75

70

65

V

= 1V

OUT

= 1.2V

= 1.5V

= 1.8V

= 2.5V

= 3.3V

V

= 1V

OUT

V

= 1V

= 1.2V

= 1.5V

= 1.8V

= 2.5V

OUT

= 1.2V

= 1.5V

= 1.8V

2

4

6

10

2

4

6

10

2

4

6

10

0

8

0

8

0

8

LOAD CURRENT (A)

4648 G01

4648 G02

4648 G03

CCM, Burst Mode and Pulse-

Skipping Mode Efficiency

(V_IN= 3.3V, V_OUT= 1.5V)

CCM, Burst Mode and Pulse-

Skipping Mode Efficiency

(V_IN= 5V, V_OUT= 1.5V)

3.3V_IN, 1V_OUTLoad Transient

100

90

100

90

V

OUT

80

100mV/DIV

AC-COUPLED

70

60

50

60

50

I

OUT

5A/DIV

AC-COUPLED

40

30

20

10

0

40

30

20

10

0

4648 G06

20µs/DIV

3.3V , 1V , 5A TO 10A LOAD STEP, 5A/µs

IN

OUT

C

= 1 • 22µF, 6.3V, 1210 + 2 • 100µF 1210

CCM

CERAMIC CAPACITORS

Burst Mode OPERATION

PULSE SKIPPING

Burst Mode OPERATION

PULSE SKIPPING

NO C CAPACITOR

FF

0.01

0.1

1

10

0.01

0.1

1

10

LOAD CURRENT (A)

4648 G04

4648 G05

5V_IN, 1V_OUTLoad Transient

3.3V_IN, 1.5V_OUTLoad Transient

5V_IN, 1.5V_OUTLoad Transient

V

OUT

100mV/DIV

AC-COUPLED

I

OUT

5A/DIV

AC-COUPLED

4648 G07

4648 G08

4648 G09

20µs/DIV

3.3V , 1.5V , 5A TO 10A LOAD STEP, 5A/µs

20µs/DIV

5V , 1V , 5A TO 10A LOAD STEP, 5A/µs

5V , 1.5V , 5A TO 10A LOAD STEP, 5A/µs

IN

OUT

IN

OUT

IN

OUT

C

= 1 • 22µF, 6.3V, 1210 + 2 • 100µF 6.3V

C

= 1 • 22µF, 6.3V, 1210 + 2 • 100µF 6.3V

C

= 1 • 22µF, 6.3V, 1210 + 2 • 100µF 6.3V

OUT

1210 CERAMIC CAPACITORS

NO C CAPACITOR

1210 CERAMIC CAPACITORS

NO C CAPACITOR

1210 CERAMIC CAPACITORS

NO C CAPACITOR

FF

4648f

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For more information www.linear.com/LTM4648

LTM4648

Typical perForMance characTerisTics

3.3V_IN, 2.5V_OUTLoad Transient

5V_IN, 2.5V_OUTLoad Transient

5V_IN, 3.3V_OUTLoad Transient

V

OUT

100mV/DIV

AC-COUPLED

I

OUT

5A/DIV

AC-COUPLED

4648 G10

4648 G11

4648 G12

20µs/DIV

3.3V , 2.5V , 5A TO 10A LOAD STEP, 5A/µs

5V , 2.5V , 5A TO 10A LOAD STEP, 5A/µs

5V , 3.3V , 5A TO 10A LOAD STEP, 5A/µs

IN

OUT

IN

OUT

IN

OUT

C

= 1 • 22µF, 6.3V, 1210 + 2 • 100µF 6.3V

C

= 1 • 22µF, 6.3V, 1210 + 2 • 100µF 6.3V

C

= 1 • 22µF, 6.3V, 1210 + 2 • 100µF 6.3V

OUT

1210 CERAMIC CAPACITORS

NO C CAPACITOR

FF

Output Start-Up

RUN

2V/DIV

RUN

2V/DIV

PGOOD

2V/DIV

PGOOD

2V/DIV

V

OUT

0.5V/DIV

I

IN

I

IN

0.5A/DIV

4648 G13

4648 G14

5V

10ms/DIV

5V

10ms/DIV

I = 10A START-UP

O

IN

OUT

IN

1.5V

OUT

I

= 0A START-UP

O

C

= 0.1µF

C

= 0.1µF

SS

Output Short Circuit

V

OUT

0.5V/DIV

V

I

IN

OUT

0.5V/DIV

I

IN

0.5A/DIV

4648 G15

4648 G16

5V

50µs/DIV

5V

50µs/DIV

IN

OUT

IN

1.5V

OUT

I

= 0A

I

= 10A

OUT

4648f

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For more information www.linear.com/LTM4648

LTM4648

pin FuncTions

PACKAGE ROW AND COLUMN LABELING MAY VARY

V

(G9): This pin is connected to the top of the

OUT_LCL

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

internal top feedback resistor for the output. When the

remote sense amplifier is used in the LTM4648, connect

the remote sense amplifier output DIFFOUT to V

GND (A1-A5, A7-A11, B1, B9-B11, E1, F3, F5, G1-G7):

GroundPinsforBothInputandOutputReturns.Allground

pins need to connect with large copper areas underneath

the unit.

OUT_LCL

to drive the 10k top feedback resistor. When the remote

sense amplifier is not used in the LTM4648, connect

V

to V

directly.

OUT

OUT_LCL

FREQ (E3): Frequency Set Pin. A 10µA current is sourced

from this pin. A resistor from this pin to ground sets a

voltage, that in turn, programs the operating frequency.

Alternatively, this pin can be driven with a DC voltage that

can set the operating frequency. See the Applications In-

formation section. The LTM4648 has an internal resistor

to program frequency to 450kHz.

TEMP (A6): Onboard Temperature Diode for Monitoring

the VBE Junction Voltage Change with Temperature. See

the Applications Information section.

CLKIN (B3): External Synchronization Input to Phase De-

tector Pin. A clock on this pin will enable synchronization

with forced continuous operation. See the Applications

Information section.

TRACK/SS (E5): Output Voltage Tracking Pin and Soft-

Start Inputs. The pin has a 1.2µA pull-up current source.

A capacitor from this pin to ground will set a soft-start

ramp rate. In tracking, the regulator output can be tracked

to a different voltage. The different voltage is applied to

a voltage divider then the slave output’s track pin. This

voltage divider is equal to the slave output’s feedback

divider for coincidental tracking. See the Applications

Information section.

PHMODE (B4): This pin can be tied to GND, tied to INTV

CC

or left floating. This pin determines the relative phases

between the internal controllers and the phasing of the

CLKOUT signal. See Table 2 in the Operation section.

MODE(B5):ModeSelectInput.ConnectthispintoINTV

CC

to enable Burst Mode operation. Connect to ground to

enable forced continuous mode of operation. Floating this

pin will enable pulse-skipping mode of operation.

NC(B7-B8, C3-C4):NoConnectionPins. Eitherfloatthese

FB(E7):TheNegativeInputoftheErrorAmplifier.Internally,

pins or connect them to GND for thermal purpose.

this pin is connected to V

with a 10k precision

OUT_LCL

resistor. Different output voltages can be programmed

V (C1, C8, C9, D1, D3-D5, D7-D9 and E8): Power Input

IN

with an additional resistor between V and ground pins.

FB

Pins. Apply input voltage between these pins and GND

In PolyPhase operation, tying the V pins together allows

FB

pins. Recommend placing input decoupling capacitance

for parallel operation. See the Applications Information

directly between V pins and GND pins.

IN

section for details.

V

(C10-C11, D10-D11, E9-E11, F9-F11, G10-G11):

OUT

RUN (F1): Run Control Pin. A voltage above 1.4V will turn

on the module. The RUN pin has a 1µA pull-up current,

oncetheRUNpinreaches1.2Vanadditional4.5µApull-up

current is added to this pin.

Power Output Pins. Apply output load between these pins

and GND pins. Recommend placing output decoupling

capacitance directly between these pins and GND pins.

See Table 1.

CLKOUT (F2): Output Clock Signal for PolyPhase Opera-

tion. The phase of CLKOUT is determined by the state of

the PHMODE pin.

SW (C5): Switching Node of the Circuit. This pin is used

to check the switching frequency. Leave pin floating. A

resistor-capacitor snubber can be placed from SW to

PGND to eliminate high frequency switch node ringing.

See the Applications Information section.

INTV (F4): Internal 5V LDO for Driving the Control Cir-

CC

cuitry and the Power MOSFET Drivers. The 5V LDO has

a 100mA current limit.

PGOOD (C7): Output Voltage Power Good Indicator.

Open-drain logic output that is pulled to ground when the

output voltage is not within 10% of the regulation point.

4648f

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For more information www.linear.com/LTM4648

LTM4648

pin FuncTions

DIFFP (F8): Input to the Remote Sense Amplifier. This

pin connects to the output remote sense point. Connect

to GND when not used.

COMP(F6):CurrentControlThresholdandErrorAmplifier

Compensation Point. The current comparator threshold

increases with this control voltage. Tie all COMP pins

together in parallel operation.

DIFFOUT (G8): Output of the Remote Sense Amplifier.

This pin connects to the V

pin for remote sense

DIFFN (F7): Input to the Remote Sense Amplifier. This

pin connects to the ground remote sense point. Connect

to GND when not used.

OUT_LCL

applications. Otherwise float when not used.

block DiagraM

INTV

CC

V

OUT_LCL

V

OUT

1M

10k

V

IN

PGOOD

> 1.4V = ON

< 1.1V = OFF

MAX = 5V

R1

R2

V

IN

RUN

V

BOOST

CONVERTER

IN

2.375V TO 5.5V

+

1µF

C

IN

COMP

10k

0.5%

5V

M1

M2

INTERNAL

COMP

0.35µH

V

1.5V

10A

OUT

V

OUT

GND

POWER

CONTROL

+

V

FB

C

OUT

f

SET

6.65k

1%

GND

R

fSET

115k

INTERNAL

LOOP

FILTER

TRACK/SS

INTV

CC

DIFFN

DIFFP

–

+

C

SS

CLKIN

DIFF

AMP

MODE

–

250k

DIFF_OUT

INTV

CC

1µF

TEMP

4648 F01

Figure 1. Simplified LTM4648 Block Diagram

4648f

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For more information www.linear.com/LTM4648

LTM4648

operaTion

Power Module Description

The LTM4648 is internally compensated to be stable over

all operating conditions. Table 3 provides a guideline for

input and output capacitances for several operating con-

ditions. The Linear Technology µModule Power Design

Tool will be provided for transient and stability analysis.

The LTM4648 is a high performance single output stand-

alone nonisolated switching mode DC/DC power supply.

It can provide up to 10A output current with few exter-

nal input and output capacitors. This module provides

precisely regulated output voltage programmable via an

external resistor from 0.6VDC to 5VDC over a 2.375V to

5.5V input range. The typical application schematic is

shown in Figure 18.

The V pin is used to program the output voltage with a

FB

single external resistor to ground.

A remote sense amplifier is provided in the LTM4648 for

accuratelysensingoutputvoltages≤3.3Vattheloadpoint.

The LTM4648 has an integrated constant-frequency cur-

rentmoderegulator, powerMOSFETs, inductor, andother

supporting discrete components. The typical switching

frequency is 450kHz. For switching noise-sensitive ap-

plications, it can be externally synchronized from 350kHz

to 650kHz. See the Applications Information section.

Multiphase operation can be easily employed with the

synchronization inputs using an external clock source.

See application examples.

High efficiency at light loads can be accomplished with

selectableBurstModeoperationusingtheMODEpin.These

light load features will accommodate battery operation.

Efficiency graphs are provided for light load operation in

the Typical Performance Characteristics section.

With current mode control and internal feedback loop

compensation, the LTM4648 module has sufficient stabil-

ity margins and good transient performance with a wide

range of output capacitors, especially with all ceramic

output capacitors.

A diode connected PNP transistor with base and collector

grounded is included in the module as a general purpose

single-ended temperature monitor. The temperature

monitor is intended to be used as a general temperature

monitor, see Applications Information section

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit in an overcurrent condition. An internal overvoltage

monitor protects the output voltage in the event of an

overvoltage >10%. The top MOSFET is turned off and the

bottom MOSFET is turned on until the output is cleared.

Theswitchingnodepinsareavailableforfunctionalopera-

tion monitoring and a resistor-capacitor snubber circuit

can be careful placed on the switching node pin to ground

to dampen any high frequency ringing on the transition

edges.SeetheApplicationsInformationsectionfordetails.

Pulling the RUN pin below 1.1V forces the regulator into a

shutdown state. The TRACK/SS pin is used for program-

ming the output voltage ramp and voltage tracking during

start-up. See the Application Information section.

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The typical LTM4648 application circuit is shown in

Figure 18. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 3 for specific external capacitor

requirements for particular applications.

error due to this current, an additional V

pin can

OUT_LCL

be tied to V , and an additional R resistor can be used

OUT

FB

to lower the total Thevenin equivalent resistance seen by

this current.

Input Capacitors

V to V

Step-Down Ratios

IN

OUT

The LTM4648 module should be connected to a low AC

impedance DC source. Additional input capacitors are

neededfortheRMSinputripplecurrentrating.TheI

There are restrictions in the V to V

step-down ratio

IN

OUT

that can be achieved for a given input voltage. The V to

IN

CIN(RMS)

V

OUT

minimum dropout is a function of load current and

equation which follows can be used to calculate the input

capacitor requirement. Typically 22µF X7R ceramics are a

good choice with RMS ripple current ratings of ~2A each.

A47µFto100µFsurfacemountaluminumelectrolyticbulk

capacitor can be used for more input bulk capacitance.

This bulk input capacitor is only needed if the input source

impedanceiscompromisedbylonginductiveleads,traces

ornotenoughsourcecapacitance.Iflowimpedancepower

planes are used, then this bulk capacitor is not needed.

at very low input voltage and high duty cycle applications

output power may be limited as the internal top power

MOSFET is not rated for 10A operation at higher ambient

temperatures. At very low duty cycles the minimum 90ns

on-time must be maintained. See the Frequency Adjust-

ment section and temperature derating curves.

Output Voltage Programming

The PWM controller has an internal 0.6V 1% reference

voltage. As shown in the Block Diagram, a 10k 0.5%

For a buck converter, the switching duty cycle can be

estimated as:

internal feedback resistor connects the V

and

OUT_LCL

V_OUT

V

pins together. When the remote sense amplifier is

D =

FB

V

IN

used, then DIFFOUT is connected to the V

pin.

OUT_LCL

If the remote sense amplifier is not used, then V

OUT_LCL

Without considering the inductor ripple current, for each

output, the RMS current of the input capacitor can be

estimated as:

connects to V . The output voltage will default to 0.6V

with no feedback resistor. Adding a resistor R from V

OUT

FB

to ground programs the output voltage:

I_OUT(MAX)

10k +R_FB

V_OUT= 0.6V •

R_FB

I_CIN(RMS)

=

• D• 1−D

(

)

η%

In the previous equation, η% is the estimated efficiency of

the power module. The bulk capacitor can be a switcher-

rated electrolytic aluminum capacitor or a Polymer

capacitor.

Table 1. V_FBResistor Table vs Various Output Voltages

V

(V)

OUT

0.6

1.0

1.2

1.5

1.8

2.5

3.3

5.0

R (k)

FB

OPEN

15

10

6.65 4.99 3.09 2.21 1.37

For parallel operation of N LTM4648, the following equa-

Output Capacitors

tion can be used to solve for R :

FB

The LTM4648 is designed for low output voltage ripple

10k

N

noise. The bulk output capacitors defined as C

are

OUT

R_FB=

chosen with low enough effective series resistance (ESR)

to meet the output voltage ripple and transient require-

V_OUT

0.6

–1

ments. C

can be a low ESR tantalum capacitor, low

OUT

ESR Polymer capacitor or ceramic capacitors. The typical

outputcapacitancerangeisfrom200µFto470µF.Additional

In parallel operation the V pins have an I current of

FB

20nA maximum each channel. To reduce output voltage

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output filtering may be required by the system designer

if further reduction of output ripple or dynamic transient

spikes is required. Table 3 shows a matrix of different

output voltages and output capacitors to minimize the

voltage droop and overshoot during a 5A/µs transient.

The table optimizes total equivalent ESR and total bulk

capacitanceto optimize thetransientperformance. Stabil-

ity criteria are considered in the Table 3 matrix, and the

Linear Technology µModule Power Design Tool will be

provided for stability analysis. Multiphase operation will

reduce effective output ripple as a function of the num-

ber of phases. Application Note 77 discusses this noise

reduction versus output ripple current cancellation, but

the output capacitance should be considered carefully as

a function of stability and transient response. The Linear

Technology µModule Power Design Tool can calculate the

output ripple reduction as the number of implemented

phase’s increases by N times.

Pulse-Skipping Mode Operation

Inapplicationswherelowoutputrippleandhighefficiency

atintermediatecurrentsaredesired, pulse-skippingmode

should be used. Pulse-skipping operation allows the

LTM4648toskipcyclesatlowoutputloads,thusincreasing

efficiency by reducing switching loss. Floating the MODE

pinenablespulse-skippingoperation.Withpulse-skipping

mode at light load, the internal current comparator may

remain tripped for several cycles, thus skipping opera-

tion cycles. This mode has lower ripple than Burst Mode

operationandmaintainsahigherfrequencyoperationthan

Burst Mode operation.

Forced Continuous Operation

In applications where fixed frequency operation is more

critical than low current efficiency, and where the lowest

output ripple is desired, forced continuous operation

should be used. Forced continuous operation can be

enabled by tying the MODE pin to ground. In this mode,

inductor current is allowed to reverse during low output

loads, the COMP voltage is in control of the current

comparator threshold throughout, and the top MOSFET

alwaysturnsonwitheachoscillatorpulse.Duringstart-up,

forced continuous mode is disabled and inductor current

is prevented from reversing until the LTM4648’s output

voltage is in regulation.

Burst Mode Operation

TheLTM4648iscapableofBurstModeoperationinwhich

the power MOSFETs operate intermittently based on load

demand, thus saving quiescent current. For applications

where maximizing the efficiency at very light loads is a

high priority, Burst Mode operation should be applied. To

enable Burst Mode operation, simply tie the MODE pin to

INTV . During Burst Mode operation, the peak current

CC

of the inductor is set to approximately 30% of the maxi-

mum peak current value in normal operation even though

the voltage at the COMP pin indicates a lower value. The

voltage at the COMP pin drops when the inductor’s aver-

age current is greater than the load requirement. As the

COMP voltage drops below 0.5V, the burst comparator

trips, causing the internal sleep line to go high and turn

off both power MOSFETs.

Frequency Selection

The LTM4648 device is internally programmed to 450kHz

switching frequency to improve power conversion ef-

ficiency. It is recommended for all of the application.

If desired, a resistor can be connected from the FREQ pin

to INTV to adjust the FREQ pin DC voltage to increase

CC

the switching frequency between default 450kHz and

maximum 650kHz. Figure 2 shows a graph of frequency

setting verses FREQ pin DC voltage. Figure 18 shows an

example of frequency programmed to 650kHz. Please be

aware FREQ pin has an accurate 10µA current sourced

from this pin when calculate the resistor value.

In sleep mode, the internal circuitry is partially turned

off, reducing the quiescent current. The load current is

now being supplied from the output capacitors. When the

output voltage drops, causing COMP to rise, the internal

sleep line goes low, and the LTM4648 resumes normal

operation. The next oscillator cycle will turn on the top

power MOSFET and the switching cycle repeats.

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900

800

700

600

500

400

300

200

100

0

Multiphase Operation

For outputs that demand more than 10A of load current,

multiple LTM4648 devices can be paralleled to provide

more output current and reduced input and output volt-

age ripple.

The CLKOUT signal together with CLKIN pin can be used

to cascade additional power stages to achieve the multi-

phase power supply solution. Tying the PHMODE pin to

INTV , GND, or (floating) generates a phase difference

CC

0

0.5

1

1.5

2

2.5

(between MODE/PLLIN and CLKOUT) of 180°, 120°, or

90° respectively as shown in Table 2. A total of 4 phases

can be cascaded to run simultaneously with respect to

each other by programming the PHMODE pin of each

LTM4648 channel to different levels. Figure 3 shows a

3-phase design and 4-phase design example for clock

phasing with the PHASMD table.

FREQ PIN VOLTAGE (V)

4648 F02

Figure 2. Operating Frequency vs FREQ Pin Voltage

PLL and Frequency Synchronization

The LTM4648 device operates over a range of frequen-

cies to improve power conversion efficiency. The nominal

switchingfrequencyis450kHz.Itcanalsobesynchronized

from 350kHz to 650kHz with an input clock that has a high

level above 2V and a low level below 0.8V at the CLKIN pin.

Once the LTM4648 is synchronizing to an external clock

frequency, it will always running in Forced Continuous

Operation. The 350kHz low end operation frequency limit

is put in place to limit inductor ripple current.

Table 2. PHASEMD and CLKOUT Signal Relationship

PHASEMD

GND

FLOAT

INTV

CC

CLKOUT

120°

90°

180°

The LTM4648 device is an inherently current mode con-

trolled device, so parallel modules will have good current

sharing. This will balance the thermals in the design. Tie

theCOMP,V ,TRACK/SSandRUNpinsofeachLTM4648

FB

together to share the current evenly. Figures 20 and 21

show a schematic of the parallel design.

3-PHASE DESIGN

120 DEGREE

CLKOUT

120 DEGREE

CLKOUT

CLKIN

0 PHASE

GND

120 PHASE

GND

240 PHASE

V

OUT

V

OUT

V

OUT

GND

PHASMD

4-PHASE DESIGN

90 DEGREE

CLKOUT

CLKIN

0 PHASE

FLOAT

90 PHASE

180 PHASE

FLOAT

270 PHASE

V

OUT

V

OUT

V

OUT

V

OUT

FLOAT

PHASMD

4648 F03

Figure 3. Eꢁamples of 3-Phase, 4-Phase Operation with PHASMD Table

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A multiphase power supply could significantly reduce

the amount of ripple current in both the input and output

capacitors. The RMS input ripple current is reduced by,

and the effective ripple frequency is multiplied by, the

number of phases used (assuming that the input voltage

isgreaterthanthenumberofphasesusedtimestheoutput

voltage). The output ripple amplitude is also reduced by

the number of phases used.

Minimum On-Time

Minimum on-time t is the smallest time duration that

ON

the LTM4648 is capable of turning on the top MOSFET.

It is determined by internal timing delays, and the gate

charge required turning on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

V_OUT

> t_ON(MIN)

Input RMS Ripple Current Cancellation

V •FREQ

IN

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current can-

cellation mathematical derivations are presented, and a

graph is displayed representing the RMS ripple current

reductionasafunctionofthenumberofinterleavedphases

(see Figure 4).

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles.Theoutputvoltagewillcontinuetoberegulated,but

the output ripple and current will increase. The minimum

on-time can be increased by lowering the switching fre-

quency. A good rule of thumb is to use an 110ns on-time.

0.60

1-PHASE

2-PHASE

0.55

3-PHASE

4-PHASE

6-PHASE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY FACTOR (V /V

)

IN

O

4648 F04

Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

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Soft-Start

output, then the slave will coincident track with the master

until it reaches its final value. The master will continue to

its final value from the slave’s regulation point. Voltage

The TRACK/SS pin of the master can be controlled by a

capacitor placed on the master regulator TRACK/SS pin

to ground. A 1.2µA current source will charge the TRACK/

SS pin up to the reference voltage and then proceed up

tracking is disabled when V

is more than 0.6V. RTA

TRACK

in Figure 5 will be equal to the R for coincident tracking.

FB

Figure 6 shows the coincident tracking waveforms.

to INTV . After the 0.6V ramp, the TRACK/SS pin will no

CC

longer be in control, and the internal voltage reference

will control output regulation from the feedback divider.

Foldback current limit is disabled during this sequence of

turn-on during tracking or soft-starting. The TRACK/SS

pins are pulled low when the RUN pin is below 1.2V. The

total soft-start time can be calculated as:

Ratiometric tracking can be achieved by a few simple cal-

culations and the slew rate value applied to the master’s

TRACK/SS pin. As mentioned above, the TRACK/SS pin

has a control range from 0V to 0.6V. The master’s TRACK/

SS pin slew rate is directly equal to the master’s output

slew rate in Volts/Time. The equation:

MR

⎛ C_SS

⎞

⎠

•10k = R_TB

SR

t_SS

=

• 0.6

⎜

⎟

⎝

1.2µA

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in Volts/Time. When coincident

Regardless of the mode selected by the MODE pin, the

regulator channels will always start in pulse-skipping

mode up to TRACK/SS = 0.5V. Between TRACK/SS = 0.5V

and 0.54V, it will operate in forced continuous mode and

revert to the selected mode once TRACK/SS > 0.54V. In

order to track with another channel once in steady state

operation, the LTM4648 is forced into continuous mode

tracking is desired, then MR and SR are equal, thus R

TB

is equal the 10k. R is derived from equation:

TA

0.6V

R_TA

=

V_TRACK

R_TB

V

FB

+

−

10k R_FB

operation as soon as V is below 0.54V regardless of the

FB

setting on the MODE pin.

where V is the feedback voltage reference of the regula-

FB

tor, and V

is 0.6V. Since R is equal to the 10k top

TRACK

TB

Output Voltage Tracking

feedback resistor of the slave regulator in equal slew rate

or coincident tracking, then R is equal to R with V

TA

FB

Output voltage tracking can be programmed externally

using the TRACK/SS pins. The output can be tracked up

and down with another regulator. The master regulator’s

output is divided down with an external resistor divider

that is the same as the slave regulator’s feedback divider

to implement coincident tracking. The LTM4648 uses an

accurate 60.4k resistor internally for the top feedback

resistor for each channel. Figure 6 shows an example of

coincident tracking. Equations:

= V

. Therefore R = 10k, and R = 10k in Figure 4.

TRACK

TB TA

Inratiometrictracking, adifferentslewratemaybedesired

for the slave regulator. R can be solved for when SR

TB

is slower than MR. Make sure that the slave supply slew

rate is chosen to be fast enough so that the slave output

voltage will reach it final value before the master output.

Each of the TRACK/SS pins will have the 1.2µA current

source on when a resistive divider is used to implement

trackingonthatspecificchannel.Thiswillimposeanoffset

on the TRACK/SS pin input. Smaller values resistors with

the same ratios as the resistor values calculated from the

above equation can be used. For example, where the 10k

is used then a 1.0k can be used to reduce the TRACK/SS

pin offset to a negligible value.

⎛

⎞

10k

R_TA

V_SLAVE= 1+

• V_TRACK

⎜

⎟

⎝

⎠

V

is the track ramp applied to the slave’s track pin.

has a control range of 0V to 0.6V, or the internal

TRACK

reference voltage. When the master’s output is divided

down with the same resistor values used to set the slave’s

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V

IN

C7

22µF

16V

C10

22µF

16V

SOFT-START

CAPACITOR

INTV

PGOOD

V

IN

CC

V

1.5V

10A

OUT2

COMP

V

OUT

C

R2

10k

SS

C11

TRACK/SS

V

100µF

6.3V

×2

OUT_LCL

LTM4648

RUN

DIFFOUT

DIFFP

FREQ

MODE

DIFFN

V

FB

GND

R

FB1

6.65k

V

IN

C3

C2

MASTER RAMP

OR OUTPUT

22µF

16V

22µF

16V

PGOOD

V

INTV

CC

IN

V

1.2V

10A

OUT1

R

TB

R

TA

COMP

V

OUT

V

OUT_LCL

10k

R1

10k

C6

TRACK/SS

RUN

100µF

6.3V

×2

LTM4648

DIFFOUT

DIFFP

FREQ

MODE

DIFFN

4628 F05

V

FB

GND

R

FB

10k

Figure 5. Dual Outputs (1.5V and 1.2V) with Tracking

Power Good

MASTER OUTPUT

SLAVE OUTPUT

The PGOOD pins are open-drain pins that can be used to

monitor valid output voltage regulation. This pin monitors

a 7.5% window around the regulation point. A resistor

can be pulled up to a particular supply voltage no greater

than 6V maximum for monitoring.

Stability Compensation

The module has already been internally compensated

for all output voltages. Table 3 is provided for most ap-

plication requirements. The Linear Technology µModule

Power Design Tool will be provided for other control loop

optimization.

TIME

4648 F06

Figure 6. Output Coincident Tracking Waveform

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Run Enable

where f is the resonant frequency of the ring, and L is the

total parasitic inductance in the switch path. If a resistor

is selected that is equal to Z, then the ringing should be

dampened. The snubber capacitor value is chosen so that

itsimpedanceisequaltotheresistorattheringfrequency.

Calculated by:

The RUN pin has an enable threshold of 1.40V maximum,

typically 1.25V with 150mV of hysteresis. It controls the

turn-on of the µModule. The RUN pin can be pulled up to

V for 5V operation, or a 5V Zener diode can be placed

IN

on the pin and a 10k to 100k resistor can be placed up to

higher than 5V input for enabling the µModule. The RUN

pin can also be used for output voltage sequencing.

1

Z_C=

2π •f•C

These values are a good place to start with. Modification

to these components should be made to attenuate the

ringing with the least amount the power loss.

In parallel operation the RUN pins can be tied together and

controlled from a single control. See the Typical Applica-

tion circuits in Figures 20 and 21. The RUN pin can also

be left floating. The RUN pin has a 1µA pull-up current

source that increases to 4.5µA during ramp-up.

Temperature Monitoring

Measuring the absolute temperature of a diode is pos-

sible due to the relationship between current, voltage

and temperature described by the classic diode equation:

Differential Remote Sense Amplifier

Anaccuratedifferentialremotesenseamplifierisprovided

in the LTM4648 to sense low output voltages accurately

at the remote load points. This is especially true for high

current loads. It is very important that the DIFFP and

DIFFN are connected properly at the output, and DIFFOUT

⎛

⎞

V_D

η• V

I_D= I_S• e

⎜

⎟

⎝

⎠

T

or

I

is connected to V

. Review the parallel schematics

V_D= η• V_T•ln ^D

OUT_LCL

in Figures 20 and 21.

I_S

where I is the diode current, V is the diode voltage, η is

D

SW Pins

the ideality factor (typically close to 1.0) and I (satura-

S

The SW pin is generally for testing purposes by monitor-

ing the pin. The SW pin can also be used to dampen out

switchnoderingingcausedbyLCparasiticintheswitched

current path. Usually a series R-C combination is used

called a snubber circuit. The resistor will dampen the

resonance and the capacitor is chosen to only affect the

high frequency ringing across the resistor.

tion current) is a process dependent parameter. V can

T

be broken out to:

k • T

q

V_T=

where T is the diode junction temperature in Kelvin, q is

the electron charge and k is Boltzmann’s constant. V is

T

If the stray inductance or capacitance can be measured or

approximated then a somewhat analytical technique can

be used to select the snubber values. The inductance is

usuallyeasiertopredict.Itcombinesthepowerpathboard

inductance in combination with the MOSFET interconnect

bond wire inductance.

approximately 26mV at room temperature (298K) and

scales linearly with Kelvin temperature. It is this linear

temperature relationship that makes diodes suitable

temperature sensors. The I term in the equation above

S

is the extrapolated current through a diode junction when

the diode has zero volts across the terminals. The I term

S

varies from process to process, varies with temperature,

First the SW pin can be monitored with a wide bandwidth

scope with a high frequency scope probe. The ring fre-

quency can be measured for its value. The impedance Z

can be calculated:

and by definition must always be less than I . Combining

D

all of the constants into one term:

η • k

q

K_D=

Z = 2π • f • L

L

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−5

where K = 8.62 , and knowing ln(I /I ) is always posi-

Thermal Considerations and Output Current Derating

D

D S

tive because I is always greater than I , leaves us with

D

S

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those param-

eters defined by JESD51-9 and are intended for use with

finite element analysis (FEA) software modeling tools that

leveragetheoutcomeofthermalmodeling,simulation,and

correlationtohardwareevaluationperformedonaµModule

package mounted to a hardware test board—also defined

by JESD51-9 (“Test Boards for Area Array Surface Mount

Package Thermal Measurements”). The motivation for

providingthesethermalcoefficientsinfoundinJESD51-12

(“Guidelines for Reporting and Using Electronic Package

Thermal Information”).

the equation that:

I

V_D= T(KELVIN) •K_D• ln ^D

I_S

where V appears to increase with temperature. It is com-

D

mon knowledge that a silicon diode biased with a current

source has an approximately –2mV/°C temperature rela-

tionship (Figure 7), which is at odds with the equation. In

fact, the I term increases with temperature, reducing the

S

ln(I /I )absolutevalueyieldinganapproximately–2mV/°C

D S

composite diode voltage slope.

Many designers may opt to use laboratory equipment

and a test vehicle such as the demo board to anticipate

the µModule regulator’s thermal performance in their ap-

plicationatvariouselectricalandenvironmentaloperating

conditions to compliment any FEA activities. Without FEA

software, the thermal resistances reported in the Pin Con-

figuration section are in-and-of themselves not relevant to

providing guidance of thermal performance; instead, the

derating curves provided in the data sheet can be used in

a manner that yields insight and guidance pertaining to

one’s application usage, and can be adapted to correlate

thermal performance to one’s own application.

1.0

I

= 100µA

D

0.8

∆V

D

0.6

0.4

–173

–73

27

127

TEMPERATURE (°C)

4648 F07

Figure 7. Diode Voltage, V_D, vs Temperature T (°C)

for Different Bias Currents

The Pin Configuration section typically gives four thermal

coefficients explicitly defined in JESD51-12; these coef-

ficients are quoted or paraphrased below:

An external diode connected PNP transistor can be pulled

up to V with a resistor to set the current to 100µA for

1. θ : the thermal resistance from junction to ambient, is

IN

JA

using this diode connected transistor as a general tem-

perature monitor by monitoring the diode voltage drop

with temperature, or a specific temperature monitor can

be used that injects two currents that are at a 10:1 ratio

for very accurate temperature monitoring. See Figure 22

for an example.

the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclo-

sure. This environment is sometimes referred to as

“still air” although natural convection causes the air to

move. This value is determined with the part mounted

toaJESD51-9definedtestboard,whichdoesnotreflect

an actual application or viable operating condition.

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A graphical representation of the aforementioned ther-

mal resistances is given in Figure 8; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule.

2. θ

:thethermalresistancefromjunctiontoambi-

JCbottom

ent, is the natural convection junction-to-ambient air

thermal resistance measured in a one cubic foot sealed

enclosure.Thisenvironmentissometimesreferredtoas

“still air” although natural convection causes the air to

move. This value is determined with the part mounted

toaJESD51-9definedtestboard,whichdoesnotreflect

an actual application or viable operating condition.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal op-

erating conditions of a μModule. For example, in normal

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sivelythroughthetoporexclusivelythroughbottomofthe

3. θ

: the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

component power dissipation flowing through the top

of the package. As the electrical connections of the

typical µModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

µModule—asthestandarddefinesforθ

andθ

,

JCtop

JCbottom

respectively.Inpractice,powerlossisthermallydissipated

inbothdirectionsawayfromthepackage—granted, inthe

absence of a heat sink and airflow, a majority of the heat

flow is into the board.

As in the case of θ

, this value may be useful

JCbottom

for comparing packages but the test conditions don’t

generally match the user’s application.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

4. θ : the thermal resistance from junction to the printed

JB

circuitboard,isthejunction-to-boardthermalresistance

wherealmostalloftheheatflowsthroughthebottomof

the µModule and into the board, and is really the sum of

the θ

and the thermal resistance of the bottom

JCbottom

of the part through the solder joints and through a por-

tion of the board. The board temperature is measured a

specified distance from the package, using a two sided,

two layer board. This board is described in JESD51-9.

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4648 F08

µMODULE DEVICE

Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

4648f

18

For more information www.linear.com/LTM4648

LTM4648

applicaTions inForMaTion

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9topredictpowerlossheatflowandtemperature

readingsatdifferentinterfacesthatenablethecalculationof

theJEDEC-definedthermalresistancevalues;(3)themodel

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. An outcome of this

process and due-diligence yields a set of derating curves

provided in other sections of this data sheet. After these

laboratory test have been performed and correlated to the

and should accurately equal the θ value because ap-

JA

proximately 100% of power loss flows from the junction

through the board into ambient with no airflow or top

mounted heat sink.

The 1.5V, 2.5V and 3.3V power loss curves in Figures 9

and 10 can be used in coordination with the load current

derating curves in Figures 11 to 15 for calculating an

approximate θ thermal resistance for the LTM4648 with

JA

variousheatsinkingandairflowconditions.Thepowerloss

curves are taken at room temperature, and are increased

with a multiplicative factor according to the ambient

temperature. This approximate factor is: 1.4 for 120°C.

The derating curves are plotted with the output current

starting at 10A and the ambient temperature at 40°C. The

outputvoltagesare1.5V, 2.5Vand3.3V. Thesearechosen

to include the lower and higher output voltage ranges for

correlating the thermal resistance. Thermal models are

derived from several temperature measurements in a

controlled temperature chamber along with thermal mod-

eling analysis. The junction temperatures are monitored

while ambient temperature is increased with and without

airflow.Thepowerlossincreasewithambienttemperature

change is factored into the derating curves. The junctions

µModulemodel,thentheθ andθ aresummedtogether

JB

BA

to correlate quite well with the µModule model with no

airflow or heat sinking in a properly define chamber. This

θ

+ θ value is shown in the Pin Configuration section

JB

BA

1.6

1.4

1.2

1.0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

1.5V

OUT

0.8

0.6

2.5V

OUT

0.4

0.2

0

0.4

0.2

0

1.5V

2.5V

3.3V

OUT

2

4

8

0

10

6

0

2

4

6

8

10

LOAD CURRENT (A)

4648 F09

4648 F10

Figure 9. 3.3V_INto 2.5V_OUTand 1.5V_OUTPower Loss

Figure 10. 5V_INto 3.3V_OUT, 2.5V_OUTand 1.5V_OUTPower Loss

4648f

19

For more information www.linear.com/LTM4648

LTM4648

applicaTions inForMaTion

12

10

8

12

10

8

12

10

8

6

4

400LFM

200LFM

0LFM

400LFM

200LFM

0LFM

400LFM

200LFM

0LFM

2

0

40

60

80

100

120

0

40

60

80

100

120

0

40

60

80

100

120

20

AMBIENT TEMPERATURE (°C)

4648 F11

4648 F12

4648 F13

Figure 11. No Heat Sink with

3.3V_INto 1.5V_OUT

Figure 12. No Heat Sink with

5V_INto 1.5V_OUT

Figure 13. No Heat Sink with

3.3V_INto 2.5V_OUT

12

10

8

12

10

8

6

4

400LFM

2

400LFM

200LFM

0LFM

2

200LFM

0LFM

0

40

60

80

100

120

0

40

60

80

100

120

20

AMBIENT TEMPERATURE (°C)

4648 F14

4648 F15

Figure 14. No Heat Sink with 5V_INto 2.5V_OUT

Figure 15. No Heat Sink with 5V_INto 3.3V_OUT

95°C ambient temperature is subtracted from the 120°C

junction temperature, then the difference of 25°C divided

are maintained at 120°C maximum while lowering output

currentorpowerwithincreasingambienttemperature.The

decreasedoutputcurrentwilldecreasetheinternalmodule

loss as ambient temperature is increased. The monitored

junction temperature of 120°C minus the ambient operat-

ing temperature specifies how much module temperature

rise can be allowed. As an example in Figure 12 the load

current is derated to ~8A at ~95°C with no air or heat sink

and the power loss for the 5V to 1.5V at 8A output is about

1.68W. The 1.68W loss is calculated with the ~1.2W room

temperature loss from the 5V to 1.5V power loss curve at

8A, and the 1.4 multiplying factor at 120°C junction. If the

by 1.68W equals a 15°C/W θ thermal resistance. Table

JA

4 specifies a 14°C/W value which is very close. Table 4,

Table 5 and Table 6 provide equivalent thermal resistances

for 1.5V, 2.5V and 3.3V outputs with and without airflow.

The derived thermal resistances in Tables 4, 5 and 6 for

the various conditions can be multiplied by the calculated

power loss as a function of ambient temperature to derive

temperature rise above ambient, thus maximum junction

temperature.Roomtemperaturepowerlosscanbederived

from the efficiency curves in the Typical Performance

4648f

20

For more information www.linear.com/LTM4648

LTM4648

applicaTions inForMaTion

•ꢀ Place high frequency ceramic input and output capaci-

tors next to the V , GND and V

pins to minimize

IN

OUT

high frequency noise.

•ꢀ Place a dedicated power ground layer underneath the

unit.

•ꢀ Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

•ꢀ Do not put vias directly on the pads, unless they are

capped.

•ꢀ Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

Figure 16. Thermal Image 5V_INto 1.5V_OUTat 10A

(No Heat Sink, No Air Flow and Room Temperature)

Figure17givesagoodexampleoftherecommendedlayout.

Characteristicssectionandadjustedwiththeaboveambient

temperaturemultiplicativefactors.Theprintedcircuitboard

is a 1.6mm thick four layer board with two ounce copper

for the two outer layers and one ounce copper for the two

inner layers. The PCB dimensions are 95mm × 76mm.

V

OUT

GND

C

OUT

Safety Considerations

The LTM4648 module does not provide isolation from V

IN

to V . There is no internal fuse. If required, a slow blow

OUT

fuse with a rating twice the maximum input current needs

tobeprovidedtoprotecteachunitfromcatastrophicfailure.

Layout Checklist/Eꢁample

C

IN

The high integration of LTM4648 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout con-

siderations are still necessary.

GND

V

IN

•ꢀ Use large PCB copper areas for high current path,

including V , GND and V . It helps to minimize the

IN

OUT

4648 F17

PCB conduction loss and thermal stress.

Figure 17. Recommended PCB Layout

4648f

21

For more information www.linear.com/LTM4648

LTM4648

applicaTions inForMaTion

Table 3. Output Voltage Response vs Component Matriꢁ (Refer to Figure 18) 0A to 5A Load Step Typical Measured Values

C

OUT

IN

(BULK)*

VENDORS

PART NUMBER (CERAMIC) VENDORS

PART NUMBER

(CERAMIC) VENDORS

PART NUMBER

150µF, 16V SANYO OSCON 25HVH150MT 22µF, 16V

MURATA GRM32ER71C226KE18L 100µF, 6.3V MURATA GRM32ER60J107ME20L

AVX

12106D107MAT

C

OUT

RECOVERY LOAD STEP

IN

V

(BULK)* (CERAMIC) (CERAMIC)

C

(pF)

V

TIME

25µs

SPEED

5A/µs

R

FB

FREQ

450kHz

OUT

IN

FF

DROOP

P-P

1V

2.375V, 3.3, 5V

120µF*

None

65mV

70mV

130mV

140mv

15kΩ

10kΩ

22µF × 3 100µF × 3

1.2V

2.375V, 3.3V,

5V

1.5V

2.5V

3.3V

3.3V, 5V

5V

120µF*

None

80mV

110mV

140mV

160mV

230mV

290mV

30µs

40µs

5A/µs

6.65kΩ 450kHz

3.09kΩ 450kHz

2.21kΩ 450kHz

22µF × 3 100µF × 3

*Bulk capacitor is optional if V has very low input impedance.

IN

Table 4. 1.5V Output

DERATING CURVE

Figures 11, 12

V

(V)

POWER LOSS CURVE

Figures 9, 10

AIR FLOW (LFM)

HEAT SINK

θ

JA

(°C/W)

14

IN

3.3, 5

0

None

Figures 9, 10

200

400

12

Figures 9, 10

10

Table 5. 2.5V Output

DERATING CURVE

Figure 13, 14

V

(V)

POWER LOSS CURVE

Figures 9, 10

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

14

IN

3.3, 5

0

Figure 13, 14

Figures 9, 10

200

400

None

12

Figure 13, 14

Figures 9, 10

None

10

Table 6. 3.3V Output

DERATING CURVE

Figure 15

V

(V)

POWER LOSS CURVE

Figure 10

AIR FLOW (LFM)

HEAT SINK

None

θ

(°C/W)

IN

JA

5

0

14

12

10

Figure 15

5

Figure 10

200

400

None

Figure 15

Figure 10

None

4648f

22

For more information www.linear.com/LTM4648

LTM4648

Typical applicaTions

FREQ

CLKIN

V

1.2V

10A

OUT

V

IN

V

IN

OUT

2.375V TO 5.5V

C

22µF

10V

OUT1

IN

INTV

SW

V

CC

OUT_LCL

DIFFOUT

C

100µF

6.3V

OUT2

100µF

6.3V

RUN

DIFFP

LTM4648

MODE

DIFFN

PHMODE

TRACK/SS

V

FB

COMP

R

FB

TEMP

GND

PGOOD

CLKOUT

10k

C1

0.1µF

4648 F18

Figure 18. 2.375V to 5.5V_IN, 1.2V at 10A Design

1M

FREQ

CLKIN

V

2.5V

8A

OUT

V

IN

V

IN

OUT

3.3V TO 5.5V

C

22µF

10V

C

IN

22µF

10V

IN

100µF

6.3V

100µF

6.3V

INTV

SW

V

OUT_LCL

CC

RUN

DIFFP

LTM4648

MODE

DIFFN

PHMODE

V

FB

TRACK/SS

COMP

R

FB

TEMP

GND

PGOOD

CLKOUT

3.09k

C1

0.1µF

4648 F19

Figure 19. 3.3V to 5V V_IN, 2.5V_OUTat 8A Design with Increased 650kHz Frequency

4648f

23

For more information www.linear.com/LTM4648

LTM4648

Typical applicaTions

FREQ

CLKIN

V

1.5V

30A

OUT

V

IN

2.375V TO 5.5V

V

IN

OUT

V

OUT_LCL

C

22µF

10V

C

IN1

OUT1

INTV

SW

CC

100µF

6.3V

C

OUT2

DIFFOUT

DIFFP

100µF

6.3V

RUN

LTM4648

MODE

DIFFN

PHMODE

TRACK/SS

V

FB

R

FB

6.65k

COMP

C1

0.1µF

TEMP

GND

PGOOD

CLKOUT

FREQ

IN

CLKIN

OUT

V

OUT_LCL

V

C

22µF

10V

OUT3

OUT4

IN2

INTV

SW

CC

100µF

6.3V

100µF

6.3V

DIFFOUT

DIFFP

RUN

LTM4648

MODE

DIFFN

PHMODE

TRACK/SS

V

FB

COMP

TEMP

GND

PGOOD

CLKOUT

FREQ

IN

CLKIN

V

OUT

V

OUT_LCL

C

22µF

10V

OUT5

OUT6

IN3

INTV

SW

CC

100µF

6.3V

100µF

6.3V

DIFFOUT

DIFFP

RUN

LTM4648

MODE

DIFFN

4648 F20

PHMODE

TRACK/SS

V

FB

COMP

TEMP

GND

PGOOD

CLKOUT

PGOOD

Figure 20. Three LTM4648 in Parallel, 1.5V at 30A Design

4648f

24

For more information www.linear.com/LTM4648

LTM4648

Typical applicaTions

FREQ

CLKIN

FREQ

CLKIN

V

3.3V

8A

V

1.8V

10A

OUT1

OUT3

V

IN

5V

V

IN

OUT

IN

OUT

V

OUT_LCL

C

OUT5

C

22µF

10V

C

22µF

10V

OUT1

IN1

IN3

INTV

SW

V

INTV

SW

CC

OUT_LCL

CC

100µF

6.3V

100µF

6.3V

C

OUT6

100µF

6.3V

C

OUT2

DIFFOUT

DIFFP

DIFFOUT

DIFFP

100µF

6.3V

RUN

V

LTM4648

OUT1

MODE

DIFFN

MODE

DIFFN

R6

10k

PHMODE

TRACK/SS

V

PHMODE

TRACK/SS

V

FB

COMP

R1

2.21k

R5

4.99k

R7

4.99k

TEMP

GND

PGOOD

CLKOUT

TEMP

GND

PGOOD

CLKOUT

C1

0.1µF

FREQ

CLKIN

FREQ

CLKIN

V

2.5V

10A

V

1.5V

10A

OUT2

OUT4

V

IN

OUT

IN

OUT

V

OUT_LCL

C

OUT7

C

22µF

10V

C

22µF

10V

OUT3

IN2

IN4

INTV

SW

V

INTV

SW

CC

OUT_LCL

CC

C

100µF

6.3V

100µF

6.3V

OUT8

C

OUT4

DIFFOUT

DIFFP

DIFFOUT

DIFFP

100µF

6.3V

100µF

6.3V

RUN

V

LTM4648

OUT1

MODE

DIFFN

MODE

DIFFN

R3

10k

R9

10k

PHMODE

TRACK/SS

V

PHMODE

TRACK/SS

V

FB

COMP

R2

3.09k

R2

6.65k

R4

3.09k

R10

6.65k

TEMP

GND

PGOOD

CLKOUT

TEMP

GND

PGOOD

CLKOUT

4648 F21

Figure 21. Quad Outputs 4-Phase LTM4648 Regulator with Tracking Function

FREQ

CLKIN

V

1.5V

10A

OUT

V

IN

2.375V TO 5.5V

V

IN

OUT

V

OUT_LCL

C

22µF

10V

C

IN

OUT1

INTV

SW

CC

C

100µF

6.3V

OUT2

0.1µF

100µF

6.3V

DIFFOUT

DIFFP

RUN

LTM4648

MODE

DIFFN

PHMODE

TRACK/SS

V

FB

COMP

V

IN

100µA

R

=

T

R

FB

TEMP

GND

PGOOD

CLKOUT

6.65k

C1

0.1µF

V

IN

MC

A/D

4648 F22

R

Figure 22. Single LTM4648 10A Design with Temperature Monitoring

CLOCK

V

1.2V

10A

OUT

CLKIN

V

1.8V

10A

OUT

V

IN

5V

V

IN

OUT

IN

OUT

V

OUT_LCL

C

22µF

10V

C

22µF

10V

IN1

IN2

C

OUT4

100µF

6.3V

OUT1

OUT2

OUT3

INTV

SW

V

INTV

SW

CC

OUT_LCL

CC

100µF

6.3V

100µF

6.3V

100µF

6.3V

DIFFOUT

DIFFP

DIFFOUT

DIFFP

RUN

LTM4648

MODE

DIFFN

MODE

DIFFN

R2

INTV

PHMODE

V

CC

INTV

PHMODE

V

FB

CC

FB

10k

MASTER SLOPE

TRACK/SS

COMP

TRACK/SS

COMP

R1

10k

R4

4.99k

R3

4.99k

TEMP

GND

PGOOD

CLKOUT

TEMP

GND

PGOOD

CLKOUT

4648 F23

CLOCK

Figure 23. Dual Outputs 2-Phase LTM4648 Regulator with Tracking Function

4648f

25

For more information www.linear.com/LTM4648

LTM4648

package DescripTion

Please refer to http://www.linear.com/product/LTM4648#packaging for the most recent package drawings.

Z

/ / b b b

Z

3 . 8 1 0

2 . 5 4 0

1 . 2 7 0

0 . 3 1 7 5

1 . 2 7 0

0 . 0 0 0

2 . 5 4 0

3 . 8 1 0

4648f

26

For more information www.linear.com/LTM4648

LTM4648

package DescripTion

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

LTM4648 Component BGA Pinout

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

A1

A2

GND

TEMP

GND

B1

B2

GND

–

C1

C2

V_IN

–

D1

D2

V_IN

–

E1

E2

E3

E4

GND

–

F1

F2

RUN

CLCKOUT

GND

G1

G2

GND

A3

B3

CLKIN

PHMODE

MODE

–

C3

NC

D3

V_IN

–

FREQ

–

F3

G3

GND

A4

B4

C4

NC

D4

F4

INTVCC

GND

G4

GND

A5

B5

C5

SW

–

D5

E5 TRACK/SS

F5

G5

GND

A6

B6

C6

D6

E6

E7

–

F6

COMP

DIFFN

DIFFP

V_OUT

G6

GND

A7

B7

NC

C7

PGOOD

V_IN

D7

V_IN

V_OUT

FB

F7

G7

GND

A8

B8

NC

C8

D8

E8

V_IN

F8

G8

DIFFOUT

V_{OUT_LCL}

V_OUT

A9

B9

GND

C9

V_IN

D9

E9

V_OUT

F9

G9

A10

A11

B10

B11

C10

C11

V_OUT

D10

D11

E10

E11

F10

F11

V_OUT

G10

G11

V_OUT

4648f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

For more information www.linear.com/LTM4648

LTM4648

Typical applicaTion

Design resources

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

ꢀ

•ꢀSelector Guides

ꢀ

•ꢀQuick Start Guide

•ꢀDemo Boards and Gerber Files

•ꢀFree Simulation Tools

•ꢀPCB Design, Assembly and Manufacturing Guidelines

•ꢀPackage and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

TechClip Videos

Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management

Linear Technology’s family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LTM4627

20V, 15A Step-Down µModule Regulator

4.5V ≤ V ≤ 20V, 0.6V ≤ V

OUT

BGA

≤ 5V, PLL input, Remote Sense Amplifier,

IN

OUT

V

Tracking, 15mm × 15mm × 4.3mm LGA and 15mm × 15mm × 4.9mm

LTM4620A

LTM4613

LTM4608A

LTM4649

LTC2974

Dual 16V, 13A or Single 26A Step-Down µModule

Regulator

4.5V ≤ V ≤ 16V, 0.6V ≤ V

OUT

≤ 5.3V, PLL Input, Remote Sense Amplifier,

IN

OUT

V

Tracking, 15mm × 15mm × 4.41mm LGA

36V , 8A EN55022 Class B Certified DC/DC Step-Down 5V ≤ V ≤ 36V, 3.3V ≤ V

≤ 15V, PLL Input, V

Tracking and Margining,

IN

OUT

µModule Regulator

15mm × 15mm × 4.32mm LGA

2.7V ≤ V ≤ 5.5V, 0.6V ≤ V ≤ 5V, V Tracking, CLKIN

OUT

Low V , 8A Step-Down µModule

IN

OUT

9mm × 15mm × 2.82mm LGA

16V, 10A Step-Down µModule Regulator

4.5V ≤ V ≤ 16V, 0.6V ≤ V

OUT

≤ 3.3V, PLL Input, Remote Sense Amplifier,

OUT

IN

V

Tracking, 9mm × 15mm × 4.92mm BGA

2

Quad Digital Power Supply Manager with EEPROM

I C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel

Voltage, Current and Temperature Measurements

4648f

LT 1115 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

For more information www.linear.com/LTM4648

●

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4648

 LINEAR TECHNOLOGY CORPORATION 2015


型号：	LTM4648IY#PBF
厂家：	Linear
描述：	LTM4648 - Low VIN, 10A Step-Down µModule (Power Module) Regulator; Package: BGA; Pins: 68; Temperature Range: -40°C to 85°C
文件：	总28页 (文件大小：407K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4648IY#PBF [Linear]

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