LTM4646IY#PBF_技术文档

LTM4646

Dual 10A or

Single 20A µModule Regulator

FEATURES

DESCRIPTION

®

The LTM 4646 is a complete dual 10A output switching

n

Dual 10A or Single 20A Output

n

Wide Input Voltage Range: 4.5V to 20V

mode DC/DC power supply. Included in the package are

the switching controller, power FETs, inductors, and all

supporting components. Operating from an input voltage

range of 4.5V to 20V, the LTM4646 supports two outputs

each with an output voltage range of 0.6V to 5.5V, set by

external resistors. Its high efficiency design delivers up to

10A continuous current for each output. Only a few input

and output capacitors are needed.

n

2.375V

with CPWR Bias

MIN

n

Output Voltage Range: 0.6V to 5.5V

1.5ꢀ Maꢁiꢂuꢂ ꢃotal DC Output Error

Multiphase Current Sharing

Differential Remote Sense Amplifier, Each Channel

Current Mode Control/Fast Transient Response

Up to 96% Efficiency

Adjustable Switching Frequency (250kHz to 1.3MHz)

Frequency Synchronization

The device supports frequency synchronization, multiphase

operation, high efficiency light load operation and output

voltage tracking for supply rail sequencing and has an

onboard temperature diode per channel for device tempera-

ture monitoring. High switching frequency and a current

mode architecture enable a very fast transient response to

line and load changes without sacrificing stability.

Overcurrent Foldback Protection

Output Overvoltage Protection

Internal or External Compensation

Built-In Temperature Monitoring Diode

SnPb or RoHS Compliant Finish

11.25mm × 15mm × 5.01mm BGA Package

Fault protection features include overvoltage and overcur-

rent protection. The power module is offered in a small

footprint 11.25mm × 15mm × 5.01mm BGA package.

The LTM4646 is available with SnPb or RoHS compliant

terminal finish.

APPLICATIONS

n

Point-of-Load Power Supplies

n

Telecom and Networking Equipment

n

Industrial Equipment

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611.

n

Medical Equipment

Click to view associated ꢃechClip Videos.

Efficiency, 12V to 0.9V,

TYPICAL APPLICATION

1.2V at 10A Each

V

IN

95

4.5V

10μF

TO 20V

×4

130k

90

V

RUN1

RUN2

V

IN1 IN2

CPWR

INTV

CC

VRNG

MODE_PLLIN

DRV

CC

85

4.7µF

V

OUT1

V

OUT2

V

0.9V

AT 10A

1.2V

OUT2

V

OUT1

80

AT 10A

V

OUTS2

OUTS1

LTM4646

V

FB1

100µF

×4

FB2

100μF

×4

75

121k

60.4k

30.1k

12V TO 1.2V EFF, 500kHz

IN

–

V

12V TO 0.9V EFF, 400kHz

IN

OUTS1

OUTS2

70

COMP1A

COMP2A

COMP2B

1

2

3

4

5

6

7

8

9

10

COMP1B

PINS NOT USED IN THIS CIRCUIT:

PGOOD1, PGOOD2, EXTV

OUTPUT CURRENT (A)

TRACK/SS1

TRACK/SS2

4646 TA01b

FREQ

115k

SGND GND

,

CC

0.1µF

+ – +

TEMP1 , TEMP1 , TEMP2 , TEMP2

–

4646 TA01a

PHASMD, CLKOUT, SW1, SW2

4646f

1

For more information www.linear.com/LTM4646

LTM4646

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

1

2

3

4

5

6

7

8

CPWR, V , V ....................................... –0.3V to 22V

IN1 IN2

–

TEMP2

V

, V

SW1 SW2

................................................... –2V to 22V

A

B

C

D

E

F

PGOOD1, PGOOD2, RUN1, RUN2, DRV ,

CC

V

IN2

+

TEMP2

INTV , EXTV , V , V , V

CC CC OUT1 OUT2 OUTS1

,

V

OUT2

V

..................................................... –0.3V to 6V

GND

OUTS2

TRACK/SS1, TRACK/SS2............................. –0.3V to 5V

FREQ, VRNG, PHASMD,

GND

SW2

–

VRNG SGND OUTS2 RUN2

V

MODE_PLLIN ............................–0.3V to INTV +0.3

CC

–

EXTV

V

COMP2B OUTS2 COMP2A

V

FB2 PGOOD2

CC

V

(Note 6)....................................... –0.3V to V

OUTS1

FB1

–

V

(Note 6)..........................–0.3V to INTV +0.3V

CC

OUTS2

MODE_

FREQ TRACK/SS2 PLLIN CLKOUT

CPWR

INTV

CC

COMP1A, COMP2A (Note 6) ..................... –0.3V to 2.7V

COMP1B, COMP2B, V , V ................. –0.3V to 2.7V

FB1 FB2

DRV

CC

V V

COMP1B OUTS1 COMP1A FB1 PGOOD1

DRV Peak Output Current.................................100mA

CC

G

H

J

Internal Operating Temperature

TRACK/SS1

PHASMD SGND

RUN1

Range (Note 2) .................................. –40°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Solder Reflow Package Body Temperature.... 245°C

–

SW1

V

GND

OUTS1

–

V

OUT1

TEMP1

K

V

GND

+

IN1

TEMP1

L

BGA PACKAGE

88-LEAD (15mm ꢀ 11.25mm ꢀ 5..01mm)

T

JMAX

= 125°C, ꢁ

= 12.6°C/W, ꢁ

= 1.8°C/W,

JCbottom

JCtop

ꢁ

= 2.3°C/W, ꢁ = 9.6°C/W

JB

JA

ꢁ VALUES DEFINED PER JESD51-12

WEIGHT = 2.1g

http://www.linear.coꢂ/product/LꢃM4646#orderinfo

ORDER INFORMATION

PARꢃ MARKING*

PACKAGE

MSL

ꢃEMPERAꢃURE RANGE

(SEE NOꢃE 2)

PARꢃ NUMBER

LTM4646EY#PBF

LTM4646IY#PBF

LTM4646IY

BALL FINISH

SAC305 (RoHS)

SnPb (63/37)

DEVICE

FINISH CODE

ꢃYPE

RAꢃING

LTM4646Y

e1

BGA

3

–40°C to 125°C

e0

• Consult Marketing for parts specified with wider operating temperature

ranges. *Device temperature grade is indicated by a label on the shipping

container. Ball finish code is per IPC/JEDEC J-STD-609.

• Recommended BGA PCB Assembly and Manufacturing Procedures:

www.linear.com/umodule/pcbassembly

• BGA Package and Tray Drawings: www.linear.com/packaging

• Terminal Finish Part Marking: www.linear.com/leadfree

4646f

2

For more information www.linear.com/LTM4646

LTM4646

ELECTRICAL CHARACTERISTICS ꢃhe l denotes the specifications which apply over the specified internal

operating teꢂperature range (Note 2). Specified as each individual output channel. ꢃ = 25°C, V = 12V and V

A IN

, V

RUN1 RUN2

at 5V

unless otherwise noted. Per the typical application in Figure 18.

SYMBOL

PARAMEꢃER

CONDIꢃIONS

MIN

ꢃYP

MAX

20

UNIꢃS

l

V

IN(DC)

Input DC Voltage

2.375V with 5V External Bias on CPWR, 4.5V

Min without Bias

2.375

V

Input Control Power Voltage

Input Range of Bias

4.5

20

V

CPWR(DC)

Normally Connected to V

IN

l

V

Output Voltage Range

(Note 8)

0.6

5.5

V

OUT1, 2 (Range)

V

,

Output Voltage, Total Variation

with Line and Load

C

IN

= 10µF ꢀ4, C

= 100µF ꢀ4, Ceramic V

1.4775

1.5

1.5225

OUT1(DC)

OUT

V

= 1.5V

OUT2(DC)

Input Specifications

V

, V

RUN1 RUN2

RUN Pin On/Off Threshold

RUN Pin On Hysteresis

RUN Rising

1.1

1.2

160

100

1

1.3

V

mV

kΩ

A

V , V

RUN1HYS RUN2HYS

R

, R

RUN1 RUN2

RUN1, RUN2 Resistance

Input Inrush Current at Start-Up

Pull-Down Resistance

I = 0A, C = 10µF ×4, C = 0.01µF,

OUT

I

INRUSH(VIN)

IN

SS

C

OUT

= 100µF ×4, V

= 1.5V, V

= 1.5V,

OUT2

OUT1

V

= 12V

IN

I

Input Supply Bias Current

I

= 0.1A, f = 1MHz, Pulse-Skipping Mode

SW

17

35

40

mA

µA

Q(VIN)

OUT

I

= 0.1A, f = 1MHz, Switching Continuous

SW

OUT

Shutdown, RUN = 0, V = 12V

IN

I

Input Supply Current

V

= 4.5V, V

= 1.5V, I

= 10A, f = 1MHz

SW

3.9

A

S(VIN)

IN

OUT

= 12V, V

= 1.5V, I

= 10A, f = 1MHz

SW

1.45

IN

OUT

Output Specifications

I , I

OUT1(DC) OUT2(DC)

Output Continuous Current Range

Line Regulation Accuracy

V

= 12V, V = 1.5V (Notes 7, 8)

OUT

0

10

A

IN

l

∆V

/V

OUT1(LINE) OUT1

V

I

= 1.5V, V from 4.5V to 20V

IN

0.01

0.15

15

0.025

%/V

OUT

/V

OUT2(LINE) OUT2

= 0A for Each Output

OUT

l

∆V

/V

OUT1(LOAD) OUT1

Load Regulation Accuracy

For Each Output, V

= 1.5V, 0A to 10A

0.3

%

OUT

/V

OUT2(LOAD) OUT2

V = 12V (Note 7)

IN

V , V

OUT1(AC) OUT2(AC)

Output Ripple Voltage

For Each Output, I

= 0A, C

= 100µF ×4,

mV

OUT

P-P

V

C

= 1.5V, Frequency = 350kHz

OUT

f (Each Channel)

S

Output Ripple Voltage Frequency

Turn-On Overshoot

= 12V, V

= 1.5V, R = 115kΩ (Note 4)

FREQ

350

10

kHz

mV

IN

OUT

∆V

OUTSTART

= 100µF ×4, V

= 1.5V, I

= 0A V =

OUT IN

OUT

(Each Channel)

12V, C = 0.01µF

SS

t

Turn-On Time

C

= 100µF ×4, No Load, TRACK/SS with

OUT

5

ms

START

(Each Channel)

0.01µF to GND, V = 12V

IN

∆V

Peak Deviation for Dynamic Load

Load: 0A to 6A to 0A

50

mV

OUT(LS)

(Each Channel)

C

OUT

= 100µF ×4

V

= 12V, V

= 1.5V

IN

OUT

t

Settling Time for Dynamic Load Step Load: 0A to 6A to 0A

20

µs

SETTLE

(Each Channel)

C = 100µF ×4

OUT

V

= 12V, V

= 1.5V

IN

OUT

I

Output Current Limit

V

IN

= 12V, V

= 1.5V

20

A

OUT(PK)

OUT

(Each Channel)

4646f

3

For more information www.linear.com/LTM4646

LTM4646

ELECTRICAL CHARACTERISTICS ꢃhe l denotes the specifications which apply over the specified internal

operating teꢂperature range (Note 2). Specified as each individual output channel. ꢃ = 25°C, V = 12V and V

A IN

, V

RUN1 RUN2

at 5V

unless otherwise noted. Per the typical application in Figure 18.

SYMBOL

PARAMEꢃER

CONDIꢃIONS

MIN

ꢃYP

MAX

UNIꢃS

Control Section

l

V

Voltage at V Pin

FB1

I

= 0A, V

= 1.5V

0.592

0.296

0.600 0.608

0.3 0.304

V

FB1

OUT

V

Voltage at V Pin

FB2

I

= 0A, V

= 1.5V

FB2

OUT

V

FB2

is Gained Back Up by 2x Internal to 0.6V

I , I

FB1 FB2

(Note 6)

0

50

nA

l

V V

OVL1, OVL2

Feedback Overvoltage Lockout

V

Rising

0.630

0.315

0.645 0.660

0.323 0.330

V

FB1

V

Rising

FB2

I

,

Track Pin Soft-Start Pull-Up Current TRACK/SS1,TRACK/SS2 = 0V

1.0

µA

TRACK/SS1

I

TRACK/SS2

UVLO

INTV Undervoltage Lockout

CC

INTV Falling V (Note 6)

CC IN

3.3

3.7

V

INTV Rising V (Note 6)

CC IN

4.2

90

4.5

t

Minimum Top Gate Off-Time

Minimum Top Gate On-Time

(Note 6)

ns

OFF(MIN)

t

(Note 6)

30

ON(MIN)

R

, R

FBHI1 FBHI2

Resistor Between V

, V

OUTS1 OUTS2

60.05

60.4

60.75

0.3

2

kΩ

and V , V Pins for Each Output

FB1 FB2

V , V

PGOOD1 PGOOD2

PGOOD Voltage Low

I

= 2mA

0.1

V

PGOOD

Low

I

PGOOD Leakage Current

PGOOD Trip Level

V

= 5V

–2

0

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

PGOOD

FB

–7.5

7.5

%

Ramping Positive

Internal Linear Regulator

DRV

Internal DRV Voltage

CC

6V < CPWR < 20V

I = 0mA to 100mA

CC

5.0

5.3

5.6

V

CC

DRV

DRV Load Regulation

CC

–1.3

–3.0

%

CC

Load Regulation

V

EXTV Switchover Voltage

CC

EXTV Ramping Positive

CC

4.4

4.6

80

4.8

V

mV

EXTVCC

V

EXTV Dropout

CC

I

CC

= 20mA, V = 5V

EXTVCC

120

EXTVCC(DROP)

V

EXTV Hysteresis

CC

200

EXTVCC(HYST)

Frequency and Clock Synchronization

Frequency Nominal Nominal Frequency

R

= 115kΩ

300

350

250

1.3

400

kHz

MHz

kΩ

FREQ

Frequency Low

Frequency High

Lowest Frequency

= 165kΩ (Note 5)

= 29.4kΩ

Highest Frequency

1.17

1.43

R

MODE_PLLIN Input Resistance

MODE_PLLIN to SGND

600

MODE_PLLIN

Channel 2 Phase

V

Phase Relative to V

PHASMD = SGND

PHASMD = Float

180

240

Deg

OUT2

OUT1

PHASMD = INTV

CC

CLKOUT Phase

Phase (Relative to V

)

PHASMD = SGND

PHASMD = Float

60

90

Deg

OUT1

PHASMD = INTV

120

CC

V

High

Clock Input High Level to MODE_PLLIN

Clock Input Low Level to MODE_PLLIN

2

V

PLLIN

V

Low

0.5

PLLIN

4646f

4

For more information www.linear.com/LTM4646

LTM4646

ELECTRICAL CHARACTERISTICS ꢃhe l denotes the specifications which apply over the specified internal

operating teꢂperature range (Note 2). Specified as each individual output channel. ꢃ = 25°C, V = 12V and V

A IN

, V

RUN1 RUN2

at 5V

unless otherwise noted. Per the typical application in Figure 18.

SYMBOL

PARAMEꢃER

CONDIꢃIONS

MODE_PLLIN Clock Duty Cycle = 50%

MIN

250

ꢃYP

MAX

1300

UNIꢃS

f

Frequency SYNC Capture Range

kHz

SYNC

(Each Channel)

VRNG I

SET Current Limit

Per Channel

VRNG = INTV , I

to 10A, I ~22A

LIMIT

20

9

A

LIMIT

CC OUT

VRNG = SGND, I

to 5A, I

~11A

OUT

LIMIT

t

Delay from V Fault (OV/UV) to

FB

(Note 6)

50

μs

D(PGOOD)

PGOOD Falling

t

Delay from V Fault (OV/UV Clear) (Note 6)

FB

20

μs

D(PGOOD)

to PGOOD

TEMP Diode Voltage

Temperature Coefficient

V

, V

I = 100µA

TEMP

0.598

–2.0

V

TEMP1

TEMP2

TC V

V

TEMP

mV/°C

TEMP1,2

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: Two outputs are tested separately and the same testing condition

is applied to each output.

Note 4: The switching frequency is programmable from 250kHz to 1.3MHz.

Note 5: LTM4646 device is optimized to operate from 300kHz to 750kHz.

Note 6: These parameters are tested at wafer sort.

Note 2: The LTM4646 is tested under pulsed load conditions such

that T ≈ T . The LTM4646E is guaranteed to meet specifications from

J A

Note 7: See output current derating curves for different V , V

and T .

A

IN OUT

0°C to 125°C internal temperature. Specifications over the –40°C to

125°C internal operating temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTM4646I is guaranteed over the full –40°C to 125°C internal operating

temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors.

Note 8: For 6V ≤ V ≤ 20V, the 3.3 to 5V output current needs to be

IN

limited to 9A/channel. All other input and output combinations are 10A/

channel with recommended switching frequency included in the efficiency

graphs. Derating curves and airflow apply.

4646f

5

For more information www.linear.com/LTM4646

LTM4646

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Output Current,

V = 5V

IN

Efficiency vs Output Current,

V

= 12V

V

= 8V

IN

100

95

90

85

80

75

70

100

95

90

85

80

75

70

95

90

85

80

75

70

5.0V , 900kHz

OUT

5.0V , 1.3MHz

OUT

3.3V , 550kHz

OUT

3.3V , 850kHz

OUT

3.3V , 1.1MHz

OUT

2.5V , 550kHz

OUT

2.5V , 750kHz

OUT

2.5V , 850kHz

OUT

1.8V , 500kHz

OUT

1.8V , 600kHz

OUT

1.8V , 700kHz

OUT

1.5V , 450kHz

OUT

1.5V , 550kHz

OUT

1.5V , 600kHz

OUT

1.2V , 400kHz

OUT

1.2V , 475kHz

OUT

1.2V , 500kHz

OUT

1.0V , 350kHz

OUT

1.0V , 400kHz

OUT

1.0V , 400kHz

OUT

0.9V , 350kHz

OUT

0.9V , 400kHz

OUT

0.9V , 400kHz

OUT

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

OUTPUT CURRENT (A)

4646 G03

4646 G01

4646 G02

Dual Phase Single Output Efficiency

0.9V Single Phase Single Output

Load ꢃransient Response

1V Single Phase Single Output

Load ꢃransient Response

vs Output Current, V = 12V

IN

100

95

90

85

80

75

70

EXTV = 5V

CC

I

OUT

5A/DIV

5.0V , 1.3MHz

OUT

1V

0.9V

OUT

3.3V , 1.1MHz

OUT

33mV/DIV

2.5V , 850kHz

OUT

1.8V , 700kHz

OUT

1.5V , 600kHz

OUT

4646 G06

4646 G05

50µs/DIV

1.2V , 500kHz

OUT

1.0V , 400kHz

OUT

C

= 470µF POSCAP, 5mΩ,

C

= 470µF POSCAP, 5mΩ,

OUT

0.9V , 400kHz

OUT

100µF ×4, CERAMIC

C = 100pF,

COMP

C

= 100pF,

2

4

6

8

10 12 14 16 18 20

COMP

f = 350kHz

OUTPUT CURRENT (A)

4646 G04

1.2V Single Phase Single Output

Load ꢃransient Response

1.5V Single Phase Single Output

Load ꢃransient Response

1.8V Single Phase Single Output

Load ꢃransient Response

I

OUT

I

OUT

5A/DIV

1.8V

OUT

1.2V

11.5.5VV

OUT

33mV/DIV

4646 G08

4646 G09

4646 G07

50µs/DIV

C

= 100µF ×3, CERAMIC

C OUT= 100µF ×3, CERAMIC

OUT

C

= 100µF ×3, CERAMIC

= 100pF, C = 47pF

C

= 470µF POSCAP, 5mΩ,

OUT

C

COMP

= 100pF, C = 47pF

COMP FF

C

100µF ×4, CERAMIC

COMP

FF

f = 450kHz

f = 500kHz

C

COMP

= 100pF,

f = 350kHz

4646f

6

For more information www.linear.com/LTM4646

LTM4646

TYPICAL PERFORMANCE CHARACTERISTICS

2.5V Single Phase Single Output

Load ꢃransient Response

3.3V Single Phase Single Output

Load ꢃransient Response

5V Single Phase Single Output

Load ꢃransient Response

I

OUT

I

OUT

5A/DIV

3.3A/DIV

2.5V

3.3V

OUT

5V

OUT

67mV/DIV

4646 G10

4646 G11

4646 G12

50µs/DIV

C

= 100µF ×2, CERAMIC

= 100pF, C = 47pF

C

= 100µF ×1, CERAMIC

= 100pF, C = 47pF

C

= 100µF ×1, CERAMIC

OUT

C

= 100pF, C = 47pF

COMP FF

COMP

FF

COMP

FF

f = 500kHz

f = 750kHz

f = 950kHz

Single Phase Single Output

Start-Up, No Load

Single Phase Single Output

Start-Up, 10A Load

ꢃwo-Phase Switching and Ripple

V

OUT

V

OUT

0.5V/DIV

V

0.5V/DIV

OUT

5V/DIV

V

OUT

10mV/DIV

I

OUT

6.7A/DIV

4646 G14

4646 G15

4646 G13

20ms/DIV

1µs/DIV

50ms/DIV

12V , 1.5V

IN

AT 10A LOAD

OUT

12V TO 1V AT 20A TWO-PHASE

12V TO 1V AT 350kHz

12V , 1.5V

IN

AT NO LOAD

OUT

C

= 470µF ×1, 2.5V, SANYO POSCAP,

C

= 470µF ×1, 2.5V, SANYO POSCAP,

OUT

100µF ×4, 6.3V, CERAMIC

SOFT-START CAPACITOR = 0.1µF

USE RUN PIN TO CONTROL START-UP

100µF ×4, 6.3V, CERAMIC

SOFT-START CAPACITOR = 0.1µF

USE RUN PIN TO CONTROL START-UP

RIPPLE AT 20A LOAD

C

= 330μF, 9mΩ, 100μF ×4, CERAMIC

OUT

Short-Circuit Protection, No Load

Short-Circuit Protection, 10A Load

V

OUT

500mV/DIV

I

IN

1A/DIV

I

IN

1A/DIV

4646 G16

4646 G17

20ms/DIV

V

I

= 12V

IN

V

I

= 12V

IN

= 1.5V

OUT

= 1.5V

OUT

= NO LOAD

OUT

= 10A

OUT

4646f

7

For more information www.linear.com/LTM4646

LTM4646

(Recoꢂꢂended to Use ꢃest Points to Monitor Signal Pin Connections.)

PIN FUNCTIONS

PACKAGE ROW AND COLUMN LABELING MAY VARY

An external clock applied to MODE_PLLIN should be

within 30% of this programmed frequency to ensure

frequency lock. See the Applications Information section.

AMONG µModule PRODUCꢃS. REVIEW EACH PACKAGE

LAYOUꢃ CAREFULLY.

V

(H1, J1-J2, K1-K2, L1-L2): Power Output Pins.

OUꢃ1

SGND (D3, H3): Signal Ground Pin. Return ground path

for all analog and low power circuitry. Tie a single con-

nection to the output capacitor GND in the application.

See layout guidelines in Figure 17.

Apply output load between these pins and GND pins.

Recommend placing output decoupling capacitance

directly between these pins and GND pins. There is a

49.9Ω resistor connected between V

and V

to

OUT1

OUTS1

protect the output from an open V

. Review Table 5.

V

(G4): This pin is the + input to a unity gain differen-

OUTS1

FB1

See Note 8 in the Electrical Characteristics section for

output current guideline.

tial amplifier. This pin is connected to V

with a 60.4k

OUTS1

precision resistor internal. Different output voltages can be

programmed with an additional resistor between V and

FB1

GND (A3, A6-A7, B3, B6-B7, C3-C7, D6-D7, E6, E8, F5,

F7, G6, G8, H6-H7, J4-J7, K3, K6-K7, L3, L6-L7 ): Power

Ground Pins for Both Input and Output Returns.

–

V

pins. The differential amplifier is feeding back the

OUTS1

divided down output voltage from a remote sense divider

network to compare to the internal 0.6V reference. In 2-phase

single output operation, tie the V pin to INTV . See

V

(A1-A2, B1-B2, C1-C2, D1): Power Output Pins.

OUꢃ2

FB1

CC

Apply output load between these pins and GND pins.

Recommend placing output decoupling capacitance

directly between these pins and GND pins. There is a

Figure 1 and Applications Information section for details.

V

(E4): This pin is the + input to a non-inverting gain

FB2

of two amplifier utilizing three resistors in the feedback

network to develop a remote sense divider network. This

pin is connected to V with an internal 60.4k preci-

49.9Ω resistor connected between V

and V

to

OUT2

OUTS2

protect the output from an open V

. Review Table 5.

OUTS2

See Note 8 in the Electrical Characteristics section for

output current guideline.

sion resistor. The V

voltage is divided down to 0.3V

OUT2

then gained back up to 0.6V to compare with the internal

0.6V reference. This technique provides for equivalent

remote sensing on V . See Figure 1 and Applications

V

, V (G2, E2): These pins are connected to

OUꢃS2

OUꢃS1

the top of the internal top feedback resistor for each out-

put. Each pin can be directly connected to its specific

output, or connected to the remote sense point of V

OUT2

Information section for details.

.

OUT

ꢃRACK/SS1,ꢃRACK/SS2 (H4, F2): Output Voltage Tracking

Pin and Soft-Start Inputs. Each channel has a 1.0μA pull-up

current source. Each pin can be programmed with a soft-

start ramp rate up to the 0.6V internal reference level, then

beyond this point the internal 0.6V reference will control the

feedback loop. When one channel is configured to be master

of the two channels, then a capacitor from this pin to ground

will set the soft-start ramp rate. The remaining channel can

be set up as the slave, and have the master’s output applied

through a voltage divider to the slave output’s track pin. This

voltage divider is equal to the slave output’s feedback divider

for coincidental tracking. See the Applications Information

section. (Recommended to use test points to monitor signal

pin connections.)

It is important to connect these pins to their designated

outputs for proper regulation.

In paralleling modules, the V

pin is left floating, and

OUTS1

the V pin is connected to INTV . This will disable chan-

FB1 CC

nel 1’s error amplifier and internally connect COMP1A to

COMP2A. The PGOOD1 and TRACK/SS1 will be disabled

in this mode. Channel 2’s error amplifier will regulate the

two channel single output. See V pin description and

FB

Applications Information section.

FREQ (F1): Frequency Set Pin. A resistor from this pin to

SGND sets the operating frequency. The Equation:

41550

– 2.2 = R

(kΩ)

FREQ

f(kHz)

DRV (G7): Internal 5.3V regulator output used to source

CC

the power MOSFET drivers, and supply power to the

INTV input. A 4.7µF ceramic capacitor is needed on

CC

this pin to GND.

4646f

8

For more information www.linear.com/LTM4646

LTM4646

PIN FUNCTIONS (Recoꢂꢂended to Use ꢃest Points to Monitor Signal Pin Connections.)

CPWR (F8): Input Power to the Control IC, and Power

to the DRV Regulator. This pin is connected to V for

RUN pin will turn on the DRV , and turn on the INTV path

CC

for operation. See Figure 1 and Applications section.

CC

IN

normal 4.5V to 20V operation. For lower voltage inputs

below 4.5V, CPWR can be powered with an external 5V

bias. See Application section.

PHASMD (H2): Connect this pin to SGND, INTV , or

CC

floating this pin to select the phase of CLKOUT and chan-

nel 2. See Electrical Characteristics table and Application

section.

COMP1A, COMP2A (G3, E3): Current Control Threshold.

These pins are the output of the error amplifier and the

switching regulator’s compensation point. The current

comparator threshold increases with this control voltage.

The voltage ranges from 0V to 2.4V.

PGOOD1, PGOOD2 (G5, E5): Output Voltage Power Good

Indicator. Open-drain logic output that is pulled to ground

when the output voltage is not within 7.5% of the regula-

tion point. See Applications section.

COMP1B, COMP2B (G1, E1): Internal Compensation

Network .These pins are to be connected to their respected

COMPA pins. When Utilizing specific external compensa-

tion, then float these pins.

INꢃV (F6): Supply Input for Internal Circuitry (Not

CC

Including Gate Drivers). This bias is derived from DRV

CC

internally.

EXꢃV (E7): External Power Input. When EXTV exceeds

CC CC

MODE_PLLIN (F3): Operation Mode Selection or External

the switchover voltage (typically 4.6V), an internal switch

Clock Synchronization Input. When this pin is tied to INTV ,

CC

connects this pin to DRV and shuts down the internal

CC

forced continuous mode operation is selected. Tying this pin

to SGND allows discontinuous mode operation. When an

external clock is applied at this pin, both channels operate

in forced continuous mode and synchronize to the external

clock. This pin has an internal 600k pull-down resistor to

SGND. An external clock applied to MODE_PLLIN should

be within 30% of this programmed frequency to ensure

frequency lock.

regulator so that INTV and gate drivers draw power

CC

from EXTV . The V pin still needs to be powered up

CC IN

but draws minimum current.

+

–

+

–

ꢃEMP1 ,ꢃEMP1 and ꢃEMP2 , ꢃEMP2 (L8, K8 and

B8, A8): Onboard temperature diode for monitoring each

channel with differential connections for noise immunity.

V

(K4-K5, L4-L5) and V (A4-A5, B4-B5): Power

IN2

IN1

Input Pins. Apply input voltage between these pins and

GND pins. Recommend placing input decoupling capaci-

CLKOUꢃ (F4): Clock output with phase control using the

PHASMD pin to enable multiphase operation between

tance directly between V pins and GND pins.

IN

devices. Its output level swings between INTV and SGND.

CC

–

If clock input is present at the MODE_PLLIN pin, it will

be synchronized to the input clock, with phase set by the

PHASMD pin. If no clock is present at MODE_PLLIN, its

frequency will be set by the FREQ pin. To synchronize other

controllers, it can be connected to their MODE_PLLIN pins.

See the Applications Information section.

V

(J3): Differential Output Sense Amplifier (–) Input

OUꢃS1

of channel 1. Connect this pin to the negative terminal of

the output load capacitor of V

.

OUT1

–

V

(D4): Differential Output Sense Amplifier (–)

OUꢃS2

Input of channel 2. Connect this pin to the negative ter-

minal of the output load capacitor of V

.

OUT2

RUN1, RUN2 (H5, D5): Run Control Pins. A voltage above

1.3V will turn on each channel in the module. A voltage below

1.0V on the RUN pin will turn off the related channel. Each

RUN pin has a 1.2μA pull-up current, once the RUN pin

reaches 1.2V an additional 4.5μA pull-up current is added

to this pin. A 100k resistor to ground is internal, and can be

SW1 (H8, J8) and SW2 (C8, D8): Switching node of each

channel that is used for testing purposes. Also an R-C

snubber network can be applied to reduce or eliminate

switch node ringing, or otherwise leave floating. See the

Applications Information section.

used with a pull-up resistor to V to turn on the module using

IN

VRNG (D2): Current Limit Adjustment Range. Tying this

the external and internal resistor to program under voltage

lockout. Otherwise, an external enable signal or source can

drive these pins directly below the 6V max. Enabling either

pin to INTV sets full 10A current, or tying to SGND will

CC

lower the current limit to 5A. Default to INTV .

CC

4646f

9

For more information www.linear.com/LTM4646

LTM4646

BLOCK DIAGRAM

CPWR

EXTV

CC

DRV

CC

LDO

V

IN

V

IN

V

IN

4.5V TO 20V

DRV

CC

C

+

IN1

10µF

25V

IN2

100µF

25V

4.7µF

DRV

CC

1µF

10µF

25V

1µF

2Ω

GND

SW1

TOP G

INTV

CC

MTOP1

1µF

0.47µH

GATE

DRIVE

V

OUT1

1.5V/10A

COMP1A

+

COMP1B

1µF

BOT G

MBOT1

C

OUT1

RUN1 AND RUN2

INTERNAL

GND

TIED TOGETHER:

V

IN

COMP

R

=

PULLUP

SGND

130k

V

• 50k

FB1

IN(MIN)

–

– 50k

–

(

SEPARATE:

)

V

RUN1

–

OUTS1

1.3

+

gm

0.6V

REF

+

100k

RUN1 AND RUN2

R

–

×1

FB1

40.2k

+

V

FB1

RUN2

SGND

R

=

PULLUP

V

OUT1

49.9Ω

V

• 100k

100k

IN(MIN)

SS

60.4k

– 100k

(

)

1.3

V

CLKOUT

POWER

OUTS1

CONTROL

LOGIC

LOCATED NEAR POWER STAGES

MODE_PLLIN

+

TEMP1

INTV

CC

1µA

BLOCK

PHASMD

TEMP SENSOR

41550

R

FREQ

=

PNP

470pF

– 2.2

(

)

–

TEMP1

f(kHz)

0.645V

–

FREQ

V

PGOOD1

FB1

PGOOD1

BLOCK

115k

+

VRNG

INTV

350kHz

CC

–

+

SGND

0.555V

V

IN

V

IN

C

SS

C

IN3

IN4

10µF

25V

t

=

• 0.6V

SOFT-START

C8

(

)

1µA

10µF

25V

DRV

CC

1µF

TRACK/SS1

GND

MTOP2

SW2

C

SS

0.47µH

SGND

V

OUT2

V

OUT2

1.2V/10A

GATE

COMP2A

DRIVE

+

1µF

MBOT2

C

OUT2

COMP2B

GND

INTERNAL

COMP

R7

50k

–

V

OUTS2

–

50k

0.6V

SGND

V

R

FB2

R

x2

SS

–

+

FB3

60.4k

30.1k

gm

+

V

FB2

0.3V

SGND

+

–

+

1µA

0.6V REF

SGND

V

OUT2

49.9Ω

60.4k

TRACK/SS2

V

SEE FIGURE 18

OUTS2

LOCATED NEAR

POWER STAGES

C

SS

PGOOD2

–

+

0.645V

FB1

+

TEMP2

V

PGOOD2

BLOCK

SGND

PNP

470pF

TEMP SENSOR

–

+

–

TEMP2

0.555V

4646 F01

Figure 1. Siꢂplified LꢃM4646 Block Diagraꢂ

4646f

10

For more information www.linear.com/LTM4646

LTM4646

ꢃ = 25°C. Use Figure 1 configuration.

A

DECOUPLING REQUIREMENTS

SYMBOL

PARAMEꢃER

CONDIꢃIONS

MIN

ꢃYP

MAX

UNIꢃS

External Input Capacitor Requirement

(V = 4.5V to 20V, V = 1.5V)

C

IN1, IN2

I

= 10A

10μF ×2 (Note 8)

20

µF

IN

OUT1

= 10A

OUT2

C

IN3, IN4

(V = 4.5V to 20V, V = 1.5V)

IN OUT2

External Output Capacitor Requirement

(V = 4.5V to 20V, V = 1.5V)

C

I

= 10A (Note 8)

400

µF

OUT1

OUT2

IN

OUT1

= 10A (Note 8)

OUT2

(V = 4.5V to 20V, V

IN

= 1.5V)

OUT2

OPERATION

Power Module Description

point. As the output voltage exceeds 7.5% above regula-

tion, the bottom MOSFET will turn on to clamp the output

voltage. The top MOSFET will be turned off. This overvolt-

age protect is feedback voltage referred.

The LTM4646 is a dual-output standalone non-isolated

switching mode DC/DC power supply. It can provide two

10A outputs with few external input and output capacitors

and setup components. This module provides precisely Pulling the RUN pins below 1.3V forces the regulators

regulated output voltages programmable via external into a shutdown state, by turning off both MOSFETs.

resistors from 0.6V to 5.5V over 4.5V to 20V input The TRACK/SS pins are used for programming the out-

DC

voltages. The typical application schematic is shown in put voltage ramp and voltage tracking during start-up or

Figure 18. See Note 8 in the Electrical Characteristics sec- used for soft-starting the regulator. See the Applications

tion for output current guideline.

Information section. The LTM4646 is internally compen-

sated to be stable over all operating conditions. Table 5

provides a guideline for input and output capacitances

The LTM4646 has dual integrated controlled-on time cur-

rent mode regulators and built-in power MOSFET devices

with fast switching speed. The controlled on-time, valley

current mode control architecture, allows for not only

fast response to transients without clock delay, but also

constant frequency switching at steady load condition.

The typical switching frequency is 400kHz. For switching-

noise sensitive applications, it can be externally synchro-

®

for several operating conditions. The LTpowerCAD will

be provided for transient and stability analysis. The V

FB1

pin is used to program the channel 1 output voltage with

a single external resistor to ground, and V pin requires

FB2

two resistors to program the output. Both channel 1 and 2

have remote sense capability.

nized from 250kHz to 1.3MHz. A resistor can be used to Multiphase operation can be easily employed with the

program a free run frequency on the FREQ pin. See the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 6

Applications Information section.

phases can be cascaded to run simultaneously with

respect to each other by programming the PHASMD pin to

different levels. See the Applications Information section.

With current mode control and internal feedback loop

compensation, the LTM4646 module has sufficient sta-

bility margins and good transient performance with a wide High efficiency at light loads can be accomplished

range of output capacitors, even with all ceramic output with selectable pulse-skipping operation using the

capacitors. Optimized external compensation is supported MODE_PLLIN. These light load features will accommodate

by disconnecting the internal compensation.

battery operation. Efficiency graphs are provided for light

load operation in the Typical Performance Characteristics

section. Each channel has temperature diode included

inside the module to monitor the temperature of the

module. See the Applications Information section for

details.

Current mode control provides cycle-by-cycle fast current

limit and foldback current limit in an overcurrent condi-

tion. Internal overvoltage and undervoltage comparators

pull the open-drain PGOOD outputs low if the output feed-

back voltage exits a 7.5% window around the regulation

4646f

11

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LTM4646

APPLICATIONS INFORMATION

The typical LTM4646 application circuit is shown in

Figure 18. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 5 for specific external capacitor

requirements for particular applications.

The Thevenin equivalent of the V

equation would

OUT2

be the 0.6V with a series resistance of (60.4k || R ),

FB2

thus R

connected to the series resistance would be

FB3

(60.4k || R ) to equal the 0.3V reference.

FB2

ꢃable 1. V , V , Resistor ꢃable vs Various Output Voltages

FB1 FB2

V

0.6V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V

Open 90.9k 60.4k 40.2k 30.1k 19.1k 13.3k 8.25k

0.3V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V

Open 90.9k 60.4k 40.2k 30.1k 19.1k 13.3k 8.25k

Open 36.5k 30.1k 24.3k 20k 14.7k 11k 7.32k

OUꢃ1

V to V

IN

Step-Down Ratios

OUꢃ

R

FB1

There are restrictions in the maximum V and V

IN

step-

OUT

V

OUꢃ2

down ratio that can be achieved for a given input voltage.

Each output of the LTM4646 is capable of a wide duty

cycle that is limited by the minimum on-time t of

R

FB2

FB3

R

ON(MIN)

30ns defined as t

< D/f for narrow duty cycle,

SW

ON(MIN)

Figure 2 shows the LTM4646 used in a 2-phase single

output: Tie the V pin to INTV , which will disable

where D is duty cycle (V /V ) and f is the switch-

OUT IN SW

FB1

CC

ing frequency. The minimum off-time of 90ns t

OFF(MIN)

channel 1’s error amplifier and internally connect COMP2

to COMP1. Tie any of the compensation components to

the COMP2 pin. The COMP1 pin can be either left open

< 1 – D/f is required for higher duty cycles. See Note 8

SW

in the Electrical Characteristics section for output current

guideline.

or shorted to COMP2 externally as shown. The, V

,

OUTS1

TRACK/SS1 and PGOOD1 pins become non-operable and

can be left open. To make a single-output converter of

three or more phases, additional LTM4646 micromod

Output Voltage Prograꢂꢂing

The PWM controller has an internal 0.6V reference voltage.

As shown in Figure 1, a 60.4k internal feedback resistor

-

ules can be used. The first module should be tied the

same way as the Figure 2. If only one more channel of

an additional LTM4646 is needed, use channel 2 for the

additional phase:

connects between the V

to V and V

FB1

to V

.

OUTS1

OUTS2

FB2

It is very important that these pins be connected to their

respective outputs for proper feedback regulation. Each

channel has a 49.9Ω resistor connected from V and

OUTS1

•

Tie the COMP2 pin to the COMP2 pin of the first module.

Tie the RUN2 pin to the RUN pins of the first module.

Use 1/2 the value for R and R

V

to V

and V

, respectively. This is used to

OUT2

OUTS2

OUT1

protect the output if V

is open or left unconnected.

OUTSn

The V

output voltage will default to 0.6V with no feed-

.

OUT1

FB2

FB3

back resistor on V . Adding a resistor R from V

FB1 FB1

FB1

•

Tie V

of the additional channel to V

of the

–

OUTS2

pin to V

programs the output voltage:

OUTS1

first module then to remote sense point.

Tie the V pin to the V pin of the first module.

60.4k ꢃ R

FB1

V

OUT1

ꢂ 0.6V •

•

FB2

R

FB1

–

Tie the V

pin to the V

pin of the

OUTS2

The V

output voltage will default to 0.3V with no feed-

first module.

Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the

first module.

If both channels are needed for four phases, the addi

OUT2

back resistor on V . Adding a resistor R from V

FB2 FB2

FB2

•

–

pin to V

, and the R

resistor equal to (60.4k//

OUTS2

FB3

R

FB2

) from V to SGND programs the output voltage:

FB2

-

60.4k ꢃR

FB2

tional LTM4646 module should be tied the same way

as the first as shown in Figure 2 to disable the second

channel 1’s EA:

V

OUT2

ꢂ 0.6V •

R

FB2

ꢄ

ꢆ

ꢅ

ꢇ

ꢉ

ꢈ

60.4k • R

FB2

R

ꢂ 60.4k ||R

ꢂ

FB3

FB2

60.4k +R

•

Tie the V pin to the module’s own INTV

FB1

CC.

4646f

12

For more information www.linear.com/LTM4646

LTM4646

APPLICATIONS INFORMATION

4.5V TO 20V

INTV

CC

10μF

25V

×4

+

100μF

25V

115k

130k

INTV

CC

FREQ

V V

IN1 IN2

CPWR

DRV

INTV

EXTV

CC

PHASMD

RUN2

CC

RUN

RUN1

10k

PGOOD2

PGOOD1

SW1

PGOOD2

SW2

V

OUT

V

OUT2

1.2V

V

OUT1

AT 20A

V

OUTS2

V

OUTS1

100µF

×3

100μF

×3

LTM4646

V

FB2

INTV

V

CC

FB1

+

470μF

2.5V

30.1k

60.4k

47pF

VRNG

POSCAP

–

V

OUTS1

OUTS2

REMOTE

SENSED GND

COMP

COMP1A

COMP1B

COMP2A

COMP2B

TRACK/SS1

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

TRACK/SS2

7.15k

+

–

+

–

INTV

CC

CLKOUT

150pF

C

COMP

0.1μF

1500pF

CHANNEL 1 TEMP MONITOR DIODE

CHANNEL 2 TEMP MONITOR DIODE

4646 F02

Figure 2. 2-Phase Parallel Configurations

•

Tie the COMP2 pin to the COMP2 pin of the first module.

Tie the RUN pins to the RUN pins of the first module.

Tie the V pin to the V pin of the first module.

traces or not enough source capacitance. If low imped-

ance power planes are used, then this bulk capacitor is

not needed.

FB2

For a buck converter, the switching duty-cycle can be

estimated as:

Use 1/2 the value for R and R

FB2

.

FB3

–

•

Tie the V

pin to the V

pin of the

OUTS2

V

OUT

D ꢂ

first module.

V

IN

Tie V

of both modules together then to the

OUTS2

Without considering the inductor current ripple, for each

output, the RMS current of the input capacitor can be

estimated as:

remote sense output.

Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the

first module.

I

OUT(MAX)

I

ꢂ

• D • 1ꢋ D

(

)

See Figure 20 for an example.

CIN(RMS)

ꢊ%

Input Capacitors

In the above equation, ꢊ% is the estimated efficiency of

the power module. The bulk capacitor can be a switcher-

rated aluminum electrolytic capacitor, polymer capacitor.

The LTM4646 module should be connected to a low AC

impedance DC source. For the regulator input, four 10μF

input ceramic capacitors are used for RMS ripple current.

A 47μF to 100μF surface mount aluminum electrolytic bulk

capacitor can be used for more input bulk capacitance.

The LTM4646 is designed for low output voltage ripple

noise and good transient response. The bulk output

capacitors defined as C

are chosen with low enough

OUT

effective series resistance (ESR) to meet the output volt-

This bulk input capacitor is only needed if the input source

impedance is compromised by long inductive leads,

age ripple and transient requirements. C

can be a low

OUT

4646f

13

For more information www.linear.com/LTM4646

LTM4646

APPLICATIONS INFORMATION

ESR tantalum capacitor, low ESR polymer capacitor or

ceramic capacitor. The typical output capacitance range

for each output is from 200μF to 470μF. Additional output

filtering may be required by the system designer, if further

reduction of output ripples or dynamic transient spikes

is required. Table 5 shows a matrix of different output

voltages and output capacitors to minimize the voltage

droop and overshoot during a 7.5A/μs transient. The table

optimizes total equivalent ESR and total bulk capacitance

to optimize the transient performance. Stability criteria are

considered in the Table 5 matrix, and LTpowerCAD will be

provided for stability analysis. Multiphase operation will

reduce effective output ripple as a function of the num-

ber of phases. Application Note 77 discusses this noise

reduction versus output ripple current cancellation, but

the output capacitance should be considered carefully as a

function of stability and transient response. LTpowerCAD

can calculate the output ripple reduction as the number of

implemented phases increases by N times.

Multiphase Operation

For output loads that demand more than 10A of current,

two outputs in LTM4646 or even multiple LTM4646s can

be paralleled to run out of phase to provide more output

current without increasing input and output voltage ripple.

The MODE_PLLIN pin allows the LTM4646 to synchronize

to an external clock (between 250kHz and 1.3MHz) and

the internal phase-locked loop allows the LTM4646 to lock

onto an incoming clock phase as well. The CLKOUT signal

can be connected to the MODE_PLLIN pin of the following

stage to line up both the frequency and the phase of the

entire system. Tying the PHASMD pin to INTV , SGND,

CC

or floating the pin will select V

and CLKOUT phases

OUT2

relative to V

.

OUT1

Up to of 12 phases can be cascaded to run simultaneously

with respect to each other by programming the PHASMD

pin of each LTM4646 channel to different levels. Figure 3

shows a 2-phase design, 4-phase design and a 6-phase

design example for clock phasing with the PHASMD table.

Continuous and Discontinuous Mode Operation

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors. The RMS input ripple current is reduced by,

and the effective ripple frequency is multiplied by, the

number of phases used (assuming that the input volt-

age is greater than the number of phases used times the

output voltage).

If the MODE_PLLIN pin is tied to INTV or an external

CC

clock is applied to MODE_PLLIN, the LTM4646 will be

forced to operate in continuous mode. With load current

less than one-half of the full load peak-to-peak ripple, the

inductor current valley can drop to zero or become nega-

tive. This allows constant-frequency operation but at the

cost of low efficiency at light loads.

The output ripple amplitude is also reduced by the number

of phases used when all of the outputs are tied together to

achieve a single high output current design. The LTM4646

device is an inherently current mode controlled device, so

parallel modules will have very good current sharing. This

will balance the thermals on the design. Figure 19 shows

an example of parallel operation and pin connection.

If the MODE_PLLIN pin is left open or connected to sig-

nal ground, the channel will transition into discontinu-

ous mode operation, where a current reversal compara-

tor shuts off the bottom MOSFET as the inductor current

approaches zero, thus preventing negative inductor cur-

rent and improving light-load efficiency. In this mode,

both switches can remain off for extended periods of time.

As the output capacitor discharges by load current and the

output voltage droops lower, EA will eventually move the

ITH voltage above the zero current level (0.8V) to initiate

another switching cycle.

Input RMS Ripple Current Cancellation

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current can-

cellation mathematical derivations are presented, and

a graph is displayed representing the RMS ripple cur-

rent reduction as a function of the number of interleaved

phases. Figure 4 shows this graph.

4646f

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LTM4646

APPLICATIONS INFORMATION

2-PHASE DESIGN

PHASMD SGND FLOAT INTV

CC

FLOAT

CONTROLLER1

CONTROLLER2

CLKOUT

0

CLKOUT

180

60

180

90

240

120

MODE_PLLIN

0 DEGREES

FLOAT

180 DEGREES

V

OUT1

V

OUT2

PHASMD

4-PHASE DESIGN

90 DEGREES

CLKOUT

MODE_PLLIN

0 DEGREES

FLOAT

180 DEGREES

90 DEGREES

270 DEGREES

V

OUT1

V

OUT2

OUT1

OUT2

FLOAT

PHASMD

6-PHASE DESIGN

60 DEGREES

120 DEGREES

CLKOUT

MODE_PLLIN

CLKOUT

MODE_PLLIN

0 DEGREES

180 DEGREES

60 DEGREES

240 DEGREES 120 DEGREES

300 DEGREES

V

OUT1

V

OUT2

OUT1

OUT2

OUT1

FLOAT

PHASMD

4646 F03

Figure 3. Eꢁaꢂples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD ꢃable

0.60

1-PHASE

2-PHASE

0.55

3-PHASE

4-PHASE

0.50

6-PHASE

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (V /V

OUT IN

)

4646 F04

Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

4646f

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LTM4646

APPLICATIONS INFORMATION

Frequency Selection and Phase-Locked Loop (MODE_

The clock input levels should be no less than 2V for “high”

and no greater than 0.5V for “low”. The MODE_PLLIN pin

has an internal 600k pull-down resistor.

PLLIN and f Pins)

SEꢃ

The LTM4646 device is operated over a range of frequen-

cies to improve power conversion efficiency . It is recom-

mended to operate the lower output voltages or lower

duty cycle conversions at lower frequencies to improve

efficiency by lowering power MOSFET switching losses.

Higher output voltages or higher duty cycle conversions

can be operated at higher frequencies to limit inductor

ripple current. The efficiency graphs will show an operat-

ing frequency chosen for that condition An internal oscil-

lator (clock generator) provides phase interleaved internal

clock signals for individual channels to lock up to. The

switching frequency and phase of each switching channel

is independently controlled by adjusting the top MOSFET

turn-on time (on-time) through the one-shot timer. This

is achieved by sensing the phase relationship between

a top MOSFET turn-on signal and its internal reference

clock through a phase detector, and the time interval of the

one-shot timer is adjusted on a cycle-by-cycle basis, so

that the rising edge of the top MOSFET turn-on is always

trying to synchronize to the internal reference clock signal

for the respective channel.

During dynamic transient conditions either in the line volt-

age or load current (e.g., load step or release), the top

switch will turn on more or less frequently in response

to achieve faster transient response. This is the benefit of

the LTM4646’s controlled on-time, valley current mode

architecture. However, this process may understandably

lose phase and even frequency lock momentarily. For

relatively slow changes, phase and frequency lock can

still be maintained. For large load current steps with fast

slew rates, phase lock will be lost until the system returns

back to a steady-state condition . It may take up to several

hundred microseconds to fully resume the phase lock, but

the frequency lock generally recovers quickly, long before

phase lock does.

Miniꢂuꢂ On-ꢃiꢂe and Miniꢂuꢂ Off-ꢃiꢂe

Minimum on-time t is the smallest time duration that

ON

the LTM4646 is capable of turning on the top MOSFET on

either channel. It is determined by internal timing delays,

and the gate charge required to turn on the top MOSFET.

The LTM4646 has a minimum on time of ~30ns, and far

lower than what would be a concern based on the maxi-

mum operating frequency of 1.3MHz .

The frequency of the internal oscillator can be pro-

grammed from 250kHz to 1.3MHz by connecting a resis-

tor, R , from the FREQ pin to signal ground (SGND). The

T

FREQ pin is regulated to 1.2V internally. The value of this

resistor can be chosen according to the formula:

The below equation can be checked against the V , V

,

IN OUT

and (FREQ) frequency of operation to insure the minimum

on time t is above 30ns.

ON(MIN)

41550

R (kΩ) =

T

– 2.2

V

f(kHz)

OUT

ꢌ t

• FREQ

ON(MIN)

V

IN

For applications with stringent frequency or interfer-

ence requirements, an external clock source connected

to the MODE_PLLIN pin can be used to synchronize the

internal clock signals through a clock phase-locked loop

(Clock PLL). The LTM4646 operates in forced continuous

mode of operation when it is synchronized to the exter-

nal clock. The external clock frequency has to be within

30% of the internal oscillator frequency for successful

synchronization.

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the output ripple will increase. The on-time can be

increased by lowering the switching frequency. The

below equation can be checked against the V , V

IN

OUT,

and (FREQ) frequency of operation to insure the minimum

off time t is above 90ns.

OFF(MIN)

OUT(MAX)

V

ꢂ D

D

MAX

ꢂ 1 – FREQ • t

MAX

OFF(MIN)

V

IN(MAX)

4646f

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LTM4646

APPLICATIONS INFORMATION

Output Voltage Soft Starting and ꢃracking

TRACK/SS pin slew rate is directly equal to the master’s

output slew rate in volts per second. The equation:

Output voltage tracking can be programmed externally

using the TRACK/SS pins. The output can be tracked up

and down with another regulator. The master regulator’s

output is divided down with an external resistor divider

that is the same as the slave regulator’s feedback divider

for to implement coincident tracking. The LTM4646 uses

an accurate 60.4k resistor internally for the top feedback

resistor for each channel. Figure 5 shows an example of

coincident tracking.

MR

• 60.4k ꢂ R

TA

SR

where MR is the master’s output slew rate and SR is

the slave’s output slew rate in volts per second. When

coincident tracking is desired, then MR and SR are equal,

thus R is equal to 60.4k. R is derived from equation:

TA

TB

0.6V

R

ꢂ

TB

V

ꢄ

ꢇ

ꢉ

ꢈ

FB

TRACK

60.4k

ꢃ

ꢋ

R

SLAVE ꢂ 1ꢃ

• V

ꢆ

TRACK

60.4k

R

FB

TA

R

ꢅ

FB

where V is the feedback voltage reference of the regula-

FB

V

is the track ramp applied to the slave’s track pin.

TRACK

tor, and V

is 0.6V. Since R is equal to the 60.4k

TA

TRACK/SS

V

has a control range of 0V to 0.6V, or the internal

TRACK

top feedback resistor of the slave regulator in equal slew

rate or coincident tracking, then R is equal to R with

reference voltage. When the master’s output is divided

down with the same resistor values used to set the slave’s

output, then the slave will coincident track with the master

until it reaches its final value. The master will continue to

its final value from the slave’s regulation point. Voltage

TB

FB

V

= V

. In ratiometric tracking, a different slew

FB

TRACK/SS

rate may be desired for the slave regulator. R can be

TB

solved for when SR is slower than MR. Make sure that the

slave supply slew rate is chosen to be fast enough so that

the slave output voltage will reach it final value before the

master output. For example, MR = 20V/s, and SR = 15V/s.

Then R = 80.6k. Solve for R to equal to 80.6k.

tracking is disabled when V

is more than 0.6V.

TRACK/SS

R

TB

in Figure 5 will be equal to the R for coincident track-

FB

ing. Figure 6 shows the coincident tracking waveforms.

TA

TB

The TRACK/SS pins can be controlled by a capacitor

placed on the regulator TRACK/SS pin to ground. A 1.0μA

current source will charge the TRACK/SS pin up to the

Each of the TRACK/SS pins will have the 1.0μA current

source on when a resistive divider is used to implement

tracking on that specific channel. This will impose an off-

set on the TRACK/SS pin input. Smaller values resistors

with the same ratios as the resistor values calculated from

the above equation can be used. For example, where the

60.4k is used then a 6.04k can be used to reduce the

TRACK/SS pin offset to a negligible value.

voltage reference and then proceed up to INTV . After the

CC

0.6V ramp, the TRACK/SS pin will no longer be in control,

and the internal voltage reference will control output regu-

lation from the feedback divider. Foldback current limit is

disabled during this sequence of turn-on during tracking

or soft-starting. The TRACK/SS pins are pulled low when

the RUN pin is below 1.2V. The total soft-start time can

be calculated as:

Power Good

Each PGOOD pin is connected to an internal open-drain

N-channel MOSFET. An external resistor or current source

ꢄ

ꢆ

ꢅ

ꢇ

ꢉ

ꢈ

C

SS

t

ꢂ

• 0.6V

SOFT-START

can be used to pull this pin up to 6V (e.g., V

or

1.0µA

OUT1,2

DRV ). Overvoltage or undervoltage comparators (OV,

CC

Ratiometric tracking can be achieved by a few simple

calculations and the slew rate value applied to the mas-

ter’s TRACK/SS pin. As mentioned above, the TRACK/SS

pin has a control range from 0 to 0.6V. The master’s

UV) turn on the MOSFET and pull the PGOOD pin low

when the feedback voltage is outside the 7.5% window

of the reference voltage. The PGOOD pin is also pulled low

when the channel’s RUN pin is below the 1.2V threshold

4646f

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LTM4646

APPLICATIONS INFORMATION

4.5V TO 20V

10μF

25V

×4

+

4.7μF

100μF

25V

INTV

CC

130k

115k

INTV

CC

INTV

CC

FREQ

RUN1

V V

IN1 IN2

CPWR

DRV

INTV

CC

EXTV

CC

PHASMD

RUN2

CC

RUN1

10k

RUN1

10k

PGOOD2

PGOOD1

SW1

PGOOD2

SW2

V

OUT1

V

OUT2

V

OUT2

V

OUT1

1.2V AT 10A

0.9V AT 10A

V

OUTS2

V

OUTS1

+

100µF

×4

470μF

2.5V

LTM4646

V

+

470μF

2.5V

FB2

V

100μF

FB1

R

40.2k

FB

×4

POSCAP

60.4k

VRNG

POSCAP

INTV

121k

CC

–

V

OUTS1

OUTS2

REMOTE

SENSED GND

COMP1A

COMP1B

COMP2A

COMP2B

TRACK/SS1

TRACK/SS2

R

TA

+ – + –

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

CLKOUT

INTV

CC

60.4k

100pF

R

V

TB

OUT1

100pF

0.1μF

121k

CHANNEL 1 TEMP MONITOR DIODE

CHANNEL 2 TEMP MONITOR DIODE

4646 F05

RAMP TIME

t

= (C /1.0μA) • 0.6V

SS

SOFTSTART

Figure 5. Eꢁaꢂple of Output ꢃracking Application Circuit

MASTER OUTPUT

SLAVE OUTPUT

TIME

4646 F06

Figure 6. Output Coincident ꢃracking Waveforꢂ

4646f

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LTM4646

APPLICATIONS INFORMATION

(hysteresis applies), or in undervoltage lockout (UVLO).

In an overvoltage (OV) condition, MT is turned off and MB

is turned on immediately without delay and held on until

the overvoltage condition clears. This happens regardless

of any other condition as long as the RUN pin is enabled.

EXTV allows an external 5V supply to power the

CC

LTM4646 and reduce power dissipation from the internal

low dropout 5V regulator. The power loss savings can be

calculated by:

(CPWR – 5V) • 50mA = P

LOSS

For example, upon enabling the RUN1 pin, if V

is prebi-

OUT

EXTV has a threshold of 4.6V for activation, and a maxi-

CC

ased at more than 7.5% above the programmed regulated

voltage, the OV stays triggered and BG forced on until

is pulled a ~2.5% hysteresis below the 7.5% OV

mum rating of 6V. When using a 5V input, connect this

5V input to EXTV also to maintain a 5V gate drive level.

CC

V

OUT

EXTV must sequence on after CPWR, and EXTV must

CC CC

threshold.

sequence off before CPWR.

Stability Coꢂpensation

CPWR (Control Power)

The module has already been internally compensated for

all output voltages. Table 5 is provided for most applica-

tion requirements. LTpowerCAD will be provided for other

control loop optimization. Use LTpowerCAD when tying

output in parallel for higher current. External compensa-

tion may be necessary.

The LTM4646 module has a CPWR pin that is biased with

a supply voltage minimum of 4.5V, and up to V maxi-

IN

mum in normal operation. When operating at lower input

voltages below the 4.5V minimum, this pin can biased

with an alternate source to power the controller section

while operating down to the 2.375V minimum.

Run Enable

For example, if 3.3V is supplied to V , and a 5V bias with

IN

a 50mA capability was used to source the CPWR pin, then

3.3V input power conversion can be implemented. Even

though the CPWR can operate from 4.5V to 20V, a lower

bias will lower the power loss if the module. See Figure 21

for an example.

The RUN pins have an enable threshold of 1.3V maximum,

typically 1.2V with 100mV of hysteresis. They control the

turn on each of the channels and DRV and INTV . A

CC

100k resistor to ground is internal, and can be used with

a pull-up resistor to V to turn on the module using the

IN

external and internal resistor to program under voltage

lock out. Otherwise an external enable signal or source

can drive these pins directly below the 6V max. The RUN

pins can also be used for output voltage sequencing.

In parallel operation the RUN pins can be tie together

and controlled from a single control. See the Typical

Application circuits in Figure 21.

Output Reꢂote Sense

The LTM4646’s differential output sensing schemes are

distinct from conventional schemes where the regulated

output and its ground reference are directly sensed with

a difference amplifier whose output is then divided down

with an external resistor divider and fed into the error

amplifier input. This conventional scheme is limited by

the common mode input range of the difference amplifier

and typically limits differential sensing to the lower range

of output voltages.

DRV , INꢃV , and EXꢃV

CC CC

CC

The LTM4646 module has an internal 5.3V low dropout

regulator (DRV ) that is derived from the input voltage

CC

The LTM4646 allows for seamless differential output

sensing by sensing the resistively divided feedback volt-

age differentially. This allows for differential sensing in the

full output range from 0.6V to 5.5V. Channel 1’s difference

amplifier (DIFFAMP) has a bandwidth of around 8MHz,

and channel 2’s feedback amplifier has a bandwidth of

around 4MHz, both high enough so as to not affect main

through the CPWR (control power) pin. This regulator is

used to power the INTV control circuitry and the power

CC

MOSFET drivers. This regulator can source up to 100mA,

and typically uses ~50mA for powering the device at the

maximum frequency. This internal 5.3V supply is enabled

by either RUN1 or RUN2.

loop compensation and transient behavior.

4646f

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LTM4646

APPLICATIONS INFORMATION

The LTM4646 differential output sensing can correct for

up to 300mV of common-mode deviation in the output’s

power and ground lines on channel 1, and 200mV on

channel 2.

place to start with. Modification to these components

should be made to attenuate the ringing with the least

amount of power loss.

ꢃeꢂperature Monitoring (ꢃEMP1 and ꢃEMP2)

To avoid noise coupling into the feedback voltages, the

A diode connected PNP transistor is used for tempera-

ture monitoring. Measuring the absolute temperature of a

diode is possible due to the relationship between current,

voltage and temperature described by the classic diode

equation:

resistor dividers should be placed close to the V

and

OUTS1

–

V

, or V

and V

pins. Remote output and

OUTS1

OUTS2

ground traces should be routed together as a differential

pair to the remote output. For best accuracy, these traces

to the remote output and ground should be connected as

close as possible to the desired regulation point. Review

the parallel schematics in Figure 20.

ꢄ

ꢆ

ꢅ

ꢇ

ꢉ

ꢈ

V

D

I ꢂ I • e

D

S

ꢊ • V

T

or

OUꢃPUꢃ CURRENꢃ RANGE PIN (VRNG)

I

D

V ꢂ ꢊ • V • ln

Tying the VRNG pin to SGND will set the output current to

D

T

I

S

5A, and ~9A current limit. Tying the VRNG pin to INTV

CC

will set the output current to 10A, and ~20A current limit.

where I is the diode current, V is the diode voltage, ꢊ

D

is the ideality factor (typically close to 1.0) and I (satu-

S

SW Pins

ration current) is a process dependent parameter. V can

T

be broken out to:

k • T

The SW pins are generally for testing purposes by moni-

toring these pins. These pins can also be used to dampen

out switch node ringing caused by LC parasitic in the

switched current paths. Usually a series R-C combination

is used called a snubber circuit. The resistor will dampen

the resonance and the capacitor is chosen to only affect

the high frequency ringing.

V ꢂ

T

q

where T is the diode junction temperature in Kelvin, q is

the electron charge and k is Boltzmann’s constant. V is

T

approximately 26mV at room temperature (298K) and

scales linearly with Kelvin temperature. It is this linear

temperature relationship that makes diodes suitable tem-

If the stray inductance or capacitance can be measured

or approximated then a somewhat analytical technique

can be used to select the snubber values. The inductance

is usually easier to predict. It combines the power path

board inductance in combination with the MOSFET inter-

connect bond wire inductance. First the SW pin can be

monitored with a wide bandwidth scope with a high fre-

quency scope probe. The ring frequency can be measured

for its value. The impedance Z can be calculated:

perature sensors. The I term in the equation above is the

S

extrapolated current through a diode junction when the

diode has zero volts across the terminals. The I term

S

varies from process to process, varies with temperature,

and by definition must always be less than I . Combining

D

all of the constants into one term:

ꢊ • k

K ꢂ

D

q

Z(L) = 2πfL

where f is the resonant frequency of the ring, and L is the

total parasitic inductance in the switch path. If a resistor

is selected that is equal to Z, then the ringing should be

dampened. The snubber capacitor value is chosen so that

its impedance is equal to the resistor at the ring frequency.

Calculated by: Z(C) = 1/(2πfC). These values are a good

where K = 8.62 – 5, and knowing ln(I /I ) is always

D D S

positive because I is always greater than I , leaves us

D S

with the equation that:

4646f

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LTM4646

APPLICATIONS INFORMATION

K’ = K • In(10) = 198µV/k

D D

I

D

V ꢂ T(KELVIN) • K • ln

D

I

yields

S

∆V = K’ • T(KELVIN)

D D

where V appears to increase with temperature. It is com-

D

mon knowledge that a silicon diode biased with a current

source has an approximate –2mV/°C temperature rela-

Solving for temperature:

∆V

D

tionship (Figure 7), which is at odds with the equation

T(KELVIN) ꢂ

,

K'

D

1.0

I

= 100µA

D

T(KELVIN) ꢂ [ꢍC]ꢃ 273.15,

[ꢍC] ꢂ T(KELVIN)ꢋ 273.15

I

= 10µA

D

0.8

means that if we take the difference in voltage across the

diode measured at two currents with a ratio of 10, the result-

ing voltage is 198μV per Kelvin of the junction with a zero

intercept at 0 Kelvin. The diode connected PNP transistor at

∆V

D

0.6

+ –

the TEMP , TEMP pins can be used to monitor the internal

temperature of the LTM4646. A general temperature moni-

0.4

–173

–73

27

127

tor can be implemented by connecting a resistor between

+

TEMP and V to set the current to 100µA, grounding the

IN

TEMPERATURE (°C)

4646 F07

–

TEMP pin, and then monitoring the diode voltage drop

Figure 7. Diode Voltage V vs ꢃeꢂperature ꢃ(°C)

D

with temperature. A more accurate temperature monitor

can be achieved with a circuit injecting two currents that

are at a 10:1 ratio. See LTC2997 data sheet.

for Different Bias Currents

term, increases with temperature, reducing the ln(I /I )

D S

absolute value yielding an approximate –2mV/°C com-

posite diode voltage slope.

ꢃherꢂal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those param-

eters defined by JESD51-12 and are intended for use with

finite element analysis (FEA) software modeling tools that

leverage the outcome of thermal modeling, simulation,

and correlation to hardware evaluation performed on a

To obtain a linear voltage proportional to temperature,

we cancel the I variable in the natural logarithm term to

S

remove the I dependency from the following equation.

S

This is accomplished by measuring the diode voltage at

two currents I , and I , where I = 10 • I .

1 2 1 2

®

μModule package mounted to a hardware test board.

Subtracting we get:

I

2

The motivation for providing these thermal coefficients

is found in JESD51-12 (“Guidelines for Reporting and

Using Electronic Package Thermal Information”). Many

designers may opt to use laboratory equipment and a test

vehicle such as the demo board to anticipate the μModule

regulator’s thermal performance in their application at

various electrical and environmental operating conditions

to compliment any FEA activities. Without FEA software,

the thermal resistances reported in the Pin Configuration

section are in-and-of themselves not relevant to provid-

ing guidance of thermal performance; instead, the derat-

1

∆V ꢂ T(KELVIN) • K •In ꢋ T(KELVIN) • K •In

I

S

D

I

S

Combining like terms, then simplifying the natural log

terms yields:

∆V = T(KELVIN) • K • In(10)

D D

and redefining constant

ing curves provided in the data sheet can be used in a

4646f

21

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LTM4646

APPLICATIONS INFORMATION

manner that yields insight and guidance pertaining to

one’s application-usage, and can be adapted to corre-

late thermal performance to one’s own application. The

Pin Configuration section gives four thermal coefficients

explicitly defined in JESD51-12; these coefficients are

quoted or paraphrased below:

typical μModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of ꢁ

, this value may be useful

JCbottom

for comparing packages but the test conditions don’t

generally match the user’s application.

1. ꢁ , the thermal resistance from junction to ambient,

4. ꢁ , the thermal resistance from junction to the

JA

JB

is the natural convection junction-to-ambient air ther-

mal resistance measured in a one cubic foot sealed

enclosure. This environment is sometimes referred to

as “still air” although natural convection causes the

air to move. This value is determined with the part

mounted to a 95mm × 76mm PCB with four layers.

printed circuit board, is the junction-to-board thermal

resistance where almost all of the heat flows through

the bottom of the μModule and into the board, and

is really the sum of the ꢁ

and the thermal

JCbottom

resistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from

the package.

2. ꢁ

, the thermal resistance from junction to the

JCbottom

bottom of the product case, is determined with all

of the component power dissipation flowing through

the bottom of the package. In the typical μModule,

the bulk of the heat flows out the bottom of the pack-

age, but there is always heat flow out into the ambi-

ent environment. As a result, this thermal resistance

value may be useful for comparing packages but

the test conditions don’t generally match the user’s

application.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 8; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the μModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal oper-

ating conditions of a μModule regulator. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the μModule package—as the standard defines

3. ꢁ

, the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

component power dissipation flowing through the top

of the package. As the electrical connections of the

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4646 F08

µMODULE DEVICE

Figure 8. Graphical Representation of JESD51-12 ꢃherꢂal Coefficients

4646f

22

For more information www.linear.com/LTM4646

LTM4646

APPLICATIONS INFORMATION

for ꢁ

and ꢁ

, respectively. In practice, power

JCbottom

bottom substrate material has very low thermal resistance

to the printed circuit board. An external heat sink can be

applied to the top of the device for excellent heat sinking

with airflow.

JCtop

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4646, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to differ-

ent junctions of components or die are not exactly linear

with respect to total package power loss. To reconcile this

complication without sacrificing modeling simplicity—

but also, not ignoring practical realities—an approach

has been taken using FEA software modeling along with

laboratory testing in a controlled-environment chamber

to reasonably define and correlate the thermal resistance

values supplied in this data sheet: (1) Initially, FEA soft-

ware is used to accurately build the mechanical geometry

of the LTM4646 and the specified PCB with all of the cor-

rect material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

defined JEDEC environment consistent with JESD51-12

to predict power loss heat flow and temperature readings

at different interfaces that enable the calculation of the

JEDEC-defined thermal resistance values; (3) the model

and FEA software is used to evaluate the LTM4646 with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. The outcome of this

process and due diligence yields a set of derating curves

provided in other sections of this data sheet. After these

Safety Considerations

The LTM4646 modules do not provide isolation from V

IN

to V . There is no internal fuse. If required, a slow blow

OUT

fuse with a rating twice the maximum input current needs

to be provided to protect each unit from catastrophic

failure. The fuse or circuit breaker should be selected

to limit the current to the regulator during overvoltage

in case of an internal top MOSFET fault. If the internal

top MOSFET fails, then turning it off will not resolve the

overvoltage, thus the internal bottom MOSFET will turn

on indefinitely trying to protect the load. Under this fault

condition, the input voltage will source very large cur-

rents to ground through the failed internal top MOSFET

and enabled internal bottom MOSFET. This can cause

excessive heat and board damage depending on how

much power the input voltage can deliver to this system.

A fuse or circuit breaker can be used as a secondary fault

protector in this situation.

The device does support over current protection.

Temperature diodes are provided for monitoring inter-

nal temperature, and can be used to detect the need for

thermal shutdown that can be done by controlling the

RUN pin.

Power Derating

The 5V, 8V and 12V power loss curves in Figures 9

through 11 can be used in coordination with the load

current derating curves in Figures 12 to 16 for calculating

laboratory tests have been performed, then the ꢁ and

JB

an approximate ꢁ thermal resistance for the LTM4646

JA

ꢁ

BA

LTM4646 model with no airflow or heat sinking in a define

are summed together to correlate quite well with the

with airflow conditions. The power loss curves are taken

at room temperature, and are increased with a 1.35 to 1.4

multiplicative factor at 125°C. These factors come from

the fact that the power loss of the regulator increases

about 45% from 25°C to 150°C, thus a 50% spread

chamber. This ꢁ + ꢁ value should accurately equal

JB

BA

the ꢁ value because approximately 100% of power loss

JA

flows from the junction through the board into ambient

with no airflow or top mounted heat sink. Each system has

its own thermal characteristics, therefore thermal analysis

must be performed by the user in a particular system.

The LTM4646 has been designed to effectively remove

heat from both the top and bottom of the package. The

4646f

23

For more information www.linear.com/LTM4646

LTM4646

APPLICATIONS INFORMATION

over 125°C delta equates to ~0.35%/°C loss increase. A

125°C maximum junction minus 25°C room temperature

equates to a 100°C increase. This 100°C increase multi-

plied by 0.35%/°C equals a 35% power loss increase at

the 125°C junction, thus the 1.35 multiplier.

calculated with the ~2.25W room temperature loss from

the 12V to 1.0V power loss curve at 14.5A, and the 1.35

multiplying factor at 125°C ambient. If the 95°C ambient

temperature is subtracted from the 125°C junction tem-

perature, then the difference of 30°C divided by 3.04W

equals a 9.9°C/W ꢁ thermal resistance. Table 2 speci-

JA

The derating curves are plotted with V

and V

in

OUT1

OUT2

fies a 10.1°C/W value which is pretty close. The airflow

graphs are more accurate due to the fact that the ambient

temperature environment is controlled better with airflow.

parallel single output operation starting at 20A of load

with low ambient temperature. The output voltages are

1V, 2.5V and 5V. These are chosen to include the lower

and higher output voltage ranges for correlating the ther-

mal resistance. Thermal models are derived from several

temperature measurements in a controlled temperature

chamber along with thermal modeling analysis.

As an example in Figure 13, the load current is derated to

~16.5A at ~95°C with 200LFM of airflow and the power

loss for the 12V to 1.0V at 16.5A output is a 3.7W loss.

The 3.7W loss is calculated with the ~2.75W room tem-

perature loss from the 12V to 1.0V power loss curve at

16.5A, and the 1.35 multiplying factor at 125°C ambient.

If the 95°C ambient temperature is subtracted from the

125°C junction temperature, then the difference of 30°C

The junction temperatures are monitored while ambient

temperature is increased with and without airflow. The

power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at ~120°C maximum while lowering output

current or power while increasing ambient temperature.

The decreased output current will decrease the internal

module loss as ambient temperature is increased.

divided by 3.7W equals a 8.1°C/W ꢁ thermal resistance.

JA

Table 2 specifies a 8.1°C/W value which is pretty close.

Tables 2 through 4 provide equivalent thermal resistances

for 1V, 2.5V and 5V outputs with and without airflow.

The monitored junction temperature of 120°C minus the

ambient operating temperature specifies how much tem-

perature rise can be allowed. As an example in Figure 13,

the load current is derated to ~14.5A at ~95°C with no

air or heat sink and the power loss for the 12V to 1.0V

at 14.5A output is a ~3.04W loss. The ~3.04W loss is

The derived thermal resistances in Tables 2 through 4

for the various conditions can be multiplied by the calcu-

lated power loss as a function of ambient temperature to

derive temperature rise above ambient, thus maximum

junction temperature. Room temperature power loss can

be derived from the power loss curves and adjusted with

4646f

24

For more information www.linear.com/LTM4646

LTM4646

APPLICATIONS INFORMATION

ꢃable 2. 1.0V Output

BGA

DERAꢃING CURVE

Figures 12, 13

V

(V)

POWER LOSS CURVE

Figure 9, 11

AIRFLOW (LFM)

HEAꢃ SINK

None

ꢎ

(°C/W)

JA

IN

5, 12

0

10.1

8.1

Figure 9, 11

200

400

None

Figure 9, 11

None

7.4

ꢃable 3. 2.5V Output

BGA

DERAꢃING CURVE

Figures 14, 15

V

(V)

POWER LOSS CURVE

Figure 9, 11

AIRFLOW (LFM)

HEAꢃ SINK

None

ꢎ

(°C/W)

JA

IN

5, 12

0

10.1

8.0

5, 12

Figure 9, 11

200

400

None

Figure 9, 11

None

7.4

ꢃable 4. 5V Output (EXꢃV electrically connected to 5V

CC

)

OUꢃ

BGA

DERAꢃING CURVE

Figures 16

V

IN

(V)

POWER LOSS CURVE

Figure 11

AIRFLOW (LFM)

HEAꢃ SINK

None

ꢎ

(°C/W)

JA

12

0

8.5

7.0

6.3

Figures 16

Figure 11

200

400

None

Figures 16

Figure 11

None

HEAꢃ SINK MANUFACꢃURER

PARꢃ NUMBER

3-0504035UT411

WEBSIꢃE

www.coolinnovations.com

Cool Innovations

Thermally conductive adhesive tape pre-attached, Chomerics P/N T411

ꢃable 5. Capacitor Matriꢁ (All Paraꢂeters Are ꢃypical and Dependent on Board Layout)

VENDORS

Taiyo Yuden

Murata

VALUE

PARꢃ NUMBER

C3216X7S0J226M

GRM31CR61C226KE15L Panasonic POSCAP

GRM32ER60J107M Panasonic POSCAP

18126D107MAT Panasonic

VENDORS

VALUE

PARꢃ NUMBER

EEFGX0E471R

2R5TPD470M5

6TPD470M

22μF, 25V

100μF, 6.3V

Panasonic SP

470μF, 2.5V

470μF, 6.3V

100μF, 20V

Murata

AVX

20SEP100M

V

OUꢃ

C

IN

C

IN

C

OUꢃ1

C

OUꢃ2

C

COMP

V

IN

DROOP P-P DEVIAꢃION RECOVERY ꢃIME LOAD SꢃEP FREQ

FF

(V) (CERAMIC) (BULK)** (CERAMIC) (CERAMIC/BULK) (pF)

0.9

1

(pF)

100

(V)

(ꢂV)

26

(ꢂV)

52

(µs)

30

25

20

(A/µs)

(kHz)

400

22μF ×4

100μF

100μF ×4

100μF ×3

100μF ×2

100μF ×1

470μF ×2

None

5,12

5

26

52

400

1.2

1.5

1.8

2.5

3.3

5

30

60

5

500

47

44

88

5

600

None

44

88

5

700

None

53

107

133

185

5

850

None

67

3.3

1100

1300

None

67

**Bulk capacitance is optional if V has very low input impedance.

IN

4646f

25

For more information www.linear.com/LTM4646

LTM4646

APPLICATIONS INFORMATION

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

6

5

4

3

2

1

5.0V , 900kHz, EXTV = 5V

OUT CC

5.0V , 1.3MHz, EXTV = 5V

OUT CC OUT

3.3V , 550kHz

OUT

3.3V , 850kHz

OUT

3.3V , 1.1MHz

OUT

2.5V , 550kHz

OUT

2.5V , 750kHz

OUT

2.5V , 850kHz

OUT

1.8V , 500kHz

OUT

1.8V , 600kHz

OUT

1.8V , 700kHz

OUT

1.5V , 450kHz

OUT

1.5V , 550kHz

OUT

1.5V , 600kHz

OUT

1.2V , 400kHz

OUT

1.2V , 475kHz

OUT

1.2V , 500kHz

OUT

1.0V , 350kHz

OUT

1.0V , 400kHz

OUT

0.9V , 350kHz

OUT

0.9V , 400kHz

OUT

1.0V , 400kHz

OUT

0.9V , 400kHz

OUT

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

0

2

4

6

8

10 12 14 16 18 20

OUTPUT CURRENT (A)

4646 G09

4646 G10

4646 G11

Figure 9. 5V Power Loss Curve

IN

Figure 10. 8V Power Loss Curve

IN

Figure 11. 12V Power Loss Curve

IN

20

16

12

8

20

16

12

8

20

16

12

8

4

0LFM

200LFM

400LFM

200LFM

400LFM

200LFM

400LFM

0

60

70

80

90

100

110

120

60

70

80

90

100

110

120

60

70

80

90

100

110

120

AMBIENT TEMPERATURE (°C)

4646 G12

4646 G13

4646 G14

Figure 13. 12V to 1V Derating Curve,

Figure 14. 5V to 2.5V Derating

Curve, No Heat Sink,

= 550kHz, EXꢃV

Figure 12. 5V to 1V Derating

Curve, No Heat Sink,

No Heat Sink, f = 400kHz

SW

f

= 350kHz, EXꢃV

CC

SW

CC

SW

Electrically Connected to V

IN

20

16

12

8

16

12

8

4

0LFM

200LFM

400LFM

70 80

AMBIENT TEMPERATURE (°C)

0

60

0

90

100

110

120

60

70

80

90

100

110

120

AMBIENT TEMPERATURE (°C)

4646 G15

4646 G16

Figure 15. 12V to 2.5V Derating

Curve, No Heat Sink, f = 850kHz

SW

Figure 16. 12V to 5V Derating

Curve, No Heat Sink,

= 1.3MHz, EXꢃV

f

SW

CC

Electrically Connected to V

OUꢃ

4646f

26

For more information www.linear.com/LTM4646

LTM4646

APPLICATIONS INFORMATION

the above ambient temperature multiplicative factors. The

printed circuit board is a 1.6mm thick four layer board

with two ounce copper for the two outer layers and one

ounce copper for the two inner layers.

GND

V

IN2

V

IN2

Use a separated SGND ground copper area for compo-

nents connected to signal pins. Connect the SGND to GND

underneath the unit.

GND

V

OUT1

OUT2

GND

•

For parallel modules, tie the V

V , and COMP

OUT, FB

4646 F17a

(a)

pins together. Use an internal layer to closely connect

these pins together. The TRACK/SS pin can be tied a

common capacitor for regulator soft-start.

TOP LAYER

15mm x 11.25mm x 5.01mm

GND

•

Bring out test points on the signal pins for monitoring.

Figures 17a and 17b give a good example of the recom-

mended layout.

V

IN2

V

IN2

GND

Layout Checklist/Eꢁaꢂple

The high integration of LTM4646 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

V

OUT2

V

OUT1

GND

4646 F17b

(b)

BOTTOM LAYER

15mm x 11.25mm x 5.01mm

•

Use large PCB copper areas for high current paths,

including V , GND, V and V . It helps to mini-

Figure 17. Recoꢂꢂended PCB Layout

IN

OUT1

OUT2

mize the PCB conduction loss and thermal stress.

Place high frequency ceramic input and output capac-

itors next to the V , GND and V pins to minimize

•

IN

OUT

high frequency noise.

Place a dedicated power ground layer underneath the

unit.

•

To minimize the via conduction loss and reduce mod-

ule thermal stress, use multiple vias for interconnec-

tion between top layer and other power layers.

•

Do not put vias directly on the pads, unless they are

capped or plated over.

4646f

27

For more information www.linear.com/LTM4646

LTM4646

TYPICAL APPLICATIONS

4.5V TO 20V

+

4.7μF

10μF

INTV

100μF

CC

25V

130k

25V

115k

×4

INTV

CC

INTV

CC

FREQ

RUN1

V V

IN1 IN2

CPWR

DRV

INTV

EXTV

CC

PHASMD

RUN2

CC

RUN1

10k

RUN1

10k

PGOOD2

PGOOD1

SW1

PGOOD2

SW2

V

OUT2

V

OUT1

V

1.5V

OUT2

V

OUT1

1.5V AT 10A

AT 10A

V

OUTS2

V

OUTS1

LTM4646

V

FB2

100µF

×3

V

FB1

100μF

×3

R

24.3k

FB

40.2k

VRNG

INTV

40.2k

CC

–

REMOTE

SENSED

GND

V

OUTS1

OUTS2

COMP1A

COMP1B

COMP2A

COMP2B

TRACK/SS1

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

TRACK/SS2

+

–

+

–

CLKOUT

INTV

CC

100pF

0.1μF

100pF

C

COMP

0.1μF

C

COMP

CHANNEL 1 TEMP MONITOR DIODE

CHANNEL 2 TEMP MONITOR DIODE

4646 F18

Figure 18. 4.5V to 20V Input to 1.5V Dual Output, at 10A Each

4.5V TO 14V

+

4.7μF

10μF

25V

×4

100μF

25V

INTV

CC

130k

115k

INTV

CC

FREQ

RUN1

V V

IN1 IN2

CPWR

DRV

INTV

EXTV

CC

PHASMD

RUN2

CC

RUN1

10k

PGOOD1

SW1

PGOOD2

SW2

PGOOD2

V

OUT

V

OUT2

0.75V

V

OUT1

AT 20A

V

OUTS2

V

OUTS1

100μF

×3

V

LTM4646

100µF

×3

FB2

V

FB1

470μF

2.5V

INTV

CC

+

48.1k

240k

VRNG

POSCAP

×2

–

REMOTE

SENSED

GND

V

OUTS1

OUTS2

COMP

COMP1A

COMP1B

COMP2A

COMP2B

TRACK/SS1

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

TRACK/SS2

100pF

+

–

+

–

INTV

CLKOUT

CC

7.15k

0.1μF

1500pF

CHANNEL 1 TEMP MONITOR DIODE

CHANNEL 2 TEMP MONITOR DIODE

C

COMP

4646 F19

Figure 19. 12V Input to 0.75V at 20A ꢃwo Phase

4646f

28

For more information www.linear.com/LTM4646

LTM4646

TYPICAL APPLICATIONS

4.5V TO 16V

10μF

4.7μF

+

INTV _U1

CC

100μF

25V

64.9k

25V

115k

×3

FREQ

RUN1

V V

IN1 IN2

CPWR

DRV

INTV

CC

EXTV

CC

PHASMD

RUN2

CC

RUN

PGOOD

PGOOD2

SW2

PGOOD1

SW1

1V AT 40A

V

OUT2

V

OUT1

V

OUTS2

V

OUTS1

FB

INTV _U1

CC

V

FB2

U1

LTM4646

100µF

×4

V

FB1

100μF

×4

18.2k

45.3k

VRNG

–

V

OUTS2

–

V

OUTS1

OUTS2

REMOTE

SENSED

GND

COMP

COMP1A

COMP1B

COMP2A

COMP2B

TRACK

TRACK/SS1

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

TRACK/SS2

+

–

+

–

INTV

CLKOUT

CC

0.1μF

100pF

CLK

CHANNEL 2 TEMP MONITOR DIODE

CHANNEL 1 TEMP MONITOR DIODE

4.5V TO 16V

10μF

25V

×3

4.7μF

INTV _U2

CC

INTV _U2

CC

115k

FREQ

RUN1

V V

IN1 IN2

CPWR

DRV

INTV

EXTV

CC

PHASMD

RUN2

CC

RUN

PGOOD1

SW1

PGOOD2

SW2

PGOOD

V

OUT1

V

OUT2

470μF

2.5V

100µF

+

V

OUTS1

V

OUTS2

×4

INTV _U2

CC

100μF

×4

U2

LTM4646

x2

V

FB1

V

FB2

FB

POSCAP

VRNG

–

V

OUTS2

–

V

OUTS1

COMP

COMP1A

COMP1B

COMP2A

COMP2B

TRACK

TRACK/SS1

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

TRACK/SS2

+

–

+

–

CLKOUT

CLK

4646 F20

100pF

CHANNEL 1 TEMP MONITOR DIODE

CHANNEL 2 TEMP MONITOR DIODE

Figure 20. Four Phase Design 1V at 40A

4646f

29

For more information www.linear.com/LTM4646

LTM4646

TYPICAL APPLICATIONS

V

5V BIAS AT 50mA

3.3V

IN

22μF

+

6.3V

220μF

115k

×4

6.3V

3.3V

4.7μF

INTV

CC

3.3V

49.9k

FREQ

V V

IN1 IN2

CPWR

DRV

INTV

EXTV

PHASMD

CC

10k

RUN1

RUN2

PGOOD1

PGOOD2

SW2

PGOOD2

V

OUT2

SW1

V

OUT1

V

1.8V

OUT2

2.5V

AT 10A

V

OUT1

OUTS1

FB1

AT 10A

V

OUTS2

47pF

100μF

×2

V

FB2

LTM4646

100µF

×3

20k

30.1k

19.1k

VRNG

INTV

CC

–

REMOTE

SENSED

GND

V

OUTS1

OUTS2

COMP1A

COMP1B

COMP2A

COMP2B

TRACK/SS1

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

TRACK/SS2

100pF

+

–

+

–

100pF

INTV

CLKOUT

CC

0.1μF

CHANNEL 1 TEMP MONITOR DIODE

CHANNEL 2 TEMP MONITOR DIODE

4646 F21

Figure 21. 3.3V to 1.8V, and 2.5V at 10A each with PGOOD Power Up Sequencing

100

95

90

85

80

75

3.3V TO 2.5V, 350kHz

3.3V TO 1.8V, 350kHz

70

1

2

3

4

5

6

7

8

9

10

LOAD CURRENT (A)

4646 F22

Figure 22. Efficiency, 3.3V

IN

4646f

30

For more information www.linear.com/LTM4646

LTM4646

TYPICAL APPLICATIONS

V

IN2

5V

+

22μF

6.3V

×2

56μF

16V

5V BIAS AT 50mA

V

IN1

12V

+

4.7μF

INTV

22μF

16V

×2

56μF

16V

CC

130k

115k

INTV

CC

FREQ

RUN1

V V

IN1 IN2

CPWR

DRV

INTV

EXTV

CC

PHASMD

RUN2

CC

R4

10k

PGOOD2

PGOOD1

SW1

SW2

V

OUT2

V

OUT1

V

OUT2

1.8V

V

OUT1

3.3V

UP TO 10A

AT 10A

47pF

V

OUTS2

V

OUTS1

47pF

V

LTM4646

FB2

100µF

×3

100μF

×2

V

FB1

20k

30.1k

13.3k

VRNG

INTV

CC

–

REMOTE

SENSED

GND

–

V

OUTS2

V

OUTS1

COMP2A

COMP2B

COMP1A

COMP1B

TRACK/SS1

MODE_PLLIN TEMP1 TEMP1 SGND GND TEMP2 TEMP2

TRACK/SS2

100pF

+

–

+

–

INTV

CLKOUT

CC

0.1μF

100pF

0.1μF

CHANNEL 1 TEMP MONITOR DIODE

CHANNEL 2 TEMP MONITOR DIODE

4646 F23

Figure 23. 12V to 3.3V Up to 10A, 5V to 1.8V at 10A

4646f

31

For more information www.linear.com/LTM4646

LTM4646

PACKAGE DESCRIPTION

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCꢃS. REVIEW EACH PACKAGE

LAYOUꢃ CAREFULLY.

LꢃM4646 Coꢂponent BGA Pinout

PIN ID

A1

FUNCꢃION

PIN ID

B1

FUNCꢃION

PIN ID

C1

FUNCꢃION

PIN ID FUNCꢃION

PIN ID

E1

FUNCꢃION

PIN ID

F1

FUNCꢃION

FREQ

V

OUT2

V

D1

D2

D3

D4

D5

D6

D7

D8

V

OUT2

COMP2B

OUT2

A2

V

B2

V

C2

V

VRNG

SGND

E2

V

OUTS2

F2

TRACK/SS2

MODE_PLLIN

CLKOUT

OUT2

A3

GND

B3

GND

C3

GND

SW2

E3

COMP2A

F3

–

A4

V

B4

V

IN2

C4

V

E4

V

F4

IN2

OUTS2

FB2

A5

V

B5

V

IN2

C5

RUN2

E5

PGOOD2

GND

F5

GND

IN2

A6

GND

B6

GND

C6

GND

SW2

E6

F6

INTV

CC

A7

B7

C7

E7

EXTV

F7

GND

CC

–

+

A8

TEMP2

B8

TEMP2

C8

E8

GND

F8

CPWR

PIN ID

G1

FUNCꢃION

PIN ID

H1

FUNCꢃION

PIN ID

J1

FUNCꢃION

PIN ID FUNCꢃION

PIN ID

L1

FUNCꢃION

COMP1B

V

OUT1

V

K1

K2

K3

K4

K5

K6

K7

K8

V

OUT1

G2

V

H2

PHASMD

SGND

J2

V

OUT1

V

L2

V

OUTS1

OUT1

–

G3

COMP1A

H3

J3

V

GND

L3

GND

OUTS1

G4

V

H4

TRACK/SS1

RUN1

J4

GND

SW1

V

L4

V

IN1

FB1

IN1

G5

PGOOD1

GND

H5

J5

V

L5

V

IN1

G6

H6

GND

J6

GND

L6

GND

G7

DRV

H7

GND

J7

L7

CC

–

+

G8

GND

H8

SW1

J8

TEMP1

L8

TEMP1

4646f

32

For more information www.linear.com/LTM4646

LTM4646

PACKAGE DESCRIPTION

Please refer to http://www.linear.coꢂ/product/LꢃM4646#packaging for the ꢂost recent package drawings.

Z

/ / b b b

Z

4 . 4 4 5

3 . 1 7 5

1 . 9 0 5

0 . 6 3 5

0 . 0 0 0

1 . 9 0 5

3 . 1 7 5

4 . 4 4 5

a a a

Z

4646f

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

33

For more information www.linear.com/LTM4646

LTM4646

PACKAGE PHOTO

BGA

DESIGN RESOURCES

SUBJECꢃ

DESCRIPꢃION

µModule Design and Manufacturing Resources

Design:

• Selector Guides

• Demo Boards and Gerber Files

• Free Simulation Tools

Manufacturing:

• Quick Start Guide

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

TechClip Videos

Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management

Linear Technology’s family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS

PARꢃ NUMBER DESCRIPꢃION

COMMENꢃS

LTM4642

LTM4628

Dual 4A or Single 8A Step-Down µModule Regulator

4.5V ≤ V ≤ 20V, 0.6V ≤ V

IN

≤ 5.5V, 9mm × 11.25mm × 4.92mm BGA

OUT

Dual 8A or Single 16A Step Down µModule Regulator 4.5V ≤ V ≤ 26.5V, 0.6V ≤ V

IN

≤ 5.5V, 15mm × 15mm × 4.32mm LGA 15mm

OUT

x 15mm × 4.92 BGA

LTM4620A

Dual 13A or Single 26A Step-Down µModule Regulator 4.5V ≤ V ≤ 16V, 0.6V ≤ V

IN

≤ 5.3V, 15mm × 15mm × 4.41mm LGA, 15mm

OUT

× 15mm × 5.01mm BGA

LTM4630A

Dual 18A or Single 36A Step-Down µModule Regulator 4.5V ≤ V ≤ 15V, 0.6V ≤ V

IN

≤ 5.3V, 16mm × 16mm × 4.41mm LGA, 16mm

OUT

× 16mm × 5.01mm BGA

LTM4644

LTM4637

Quad 4A Step-Down µModule Regulator

Single 20A Step-Down µModule Regulator

4.5V ≤ V ≤ 14V, 0.6V ≤ V

IN

≤ 5.5V, 9mm × 15mm × 5.01mm BGA

OUT

4.5V ≤ V ≤ 20V, 0.6V ≤ V

IN

≤ 5.5V, 15mm × 15mm × 4.32mm LGA, 15mm

OUT

× 15mm x 4.92mm BGA

LTM4645

LTM4647

Single 25A Step-Down µModule Regulator

Single 30A Step-Down µModule Regulator

4.7V ≤ V ≤ 15V, 0.6V ≤ V

IN

≤ 1.8V, 9mm × 15mm × 3.51mm BGA

≤ 1.8V, 9mm × 15mm × 5.01mm BGA

OUT

4.7V ≤ V ≤ 15V, 0.6V ≤ V

IN

OUT

4646f

LT 0118 • PRINTED IN USA

www.linear.com/LTM4646

34

For more information www.linear.com/LTM4646

ꢏꢐLINEAR TECHNOLOGY CORPORATION 2018


型号：	LTM4646IY#PBF
厂家：	Linear
描述：	LTM4646 - Dual 10A or Single 20A µModule Regulator; Package: BGA; Pins: 88; Temperature Range: -40°C to 85°C 开关
文件：	总34页 (文件大小：555K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4646IY#PBF [Linear]

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