LTM4639_15 [Linear]
Low VIN 20A DC/DC Module Step-Down Regulator;型号: | LTM4639_15 |
厂家: | Linear |
描述: | Low VIN 20A DC/DC Module Step-Down Regulator |
文件: | 总32页 (文件大小:579K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM4639
Low V 20A DC/DC
IN
µModule Step-Down Regulator
FEATURES
DESCRIPTION
The LTM®4639 is a complete 20A output high efficiency
switch mode step-down DC/DC µModule (micromodule)
regulator. Included in the package are the switching
controller, power FETs, inductor and compensation
components. Operating over an input voltage range from
2.375V to 7V, the LTM4639 supports an output voltage
n
Complete 20A Switch Mode Power Supply
n
2.375V to 7V Input Voltage Range (V < 4.5V,
IN
Need C
Bias)
PWR
n
n
0.6V to 5.5V Output Voltage Range
1.5ꢀ Maꢁimum Total DC Output Voltage Error
(–40°C to 125°C)
n
Differential Remote Sense Amplifier for Precision
Regulation (V ≤ 3.3V)
range of 0.6V to 5.5V, set by a single external resistor.
Only a few input and output capacitors are needed.
OUT
n
n
n
n
n
n
n
n
n
n
n
Current Mode Control/Fast Transient Response
Parallel Multiphase Current Sharing (Up to 80A)
Frequency Synchronization
Currentmodeoperationallowsprecisioncurrentsharingof
up to four LTM4639 regulators to obtain up to 80A output.
Highswitchingfrequencyandacurrentmodearchitecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, multiphase/current sharing,
Burst Mode operation and output voltage tracking for
supply rail sequencing. A diode-connected PNP transistor
is included for use as an internal temperature monitor. For
up to 20V input operation, please see the LTM4637.
Selectable Pulse-Skipping or Burst Mode® Operation
Soft-Start/Voltage Tracking
Up to 88% Efficiency (3.3V , 1.5V
)
IN
OUT
Overcurrent Foldback Protection
Output Overvoltage Protection
Internal Temperature Monitor
Overtemperature Protection
15mm × 15mm × 4.92mm BGA Package
The LTM4639 is offered in a 15mm × 15mm × 4.92mm
BGA package. The LTM4639 is RoHS compliant.
L, LT, LTC, LTM, PolyPhase, Burst Mode, µModule, Linear Technology, the Linear logo are
registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643.
APPLICATIONS
n
Telecom Servers and Networking Equipment
Industrial Equipment
Medical Systems
High Ambient Temperature Systems
3.3V Input Systems
n
n
n
n
TYPICAL APPLICATION
3.3V to 1.5V Efficiency
and Power Loss
3.3VIN, 1.5VOUT, 20A DC/DC µModule® Regulator
+5V BIAS
100
95
90
85
80
75
70
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.2µF
EFFICIENCY
1µF
V
IN
3.3V
22µF
6.3V
×4
C
COMPA
V
C
EXTV INTV PGOOD
IN PWR
CC
CC
V
1.5V
20A
180pF
OUT
COMPA
COMPB
TRACK/SS
RUN
V
OUT
OUT_LCL
0.1µF
5k
V
C
*
FF
100µF*
6.3V
×2
+
680µF*
2.5V
×2
180pF
DIFF_OUT
+
LTM4639
C
= 5V
PWR
FREQ = 400kHz
V
POWER LOSS
OSNS
f
SET
–
V
OSNS
100k
MODE_PLLIN
V
FB
GND OT_TEST
+
TEMP
R
**
C
*
0
2
4
6
8
10 12 14 16 18 20
FB
40.2k
BOT
22pF
–
TEMP
SGND
OUTPUT CURRENT (A)
4639 TA01b
* SEE TABLE 5
** SEE TABLE 1
4639 TA01a
4639f
1
For more information www.linear.com/LTM4639
LTM4639
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , C
OUT_LCL
MODE_PLLIN, f , TRACK/SS,
, OT_TEST .................................. –0.3V to 10V
IN PWR
MODE_PLLIN
CC
7
COMPB
RUN
V
, PGOOD, EXTV .......................... –0.3V to 6V
INTV
TRACK/SS COMPA
CC
V
IN
1
2
3
4
5
6
8
9
10
11
12
SET
–
+
A
B
C
D
E
V
V
, V
, DIFF_OUT...................–0.3V to INTV
OSNS
OSNS CC
C
PWR
V
f
IN
SET
COMPA, COMPB (Note 7) ................. –0.3V to 2.7V
FB,
OT_TEST
RUN (Note 5) ............................................... –0.3V to 5V
INTV
CC
–
INTV Peak Output Current (Note 6) ..................100mA
Internal Operating Temperature Range
CC
TEMP
EXTV
CC
PGOOD
+
TEMP
F
V
FB
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Maximum Peak Body Reflow Temperature ........... 245°C
GND
G
H
J
PGOOD
SGND
+
V
OSNS
K
L
DIFF_OUT
V
OUT
V
V
OUT_LCL
–
M
OSNS
BGA PACKAGE
133-LEAD (15mm × 15mm × 4.92mm)
T
= 125°C, θ = 9.5°C/W, θ
= 4°C/W, θ
= 6.7°C/W, θ = 4.5°C/W
J(MAX)
θ
JA
JCbottom
JCtop JB
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS; WEIGHT = 2.8g
θ VALUES DETERMINED PER JESD51-12
JA
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
LTM4639EY#PBF
LTM4639IY#PBF
LTM4639IY
PAD OR BALL FINISH
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
RATING
LTM4639Y
LTM4639Y
LTM4639Y
e1
BGA
4
–40°C to 125°C
e0
BGA
4
–40°C to 125°C
• Consult Marketing for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures: www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings: www.linear.com/packaging
• Terminal Finish Part Marking: www.linear.com/leadfree
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in
Figure 22.
SYMBOL
PARAMETER
CONDITIONS
MIN
2.375
4.5
TYP
MAX
7
UNITS
l
V
Range
Input DC Voltage Range
V
< 4.5V, C Bias
PWR
V
V
V
V
IN
IN
C
Voltage
5
6
PWR
l
l
V
V
Range
Output DC Voltage Range
0.6
5.5
1.523
OUT
Output Voltage, Total
Variation with Line and
Load
C
C
= 22µF × 3, C
OUT
= 5V
1.477
1.50
OUT(DC)
IN
PWR
= 100µF Ceramic, 470µF POSCAP
= 40.2k, MODE_PLLIN = GND
R
FB
IN
V
= 2.375V to 7V, I
= 0A to 20A (Note 4)
OUT
4639f
2
For more information www.linear.com/LTM4639
LTM4639
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in
Figure 22.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Specifications
V
V
RUN Pin On Threshold
RUN Pin On Hysteresis
Input Supply Bias Current
V
Rising
RUN
1.1
1.25
130
1.4
V
RUN
mV
RUNHYS
Q(VIN)
I
V
V
V
= 7V, V
= 7V, V
= 7V, V
= 1.5V, Burst Mode Operation, I
= 1.5V, Pulse-Skipping Mode, I
= 1.5V, Switching Continuous, I
= 0.1A
= 0.1A
= 0.1A
25
35
68
45
mA
mA
mA
µA
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
Shutdown, RUN = 0, V = C
= 7V
IN
PWR
I
I
Input Supply Current
Control Power Current
V
V
= 3.3V, V
= 1.5V, I
= 20A, C = 5V
PWR
10.35
4.93
A
A
S(VIN)
IN
IN
OUT
OUT
= 7V, V
= 1.5V, I
= 20A, C
= 5V
OUT
OUT
PWR
3.3V to 1.5V
at 0A Load, C = 5V
PWR
28
mA
PWR(IN)
IN
OUT
Output Specifications
I
Output Continuous Current
Range
V
= 3.3V, V = 1.5V (Note 4)
OUT
0
20
0.04
0.3
A
%/V
%
OUT(DC)
IN
l
l
∆V
(Line)
OUT
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
Turn-On Overshoot
V
I
= 1.5V, V from 2.375V to 7V, C
= 5V,
0.02
0.1
20
OUT
V
OUT
IN
PWR
= 0A
OUT
∆V
(Load)
OUT
V
= 1.5V, I
= 0A to 20A, V = 3.3V, C = 5V
PWR
OUT
V
OUT
OUT
IN
(Note 4)
V
I
= 0A, C
= 100µF Ceramic, 470µF POSCAP
OUT
mV
P-P
OUT(AC)
OUT
OUT
V
= 3.3V, V
= 1.5V, C
= 5V
PWR
IN
∆V
C
V
= 100µF Ceramic, 470µF POSCAP,
15
mV
ms
mV
OUT(START)
OUTLS
OUT
OUT
= 1.5V, I
= 0A, V = 3.3V, C
= 5V
OUT
IN
PWR
t
Turn-On Time
C
= 100µF Ceramic, 470µF POSCAP,
0.6
30
START
OUT
No Load, TRACK/SS = 0.001µF, V = 3.3V, C
= 5V
PWR
IN
∆V
Peak Deviation for
Dynamic Load
Load: 5A to 12.5A Load Step, 1µs Rise Time
C
V
= 100µF × 2 Ceramic, C
× 2 POSCAP,
OUT
OUT
= 5V
= 3.3V, V
= 1.5V, C
IN
OUT
PWR
t
I
Settling Time for Dynamic Load: 5A to 12.5A Load Step, 3.3V, V = 5V, V
= 1.5V
30
µs
SETTLE
IN
OUT
Load Step
C
= 100µF × 2 Ceramic, 680µF POSCAP
OUT
Output Current Limit
V
V
= 3.3V, V = 1.5V
OUT
30
30
A
A
OUTPK
IN
IN
= 7V, V
= 1.5V
OUT
Control Section
l
l
V
Voltage at V Pin
I
= 0A, V = 1.5V
OUT
0.594
0.60
–12
0.606
–25
V
nA
V
FB
FB
OUT
I
Current at V Pin
(Note 7)
FB
FB
V
Feedback Overvoltage
Lockout
0.65
1.0
0.67
0.69
OVL
I
Track Pin Soft-Start Pull-
Up Current
TRACK/SS = 0V
(Note 3)
1.2
1.4
60.75
3.6
µA
TRACK/SS
t
Minimum On-Time
100
ns
ON(MIN)
R
Resistor Between V
60.05
0
60.40
kΩ
FBHI
OUT_LCL
and V Pins
FB
Remote Sense Amplifier
+
V
V
,
Common Mode Input
Range
V
= 3.3V, Run > 1.4V, C = 5V
PWR
V
V
OSNS
OSNS CM RANGE
IN
–
V
Maximum DIFF_OUT
Voltage
I
= 300µA
INTV – 1.4
CC
DIFF_OUT(MAX)
DIFF_OUT
+
V
Input Offset Voltage
V
= V
= 1.5V, I = 100µA
DIFF_OUT
2.5
mV
OS
OSNS
DIFF_OUT
4639f
3
For more information www.linear.com/LTM4639
LTM4639
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in
Figure 22.
SYMBOL
PARAMETER
CONDITIONS
(Note 7)
MIN
TYP
1
MAX
UNITS
V/V
A
Differential Gain
Slew Rate
V
SR
(Note 6)
2
V/µs
MHz
dB
GBP
CMRR
Gain Bandwidth Product
(Note 6)
3
Common Mode Rejection (Note 7)
60
I
DIFF_OUT Current
Sourcing
2
mA
DIFF_OUT
PSRR
Power Supply Rejection
Ratio
5V < V < 7V (Note 7)
100
80
dB
IN
C
V
Tracking V
PWR
IN
R
Input Resistance
+ to GND
kΩ
IN
OSNS
PGOOD Output
V
PGOOD Trip Level
V
With Respect to Set Output
FB
FB
PGOOD
FB
V
V
–10
10
%
%
Ramping Negative
Ramping Positive
V
PGOOD Voltage Low
I
= 2mA
0.1
0.3
5.2
V
PGL
PGOOD
INTV Linear Regulator
CC
V
Source Output
5V < V < 7V, C
Tracking V
IN
4.8
4.5
5
2
V
%
INTVCC
IN
PWR
V
V
V
INTV Load Regulation
I
= 0 to 40mA, C
= 5.5V
LDOINT
EXTVCC
LDOEXT
CC
CC
PWR
l
External V Switchover
EXTV Ramping Positive, C
= 5.5V, INTV Output 5V
4.7
75
V
CC
CC
PWR
CC
EXTV Voltage Drop
I
= 25mA, V
= 5V, C = 5.5V
PWR
220
800
mV
CC
CC
EXTVCC
Oscillator and Phase-Locked Loop
f
Frequency Sync Capture
Range
MODE_PLLIN Clock Duty Cycle = 50%
250
kHz
SYNC
f
f
f
I
Nominal Frequency
Lowest Frequency
Highest Frequency
Frequency Set Current
V
V
V
= 1.2V
= 0V
450
210
700
9
500
250
770
10
550
290
850
11
kHz
kHz
kHz
µA
NOM
LOW
HIGH
FREQ
fSET
fSET
fSET
≥ 2.4V
R
MODE_PLLIN Input
Resistance
250
kΩ
MODE_PLLIN
V
V
Clock Input Level High
Clock Input Level Low
2.0
V
V
IH_MODE_PLLIN
IL_MODE_PLLIN
0.8
Temperature Diode
V
TEMP Diode Voltage
I
= 100µA
0.6
–2
V
TEMP
TEMP
l
TC V
Temperature Coefficient
mV/°C
TEMP
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
Note 3: The minimum on-time condition is specified for a peak-to-peak
Note 2: The LTM4639 is tested under pulsed load conditions such that
inductor ripple current of ~40% of I
Information section)
Load. (See the Applications
MAX
T ≈ T . The LTM4639E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4639I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
Note 4: See output current derating curves for different V , V
Note 5: Limit current into the RUN pin to less than 2mA.
Note 6: Guaranteed by design.
Note 7: 100% tested at wafer level.
and T .
A
IN OUT
4639f
4
For more information www.linear.com/LTM4639
LTM4639
TYPICAL PERFORMANCE CHARACTERISTICS
2.5V Input Efficiency Graph
3.3V Efficiency Graph
5V Efficiency Graph
100
95
90
85
80
75
70
100
95
90
85
80
75
70
100
95
90
85
80
75
70
5V TO 3.3V
5V TO 2.5V
5V TO 1.8V
5V TO 1.5V
5V TO 1.2V
5V TO 1V
3.3V TO 2.5V
3.3V TO 1.8V
3.3V TO 1.5V
3.3V TO 1.2V
3.3V TO 1V
2.5V TO 1.8V
2.5V TO 1.5V
2.5V TO 1.2V
2.5V TO 1V
C
= 5V
C
= 5V
C
= V
PWR IN
PWR
PWR
FREQ = 350kHz
FREQ = 400kHz
FREQ = 500kHz
0
6
10 12 14 16 18 20
0
6
10 12 14 16 18 20
0
6
2
4
8
2
4
8
2
4
8
10 12 14 16 18 20
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4637 G01
4639 G02
4639 G03
2.5V to 1V with 7.5A/µs Load
Step, CPWR = 5V
2.5V to 1.2V with 7.5A/µs Load
Step, CPWR = 5V
7V Efficiency Graph
100
95
90
85
80
75
70
V
V
OUT
OUT
V
= 80mV
V
= 80mV
P-P
P-P
LOAD
STEP
0A TO 7.5A
LOAD
STEP
0A TO 7.5A
7V TO 5V
7V TO 3.3V
7V TO 2.5V
7V TO 1.8V
7V TO 1.5V
7V TO 1.2V
7V TO 1V
4639 G05
4639 G06
50µs/DIV
50µs/DIV
C
= V
IN
PWR
FREQ = 550kHz
COMPA CONNECTED TO COMPB
COMPA CONNECTED TO COMPB
C
C
= 180pF, C
= 22pF, C
= 180pF
C
C
= 180pF, C
= 22pF, C
= 180pF
FF
OUT
BOT
COMPA
FF
OUT
BOT
COMPA
0
6
2
4
8
10 12 14 16 18 20
= 100µF CER ×2,
= 100µF CER ×2,
OUTPUT CURRENT (A)
680µF 2.5V 6mΩ POSCAP ×2
680µF 2.5V 6mΩ POSCAP ×2
4639 G03
2.5V to 1.5V with 7.5A/µs Load
Step, CPWR = 5V
3.3V to 1V with 7.5A/µs Load
Step, CPWR = 5V
3.3V to 1.2V with 7.5A/µs Load
Step, CPWR = 5V
V
V
V
OUT
= 80mV
P-P
OUT
OUT
V
=
V
= 80mV
V
P-P
80mV
P-P
LOAD
STEP
0A TO 7.5A
LOAD
STEP
0A TO
7.5A
LOAD
STEP
0A TO 7.5A
4639 G07
4639 G08
4639 G09
50µs/DIV
50µs/DIV
50µs/DIV
COMPA CONNECTED TO COMPB
COMPA CONNECTED TO COMPB
COMPA CONNECTED TO COMPB
C
C
= 180pF, C
= 22pF, C
= 180pF
C
C
= 180pF, C
= 22pF, C
= 180pF
C
C
= 180pF, C
= 22pF, C
= 180pF
FF
OUT
BOT
COMPA
FF
OUT
BOT
COMPA
FF
OUT
BOT
COMPA
= 100µF CER ×2,
= 100µF CER ×2,
= 100µF CER ×2,
680µF 2.5V 6mΩ POSCAP ×2
680µF 2.5V 6mΩ POSCAP ×2
680µF 2.5V 6mΩ POSCAP ×2
4639f
5
For more information www.linear.com/LTM4639
LTM4639
TYPICAL PERFORMANCE CHARACTERISTICS
3.3V to 1.5V with 7.5A/µs Load
Step, CPWR = 5V
5V to 1.8V with 7.5A/µs Load
Step, CPWR = 5V
5V to 3.3V with 7.5A/µs Load
Step, CPWR = 5V
V
V
OUT
= 80mV
P-P
OUT
=
V
V
V
P-P
250mV
P-P
80mV
OUT
V
=
LOAD
STEP
0A TO 7.5A
LOAD
STEP
0A TO
7.5A
LOAD
STEP
0A TO 7.5A
4639 G10
4639 G11
4639 G12
50µs/DIV
50µs/DIV
50µs/DIV
COMPA CONNECTED TO COMPB
COMPA CONNECTED TO COMPB
COMPA CONNECTED TO COMPB
C
C
= 180pF, C
= 22pF, C
= 180pF
C
C
= 180pF, C
= 22pF, C
= 180pF
C
C
= NONE, C
= 22pF, C
= 180pF
FF
OUT
BOT
COMPA
FF
OUT
BOT
COMPA
FF
OUT
BOT
COMPA
= 100µF CER ×2, 680µF 2.5V 6mΩ POSCAP ×2
= 100µF CER ×2, 680µF 2.5V 6mΩ POSCAP ×2
= 47µF CER ×1,
220µF 6.3V 15mΩ POSCAP ×2
7V to 5V with 7.5A/µs Load Step,
CPWR = 5V
Turn-On No Load
Start-Up Pre-Biased Load
SW
OUT
SW
OUT
V
P-P
400mV
OUT
V
=
V
0.5V/DIV
V
0.5V/DIV
LOAD
STEP
0A TO
7.5A
RUN
1V/DIV
RUN
2V/DIV
4639 G13
4639 G14
4639 G15
50µs/DIV
20ms/DIV
20ms/DIV
V
V
I
= 5V
V
V
I
= 5V
COMPA CONNECTED TO COMPB
IN
OUT
IN
= 1V
= 1V, V
= 20A
= 0.5V BIAS
OUT
C
C
= NONE, C
= 22pF, C
= 180pF
OUT
OUT
FF
OUT
BOT
COMPA
= 20A
= 22µF CER ×1,
OUT
150µF 6.3V 15mΩ POSCAP ×2
Recycling VIN (On-Off-On)
Output Short-Circuit
Output Ripple Noise
SW
SW
V
= 8mV
P-P
I
IN
V
OUT
200mA/DIV
0.5V/DIV
V
OUT
0.5V/DIV
RUN
2V/DIV
4639 G17
4639 G18
4639 G16
500µs/DIV
1µs/DIV
1s/DIV
V
V
= 5V
V
V
= 3.3V
= 1V
V
V
= 5V
IN
OUT
IN
OUT
OUT
IN
OUT
= 1V
= 1V
I
= 20A
4639f
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LTM4639
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
OT_TEST (B9): Used for Test Purposes. Float this pin, or
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
tie to V to disable overtemperature protection.
IN
f
(B12): A resistor can be applied from this pin to
SET
V
(A1-A6, B1-B6, C1-C6): Power Input Pins. Apply
IN
ground to set the operating frequency, or a DC voltage
can be applied to set the frequency. See the Applications
Information section.
input voltage between these and GND pins. Recommend
placing input decoupling capacitance directly between
V and GND pins.
IN
TRACK/SS (A9): Output Voltage Tracking Pin and Soft-
Start Inputs. The pin has a 1.2µA pull-up current source. A
capacitor from this pin to ground will set a soft-start ramp
rate. In tracking, the regulator output can be tracked to a
differentvoltage.SeetheApplicationsInformationsection.
V
(J1-J10, K1-K11, L1-L11, M1-M11): Power Output
OUT
Pins. Apply output load between these and GND pins.
Recommend placing output decoupling capacitance
between these pins and GND pins. Review Table 5. Output
range 0.6V to 5.5V.
V
(F12): The Negative Input of the Error Amplifier.
FB
GND (C7, C9, D1-D6, D8, E1-E5, E7, E9, F1-F5, F7-F9,
G1-G9, H1-H9): Power Ground Pins for Both Input and
Output.
Internally, this pin is connected to V
with a
OUT_LCL
60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between V
FB
and ground pins. In PolyPhase® operation, tying the
PGOOD(F11,G12):OutputVoltagePowerGoodIndicator.
Open-drain logic output is pulled to ground when the
output voltage exceeds a 10% regulation window. Both
pins are tied together internally.
V
pins together allows for parallel operation. See the
FB
Applications Information section.
COMPA (A11): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. Tie all
COMP pins together for parallel operation. This pin can
be compensated externally for optimized loop response
or connected to the COMPB pin. See the Applications
Information section.
SGND (G11, H11, H12): Signal Ground Pin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND. See layout
guidelines in Figure 21.
+
TEMP (F6): Temperature Monitor. See Applications In-
formation section.
COMPB (A12): Default Compensation Network
Corresponding to Table 5. Tie this pin to COMPA to use
default compensation. See the Applications Information
section.
–
TEMP (E6): Kelvin Return of the Internal Temperature
Monitor.
MODE_PLLIN (A8): Forced Continuous Mode, Burst
Mode Operation, or Pulse-Skipping Mode Selection Pin
and External Synchronization Input to Phase Detector Pin.
RUN(A10):RunControlPin.Avoltageabove1.4Vwillturn
on the module. A 5.1V Zener diode to ground is internal to
the module for limiting the voltage on the RUN pin to 5V
Connect this pin to INTV to enable pulse-skipping mode.
CC
Connect to ground to enable forced continuous mode.
FloatingthispinwillenableBurstModeoperation.Aclockon
this pin will enable synchronization with forced continuous
operation. See the Applications Information section.
andallowingtheuseofapull-upresistortoV forenabling
IN
the device. Limit current into the RUN pin to ≤ 2mA.
INTV (A7, D9): Internal 5V LDO for Driving the Control
CC
Circuitry and the Power MOSFET Drivers. Both pins are
C
PWR
(B7): Control Bias Input. Required to operate the
LTM4639 regulator below 4.5V input. For V ≥4.5V up to
internally connected. The 5V LDO has a 100mA current
IN
limit. INTV is controlled and enabled when RUN is
CC
7V connect C
sequence V before C
to V . To maintain soft-start function,
PWR
IN
IN
activated high. See Applications Section. This pin is an
, then enable the RUN pin. If
PWR
output, do not drive this pin.
the RUN pin has a pull-up resistor to V , then sequence
IN
C
after V .
PWR
IN
4639f
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LTM4639
PIN FUNCTIONS
+
EXTV (E12): External power input to an internal control
V
(J12): (+) Input to the Remote Sense Amplifier.
OSNS
CC
switchallowsanexternalsourcegreaterthan4.7V,butless
This pin connects to the output remote sense point. The
remote sense amplifier can be used for V
Connect to ground when not used.
than6VtosupplyICpowerandbypasstheinternalINTV
≤ 3.3V.
CC
OUT
LDO. EXTV must be less than V at all times during
CC
IN
power-on and power-off sequences. See the Applications
Informationsection.5Voutputapplicationcanconnectthe
5V output to this pin to improve efficiency. The 5V output
–
V
OSNS
(M12): (–) Input to the Remote Sense Amplifier.
This pin connects to the ground remote sense point. The
remote sense amplifier can be used for V
Connect to ground when not used.
≤ 3.3V.
OUT
is connected to EXTV in the 5V derating curves.
CC
V
(L12): This pin connects to V
through a 1M
OUT_LCL
OUT
DIFF_OUT (K12): Output of the Remote Sense Amplifier.
This pin connects to the V pin for remote sense
applications. Otherwise float when not used. The remote
sense amplifier can be used for V ≤ 3.3V.
resistor,andtoV witha60.4kresistor.Theremotesense
FB
OUT_LCL
amplifier output DIFF_OUT is connected to V
, and
OUT_LCL
drives the 60.4k top feedback resistor in remote sensing
applications. When the remote sense amplifier is used,
OUT
MTP1, MTP2, MTP3, MTP4, MTP5, MTP6, MTP7, (A12,
B11,C10,C11,C12,D10,D11,D12):Extramountingpads
usedforincreasedsolderintegritystrength.Leavefloating.
DIFF_OUT effectively eliminates the 1MΩ from V
to
OUT
V
. When the remote sense amplifier is not used,
OUT_LCL
then connect V
to V
directly.
OUT_LCL
OUT
4639f
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LTM4639
BLOCK DIAGRAM
PTC
OT_TEST
PGOOD
+
–
OTP
~135°C
499k
INTV
CC
+
V
OUT_LCL
V
400mV
OUT
10k
1M
V
IN
> 1.4V = ON
< 1.1V = OFF
MAX = 5V
C
R1
R2
PWR
+5V BIAS
RUN
V
IN
V
IN
2.375V TO 7V
+
5.1V
COMPA
COMPB
+
1.5µF
35V
TEMP
C
IN
60.4k
PNP
M1
–
INTERNAL
COMP
TEMP
0.3µH
V
OUT
V
OUT
1V
47pF
POWER
CONTROL
SGND
20A
+
V
FB
10µF
6.3V
M2
C
OUT
f
SET
R
FB
GND
R
90.9k
fSET
75k
INTERNAL
LOOP
2.2Ω
SGND
FILTER
INTV
CC
C SOFT-START
TRACK/SS
V
V
–
–
MODE_PLLIN
OSNS
+
DIFF
AMP
250k
+
–
+
OSNS
INTV
CC
2.2µF
C
DIFF_OUT
EXTV
CC
4639 F01
Figure 1. Simplified LTM4639 Block Diagram
4639f
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LTM4639
DECOUPLING REQUIREMENTS
TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
IN
External Input Capacitor Requirement
I
= 20A, 4× 22µF Ceramic X7R Capacitors
88
µF
OUT
(V = 2.375V to 7V, V
= 1.5V),
OUT
(See Table 5)
IN
C
≥ 4.5V
PWR
C
External Output Capacitor Requirement
(V = 2.375V to 7V, V = 1.5V),
PWR
I
= 20A (See Table 5)
400
µF
OUT
OUT
IN
OUT
C
≥ 4.5V
OPERATION
Power Module Description
Pulling the RUN pin below 1.1V forces the regulator
into a shutdown state. The TRACK/SS pin is used for
programmingtheoutputvoltagerampandvoltagetracking
during start-up. See the Application Information section.
The LTM4639 is a low input voltage,high performance
single output standalone nonisolated switching mode DC/
DC power supply. It can provide a 20A output with few
externalinputandoutputcapacitors.Thismoduleprovides
precisely regulated output voltages programmable via
The LTM4639 is internally compensated to be stable over
alloperatingconditionswithCOMPAtiedtoCOMPB. Table
5 provides a guideline for input and output capacitances
forseveraloperatingconditions.LTpowerCAD™isavailable
for transient and stability analysis. Custom compensation
can be used with the COMPA pin using the LTpowerCAD
external resistors from 0.6V to 5.5V over a 2.375V
DC
DC
to 7V input range. The typical application schematic is
shown in Figure 22.
TheLTM4639hasanintegratedconstant-frequencycurrent
mode regulator, power MOSFETs, 0.3µH inductor, and
other supporting discrete components. The switching
frequencyrangeisfrom250kHzto770kHz, andthetypical
and an external compensation network. The V pin is
FB
used to program the output voltage with a single external
resistor to ground.
operating frequency is shown in Table 5 for each V . For
Aremotesenseamplifierisprovidedforaccuratelysensing
output voltages ≤3.3V at the load point.
OUT
switchingnoise-sensitiveapplications, itcanbeexternally
synchronizedfrom250kHzto800kHz,subjecttominimum
on-time limitations. A single resistor is used to program
the frequency. See the Applications Information section.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See application examples.
With current mode control and internal feedback loop
compensation, the LTM4639 module has sufficient
stability margins and good transient performance with
a wide range of output capacitors, even with all ceramic
output capacitors.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE_PLLIN
pin. These light load features will accommodate battery
operation. Efficiency graphs are provided for light load
operation in the Typical Performance Characteristics
section.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltage in the event of an
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
+
–
A TEMP and TEMP pin is provided to allow the internal
device temperature to be monitored using an onboard
diode connected PNP transistor. This diode connected
PNP transistor can be used with TEMP monitor devices
like the LTC2990, LTC2997, LTC2974 and LTC2978.
Overtemperature protection will turn off the regulator’s
RUNpinat~130°Cto137°C.SeeApplicationsInformation.
4639f
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LTM4639
APPLICATIONS INFORMATION
The typical LTM4639 application circuit is shown in Fig-
ure 22. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 5 for specific external capacitor
requirements for particular applications.
Input Capacitors
The LTM4639 module should be connected to a low AC-
impedance DC source. Additional input capacitors are
neededfortheRMSinputripplecurrentrating.TheI
CIN(RMS)
equation which follows can be used to calculate the input
capacitor requirement. Typically 22µF X7R ceramics are a
good choice with RMS ripple current ratings of ~ 2A each.
A47µFto100µFsurfacemountaluminumelectrolyticbulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedanceiscompromisedbylonginductiveleads,traces
ornotenoughsourcecapacitance.Iflowimpedancepower
planes are used, then this bulk capacitor is not needed.
V to V
IN
Step-Down Ratios
OUT
There are restrictions in the V to V
step-down ratio
IN
OUT
that can be achieved for a given input voltage. The duty
cycle is 94% typical at 500kHz operation. The V to V
IN
OUT
minimumdropoutisafunctionofloadcurrentandoperation
at very low input voltage and high duty cycle applications.
At very low duty cycles the minimum 100ns on-time must
be maintained. See the Frequency Adjustment section and
temperature derating curves.
For a buck converter, the switching duty cycle can be
estimated as:
Output Voltage Programming
V
VIN
OUT
D=
The PWM controller has an internal 0.6V 1% reference
voltage. As shown in the Block Diagram, a 60.4k internal
Without considering the inductor ripple current, for each
output the RMS current of the input capacitor can be
estimated as:
feedback resistor connects the V
and V pins
OUT_LCL
FB
together. When the remote sense amplifier is used, then
DIFF_OUT is connected to the V pin. If the remote
OUT_LCL
sense amplifier is not used, then V
connects to
IOUT(MAX)
OUT_LCL
ICIN(RMS)
=
• D•(1–D)
V
. The output voltage will default to 0.6V with no
OUT
η%
feedbackresistor.AddingaresistorR fromV toground
FB
FB
whereη%istheestimatedefficiencyofthepowermodule.
The bulk capacitor can be a switcher-rated aluminum
electrolytic capacitor or a Polymer capacitor.
programs the output voltage:
60.4k+RFB
VOUT = 0.6V •
RFB
Output Capacitors
Table 1. VFB Resistor Table vs Various Output Voltages
(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3
Open 90.9 60.4 40.2 30.1 19.1 13.3 8.25
The LTM4639 is designed for low output voltage ripple
V
5.0
OUT
noise. The bulk output capacitors defined as C
are
OUT
R
(k)
chosen with low enough effective series resistance
FB
(ESR) to meet the output voltage ripple and transient
requirements. C
can be a low ESR tantalum capacitor,
OUT
For parallel operation of N LTM4639s, the following
low ESR Polymer capacitor or ceramic capacitors. The
typical output capacitance range is from 200µF to 800µF.
Additional output filtering may be required by the system
designer if further reduction of output ripple or dynamic
transient spikes is required. Table 5 shows a matrix
of different output voltages and output capacitors to
minimizethevoltagedroopandovershootduringa10A/µs
transient.ThetableoptimizestotalequivalentESRandtotal
bulk capacitance to optimize the transient performance.
equation can be used to solve for R :
FB
60.4k /N
RFB=
V
OUT
–1
0.6V
Tie the V pins together for each parallel output. The
FB
COMP pins must be tied together also.
4639f
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LTM4639
APPLICATIONS INFORMATION
Stability criteria are considered in the Table 5 matrix, and
LTpowerCAD is available for stability analysis and custom
compensationforloopoptimizationusingtheCOMPApin.
Multiphase operation will reduce effective output ripple
as a function of the number of phases. Application Note
77 discusses this noise reduction versus output ripple
current cancellation, but the output capacitance should be
consideredcarefullyasafunctionofstabilityandtransient
response.LTpowerCADcanbeusedtocalculatetheoutput
ripple reduction as the number of implemented phases
increase by N times.
operation. With pulse-skipping mode at light load, the
internalcurrentcomparatormayremaintrippedforseveral
cycles, thus skipping operation cycles. This mode has
lower ripple than Burst Mode operation and maintains a
higher frequency operation than Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to ground. In this
mode, inductor current is allowed to reverse during low
outputloads,theCOMPAvoltageisincontrolofthecurrent
comparator threshold throughout, and the top MOSFET
alwaysturnsonwitheachoscillatorpulse.Duringstart-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4639’s output
voltage is in regulation.
Burst Mode Operation
TheLTM4639iscapableofBurstModeoperationinwhich
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enableBurstModeoperation,simplyfloattheMODE_PLLIN
pin. During Burst Mode operation, the peak current of the
inductorissettoapproximately30%ofthemaximumpeak
current value in normal operation even though the voltage
at the COMPA pin indicates a lower value. The voltage at
the COMPA pin drops when theinductor’s average current
isgreaterthantheloadrequirement.AstheCOMPAvoltage
drops below 0.5V, the burst comparator trips, causing
the internal sleep line to go high and turn off both power
MOSFETs.
Multiphase Operation
For outputs that demand more than 20A of load current,
multiple LTM4639 devices can be paralleled to provide
more output current without increasing input and output
ripple voltage. The MODE_PLLIN pin allows the LTM4639
to be synchronized to an external clock and the internal
phase-locked loop allows the LTM4639 to lock onto input
clockphaseaswell.Thef resistorisselectedfornormal
SET
frequency, then the incoming clock can synchronize
the device over the specified range. See Figure 24 for a
synchronizing example circuit.
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMPA to rise, the internal
sleep line goes low, and the LTM4639 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors.TheRMSinputripplecurrentisreducedby,and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used. See Application Note 77.
Pulse-Skipping Mode Operation
In applications where low output ripple and high effi-
ciency at intermediate currents are desired, pulse-
skipping mode should be used. Pulse-skipping operation
allows the LTM4639 to skip cycles at low output loads,
thusincreasingefficiencybyreducingswitchingloss.Tying
The LTM4639 device is an inherently current mode
controlled device, so parallel modules will have good
current sharing. This will balance the thermals in the
the MODE_PLLIN pin to INTV enables pulse-skipping
design. Tie the COMPA and V pins of each LTM4639
CC
FB
4639f
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LTM4639
APPLICATIONS INFORMATION
together to share the current evenly. Figure 24 shows a
schematic of the parallel design.
The relationship of f voltage to switching frequency is
SET
shown in Figure 3. For low output voltages from 0.6V to
1.2V, 300kHz operation is an optimal frequency for the
best power conversion efficiency while maintaining the
inductor current to about 40% to 50% of maximum load
current. For output voltages from 1.5V to 1.8V, 450kHz
is optimal. For output voltages from 2.5V to 5V, 600kHz
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current
cancellation mathematical derivations are presented, and
a graph is displayed representing the RMS ripple current
reductionasafunctionofthenumberofinterleavedphases
(see Figure 2).
900
800
700
600
500
400
300
200
100
0
PLL, Frequency Adjustment and Synchronization
TheLTM4639switchingfrequencyissetbyaresistor(R
from the f pin to signal ground. A 10µA current (I
)
)
fSET
FREQ
SET
flowingoutofthef pinthroughR
developsavoltage
SET
fSET
on f . R
can be calculated as:
SET fSET
0
0.5
1
1.5
2
2.5
f
PIN VOLTAGE (V)
4639 F03
SET
FREQ
500kHz / V
1
RfSET
=
+0.2V
10µA
Figure 3. Relationship Between Switching
Frequency and Voltage at the fSET Pin
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
1 PHASE
2 PHASE
3 PHASE
4 PHASE
6 PHASE
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
4639 F02
OUT IN
Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Siꢁ µModule Regulators (Phases)
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LTM4639
APPLICATIONS INFORMATION
is optimal. See efficiency graphs for optimal frequency
set point.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4639 uses an
accurate 60.4k resistor internally for the top feedback
resistor.Figure4showsanexampleofcoincidenttracking.
The LTM4639 can be synchronized from 250kHz to
800kHz with an input clock that has a high level above 2V
and a low level below 0.8V. See the Typical Applications
section for synchronization examples. The LTM4639
minimum on-time is limited to approximately 100ns.
Guardband the on-time to 110ns. The on-time can be
calculated as:
1
V
OUT
60.4k
RTA
tON(MIN)
=
•
VOUT(SLAVE) = 1+
• V
TRACK
FREQ
VIN
+5V BIAS
14µF
2.2µF
V
IN
3.3V
C
IN1
22µF
16V
×4
SOFT-START
CAPACITOR
V
C
EXTV INTV PGOOD
IN PWR
CC
CC
V
1.5V
20A
OUT2
COMPA
COMPB
TRACK/SS
RUN
V
OUT
OUT_LCL
R2
5k
C11
100µF
6.3V
×2
C8
+
C
SS
180pF
V
680µF
2.5V
×2
DIFF_OUT
+
LTM4639
180pF
V
OSNS
f
SET
–
V
R4
100k
OSNS
MODE_PLLIN
V
+
FB
TEMP
R
FB1
22pF
–
TEMP
SGND
GND OT_TEST
40.2k
2.2µF
V
IN
+5V BIAS
3.3V
C
IN2
MASTER RAMP
OR OUTPUT
22µF
16V
×4
180pF
V
C
EXTV INTV PGOOD
IN PWR
CC
CC
V
1.2V
20A
OUT1
COMPA
COMPB
TRACK/SS
RUN
V
OUT
OUT_LCL
R
C6
TB
C4
R
+
R1
5k
TA
60.4k
100µF
6.3V
×2
V
680µF
2.5V
×2
60.4k
DIFF_OUT
+
LTM4639
180pF
V
OSNS
f
SET
–
V
OSNS
R3
100k
MODE_PLLIN
V
FB
+
TEMP
R
FB
22pF
–
SGND
GND OT_TEST
TEMP
60.4k
4639 F04
Figure 4. Dual Outputs (1.5V and 1.2V) with Tracking
4639f
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LTM4639
APPLICATIONS INFORMATION
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in volts/time. When coincident
V
TRACK
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.6V, or the internal
TRACK
V
tracking is desired, then MR and SR are equal, thus R
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue
to its final value from the slave’s regulation point (see
TB
is equal to 60.4k. R is derived from equation:
TA
0.6V
RTA=
VFB VFB VTRACK
+
–
Figure 5). Voltage tracking is disabled when V
is
60.4k RFB
RTB
TRACK
more than 0.6V. R in Figure 4 will be equal to R for
TA
FB
whereV isthefeedbackvoltagereferenceoftheregulator,
FB
TRACK
coincident tracking.
and V
is 0.6V. Since R is equal to the 60.4k top
TB
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R is equal to R with V
=
FB
TA
FB
MASTER OUTPUT
SLAVE OUTPUT
V
.ThereforeR =60.4k,andR =60.4kinFigure4.
TRACK
TB TA
OUTPUT
VOLTAGE
Inratiometrictracking, adifferentslewratemaybedesired
for the slave regulator. R can be solved for when SR
TB
is slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach its final value before the master output.
4639 F05
TIME
For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then R
TB
= 75k. Solve for R to equal 51.1k.
Figure 5. Output Voltage Coincident Tracking Characteristics
TA
For applications that do not require tracking or
The TRACK/SS pin of the master can be controlled by an
externalramporthesoft-startfunctionofthatregulatorcan
be used to develop that master ramp. The LTM4639 can
be used as a master by setting the ramp rate on its track
pin using a soft-start capacitor. A 1.2µA current source
is used to charge the soft-start capacitor. The following
equation can be used:
sequencing, simply tie the TRACK/SS pin to INTV to
CC
let RUN control the turn on/off. When the RUN pin is
below its threshold or the V undervoltage lockout, then
IN
TRACK/SS is pulled low.
Overcurrent and Overvoltage Protection
The LTM4639 has overcurrent protection (OCP) in a
short circuit. The internal current comparator threshold
folds back during a short to reduce the output current. An
overvoltage condition (OVP) above 10% of the regulated
outputvoltagewillforcethetopMOSFEToffandthebottom
MOSFETonuntiltheconditioniscleared.Foldbackcurrent
limiting is disabled during soft-start or tracking start-up.
CSS
1.2µA
tSOFT-START = 0.6V •
Ratiometric tracking can be achieved by a few simple
calculationsandtheslewratevalueappliedtothemaster’s
TRACK/SS pin. As mentioned above, the TRACK/SS pin
has a control range from 0V to 0.6V. The master’s
TRACK/SS pin slew rate is directly equal to the master’s
output slew rate in volts/time. The equation:
MR
SR
•60.4k=RTB
4639f
15
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LTM4639
APPLICATIONS INFORMATION
Temperature Monitoring
temperature sensors. The I term in the equation above
S
is the extrapolated current through a diode junction when
Measuring the absolute temperature of a diode is possible
due to the relationship between current, voltage and
temperature described by the classic diode equation:
the diode has zero volts across the terminals. The I term
S
varies from process to process, varies with temperature,
and by definition must always be less than I . Combining
D
all of the constants into one term:
VD
η• V
I =I • e
D
S
T
η•k
q
KD =
or
I
IS
−5
VD = η• VT •ln D
whereK =8.62 ,andknowingln(I /I )isalwayspositive
D
D S
because I is always greater than I , leaves us with the
D
S
equation that:
where I is the diode current, V is the diode voltage, η is
D
D
the ideality factor (typically close to 1.0) and I (saturation
S
I
IS
VD = T(KELVIN)•KD •ln D
current) is a process dependent parameter. V can be
T
broken out to:
where V appears to increase with temperature. It is
k • T
q
D
VT =
common knowledge that a silicon diode biased with a
current source has an approximate –2mV/°C temperature
relationship (Figure 6), which is at odds with the equation.
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. V is
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable
Infact,theI termincreaseswithtemperature,reducingthe
S
T
ln(I /I ) absolute value yielding an approximate –2mV/°C
D S
composite diode voltage slope.
1.0
0.8
I
I
= 100µA
= 10µA
D
D
∆V
D
0.6
0.4
–173
–73
27
127
TEMPERATURE (°C)
4639 F06
Figure 6. Diode Voltage VD vs Temperature T(°C)
for Different Bias Currents
4639f
16
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LTM4639
APPLICATIONS INFORMATION
To obtain a linear voltage proportional to temperature,
Run Enable
we cancel the I variable in the natural logarithm term to
S
The RUN pin is used to enable the power module or
sequence the power module. The threshold is 1.25V, and
the pin has an internal 5.1V Zener to protect the pin. The
RUN pin can be used as an undervoltage lockout (UVLO)
function by connecting a resistor divider from the input
supply to the RUN pin:
remove the I dependency from the following equation.
S
This is accomplished by measuring the diode voltage at
two currents I , and I , where I = 10 • I
1
2
1
2
Subtracting we get:
I2
IS
I1
IS
∆VD = T(KELVIN)•KD •In −T(KELVIN)•KD •In
V
UVLO
= ((R1+R2)/R2) • 1.25V
Combining like terms, then simplifying the natural log
terms yields:
See Figure 1, Simplified Block Diagram.
INTV Regulator
CC
∆V = T(KELVIN) • K • In(10)
D
D
The LTM4639 has an internal low dropout regulator from
and redefining constant
V
called INTV . This regulator output has a 2.2µF
IN
CC
ceramic capacitor internal. An additional 2.2µF ceramic
capacitor is needed on this pin to ground. This regulator
powers the internal controller and MOSFET drivers. The
gate driver current is ~20mA for 750kHz operation. The
regulator loss can be calculated as:
K’ = K • In(10) = 198µV/k
D
D
yields
∆V = K’ • T(KELVIN)
D
D
Solving for temperature:
(V – 5V) • 20mA = P
IN
LOSS
∆VD
K'D
T(KELVIN)=
,
EXTV external voltage source ≥ 4.7V can be applied to
CC
thispintoeliminatetheinternalINTV LDOpowerlossand
CC
T(KELVIN)=[°C]+273.15,
[°C]= T(KELVIN)−273.15
increase regulator efficiency. A 5V supply can be applied
to run the internal circuitry and power MOSFET driver. If
unused, leave pin floating. EXTV must be less than V
CC
IN
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198µV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
at all times during power-on and power-off sequences.
Stability Compensation
TheLTM4639hasalreadybeeninternallycompensatedfor
alloutputvoltages.Table5isprovidedformostapplication
requirements. LTpowerCAD is available for other control
loop optimization.
+
–
The diode connected PNP transistor at the TEMP , TEMP
pins can be used to monitor the internal temperature of
the LTM4639. A general temperature monitor can be
+
–
implemented by connecting a resistor between TEMP
Thermal Considerations and Output Current Derating
and V to set the current to 100µA, grounding the TEMP
IN
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those
parametersdefinedbyJESD51-12andareintendedforuse
withfiniteelementanalysis(FEA)softwaremodelingtools
thatleveragetheoutcomeofthermalmodeling,simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients
in found in JESD51-12 (“Guidelines for Reporting and
pin, and then monitoring the diode voltage drop with
temperature. A more accurate temperature monitor can
be achieved with a circuit injecting two currents that are
at a 10:1 ratio. See Figure 22 for an example.
Overtemperature Protection
The internal overtemperature protection monitors the
internal temperature of the module and shuts off the
regulator at ~130°C to 137°C. Once the regulator cools
down the regulator will restart.
Using Electronic Package Thermal Information”).
4639f
17
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LTM4639
APPLICATIONS INFORMATION
Manydesignersmayopttouselaboratoryequipmentanda
testvehiclesuchasthedemoboardtopredicttheµModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
sectionare, inandofthemselves, notrelevanttoproviding
guidance of thermal performance; instead, the derating
curves provided in this data sheet can be used in a
manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
4 θ , the thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
where almost all of the heat flows through the bottom
oftheµModulepackageandintotheboard, andisreally
the sum of the θ
and the thermal resistance of
JCbottom
the bottom of the part through the solder joints and a
portionoftheboard.Theboardtemperatureismeasured
a specified distance from the package.
A graphical representation of the aforementioned thermal
resistances is given in Figure 7; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
ThePinConfigurationsectiongivesfourthermalcoefficients
explicitly defined in JESD51-12; these coefficients are
quoted or paraphrased below:
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operatingconditionsofaµModuleregulator. Forexample,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through
bottom of the µModule package—as the standard defines
1 θ , the thermal resistance from junction to ambient,
JA
is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure.Thisenvironmentissometimesreferredtoas
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
for θ
and θ
, respectively. In practice, power
JCtop
JCbottom
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
2 θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through
the bottom of the package. In the typical µModule
regulator, the bulk of the heat flows out the bottom of
the package, but there is always heat flow out into the
ambientenvironment.Asaresult,thisthermalresistance
valuemaybeusefulforcomparingpackagesbutthetest
conditionsdon’tgenerallymatchtheuser’sapplication.
Within the LTM4639, be aware there are multiple power
devices and components dissipating power, with a
consequence that the thermal resistances relative to
different junctions of components or die are not exactly
linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometryoftheLTM4639andthespecifiedPCBwithallof
thecorrectmaterialcoefficientsalongwithaccuratepower
losssourcedefinitions;(2)thismodelsimulatesasoftware-
defined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
3 θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
4639f
18
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LTM4639
APPLICATIONS INFORMATION
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4639 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
processandduediligenceyieldsthesetofderatingcurves
shown in this data sheet.
ambient temperature at ~40°C. The output voltages are
1V, 2.5V and 5V. These are chosen to include the lower,
middle and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived
from several temperature measurements in a controlled
temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambienttemperatureisincreasedwithandwithoutairflow.
Thepowerlossincreasewithambienttemperaturechange
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
currentorpowerwithincreasingambienttemperature.The
decreasedoutputcurrentwilldecreasetheinternalmodule
loss as ambient temperature is increased. The monitored
junctiontemperatureof120°Cminustheambientoperating
temperaturespecifieshowmuchmoduletemperaturerise
canbeallowed,asanexample,inFigure13 theloadcurrent
is derated to ~17A at ~80°C with no air or heat sink and
the power loss for the 7V to 1.0V at 17A output is about
4.2W. The 4.2W loss is calculated with the ~3W room
The 1V, 2.5V and 5V power loss curves in Figures 8 to 10
can be used in coordination with the load current derating
curves in Figures 11 to 20 for calculating an approximate
θ
JA
thermal resistance for the LTM4639 with various
heat sinking and airflow conditions. The power loss
curves are taken at room temperature and are increased
with a multiplicative factor according to the junction
temperature, which is 1.4 for 120°C. The derating curves
are plotted with the output current starting at 20A and the
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4639 F07
µMODULE DEVICE
Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients
4639f
19
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
temperature loss from the 7V to 1.0V power loss curve at
17A, and the 1.4 multiplying factor at 120°C junction. If the
80°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 40°C divided
calculatedpowerlossasafunctionofambienttemperature
to derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss
can be derived from the efficiency curves in the Typical
Performance Characteristics section and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit boardisa1.6mm thickfour layerboardwith
two ounce copper for the two outer layers and one ounce
copper for the two inner layers. The PCB dimensions are
by 4.2W equals a 9.5°C/W θ thermal resistance. Table
JA
2 specifies a 10°C/W value which is very close. Table 2
through Table 4 provides equivalent thermal resistances
for 1.0V, 2.5V and 5V outputs with and without airflow and
heat sinking. The derived thermal resistances in Tables 2
thru 4 for the various conditions can be multiplied by the
95mm × 76mm. The BGA heat sinks are listed
in Table 6.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
7V TO 5V POWER LOSS
3.3V TO 1.8V POWER LOSS
3.3V TO 1.5V POWER LOSS
3.3V TO 1.2V POWER LOSS
3.3V TO 1V POWER LOSS
5V TO 3.3V POWER LOSS
7V TO 3.3V POWER LOSS
7V TO 2.5V POWER LOSS
7V TO 1.8V POWER LOSS
7V TO 1.5V POWER LOSS
7V TO 1.2V POWER LOSS
7V TO 1V POWER LOSS
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V TO 2.5V POWER LOSS
5V TO 1.8V POWER LOSS
5V TO 1.5V POWER LOSS
5V TO 1.2V POWER LOSS
5V TO 1V POWER LOSS
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4639 F08
4639 F09
4639 F10
Figure 10. 7V Input Power Loss Curves
Figure 9. 5V Input Power Loss Curves
Figure 8. 3.3V Input Power Loss Curves
25
25
20
25
20
15
20
15
15
10
10
5
10
5
5
0 LFM
200 LFM
400 LFM
0 LFM
0 LFM
200 LFM
400 LFM
200 LFM
400 LFM
0
0
0
0
20
40
60
80 100 120 140
0
20
40
60
80
100
120
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4639 F12
4639 F11
4639 F13
Figure 11. 5VIN to 1.0VOUT No Heat Sink
Figure 13. 7VIN to 1.0VOUT No Heat Sink
Figure 12. 5VIN to 1.0VOUT with Heat Sink
4639f
20
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LTM4639
APPLICATIONS INFORMATION
25
25
25
20
20
20
15
15
15
10
5
10
5
10
5
0 LFM
0 LFM
0 LFM
200 LFM
400 LFM
200 LFM
400 LFM
200 LFM
400 LFM
0
0
0
0
20
40
60
80 100 120 140
0
20
40
60
80 100 120 140
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4639 F14
4639 F15
4639 F16
Figure 14. 7VIN to 1.0VOUT with Heat Sink
Figure 15. 5VIN to 2.5VOUT No Heat Sink Figure 16. 5VIN to 2.5VOUT with Heat Sink
25
20
25
20
15
10
15
10
5
0
5
0
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0
20
40
60
80 100 120 140
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
4639 F17
4639 F18
Figure 17. 7VIN to 2.5VOUT No Heat Sink
Figure 18. 7VIN to 2.5VOUT with Heat Sink
25
20
25
20
15
10
15
10
5
0
5
0
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0
20
40
60
80 100 120 140
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
4639 F19
4639 F20
Figure 19. 7VIN to 5VOUT No Heat Sink,
EXTVCC = 5V, CPWR = 7V
Figure 20. 7VIN to 5VOUT with Heat Sink,
EXTVCC = 5V, CPWR = 7V
4639f
21
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LTM4639
APPLICATIONS INFORMATION
Table 2. 1V Output
DERATING
CURVE
POWER LOSS
AIRFLOW
(LFM)
V
CURVE
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
HEAT SINK
None
θ
JA
(°C/W)
IN
Figures 11, 13
Figures 11, 13
Figures 11, 13
Figures 12, 14
Figures 12, 14
Figures 12, 14
5V, 7V
5V, 7V
5V, 7V
5V, 7V
5V, 7V
5V, 7V
0
10
8
200
400
0
None
None
7
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
9
200
400
6.5
5.5
Table 3. 2.5V Output
DERATING
CURVE
POWER LOSS
CURVE
AIRFLOW
(LFM)
V
HEAT SINK
None
θ
JA
(°C/W)
12
IN
Figures 15, 17
Figures 15, 17
Figures 15, 17
Figures 16, 18
Figures 16, 18
Figures 16, 18
5V, 7V
5V, 7V
5V, 7V
5V, 7V
5V, 7V
5V, 7V
Figure 9
Figure 9
Figure 9
Figure 9
Figure 9
Figure 9
0
200
400
0
None
11
None
10
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
10.5
9.5
8
200
400
Table 4. 5V Output (5V Output Connected to EXTVCC Pin)
DERATING
CURVE
POWER LOSS
CURVE
AIRFLOW
(LFM)
V
HEAT SINK
None
θ
JA
(°C/W)
IN
Figures 19
Figures 19
Figures 19
Figures 20
Figures 20
Figures 20
7V
7V
7V
7V
7V
7V
Figure 10
Figure 10
Figure 10
Figure 10
Figure 10
Figure 10
0
12
11
10
10.5
8
200
400
0
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
200
400
7
4639f
22
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LTM4639
APPLICATIONS INFORMATION
Table 5*. Output Voltage Response vs Component Matriꢁ (Refer to Figure 22). Typical Measured Values
C
AND C
C
AND C
OUT1
OUT2
OUT1 OUT2
CERAMIC VENDORS
VALUE
PART NUMBER
C3216X7S0J226M
BULK VENDORS
Sanyo POSCAP
Panasonic
VALUE
PART NUMBER
2R5TPF680M6L
EEFCXOG221ER
10TBF150M
TDK
22µF, 6.3V
22µF, 10V
47µF, 10V
100µF, 6.3V
100µF, 6.3V
100µF, 6.3V
680µF, 2.5V
220µF, 4V
150µF, 10V
Murata
Murata
TDK
GRM31CR61C226KE15L
GRM31CR61A476KE15L
C4532X5R0J107MZ
GRM32ER60J107M
18126D107MAT
Sanyo POSCAP
C
BULK VENDOR
VALUE
PART NUMBER
Murata
AVX
IN
Sanyo
100µF, 16V
16SVP100M
Standard Internal Compensation COMPA and COMPB Tied Together
PEAK-TO-
FREQ (kHz)
C
PEAK
RECOVERY LOAD
TRACK
OUT2
V
C
C
IN
C
(CERAMIC
C
C
BOT
C
V
DROOP DEVIATION
TIME
(µs)
STEP
R
V 2.5V,
IN
(A/µs) (kΩ) 3.3V,5V,7V
OUT
IN
OUT1
FF
COMPA
(pF)
IN
FB
*
(V) (CERAMIC) (BULK) (CERAMIC) AND BULK) (pF) (pF)
(V)
(mV)
(mV)
1
22µF × 4
22µF × 4
22µF × 4
22µF × 4
22µF × 4
100µF
100µF
100µF
100µF
100µF
100µF × 2 680µF × 2 180 22
100µF × 2 680µF × 2 180 22
100µF × 2 680µF × 2 180 22
100µF × 2 680µF × 2 180 22
180 2.5, 3.3,
5, 7
180 2.5, 3.3,
5, 7
180 2.5, 3.3,
5, 7
180 2.5, 3.3,
5, 7
34
72
34
34
34
34
24
7.5
7.5
7.5
7.5
7.5
90.9
60.4
40.2
30.1
19.1
350, 400,
500, 500
350, 400,
500, 500
350, 400,
500, 500
350, 400,
500, 500
1.2
1.5
1.8
2.5
37
37
72
80
38
80
47µF
220µF
-
22
180
3.3,
5, 7
111
225
400, 500,
550
3.3
5
22µF × 4
22µF × 4
100µF
100µF
22µF
22µF
150µF
150µF
-
-
22
22
180
180
5,7
7
150
187
300
370
24
24
7.5
7.5
13.3
8.25
500, 550
550
*
Bulk capacitance is optional if V has very low input impedance.
IN
Additional Bulk Capacitance may be required for ≤ 3.3V input
Depends on Source Impedance
4639f
23
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LTM4639
APPLICATIONS INFORMATION
Table 6*. Output Voltage Response vs Component Matriꢁ (Refer to Figure 22). Typical Measured Values
C
AND C
OUT2
OUT1
CERAMIC VENDORS
VALUE
PART NUMBER
GRM31CR60G227M
GRM31CR61A476KE15L
Murata
220µF, 4V
47µF, 10V
Murata
LTpowerCAD Can Be Used to Optimize the Control Loop Response. Eꢁamples Are Shown Using Ceramic Only for High Performance
Transient Response
PEAK-TO-
PEAK
FREQ (kHz)
TRACK
2.5V,
C
REC. LOAD
OUT2
V
C
C
C
(CER &
C
FF
C
R
C
C
V
DROOP DEVIATION TIME STEP
R
FB
V
IN
OUT
IN
IN
OUT1
BOT
S
S
P
IN
*
(V) (CERAMIC) (BULK)
(CER) BULK) (pF) (pF)
(k)
(pF) (pF) (V) (mV)
(mV)
(µs) (A/µs) (kΩ) 3.3V,5V,7V
1
22µF × 4
22µF × 4
22µF × 4
22µF × 4
100µF 200µF
× 6
-
-
-
-
68
68
68
68
22
22
22
22
20
1200 100 2.5,
40
43
60
64
80
24
24
24
28
7.5
7.5
7.5
7.5
90.9
60.4
40.2
30.1
350, 400,
500, 500
3.3,
5, 7
1.2
1.5
1.8
100µF 200µF
× 6
20
20
20
1200 100 2.5,
88
350, 400,
500, 500
3.3,
5, 7
100µF 200µF
× 4
1200 100 2.5,
122
130
350, 400,
500, 500
3.3,
5, 7
100µF 200µF
× 4
1200 100 2.5,
350, 400,
500, 500
3.3,
5, 7
2.5
3.3
5
22µF × 4
22µF × 4
22µF × 4
100µF
100µF
100µF
47µF
× 2
47µF
× 2
47µF
× 2
-
-
-
47
47
-
22
22
22
4
4
4
4700
4700
4700
47 3.3,
5, 7
179
219
250
320
400
500
33
33
24
5
5
5
19.1
13.3
8.25
400, 500,
550
500, 550
47
5,7
47
7
550
*
Bulk capacitance is optional if V has very low input impedance.
IN
Additional Bulk Capacitance may be required for ≤ 3.3V input
Depends on Source Impedance
Table 7. Recommended Heat Sinks
HEAT SINK MANUFACTURER
AAVID Thermalloy
PART NUMBER
WEBSITE
375424B00034G
www.aavidthermalloy.com
www.coolinnovations.com
Cool Innovations
4-050503P to 4-050508P
4639f
24
For more information www.linear.com/LTM4639
LTM4639
APPLICATIONS INFORMATION
Safety Considerations
• Use large PCB copper areas for high current paths,
including V , GND and V . It helps to minimize the
IN
OUT
TheLTM4639doesnotprovidegalvanicisolationfromV
IN
PCB conduction loss and thermal stress.
to V . There is no internal fuse. If required, a slow blow
OUT
fuse with a rating twice the maximum input current needs
• Place high frequency ceramic input and output
tobeprovidedtoprotecteachunitfromcatastrophicfailure.
capacitors next to the V , GND and V
pins to
IN
OUT
minimize high frequency noise.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET
fails, then turning it off will not resolve the overvoltage,
thus the internal bottom MOSFET will turn on indefinitely
trying to protect the load. Under this fault condition, the
input voltage will source very large currents to ground
throughthefailedinternaltopMOSFETandenabledinternal
bottomMOSFET. Thiscancauseexcessiveheatandboard
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can be
used as a secondary fault protector in this situation. The
LTM4639doessupportovervoltageprotection,overcurrent
protection and overtemperature protection.
• Place a dedicated power ground layer underneath the
unit.
• To minimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped or plated over.
• Place test points on signal pins for testing.
• Use a separated SGND ground copper area for
components connected to signal pins. Connect the
SGND to GND underneath the unit.
• For parallel modules, tie the COMP and V pins
FB
Layout Checklist/Eꢁample
together. Use an internal layer to closely connect these
pins together.
The high integration of the LTM4639 makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout
considerations are still necessary.
Figure21givesagoodexampleoftherecommendedlayout.
C
CONTROL
PWR
C1
V
IN
COMPA COMPB
A1
C
C
IN
IN
OT_TEST
PGND
–
+
TEMP
TEMP
SIGNAL
GROUND
C
C
OUT
OUT
V
OUT
V
OUT
4639 F21
Figure 21. Recommended PCB Layout
4639f
25
For more information www.linear.com/LTM4639
LTM4639
TYPICAL APPLICATIONS
INTV
+5V BIAS
CC
V
IN
2.2µF
2.375V TO 7V
1µF
C
IN
22µF
25V
×4
180pF*
C7
INTV
CC
V
C
EXTV INTV PGOOD
0.1µF
IN PWR
CC
CC
V
CC
V
1.5V
20A
OUT
R1
10k
+
–
COMPA
COMPB
TRACK/SS
RUN
1.8V
D
D
V
V
REF
OUT
OUT_LCL
0.1µF
LTC2997
+
C
*
C
*
OUT1
OUT2
V
470pF
680µF
2.5V
×2
100µF
6.3V
×2
C
*
FF
DIFF_OUT
+
V
4mV/K
R3
LTM4639
180pF
PTAT
GND
V
OSNS
f
SET
–
V
OSNS
MODE_PLLIN
CONTINUOUS
MODE
100k
V
FB
C30*
22pF
+
R
*
FB
TEMP
40.2k
–
TEMP
SGND
GND OT_TEST
*SEE TABLE 5
4639 F22
Figure 22. 2.375V to 7VIN, 1.5V at 20A Design
4639f
26
For more information www.linear.com/LTM4639
LTM4639
TYPICAL APPLICATIONS
4639f
27
For more information www.linear.com/LTM4639
LTM4639
TYPICAL APPLICATIONS
2.2µF
+5V BIAS
V
IN
3.3V TO 7V
+
C20
22µF
16V
C22
22µF
16V
INTV
220µF
6.3V
CC
V
OUT
180pF
V
C
EXTV INTV
CC
1.2V AT 80A
PGOOD
IN PWR
CC
V
R1
10k
COMPA
COMPB
TRACK/SS
RUN
C28
0.22µF
V
OUT
C24
100µF
6.3V
×2
OUT_LCL
C21
680µF
2.5V
×2
+
DIFF_OUT
+
LTM4639
470pF
V
OSNS
f
SET
–
V
OSNS
V
MODE_PLLIN
+
75k
FB
TEMP
R
–
INTV
FB2 22pF
15k
CC
TEMP
SGND
GND OT_TEST
R2
143k
4-PHASE CLOCK
+
SET
V
2.2µF
LTC6902
C2
1µF
+5V BIAS
MOD
GND
DIV
PH
C14
22µF
16V
C18
22µF
16V
22µF
25V
V
C
EXTV INTV
PGOOD
IN PWR
CC
CC
COMPA
COMPB
TRACK/SS
RUN
OUT4
OUT3
OUT1
OUT2
V
OUT
OUT_LCL
C15
C18
100µF
6.3V
×2
V
+
680µF
2.5V
×2
DIFF_OUT
+
LTM4639
350kHz
V
OSNS
f
SET
–
V
OSNS
V
MODE_PLLIN
+
75k
75k
75k
FB
TEMP
–
TEMP
SGND
GND OT_TEST
2.2µF
+5V BIAS
C7
22µF
16V
C9
22µF
16V
V
C
EXTV INTV
PGOOD
IN PWR
CC
CC
COMPA
COMPB
TRACK/SS
RUN
V
OUT
OUT_LCL
C8
C11
100µF
6.3V
×2
V
+
680µF
2.5V
×2
DIFF_OUT
+
LTM4639
V
OSNS
f
SET
–
V
OSNS
V
MODE_PLLIN
+
FB
TEMP
–
TEMP
SGND
GND OT_TEST
2.2µF
+5V BIAS
C3
22µF
16V
C1
22µF
16V
22µF
25V
V
C
EXTV INTV
PGOOD
IN PWR
CC
CC
COMPA
COMPB
TRACK/SS
RUN
V
OUT
OUT_LCL
C4
C6
V
+
680µF
2.5V
×2
100µF
6.3V
×2
DIFF_OUT
+
LTM4639
V
OSNS
f
SET
–
V
OSNS
V
MODE_PLLIN
+
FB
TEMP
–
TEMP
SGND
GND OT_TEST
4639 F24
Figure 24. 1.2V, 80A, Current Sharing with 4-Phase Operation
4639f
28
For more information www.linear.com/LTM4639
LTM4639
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Pin Assignment Table (Arranged by Pin Number)
PIN ID
A1
FUNCTION
PIN ID
B1
FUNCTION
PIN ID
C1
FUNCTION
PIN ID
D1
FUNCTION PIN ID FUNCTION
PIN ID
F1
FUNCTION
GND
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
V
V
V
V
V
V
V
V
V
V
V
GND
GND
GND
GND
GND
GND
–
E1
E2
GND
GND
GND
GND
GND
TEMP
GND
–
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
A2
B2
C2
D2
F2
GND
A3
B3
C3
D3
E3
F3
GND
A4
B4
C4
D4
E4
F4
GND
A5
B5
C5
D5
E5
F5
GND
–
+
A6
B6
C6
D6
E6
F6
TEMP
A7
INTV
B7
C
PWR
C7
GND
–
D7
E7
F7
GND
GND
GND
–
CC
A8
MODE_PLLIN
TRACK/SS
RUN
B8
–
C8
D8
GND
E8
F8
A9
B9
OT_TEST
–
C9
GND
MTP2
MTP3
MTP4
D9
INTV
E9
GND
–
F9
CC
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
MTP5
MTP6
MTP7
E10
E11
E12
F10
F11
F12
COMPA
MTP1
–
PGOOD
COMPB
f
EXTV
V
FB
SET
CC
PIN ID
G1
FUNCTION
GND
PIN ID
H1
FUNCTION
GND
GND
GND
GND
GND
GND
GND
GND
GND
–
PIN ID
J1
FUNCTION
PIN ID
K1
FUNCTION PIN ID FUNCTION
PIN ID
M1
FUNCTION
V
V
V
V
V
V
V
V
V
V
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
L1
L2
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
G2
GND
H2
J2
K2
M2
G3
GND
H3
J3
K3
L3
M3
G4
GND
H4
J4
K4
L4
M4
G5
GND
H5
J5
K5
L5
M5
G6
GND
H6
J6
K6
L6
M6
G7
GND
H7
J7
K7
L7
M7
G8
GND
H8
J8
K8
L8
M8
G9
GND
H9
J9
K9
L9
M9
G10
G11
G12
–
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
OUT
SGND
PGOOD
SGND
SGND
–
V
+
OSNS
DIFF_OUT
V
V
–
OSNS
OUT_LCL
4639f
29
For more information www.linear.com/LTM4639
LTM4639
PACKAGE PHOTO
2.2µF
V
IN
7V
22µF
10V
×4
C
COMPA
V
C
EXTV INTV PGOOD
IN PWR
CC
CC
V
180pF
OUT
5V
COMPA
COMPB
TRACK/SS
RUN
V
OUT
OUT_LCL
20A
0.1µF
V
5k
+
22µF
6.3V
150µF
6.3V
DIFF_OUT
+
LTM4639
V
OSNS
f
SET
–
V
OSNS
140k
MODE_PLLIN
V
FB
+
TEMP
C
R
BOT
FB
–
TEMP
SGND
GND OT_TEST
22pF
8.25k
4639 F25
Figure 25. 7VIN, 5V at 20A Design
4639f
30
For more information www.linear.com/LTM4639
LTM4639
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
/ / b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
a a a
Z
4639f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentation
31
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM4639
TYPICAL APPLICATION
1.8V at 20A Design with Input Current and Temperature Monitoring
C
IN
R
22µF
25V
×4
S
C
P
20k
100pF
V
C
EXTV INTV PGOOD
IN PWR
CC
CC
V
C
OUT
S
1.8V
1200pF
COMPA
COMPB
TRACK/SS
RUN
V
OUT
OUT_LCL
C7
0.1µF
C4
AT 20A
R1
5k
V
220µF
6.3V
X5R
×6
10mΩ
MEASURE I
0.1µF
IN
+5V INPUT
DIFF_OUT
+
C
FF
LTM4639
68pF
V
OSNS
f
V
V1
V2
SET
CC
–
R3
CONTINUOUS MODE
V
OSNS
V
2-WIRE
MODE_PLLIN
SDA
SCL
125k
2
I C
LTC2990
FB
+
C
22pF
TEMP
INTERFACE
BOT
R
V3
V4
FB
–
ADR0
TEMP
SGND
GND OT_TEST
30.1k
470pF
ADR1 GND
4639 TA02
MEASURE TEMP
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4637
Higher V Range Than the LTM4639
4.5V ≤ V ≤ 20V, 20A
IN
IN
LTM4611
Lower V Range Than the LTM4639
1.5V ≤ V ≤ 5.5V,15A, Auxiliary V
Not Required
IN
IN
BIAS
LTM4644
Quad Output, 4A Each
Triple Output, 4A, 4A, 1.5A
Dual Output, 8A Each
2.375V ≤ V ≤ 14V, Low V Required Auxiliary V
, Current Share to 16A
IN
IN
BIAS
LTM4615
2.375V ≤ V ≤ 5.5V, Auxiliary V
Not Required
IN
BIAS
LTM4616
2.7V ≤ V ≤ 5.5V, Current Share to 16A, Auxiliary V
Not Required
IN
BIAS
LTM4608A
Lower I
and Smaller Package Than the LTM4639
2.7V ≤ V ≤ 5.5V, 8A, 9mm × 15mm × 2.8mm
IN
OUT
4639f
LT 0914 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4639
●
●
LINEAR TECHNOLOGY CORPORATION 2014
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