LTM4630EY#PBF_技术文档

LTM4630

Dual 18A or Single 36A

DC/DC µModule Regulator

FEATURES

DESCRIPTION

n

Dual 18A or Single 36A Output

TheLTM^®4630isadual18Aorsingle36Aoutputswitching

modestep-downDC/DCµModule^®(micromodule)regula-

tor. Included in the package are the switching controllers,

power FETs, inductors, and all supporting components.

Operating from an input voltage range of 4.5V to 15V, the

LTM4630supportstwooutputseachwithanoutputvoltage

range of 0.6V to 1.8V, each set by a single external resistor.

Its high efﬁciency design delivers up to 18A continuous

current for each output. Only a few input and output ca-

pacitors are needed. The LTM4630 is pin compatible with

the LTM4620 and LTM4620A (dual 13A, single 26A) and

the LTM4628 (dual 8A, single 16A).

n

Wide Input Voltage Range: 4.5V to 15V

n

Output Voltage Range: 0.6V to 1.8V

n

1.5ꢀ ꢁaꢂiꢃuꢃ ꢄotal DC Output Error Over Line,

Load and ꢄeꢃperature

Differential Reꢃote Sense Aꢃpliﬁer

n

Current ꢁode Control/Fast ꢄransient Response

n

Adjustable Switching Frequency

Overcurrent Foldback Protection

n

ꢁultiphase Parallel Current Sharing with ꢁultiple

Lꢄꢁ4630s Up to 144A

n

Frequency Synchronization

n

Internal ꢄeꢃperature ꢁonitor

The device supports frequency synchronization, multi-

phaseoperation,BurstModeoperationandoutputvoltage

tracking for supply rail sequencing and has an onboard

temperaturediodefordevicetemperaturemonitoring.High

switchingfrequencyandacurrentmodearchitectureenable

a very fast transient response to line and load changes

without sacriﬁcing stability.

n

Pin Compatible with the LTM4620 and LTM4620A (Dual

13A, Single 26A) and LTM4628 (Dual 8A, Single 16A)

Selectable Burst Mode^®Operation

n

Soft-Start/Voltage Tracking

Output Overvoltage Protection

16mm × 16mm × 4.41mm LGA and 16mm × 16mm ×

5.01mm BGA Packages

n

Fault protection features include overvoltage and

overcurrent protection. The LTM4630 is offered in 16mm

× 16mm × 4.41mm LGA and 16mm × 16mm × 5.01mm

BGA packages. The LTM4630 is ROHS compliant.

L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are

registered trademarks of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620,

6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending.

APPLICATIONS

n

Telecom and Networking Equipment

n

Storage and ATCA Cards

n

Industrial Equipment

TYPICAL APPLICATION

36A, 1.2V Output DC/DC µꢁodule Regulator

INTV

CC

1.2V_OUꢄEfﬁciency vs I_OUꢄ

4.7µF

10k

PGOOD

95

90

85

80

75

70

65

MODE_PLLIN CLKOUT INTV

EXTV

PGOOD1

CC

V

= 5V

CC

IN

V

IN

4.5V TO 15V

V

IN

V

OUT1

+

22µF

25V

×4

100µF

6.3V

470µF

6.3V

TEMP

V

OUTS1

10k

120k

V

= 12V

IN

RUN1

DIFFOUT

RUN2

SW1

TRACK1

TRACK2

V

FB1

FB2

LTM4630

5.1V

60.4k

f

0.1µF

COMP1

COMP2

SET

PHASMD

V

OUTS2

V

1.2V

36A

OUT

V

121k

OUT2

SW2

100µF

6.3V

0

2

4

6

8

10 12 14 16 18

OUTPUT CURRENT (A)

470µF

6.3V

PGOOD2

SGND

GND

DIFFP

DIFFN

4630 TA01b

PGOOD

4630 TA01a

4630fa

1

For more information www.linear.com/LTM4630

LTM4630

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

V (Note 8) ............................................... –0.3V to 16V

SW1 SW2

DIFFP, DIFFN.......................................... –0.3V to INTV

IN

V

CC

, V

................................................... –1V to 16V

COMP1, COMP2, V , V (Note 6)........ –0.3V to 2.7V

FB1 FB2

PGOOD1, PGOOD2, RUN1, RUN2,

INTV Peak Output Current ................................100mA

Internal Operating Temperature Range

(Note 2) ............................................. –40°C to 125°C

Storage Temperature Range................... –55°C to 125°C

Peak Package Body Temperature .......................... 245°C

CC

INTV , EXTV ........................................... –0.3V to 6V

CC

MODE_PLLIN, f , TRACK1, TRACK2,

SET

DIFFOUT, PHASMD................................ –0.3V to INTV

CC

V

, V

(Note 6)........ –0.3V to 6V

OUT1 OUT2 OUTS1 OUTS2

PIN CONFIGURATION

TOP VIEW

TEMP

EXTV

CC

TEMP

EXTV

CC

M

L

M

L

V

IN

K

J

K

J

H

G

F

INTV

SW2

PGOOD1

PGOOD2

RUN2

CC

CLKOUT

SW1

H

G

F

INTV

SW2

PGOOD1

PGOOD2

RUN2

CC

CLKOUT

SW1

PHASMD

RUN1

SGND

PHASMD

RUN1

SGND

MODE_PLLIN

DIFFOUT

MODE_PLLIN

GND

COMP1 COMP2

DIFFOUT

GND

COMP1 COMP2

DIFFP

E

DIFFP

DIFFN

E

TRACK1

V

TRACK2

GND

DIFFN

SGND FB2

TRACK1

V

TRACK2

SGND FB2

GND

V

FB1

D

C

B

A

V

FB1

D

C

B

A

V

f

SGND OUTS2

SET

V

f

SGND OUTS2

SET

V

OUTS1

V

OUTS1

V

OUT1

OUT2

GND

V

OUT2

GND

1

2

3

4

5

6

7

8

9

10

11

12

1

2

3

4

5

6

7

8

9

10

11

12

LGA PACKAGE

144-LEAD (16mm × 16mm × 4.41mm)

BGA PACKAGE

144-LEAD (16mm × 16mm × 4.41mm)

T

JMAX

= 125°C, Θ = 7°C/W, Θ

= 1.5°C/W, Θ

= 3.7°C/W, Θ + Θ ≅ 7°C/W

JA

JCbottom

JCtop JB JBA

T

JMAX

= 125°C, Θ = 7°C/W, Θ

= 1.5°C/W, Θ

= 3.7°C/W, Θ + Θ ≅ 7°C/W

JA

JCbottom

JCtop

JB

JBA

Θ VALUES DEFINED PER JESD 51-12

WEIGHT = 3.2g

ORDER INFORMATION

PARꢄ ꢁARKING*

PACKAGE

ꢄYPE

ꢁSL

RAꢄING

ꢄEꢁPERAꢄURE RANGE

(Note 2)

PARꢄ NUꢁBER

LTM4630EV#PBF

LTM4630IV#PBF

LTM4630EY#PBF

LTM4630IY#PBF

LTM4630IY

PAD OR BALL FINISH

Au (RoHS)

DEVICE

FINISH CODE

LTM4630V

LTM4630Y

e4

e1

e0

LGA

BGA

3

–40°C to 125°C

Au (RoHS)

SAC305 (RoHS)

SnPb (63/37)

Consult Marketing for parts speciﬁed with wider operating temperature

ranges. *Device temperature grade is indicated by a label on the shipping

container. Pad or ball ﬁnish code is per IPC/JEDEC J-STD-609.

• Recommended LGA and BGA PCB Assembly and Manufacturing

Procedures:

www.linear.com/umodule/pcbassembly

• LGA and BGA Package and Tray Drawings:

www.linear.com/packaging

• Terminal Finish Part Marking:

www.linear.com/leadfree

4630fa

2

For more information www.linear.com/LTM4630

LTM4630

ELECTRICAL CHARACTERISTICS ^ꢄhel denotes the speciﬁcations which apply over the speciﬁed internal

operating teꢃperature range. Speciﬁed as each individual output channel. ꢄ_A= 25°C (Note 2), V_IN= 12V and V_RUN1, V_RUN2at 5V

unless otherwise noted. Per the typical application in Figure 23.

SYꢁBOL

PARAꢁEꢄER

CONDIꢄIONS

ꢁIN

4.5

ꢄYP

ꢁAX

15

UNIꢄS

l

V

Input DC Voltage

Output Voltage

V

IN

0.6

1.8

OUT

V

,

Output Voltage, Total Variation with

Line and Load

1.477

1.5

1.523

C

= 22µF × 3, C

= 100µF × 1 Ceramic,

OUT1(DC)

OUT2(DC)

IN

OUT

470µF POSCAP

= 12V, V

V

IN

= 1.5V, I

= 0A to 18A

OUT

Input Speciﬁcations

V

, V

RUN Pin On/Off Threshold

RUN Pin On Hysteresis

RUN Rising

1.1

1.25

150

1

1.40

V

mV

A

RUN1 RUN2

, V

RUN1HYS RUN2HYS

I

Input Inrush Current at Start-Up

I

= 0A, C = 22µF ×3, C = 0.01µF,

OUT

= 12V

INRUSH(VIN)

OUT

C

V

IN

SS

= 100µF ×3, V

= 1.5V, V

= 1.5V,

OUT2

OUT1

IN

I

Input Supply Bias Current

Input Supply Current

V

= 12V, V

= 1.5V, Burst Mode Operation

= 1.5V, Pulse-Skipping Mode

3

mA

µA

Q(VIN)

IN

OUT

15

65

50

= 12V, V = 1.5V, Switching Continuous

OUT

Shutdown, RUN = 0, V = 12V

IN

I

V

IN

V

IN

= 5V, V

= 1.5V, I = 18A

OUT

6

2.6

A

S(VIN)

OUT

= 12V, V

= 1.5V, I

= 18A

OUT

Output Speciﬁcations

, I

I

Output Continuous Current Range

Line Regulation Accuracy

V

= 12V, V

= 1.5V (Note 7)

0

18

A

OUT1(DC) OUT2(DC)

IN

OUT

l

ΔV

/V

= 1.5V, V from 4.5V to 15V

0.01

0.5

15

0.025

%/V

OUT1(LINE) OUT1

OUT

IN

/V

I

= 0A for Each Output,

OUT

OUT2(LINE) OUT2

ΔV

/V

Load Regulation Accuracy

Output Ripple Voltage

For Each Output, V

V = 12V (Note 7)

IN

= 1.5V, 0A to 18A

0.75

%

OUT1 OUT1

OUT

/V

OUT2 OUT2

V

, V

For Each Output, I

= 0A, C

= 100µF ×3/

IN

mV

P-P

OUT1(AC) OUT2(AC)

OUT

X7R/Ceramic, 470µF POSCAP, V = 12V,

V

OUT

= 1.5V, Frequency = 450kHz

f (Each Channel)

Output Ripple Voltage Frequency

SYNC Capture Range

V

IN

= 12V, V

= 1.5V, f = 1.25V (Note 4)

500

kHz

S

OUT

SET

f

400

780

SYNC

(Each Channel)

ΔV

Turn-On Overshoot

Turn-On Time

C

V

= 100µF/X5R/Ceramic, 470µF POSCAP,

10

5

mV

ms

OUTSTART

OUT

(Each Channel)

= 1.5V, I

= 0A V = 12V

OUT IN

t

C

OUT

= 100µF/X5R/Ceramic, 470µF POSCAP,

START

(Each Channel)

No Load, TRACK/SS with 0.01µF to GND,

V

= 12V

IN

ΔV

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load

30

mV

OUT(LS)

(Each Channel)

C

= 22µF ×3/X5R/Ceramic, 470µF POSCAP

OUT

V

= 12V, V

= 1.5V

OUT

IN

t

Settling Time for Dynamic Load

Step

Load: 0% to 50% to 0% of Full Load,

20

30

µs

A

SETTLE

(Each Channel)

V

= 12V, C

= 100µF, 470µF POSCAP

IN

OUT

I

Output Current Limit

V

IN

= 12V, V

= 1.5V

OUT(PK)

OUT

(Each Channel)

Control Section

l

V

, V

Voltage at V Pins

I

= 0A, V = 1.5V

OUT

0.592

0.600

–5

0.606

–20

V

nA

V

FB1 FB2

FB

OUT

I

FB

(Note 6)

V

OVL

Feedback Overvoltage Lockout

0.64

1

0.66

1.25

0.68

1.5

TRACK1 (I),

TRACK2 (I)

Track Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V

µA

4630fa

3

For more information www.linear.com/LTM4630

LTM4630

ELECTRICAL CHARACTERISTICS ^ꢄhel denotes the speciﬁcations which apply over the speciﬁed internal

operating teꢃperature range. Speciﬁed as each individual output channel. ꢄ_A= 25°C (Note 2), V_IN= 12V and VRUN1, VRUN2 at 5V

unless otherwise noted. Per the typical application in Figure 23.

SYꢁBOL

PARAꢁEꢄER

CONDIꢄIONS

ꢁIN

ꢄYP

3.3

ꢁAX

UNIꢄS

V

UVLO

Undervoltage Lockout (Falling)

UVLO Hysteresis

0.6

V

t

Minimum On-Time

(Note 6)

90

ns

ON(MIN)

R

, R

Resistor Between V

, V

60.05

60.4

60.75

0.3

5

kΩ

FBHI1 FBHI2

OUTS1 OUTS2

and V , V Pins for Each Output

FB1 FB2

V

, V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

V

PGOOD1 PGOOD2

PGOOD

Low

I

PGOOD Leakage Current

PGOOD Trip Level

V

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PGOOD

FB

–10

10

%

INꢄV Linear Regulator

CC

V

Internal V Voltage

6V < V < 15V

4.8

4.5

5

5.2

2

V

INTVCC

CC

IN

V

INTV Load Regulation

I

CC

= 0mA to 50mA

0.5

%

INTVCC

CC

Load Regulation

V

EXTV Switchover Voltage

EXTV Ramping Positive

4.7

50

V

mV

EXTVCC

CC

EXTV Dropout

I

CC

= 20mA, V = 5V

EXTVCC

100

EXTVCC(DROP)

EXTVCC(HYST)

CC

EXTV Hysteresis

220

CC

Oscillator and Phase-Locked Loop

Frequency Nominal Nominal Frequency

f

= 1.2V

450

210

700

9

500

250

780

10

550

290

860

11

kHz

µA

SET

Frequency Low

Frequency High

Lowest Frequency

= 0V (Note 5)

> 2.4V, Up to INTV

Highest Frequency

CC

f

Frequency Set Current

MODE_PLLIN Input Resistance

SET

R

250

kΩ

MODE_PLLIN

CLKOUT

Phase (Relative to V

)

PHASMD = GND

PHASMD = Float

PHASMD = INTV

60

90

120

Deg

OUT1

CC

CLK High

CLK Low

Clock High Output Voltage

Clock Low Output Voltage

2

V

0.2

Differential Aꢃpliﬁer

A Differential

Gain

1

V/V

V

Ampliﬁer

R

Input Resistance

Measured at DIFFP Input

= V = 1.5V, I = 100µA

DIFFOUT

80

kΩ

mV

dB

IN

V

OS

Input Offset Voltage

V

DIFFP

3

DIFFOUT

PSRR Differential

Ampliﬁer

Power Supply Rejection Ratio

5V < V < 15V

90

3

IN

I

CL

Maximum Output Current

Maximum Output Voltage

Gain Bandwidth Product

Diode Connected PNP

Temperature Coefﬁcient

mA

V

I

= 300µA

INTV – 1.4

CC

OUT(MAX)

DIFFOUT

GBW

3

MHz

V

TEMP

I = 100µA

0.6

l

TC

–2.2

mV/C

4630fa

4

For more information www.linear.com/LTM4630

LTM4630

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: Two outputs are tested separately and the same testing condition

is applied to each output.

Note 4: The switching frequency is programmable from 400kHz to 750kHz.

Note 5: LTM4630 device is designed to operate from 400kHz to 750kHz

Note 6: These parameters are tested at wafer sort.

Note 2: The LTM4630 is tested under pulsed load conditions such that

T ≈ T . The LTM4630E is guaranteed to meet speciﬁcations from

J

A

Note 7: See output current derating curves for different V , V

and T .

A

IN OUT

0°C to 125°C internal temperature. Speciﬁcations over the –40°C to

125°C internal operating temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTM4630I is guaranteed over the full –40°C to 125°C internal operating

temperature range. Note that the maximum ambient temperature

consistent with these speciﬁcations is determined by speciﬁc operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors.

TYPICAL PERFORMANCE CHARACTERISTICS

Dual Phase Single Output Efﬁciency

vs Output Current, V_IN= 12V,

f_S= 450kHz

Efﬁciency vs Output Current,

V_IN= 5V, f_S= 450kHz

Efﬁciency vs Output Current,

V_IN= 12V, f_S= 450kHz

95

90

85

80

75

70

65

95

90

85

80

75

70

65

100

95

90

85

80

75

V

= 1V

V

= 1V

OUT

V

= 1V

OUT

V

= 1.2V

= 1.5V

= 1.8V

V

= 1.2V

= 1.5V

= 1.8V

= 1.2V

= 1.5V

= 1.8V

V

0

2

4

6

8

10 12 14 16 18

0

5

10 15 20 25 30 35 40

LOAD CURRENT (A)

0

2

4

6

8

10 12 14 16 18

LOAD CURRENT (A)

4630 G02

4630 G03

4630 G01

Burst ꢁode and Pulse-Skip ꢁode

Efﬁciency V_IN=12V, V_OUꢄ= 1.2V,

f_S= 450kHz

1V Single Phase Output Load

ꢄransient Response

1.2V Single Phase Output Load

ꢄransient Response

100

90

80

70

60

50

40

30

CCM

Burst Mode OPERATION

PULSE-SKIP MODE

V

OUT(AC)

50mV/Div

LOAD STEP

2A/DIV

LOAD STEP

2A/DIV

4630 G05

4630 G06

20µs/DIV

12V , 1V , 450kHz, 4.5A LOAD STEP,

12V , 1.2V , 450kHz, 4.5A LOAD STEP,

IN

OUT

IN

OUT

4.5A/µs STEP-UP AND STEP-DOWN

= 1 • 470µF 4V POSCAP + 1 • 100µF

4.5A/µs STEP-UP AND STEP-DOWN

C = 1 • 470µF 4V POSCAP + 1 • 100µF

OUT

0.01

0.1

1

10

C

OUT

LOAD CURRENT (A)

6.3V CERAMIC

4630 G04

4630fa

5

For more information www.linear.com/LTM4630

LTM4630

TYPICAL PERFORMANCE CHARACTERISTICS

1.5V Single Phase Output Load

ꢄransient Response

1.8V Single Phase Output Load

ꢄransient Response

Single Phase Start-Up with No load

V

SW

10V/Div

OUT(AC)

50mV/Div

V

OUT

0.5V/Div

LOAD STEP

2A/DIV

LOAD STEP

2A/DIV

I

IN

0.2A/Div

4630 G07

4630 G08

4630 G09

20µs/DIV

20ms/DIV

12V , 1.5V , 450kHz, 4.5A LOAD STEP,

12V , 1.8V , 450kHz, 4.5A LOAD STEP,

12V , 1.2V , 450kHz

IN

OUT

IN

OUT

IN

OUT

4.5A/µs STEP-UP AND STEP-DOWN

C

= 1 • 470µF 4V POSCAP + 1 • 100µF

OUT

C

OUT

= 1 • 470µF 4V POSCAP + 1 • 100µF

C

OUT

= 1 • 470µF 4V POSCAP + 1 • 100µF

6.3V CERAMIC, C = 0.1µF

SS

6.3V CERAMIC

Single Phase Short Circuit

Protection with 18A

Single Phase Short Circuit

Protection with No load

Single Phase Start-up with 18A

V

SW

V

SW

10V/Div

V

OUT

V

OUT

0.5V/Div

V

OUT

0.5V/Div

I

IN

1A/Div

IN

1A/Div

4630 G10

4630 G11

4630 G12

20ms/DIV

12V , 1.2V , 450kHz

50µs/DIV

12V , 1.2V , 450kHz

50µs/DIV

12V , 1.2V , 450kHz

IN OUT

C = 1 • 470µF 4V POSCAP + 1 • 100µF

OUT

IN

OUT

IN

OUT

6.3V CERAMIC

OUT

C

= 1 • 470µF 4V POSCAP + 1 • 100µF

C

= 1 • 470µF 4V POSCAP + 1 • 100µF

OUT

6.3V CERAMIC, C = 0.1µF

6.3V CERAMIC

SS

4630fa

6

For more information www.linear.com/LTM4630

LTM4630

(Recoꢃꢃended to Use ꢄest Points to ꢁonitor Signal Pin Connections.)

PIN FUNCTIONS

PACKAGE ROW AND COLUꢁN LABELING ꢁAY VARY

AꢁONG µꢁodule PRODUCꢄS. REVIEW EACH PACKAGE

LAYOUꢄ CAREFULLY.

V

(A1-A5, B1-B5, C1-C4): Power Output Pins. Apply

V

, V (D5, D7): The Negative Input of the Error

FB2

OUꢄ1

FB1

outputloadbetweenthesepinsandGNDpins.Recommend

placing output decoupling capacitance directly between

these pins and GND pins. Review Table 4. See Note 8 in

the Electrical Characteristics section for output current

guideline.

Ampliﬁer for Each Channel. Internally, this pin is con-

nected to V

or V

with a 60.4kΩ precision

OUTS1

OUTS2

resistor. Different output voltages can be programmed

with an additional resistor between V and GND pins. In

FB

PolyPhase^®operation, tying the V pins together allows

FB

for parallel operation. See the Applications Information

section for details.

GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12,

F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1,

J5, J8, J12, K1, K5-K8, K12, L1, L12, ꢁ1 , ꢁ12): Power

Ground Pins for Both Input and Output Returns.

ꢄRACK1, ꢄRACK2 (E5, D8): Output Voltage Tracking Pin

and Soft-Start Inputs. Each channel has a 1.3µA pull-up

current source. When one channel is conﬁgured to be

master of the two channels, then a capacitor from this pin

to ground will set a soft-start ramp rate. The remaining

channel can be set up as the slave, and have the master’s

output applied through a voltage divider to the slave

output’s track pin. This voltage divider is equal to the

slave output’s feedback divider for coincidental tracking.

See the Applications Information section.

V

(A8-A12, B8-B12, C9-C12): Power Output Pins.

OUꢄ2

Apply output load between these pins and GND pins.

Recommend placing output decoupling capacitance di-

rectly between these pins and GND pins. Review Table 4.

See Note 8 in the Electrical Characteristics section for

output current guideline.

V

, V

(C5, C8): This pin is connected to the top

OUꢄS1 OUꢄS2

of the internal top feedback resistor for each output. The

pin can be directly connected to its speciﬁc output, or

connected to DIFFOUT when the remote sense ampliﬁer

COꢁP1, COꢁP2 (E6, E7): Current control threshold and

error ampliﬁer compensation point for each channel. The

current comparator threshold increases with this control

voltage. Tie the COMP pins together for parallel operation.

The device is internal compensated.

is used. In paralleling modules, one of the V

pins is

OUTS

connectedtotheDIFFOUTpininremotesensingordirectly

to V with no remote sensing. It is very important to

OUT

connect these pins to either the DIFFOUT or V

since

DIFFP (E8): Positive input of the remote sense ampliﬁer.

Thispinisconnectedtotheremotesensepointoftheoutput

voltage. See the Applications Information section.

OUT

this is the feedback path, and cannot be left open. See the

Applications Information section.

f

(C6): Frequency Set Pin. A 10µA current is sourced

DIFFN (E9): Negative input of the remote sense ampliﬁer.

This pin is connected to the remote sense point of the

output GND. See the Applications Information section.

SEꢄ

from this pin. A resistor from this pin to ground sets a

voltage that in turn programs the operating frequency.

Alternatively, this pin can be driven with a DC voltage

that can set the operating frequency. See the Applications

Information section.

ꢁODE_PLLIN (F4): Force Continuous Mode, Burst Mode

Operation, or Pulse-Skipping Mode Selection Pin and

External Synchronization Input to Phase Detector Pin.

Connect this pin to SGND to force both channels into

SGND(C7, D6, G6-G7, F6-F7):SignalGroundPin. Return

ground path for all analog and low power circuitry. Tie a

single connection to the output capacitor GND in the ap-

plication. See layout guidelines in Figure 22.

force continuous mode of operation. Connect to INTV

CC

to enable pulse-skipping mode of operation. Leaving the

pin ﬂoating will enable Burst Mode operation. A clock on

the pin will force both channels into continuous mode of

operation and synchronized to the external clock applied

to this pin.

4630fa

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For more information www.linear.com/LTM4630

LTM4630

PIN FUNCTIONS ^{(Recoꢃꢃended to Use ꢄest Points to ꢁonitor Signal Pin Connections.)}

RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above

1.25V will turn on each channel in the module. A voltage

below 1.25V on the RUN pin will turn off the related chan-

nel. Each RUN pin has a 1µA pull-up current, once the

RUN pin reaches 1.2V an additional 4.5µA pull-up current

is added to this pin.

PGOOD1, PGOOD2 (G9, G8): Output Voltage Power

Good Indicator. Open drain logic output that is pulled to

ground when the output voltage is not within 10% of

the regulation point.

INꢄV (H8): Internal 5V Regulator Output. The control

CC

circuits and internal gate drivers are powered from this

DIFFOUꢄ (F8): Internal Remote Sense Ampliﬁer Output.

voltage. Decouple this pin to PGND with a 4.7µF low ESR

Connect this pin to V

or V

depending on which

tantalumorceramic.INTV isactivatedwheneitherRUN1

OUTS1

OUTS2

CC

outputisusingremotesense.Inparalleloperationconnect

one of the V pin to DIFFOUT for remote sensing.

or RUN2 is activated.

OUTS

ꢄEꢁP (J6): Onboard General Purpose Temperature Diode

for Monitoring the VBE Junction Voltage Change with

Temperature. See the Applications Information section.

SW1, SW2 (G2, G11): Switching node of each channel

that is used for testing purposes. Also an R-C snubber

network can be applied to reduce or eliminate switch node

ringing, or otherwise leave ﬂoating. See the Applications

Information section.

EXꢄV (J7): External power input that is enabled through

CC

a switch to INTV whenever EXTV is greater than 4.7V.

CC

Do not exceed 6V on this input, and connect this pin to

V when operating V on 5V. An efﬁciency increase will

PHASꢁD(G4):ConnectthispintoSGND,INTV ,orﬂoat-

CC

IN

ing this pin to select the phase of CLKOUT to 60 degrees,

occur that is a function of the (V – INTV ) multiplied by

IN

CC

120 degrees, and 90 degrees respectively.

powerMOSFETdrivercurrent.Typicalcurrentrequirement

is 30mA. V must be applied before EXTV , and EXTV

CC

IN

CC

CLKOUꢄ (G5): Clock output with phase control using the

PHASMD pin to enable multiphase operation between

devices. See the Applications Information section.

must be removed before V .

IN

V (ꢁ2-ꢁ11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):

IN

Power Input Pins. Apply input voltage between these pins

and GND pins. Recommend placing input decoupling

capacitance directly between V pins and GND pins.

IN

4630fa

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For more information www.linear.com/LTM4630

LTM4630

SIMPLIFIED BLOCK DIAGRAM

PGOOD1

V

IN

4.5V TO 15V

TRACK1

SS CAP

V

IN

C

22µF

25V

C

IN1

IN2

0.1µF

22µF

25V

GND

R

T

V

R

TEMP

CLKOUT

RUN1

IN

= 100µA

V

IN

MTOP1

MBOT1

T

SW1

V

OR TEMP

MONITORS

0.33µH

V

OUT1

1.5V

+

18A

MODE_PLLIN

PHASEMD

0.22µF

C

OUT1

GND

V

OUTS1

COMP1

60.4k

V

FB1

INTERNAL

COMP

R

FB1

40.2k

SGND

POWER

CONTROL

PGOOD2

TRACK2

V

IN

INTV

CC

C

22µF

25V

C

22µF

25V

IN3

IN4

SS CAP

0.1µF

4.7µF

EXTV

GND

SW2

CC

MTOP2

MBOT2

0.33µH

V

1.2V

18A

OUT2

V

OUT2

+

RUN2

0.22µF

C

OUT2

GND

V

OUTS2

60.4k

COMP2

V

FB2

+

–

R

FB2

INTERNAL

COMP

60.4k

f

SET

INTERNAL

FILTER

R

FSET

SGND

DIFFOUT

DIFFN

DIFFP

4630 BD

Figure 1. Siꢃpliﬁed Lꢄꢁ4630 Block Diagraꢃ

ꢄ_A= 25°C. Use Figure 1 conﬁguration.

CONDIꢄIONS

DECOUPLING REQUIREMENTS

SYꢁBOL

PARAꢁEꢄER

ꢁIN

ꢄYP

ꢁAX

UNIꢄS

External Input Capacitor Requirement

C

(V = 4.5V to 15V, V

= 1.5V)

= 1.2V)

I

= 18A

44

µF

IN1, IN2

IN1

OUT1

OUT2

OUT1

OUT2

C

(V = 4.5V to 15V, V

IN2

IN3, IN4

External Output Capacitor Requirement

C

(V = 4.5V to 15V, V

= 1.5V)

= 1.2V)

I

= 18A

400

µF

OUT1

OUT2

IN1

OUT1

OUT2

OUT1

OUT2

(V = 4.5V to 15V, V

IN2

4630fa

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For more information www.linear.com/LTM4630

LTM4630

OPERATION

Power ꢁodule Description

used for soft-starting the regulator. See the Applications

Information section.

The LTM4630 is a dual-output standalone nonisolated

switching mode DC/DC power supply. It can provide two

18A outputs with few external input and output capacitors

and setup components. This module provides precisely

regulated output voltages programmable via external

TheLTM4630isinternallycompensatedtobestableoverall

operatingconditions.Table4providesaguidelineforinput

and output capacitances for several operating conditions.

TheLinearTechnologyµModulePowerDesignToolwillbe

resistors from 0.6V to 1.8V over 4.5V to 15V input

DC

voltages. The typical application schematic is shown in

Figure 23.

provided for transient and stability analysis. The V pin is

FB

used to program the output voltage with a single external

resistor to ground. A differential remote sense ampliﬁer is

available for sensing the output voltage accurately on one

of the outputs at the load point, or in parallel operation

sensing the output voltage at the load point.

TheLTM4630hasdualintegratedconstant-frequencycur-

rent mode regulators and built-in power MOSFET devices

withfastswitchingspeed. Thetypicalswitchingfrequency

is 500kHz. For switching-noise sensitive applications, it

can be externally synchronized from 400kHz to 780kHz. A

resistor can be used to program a free run frequency on

the FSET pin. See the Applications Information section.

Multiphase operation can be easily employed with the

MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12

phases can be cascaded to run simultaneously with re-

spect to each other by programming the PHASMD pin to

different levels. See the Applications Information section.

With current mode control and internal feedback loop

compensation, the LTM4630 module has sufﬁcient stabil-

ity margins and good transient performance with a wide

range of output capacitors, even with all ceramic output

capacitors.

High efﬁciency at light loads can be accomplished with

selectable Burst Mode operation or pulse-skipping opera-

tion using the MODE_PLLIN pin. These light load features

willaccommodatebatteryoperation.Efﬁciencygraphsare

providedforlightloadoperationintheTypicalPerformance

Characteristics section. See the Applications Information

section for details.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limitandfoldbackcurrentlimitinanovercurrentcondition.

Internal overvoltage and undervoltage comparators pull

the open-drain PGOOD outputs low if the output feedback

voltage exits a 10% window around the regulation point.

As the output voltage exceeds 10% above regulation, the

bottom MOSFET will turn on to clamp the output voltage.

ThetopMOSFETwillbeturnedoff.Thisovervoltageprotect

is feedback voltage referred.

A general purpose temperature diode is included inside

the module to monitor the temperature of the module. See

the Applications Information section for details.

The switch pins are available for functional operation

monitoring and a resistor-capacitor snubber circuit can

be careful placed on the switch pin to ground to dampen

any high frequency ringing on the transition edges. See

the Applications Information section for details.

Pulling the RUN pins below 1.1V forces the regulators

into a shutdown state, by turning off both MOSFETs.

The TRACK pins are used for programming the output

voltage ramp and voltage tracking during start-up or

4630fa

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For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

The typical LTM4630 application circuit is shown in Fig-

ure 23. External component selection is primarily deter-

mined by the maximum load current and output voltage.

RefertoTable4forspeciﬁcexternalcapacitorrequirements

for particular applications.

Inparalleloperation,theV pinshaveanI currentof20nA

FB

maximumeachchannel.Toreduceoutputvoltageerrordue

to this current, an additional V

pin can be tied to V

,

OUTS

OUT

andanadditionalR resistorcanbeusedtolowerthetotal

FB

Thevenin equivalent resistance seen by this current. For

exampleinFigure2,thetotalTheveninequivalentresistance

of the V pin is (60.4k//R ), which is 30.2k where R is

V to V

Step-Down Ratios

IN

OUꢄ

FB

equal to 60.4k for a 1.2V output. Four phases connected

in parallel equates to a worse case feedback current of

There are restrictions in the maximum V and V

step-

IN

OUT

down ratio that can be achieved for a given input voltage.

Each output of the LTM4630 is capable of 98% duty cycle,

4 • I = 80nA maximum. The voltage error is 80nA • 30.2k

FB

= 2.4mV. If V

is connected, as shown in Figure 2, to

OUTS2

but the V to V

minimum dropout is still shown as a

IN

OUT

V

,andanother60.4kresistorisconnectedfromV to

OUT

FB2

function of its load current and will limit output current

capability related to high duty cycle on the top side switch.

ground, then the voltage error is reduced to 1.2mV. If the

voltage error is acceptable then no additional connections

arenecessary.Theonboard60.4kresistoris0.5%accurate

Minimum on-time t

is another consideration in

ON(MIN)

operating at a speciﬁed duty cycle while operating at a

certain frequency due to the fact that t < D/f

and the V resistor can be chosen by the user to be as

FB

,

SW

ON(MIN)

accurate as needed. All COMP pins are tied together for

current sharing between the phases. The TRACK/SS pins

can be tied together and a single soft-start capacitor can

be used to soft-start the regulator. The soft-start equation

willneedtohavethesoft-startcurrentparameterincreased

by the number of paralleled channels. See Output Voltage

Tracking section.

where D is duty cycle and f is the switching frequency.

SW

t

is speciﬁed in the electrical parameters as 90ns.

ON(MIN)

Output Voltage Prograꢃꢃing

ThePWMcontrollerhasaninternal0.6Vreferencevoltage.

AsshownintheBlockDiagram,a60.4kΩinternalfeedback

resistor connects between the V

to V and V

OUTS1

FB1 OUTS2

to V . It is very important that these pins be connected

FB2

to their respective outputs for proper feedback regulation.

4 PARALLELED OUTPUTS

LTM4630

60.4k

V

COMP1

COMP2

OUT1

OUT2

FOR 1.2V AT 70A

OvervoltagecanoccuriftheseV

andV

pinsare

OUTS1

OUTS2

left ﬂoating when used as individual regulators, or at least

one of them is used in paralleled regulators. The output

voltage will default to 0.6V with no feedback resistor on

V

OUTS1

OUTS2

V

OPTIONAL CONNECTION

V

FB1

either V or V . Adding a resistor R from V pin to

FB1

FB2

FB

60.4k

TRACK1

TRACK2

GND programs the output voltage:

V

FB2

60.4k+ R_FB

OPTIONAL

FB

60.4k

V_OUT= 0.6V •

R

R_FB

LTM4630

60.4k

V

COMP1

COMP2

OUT1

OUT2

V

ꢄable 1. V_FBResistor ꢄable vs Various Output Voltages

USE TO LOWER

V

OUTS1

OUTS2

TOTAL EQUIVALENT

RESISTANCE TO LOWER

V

0.6V

1.0V

1.2V

1.5V

1.8V

30.2k

OUꢄ

R

Open

90.9k

60.4k

40.2k

I

FB

VOLTAGE ERROR

FB

V

FB1

For parallel operation of multiple channels the same feed-

back setting resistor can be used for the parallel design.

60.4k

TRACK1

TRACK2

V

FB2

0.1µF

R

FB

60.4k

This is done by connecting the V

to the output as

OUTS1

4630 F02

shown in Figure 2, thus tying one of the internal 60.4k

resistors to the output. All of the V pins tie together with

FB

Figure 2. 4-Phase Parallel Conﬁgurations

one programming resistor as shown in Figure 2.

4630fa

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LTM4630

APPLICATIONS INFORMATION

Input Capacitors

µModule Power Design Tool will be provided for stability

analysis.Multiphaseoperationwillreduceeffectiveoutput

ripple as a function of the number of phases. Application

Note 77 discusses this noise reduction versus output

ripple current cancellation, but the output capacitance

should be considered carefully as a function of stability

and transient response. The Linear Technology µModule

Power Design Tool can calculate the output ripple reduc-

tion as the number of implemented phases increases by

N times. A small value 10Ω to 50Ω resistor can be place

The LTM4630 module should be connected to a low ac-

impedance DC source. For the regulator input four 22µF

input ceramic capacitors are used for RMS ripple current.

A47µFto100µFsurfacemountaluminumelectrolyticbulk

capacitor can be used for more input bulk capacitance.

This bulk input capacitor is only needed if the input source

impedanceiscompromisedbylonginductiveleads,traces

ornotenoughsourcecapacitance.Iflowimpedancepower

planes are used, then this bulk capacitor is not needed.

in series from V

to the V

pin to allow for a bode

OUT

OUTS

For a buck converter, the switching duty-cycle can be

estimated as:

plot analyzer to inject a signal into the control loop and

validate the regulator stability. The same resistor could

be place in series from V

to DIFFP and a bode plot

OUT

V_OUT

V

IN

analyzer could inject a signal into the control loop and

validate the regulator stability.

D =

Without considering the inductor current ripple, for each

output, the RMS current of the input capacitor can be

estimated as:

Burst ꢁode Operation

The LTM4630 is capable of Burst Mode operation on each

regulator in which the power MOSFETs operate intermit-

tently based on load demand, thus saving quiescent cur-

rent. For applications where maximizing the efﬁciency at

very light loads is a high priority, Burst Mode operation

should be applied. Burst Mode operation is enabled with

the MODE_PLLIN pin ﬂoating. During this operation, the

peak current of the inductor is set to approximately one

third of the maximum peak current value in normal opera-

tion even though the voltage at the COMP pin indicates

a lower value. The voltage at the COMP pin drops when

the inductor’s average current is greater than the load

requirement. As the COMP voltage drops below 0.5V, the

BURST comparator trips, causing the internal sleep line

to go high and turn off both power MOSFETs.

I_OUT(MAX)

I_CIN(RMS)

=

• D• 1− D

(

)

η%

In the above equation, η% is the estimated efﬁciency of

the power module. The bulk capacitor can be a switcher-

rated electrolytic aluminum capacitor, Polymer capacitor.

Output Capacitors

The LTM4630 is designed for low output voltage ripple

noise and good transient response. The bulk output

capacitors deﬁned as C

are chosen with low enough

OUT

effective series resistance (ESR) to meet the output volt-

age ripple and transient requirements. C can be a low

OUT

ESR tantalum capacitor, the low ESR polymer capacitor

or ceramic capacitor. The typical output capacitance range

for each output is from 200µF to 470µF. Additional output

ﬁltering may be required by the system designer, if further

reduction of output ripples or dynamic transient spikes

is required. Table 4 shows a matrix of different output

voltages and output capacitors to minimize the voltage

droop and overshoot during a 4.5A/µs transient. The table

optimizes total equivalent ESR and total bulk capacitance

tooptimizethetransientperformance.Stabilitycriteriaare

consideredintheTable4matrix,andtheLinearTechnology

In sleep mode, the internal circuitry is partially turned off,

reducing the quiescent current to about 450µA for each

output. The load current is now being supplied from the

output capacitors. When the output voltage drops, caus-

ing COMP to rise above 0.5V, the internal sleep line goes

low, and the LTM4630 resumes normal operation. The

next oscillator cycle will turn on the top power MOSFET

and the switching cycle repeats. Either regulator can be

conﬁgured for Burst Mode operation.

4630fa

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For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

Pulse-Skipping ꢁode Operation

(floating) generates a phase difference (between

MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,

or 90 degrees respectively. A total of 12 phases can be

cascadedtorunsimultaneouslywithrespecttoeachother

byprogrammingthePHASMDpinofeachLTM4630chan-

nel to different levels. Figure 3 shows a 2-phase design,

4-phase design and a 6-phase design example for clock

phasing with the PHASMD table.

In applications where low output ripple and high efﬁ-

ciencyatintermediatecurrentsaredesired,pulse-skipping

mode should be used. Pulse-skipping operation allows

the LTM4630 to skip cycles at low output loads, thus

increasing efﬁciency by reducing switching loss. Tying

the MODE_PLLIN pin to INTV enables pulse-skipping

CC

operation. At light loads the internal current comparator

may remain tripped for several cycles and force the top

MOSFETtostayoffforseveralcycles,thusskippingcycles.

The inductor current does not reverse in this mode. This

modewillmaintainhighereffectivefrequenciesthuslower

output ripple and lower noise than Burst Mode operation.

Eitherregulatorcanbeconﬁguredforpulse-skippingmode.

A multiphase power supply signiﬁcantly reduces the

amount of ripple current in both the input and output ca-

pacitors. The RMS input ripple current is reduced by, and

the effective ripple frequency is multiplied by, the number

of phases used (assuming that the input voltage is greater

thanthenumberofphasesusedtimestheoutputvoltage).

Theoutputrippleamplitudeisalsoreducedbythenumber

of phases used when all of the outputs are tied together

to achieve a single high output current design.

Forced Continuous Operation

In applications where ﬁxed frequency operation is more

critical than low current efﬁciency, and where the lowest

output ripple is desired, forced continuous operation

should be used. Forced continuous operation can be

enabled by tying the MODE_PLLIN pin to GND. In this

mode, inductor current is allowed to reverse during low

output loads, the COMP voltage is in control of the current

comparator threshold throughout, and the top MOSFET

alwaysturnsonwitheachoscillatorpulse.Duringstart-up,

forced continuous mode is disabled and inductor current

is prevented from reversing until the LTM4630’s output

voltage is in regulation. Either regulator can be conﬁgured

for force continuous mode.

The LTM4630 device is an inherently current mode con-

trolled device, so parallel modules will have very good

current sharing. This will balance the thermals on the

design. Figure 26 shows an example of parallel operation

and pin connection.

Input RꢁS Ripple Current Cancellation

Application Note 77 provides a detailed explanation of

multiphaseoperation.TheinputRMSripplecurrentcancel-

lationmathematicalderivationsarepresented,andagraph

isdisplayedrepresentingtheRMSripplecurrentreduction

asafunctionofthenumberofinterleavedphases. Figure4

shows this graph.

ꢁultiphase Operation

For output loads that demand more than 18A of current,

two outputs in LTM4630 or even multiple LTM4630s can

be paralleled to run out of phase to provide more output

currentwithoutincreasinginputandoutputvoltageripples.

The MODE_PLLIN pin allows the LTM4630 to synchronize

to an external clock (between 400kHz and 780kHz) and

theinternalphase-locked-loopallowstheLTM4630tolock

onto incoming clock phase as well. The CLKOUT signal

can be connected to the MODE_PLLIN pin of the following

stage to line up both the frequency and the phase of the

Frequency Selection and Phase-Lock Loop

(ꢁODE_PLLIN and f Pins)

SEꢄ

TheLTM4630deviceisoperatedoverarangeoffrequencies

toimprovepowerconversionefﬁciency.Itisrecommended

to operate the module at 500kHz over the output range for

the best efﬁciency and inductor current ripple

The LTM4630 switching frequency can be set with an

external resistor from the f

pin to SGND. An accurate

SET

10µA current source into the resistor will set a voltage

that programs the frequency or a DC voltage can be

entiresystem. TyingthePHASMDpintoINTV , SGND, or

CC

4630fa

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LTM4630

APPLICATIONS INFORMATION

2-PHASE DESIGN

PHASMD SGND FLOAT INTV

CC

FLOAT

CONTROLLER1

CONTROLLER2

CLKOUT

0

CLKOUT

180

60

180

90

240

120

MODE_PLLIN

0 PHASE

180 PHASE

V

OUT2

OUT1

PHASMD

4-PHASE DESIGN

90 DEGREE

CLKOUT

MODE_PLLIN

0 PHASE

FLOAT

180 PHASE

90 PHASE

270 PHASE

V

OUT1

V

OUT2

OUT1

OUT2

FLOAT

PHASMD

6-PHASE DESIGN

60 DEGREE

CLKOUT

MODE_PLLIN

CLKOUT

MODE_PLLIN

0 PHASE

SGND

180 PHASE

60 PHASE

SGND

240 PHASE

120 PHASE

FLOAT

300 PHASE

V

OUT1

V

OUT1

V

OUT2

OUT1

OUT2

PHASMD

4630 F03

Figure 3. Eꢂaꢃples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASꢁD ꢄable

0.60

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY FACTOR (V /V

)

OUT IN

4630 F04

Figure 4. Input RꢁS Current Ratios to DC Load Current as a Function of Duty Cycle

4630fa

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For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

applied. Figure 5 shows a graph of frequency setting

Low duty cycle applications may approach this minimum

on-time limit and care should be taken to ensure that:

verses programming voltage. An external clock can be

applied to the MODE_PLLIN pin from 0V to INTV over

CC

V_OUT

V •FREQ

IN

a frequency range of 400kHz to 780kHz. The clock input

high threshold is 1.6V and the clock input low threshold

is 1V. The LTM4630 has the PLL loop ﬁlter components

on board. The frequency setting resistor should always

be present to set the initial switching frequency before

locking to an external clock. Both regulators will operate

in continuous mode while being externally clock.

> t_ON(MIN)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

buttheoutputrippleandcurrentwillincrease.Theon-time

can be increased by lowering the switching frequency. A

good rule of thumb is to keep on-time longer than 110ns.

The output of the PLL phase detector has a pair of comple-

mentary current sources that charge and discharge the

internal ﬁlter network. When the external clock is applied

Output Voltage ꢄracking

then the f

frequency resistor is disconnected with

Output voltage tracking can be programmed externally

using the TRACK pins. The output can be tracked up and

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider to imple-

ment coincident tracking. The LTM4630 uses an accurate

60.4k resistor internally for the top feedback resistor for

each channel. Figure 6 shows an example of coincident

tracking. Equations:

SET

an internal switch, and the current sources control the

frequency adjustment to lock to the incoming external

clock. When no external clock is applied, then the internal

switch is on, thus connecting the external f frequency

SET

set resistor for free run operation.

900

800

700

600

500

400

300

200

100

0





60.4k

R_TA

SLAVE = 1+

• V

TRACK









V

is the track ramp applied to the slave’s track pin.

has a control range of 0V to 0.6V, or the internal

TRACK

reference voltage. When the master’s output is divided

down with the same resistor values used to set the slave’s

output, then the slave will coincident track with the master

until it reaches its ﬁnal value. The master will continue to

its ﬁnal value from the slave’s regulation point. Voltage

0

0.5

1

1.5

2

2.5

f

PIN VOLTAGE (V)

SET

4630 F05

Figure 5. Operating Frequency vs f_SEꢄPin Voltage

tracking is disabled when V

is more than 0.6V. R

TRACK

TA

in Figure 6 will be equal to the R for coincident tracking.

FB

Figure 7 shows the coincident tracking waveforms.

ꢁiniꢃuꢃ On-ꢄiꢃe

The TRACK pin of the master can be controlled by a

capacitor placed on the master regulator TRACK pin to

ground. A 1.3µA current source will charge the TRACK

pin up to the reference voltage and then proceed up

Minimum on-time t is the smallest time duration that

ON

the LTM4630 is capable of turning on the top MOSFET on

either channel. It is determined by internal timing delays,

and the gate charge required turning on the top MOSFET.

4630fa

15

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

INTV

CC

C10

4.7µF

R2

10k

PGOOD

MODE_PLLIN CLKOUT INTV

EXTV

PGOOD1

CC

4V TO 15V INTERMEDIATE BUS

1.5V AT 18A

V

OUT1

IN

C4

22µF

25V

C3

22µF

25V

C2

22µF

25V

C1

22µF

25V

C6

100µF

6.3V

C8

R1*

10k

R6

100k

TEMP

V

OUTS1

SW1

470µF

6.3V

RUN1

RUN2

V

FB1

FB2

TRACK1

TRACK2

D1*

5.1V ZENER

MASTER

LTM4630

R

FB

60.4k

40.2k

COMP1

COMP2

C

SS

0.1µF

R

TA

TB

f

SET

1.2V AT 18A

60.4k

PHASMD

V

OUTS2

SLAVE

V

OUT2

SW2

1.5V

C5

100µF

6.3V

C7

470µF

6.3V

R4

121k

PGOOD

PGOOD2

DIFFN DIFFOUT

INTV

SGND

GND

DIFFP

CC

R9

10k

RAMP TIME

t

= (C /1.3µA) • 0.6

SOFTSTART

* PULL-UP RESISTOR AND ZENER ARE OPTIONAL.

SS

4630 F06

Figure 6. Eꢂaꢃple of Output ꢄracking Application Circuit

RegardlessofthemodeselectedbytheMODE_PLLINpin,

the regulator channels will always start in pulse-skipping

mode up to TRACK = 0.5V. Between TRACK = 0.5V and

0.54V, it will operate in forced continuous mode and revert

totheselectedmodeonceTRACK>0.54V. Inordertotrack

with another channel once in steady state operation, the

LTM4630 is forced into continuous mode operation as

MASTER OUTPUT

SLAVE OUTPUT

soon as V is below 0.54V regardless of the setting on

FB

the MODE_PLLIN pin.

Ratiometric tracking can be achieved by a few simple

calculationsandtheslewratevalueappliedtothemaster’s

TRACK pin. As mentioned above, the TRACK pin has a

control range from 0 to 0.6V. The master’s TRACK pin

slew rate is directly equal to the master’s output slew rate

in Volts/Time. The equation:

TIME

4630 F07

Figure 7. Output Coincident ꢄracking Waveforꢃ

to INTV_CC. After the 0.6V ramp, the TRACK pin will no

longer be in control, and the internal voltage reference

will control output regulation from the feedback divider.

Foldback current limit is disabled during this sequence

of turn-on during tracking or soft-starting. The TRACK

pins are pulled low when the RUN pin is below 1.2V. The

total soft-start time can be calculated as:

MR

SR

• 60.4k = R_TB

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in Volts/Time. When coincident





C_SS

1.3µA

t_SOFT-START

=

• 0.6









4630fa

16

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

Run Enable

tracking is desired, then MR and SR are equal, thus R

TB

is equal the 60.4k. R is derived from equation:

TA

TheRUNpinshaveanenablethresholdof1.4Vmaximum,

typically1.25Vwith150mVofhysteresis. Theycontrolthe

turnoneachofthechannelsandINTV .Thesepinscanbe

pulleduptoV for5Voperation,ora5VZenerdiodecanbe

placedonthepinsanda10kto100kresistorcanbeplaced

up to higher than 5V input for enabling the channels. The

RUN pins can also be used for output voltage sequencing.

In parallel operation the RUN pins can be tie together and

controlled from a single control. See the Typical Applica-

tion circuits in Figure 23.

0.6V

R_TA

=

CC

V

V_TRACK

R_TB

FB

+

−

IN

60.4k R_FB

where V is the feedback voltage reference of the regula-

FB

tor, and V

is 0.6V. Since R is equal to the 60.4k

TRACK

TB

top feedback resistor of the slave regulator in equal slew

rate or coincident tracking, then R is equal to R with

TA

FB

V

= V

. Therefore R = 60.4k, and R = 60.4k in

TRACK TB TA

FB

Figure 6.

INꢄV and EXꢄV

CC

Inratiometrictracking, adifferentslewratemaybedesired

The LTM4630 module has an internal 5V low dropout

regulator that is derived from the input voltage. This regu-

lator is used to power the control circuitry and the power

MOSFET drivers. This regulator can source up to 70mA,

and typically uses ~30mA for powering the device at the

maximum frequency. This internal 5V supply is enabled

by either RUN1 or RUN2.

for the slave regulator. R can be solved for when SR is

TB

slower than MR. Make sure that the slave supply slew rate

ischosentobefastenoughsothattheslaveoutputvoltage

will reach it ﬁnal value before the master output.

For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then

R

TB

= 76.8k. Solve for R to equal to 49.9k.

TA

EXTV allowsanexternal5VsupplytopowertheLTM4630

andreducepowerdissipationfromtheinternallowdropout

5V regulator. The power loss savings can be calculated by:

Each of the TRACK pins will have the 1.3µA current source

on when a resistive divider is used to implement tracking

on that speciﬁc channel. This will impose an offset on the

TRACK pin input. Smaller values resistors with the same

ratios as the resistor values calculated from the above

equation can be used. For example, where the 60.4k is

used then a 6.04k can be used to reduce the TRACK pin

offset to a negligible value.

CC

(V – 5V) • 30mA = PLOSS

IN

EXTV has a threshold of 4.7V for activation, and a

CC

maximum rating of 6V. When using a 5V input, connect

this 5V input to EXTV also to maintain a 5V gate drive

CC

level. EXTV must sequence on after V , and EXTV

CC

IN

CC

must sequence off before V .

IN

Power Good

The PGOOD pins are open drain pins that can be used to

monitor valid output voltage regulation. This pin monitors

a 10% window around the regulation point. A resistor can

be pulled up to a particular supply voltage no greater than

6V maximum for monitoring.

Differential Reꢃote Sense Aꢃpliﬁer

Anaccuratedifferentialremotesenseampliﬁerisprovided

to sense low output voltages accurately at the remote

load points. This is especially true for high current loads.

The ampliﬁer can be used on one of the two channels, or

on a single parallel output. It is very important that the

DIFFP and DIFFN are connected properly at the output,

and DIFFOUT is connected to either V

In parallel operation, the DIFFP and DIFFN are connected

properly at the output, and DIFFOUT is connected to

Stability Coꢃpensation

The module has already been internally compensated

for all output voltages. Table 4 is provided for most ap-

plication requirements. The Linear Technology µModule

Power Design Tool will be provided for other control loop

optimization.

or V

.

OUTS1

OUTS2

one of the V

pins. Review the parallel schematics in

OUTS

Figure 24 and review Figure 2.

4630fa

17

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

SW Pins

where V is the thermal voltage (kT/q), and n, the ideality

T

factor, is 1 for the diode connected PNP transistor be-

The SW pins are generally for testing purposes by moni-

toring these pins. These pins can also be used to dampen

out switch node ringing caused by LC parasitic in the

switched current paths. Usually a series R-C combina-

tion is used called a snubber circuit. The resistor will

dampen the resonance and the capacitor is chosen to

only affect the high frequency ringing across the resistor.

If the stray inductance or capacitance can be measured or

approximated then a somewhat analytical technique can

be used to select the snubber values. The inductance is

usuallyeasiertopredict.Itcombinesthepowerpathboard

inductance in combination with the MOSFET interconnect

bond wire inductance.

ing used in the LTM4630. I is expressed by the typical

S

empirical equation:













–V_G0

V_T

I_S= I₀exp

where I is a process and geometry dependent current, (I

0

is typically around 20k orders of magnitude larger than I

S

at room temperature) and V is the band gap voltage of

G0

1.2V extrapolated to absolute zero or –273°C.

If we take the I equation and substitute into the V equa-

S

D

tion, then we get:

First the SW pin can be monitored with a wide bandwidth

scope with a high frequency scope probe. The ring fre-

quency can be measured for its value. The impedance Z

can be calculated:

 

kT

q

I₀

 

kT

q





V_D= V_G0–

ln

, V_T=









I

 

D

The expression shows that the diode voltage decreases

(linearly if I were constant) with increasing temperature

and constant diode current. Figure 6 shows a plot of V

vs Temperature over the operating temperature range of

0

ZL = 2πfL,

D

where f is the resonant frequency of the ring, and L is the

total parasitic inductance in the switch path. If a resistor

is selected that is equal to Z, then the ringing should be

dampened. The snubber capacitor value is chosen so that

its impedance is equal to the resistor at the ring frequency.

Calculatedby:ZC=1/(2πfC).Thesevaluesareagoodplace

to start with. Modiﬁcation to these components should

be made to attenuate the ringing with the least amount

of power loss.

the LTM4630.

If we take this equation and differentiate it with respect to

temperature T, then:

dV_D

dT

V_G0– V_D

T

= –

This dV /dT term is the temperature coefﬁcient equal to

about –2mV/K or –2mV/°C. The equation is simpliﬁed for

the ﬁrst order derivation.

D

ꢄeꢃperature ꢁonitoring

A diode connected PNP transistor is used for the TEMP

monitor function by monitoring its voltage over tempera-

ture. The temperature dependence of this diode voltage

can be understood in the equation:

Solving for T, T = –(V – V )/(dV /dT) provides the

G0

D

temperature.

1st Example: Figure 8 for 27°C, or 300K the diode

voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/

–2.0 mV/K)

 

I_D

V_D= nV_Tln

 

I

 

2nd Example: Figure 8 for 75°C, or 350K the diode

voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/

–2.0mV/K)

S

4630fa

18

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

Converting the Kelvin scale to Celsius is simply taking the

Kelvin temp and subtracting 273 from it.

the µModule regulator’s thermal performance in their ap-

plicationatvariouselectricalandenvironmentaloperating

conditions to compliment any FEA activities. Without FEA

software, the thermal resistances reported in the Pin Con-

ﬁguration section are in-and-of themselves not relevant to

providing guidance of thermal performance; instead, the

derating curves provided in the data sheet can be used in

a manner that yields insight and guidance pertaining to

one’s application-usage, and can be adapted to correlate

thermal performance to one’s own application.

A typical forward voltage is given in the electrical charac-

teristics section of the data sheet, and Figure 6 is the plot

of this forward voltage. Measure this forward voltage at

27°C to establish a reference point. Then using the above

expression while measuring the forward voltage over

temperature will provide a general temperature monitor.

Connect a resistor between TEMP and V to set the cur-

IN

rent to 100µA. See Figure 24 for an example.

The Pin Conﬁguration section typically gives four thermal

coefﬁcients explicitly deﬁned in JESD 51-12; these coef-

ﬁcients are quoted or paraphrased below:

0.8

I

= 100µA

D

0.7

0.6

0.5

0.4

0.3

1. θ , the thermal resistance from junction to ambient, is

JA

the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclo-

sure.Thisenvironmentissometimesreferredtoas“still

air”althoughnaturalconvectioncausestheairtomove.

This value is determined with the part mounted to a

JESD 51-9 deﬁned test board, which does not reﬂect

an actual application or viable operating condition.

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

4630 F08

2. θ

, the thermal resistance from junction to the

JCbottom

Figure 8. Diode Voltage V_Dvs ꢄeꢃperature ꢄ(K)

for Different Bias Currents

bottom of the product case, is the junction-to-board

thermal resistance with all of the component power

dissipation ﬂowing through the bottom of the package.

In the typical µModule, the bulk of the heat ﬂows out

the bottom of the package, but there is always heat

ﬂow out into the ambient environment. As a result, this

thermal resistance value may be useful for comparing

packages but the test conditions don’t generally match

the user’s application.

ꢄherꢃal Considerations and Output Current Derating

The thermal resistances reported in the Pin Conﬁguration

section of the data sheet are consistent with those param-

eters deﬁned by JESD51-9 and are intended for use with

ﬁnite element analysis (FEA) software modeling tools that

leverage the outcome of thermal modeling, simulation,

and correlation to hardware evaluation performed on a

µModulepackagemountedtoahardwaretestboard—also

deﬁned by JESD51-9 (“Test Boards for Area Array Surface

MountPackageThermalMeasurements”).Themotivation

for providing these thermal coefﬁcients is found in JESD

51-12 (“Guidelines for Reporting and Using Electronic

Package Thermal Information”).

3. θ

, the thermal resistance from junction to top of

JCTOP

the product case, is determined with nearly all of the

component power dissipation ﬂowing through the top

of the package. As the electrical connections of the

typical µModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat ﬂows from the junction to the top of the part.

As in the case of θ

, this value may be useful

JCBOTTOM

Many designers may opt to use laboratory equipment

and a test vehicle such as the demo board to anticipate

for comparing packages but the test conditions don’t

generally match the user’s application.

4630fa

19

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

4. θ , the thermal resistance from junction to the printed

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacriﬁcing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably deﬁne and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the speciﬁed PCB with all

of the correct material coefﬁcients along with accurate

power loss source deﬁnitions; (2) this model simulates

a software-deﬁned JEDEC environment consistent with

JSED51-9topredictpowerlossheatﬂowandtemperature

readingsatdifferentinterfacesthatenablethecalculationof

theJEDEC-deﬁnedthermalresistancevalues;(3)themodel

and FEA software is used to evaluate the µModule with

heat sink and airﬂow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamberwhileoperatingthedeviceatthesamepowerloss

as that which was simulated. An outcome of this process

and due-diligence yields a set of derating curves provided

in other sections of this data sheet. After these laboratory

test have been performed and correlated to the µModule

JB

circuitboard,isthejunction-to-boardthermalresistance

wherealmostalloftheheatﬂowsthroughthebottomof

the µModule and into the board, and is really the sum of

the θ

and the thermal resistance of the bottom

JCbottom

of the part through the solder joints and through a por-

tion of the board. The board temperature is measured a

speciﬁed distance from the package, using a two sided,

two layer board. This board is described in JESD 51-9.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters deﬁned by JESD 51-12 or provided in the

Pin Conﬁguration section replicates or conveys normal

operatingconditionsofaµModule.Forexample,innormal

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sivelythroughthetoporexclusivelythroughbottomofthe

µModule—asthestandarddeﬁnesforθ

andθ

,

JCtop

JCbottom

respectively.Inpractice,powerlossisthermallydissipated

inbothdirectionsawayfromthepackage—granted, inthe

absence of a heat sink and airﬂow, a majority of the heat

ﬂow is into the board.

model, then the θ and θ are summed together to cor-

JB

BA

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relatequite wellwith the µModule modelwithno airﬂowor

heat sinking in a properly deﬁne chamber. This θ + θ

JB

BA

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4630 F10

µMODULE DEVICE

Figure 9. Graphical Representation of JESD51-12 ꢄherꢃal Coefﬁcients

4630fa

20

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

valueisshowninthePinConﬁgurationsectionandshould

Power Derating

accurately equal the θ value because approximately

JA

The 1.0V and 1.5V power loss curves in Figures 13 and 14

can be used in coordination with the load current derating

curves in Figures 15 to 22 for calculating an approximate

100% of power loss ﬂows from the junction through the

board into ambient with no airﬂow or top mounted heat

sink. Each system has its own thermal characteristics,

therefore thermal analysis must be performed by the user

in a particular system.

Θ thermal resistance for the LTM4630 with various heat

JA

sinking and airﬂow conditions. The power loss curves are

taken at room temperature, and are increased with a 1.35

to 1.4 multiplicative factor at 125°C. These factors come

fromthe fact that thepowerloss of theregulatorincreases

about 45% from 25°C to 150°C, thus a 50% spread over

125°C delta equates to ~0.35%/°C loss increase. A 125°C

maximumjunctionminus25°Croomtemperatureequates

to a 100°C increase. This 100°C increase multiplied by

0.35%/°C equals a 35% power loss increase at the 125°C

junction, thus the 1.35 multiplier.

The LTM4630 module has been designed to effectively

remove heat from both the top and bottom of the pack-

age. The bottom substrate material has very low thermal

resistance to the printed circuit board. An external heat

sink can be applied to the top of the device for excellent

heat sinking with airﬂow.

Figures10and11showtemperatureplotsoftheLTM4630

with no heat sink and 200LFM airﬂow.

The derating curves are plotted with CH1 and CH2 in

parallel single output operation starting at 36A of load

with low ambient temperature. The output voltages are

1.0V and 1.5V. These are chosen to include the lower and

higher output voltage ranges for correlating the thermal

resistance. Thermal models are derived from several

temperature measurements in a controlled temperature

chamber along with thermal modeling analysis.

These plots equate to a paralleled 12V to 1.0V at 36A

design operating at 84.5% efﬁciency, and 12V to 1.2V at

36A design operating at 86% efﬁciency.

Safety Considerations

The LTM4630 modules do not provide isolation from V

IN

to V . There is no internal fuse. If required, a slow blow

OUT

fuse with a rating twice the maximum input current needs

to be provided to protect each unit from catastrophic

failure. The device does support over current protection.

A temperature diode is provided for monitoring internal

temperature,andcanbeusedtodetecttheneedforthermal

shutdown that can be done by controlling the RUN pin.

Figure 11. ꢄherꢃal Iꢃage 12V to 1.2V,

36A with 200LFꢁ without Heat Sink

Figure 10. ꢄherꢃal Iꢃage 12V to 1.0V,

36A with 200LFꢁ without Heat Sink

4630fa

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LTM4630

APPLICATIONS INFORMATION

The junction temperatures are monitored while ambient

temperature is increased with and without airﬂow. The

power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at ~120°C maximum while lowering output

current or power while increasing ambient temperature.

The decreased output current will decrease the internal

module loss as ambient temperature is increased.

from the efﬁciency curves and adjusted with the above

ambient temperature multiplicative factors. The printed

circuit board is a 1.6mm thick four layer board with two

ounce copper for the two outer layers and one ounce

copper for the two inner layers. The PCB dimensions are

101mm×114mm. TheBGAheatsinksarelistedinTable3.

Layout Checklist/Eꢂaꢃple

The high integration of LTM4630 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

The monitored junction temperature of 120°C minus

the ambient operating temperature speciﬁes how much

module temperature rise can be allowed. As an example in

Figure15,theloadcurrentisderatedto~25Aat~86°Cwith

no air or heat sink and the power loss for the 12V to 1.0V

at 25A output is a ~5.5W loss. The 5.5W loss is calculated

with the ~4.1W room temperature loss from the 12V to

1.0V power loss curve at 25A, and the 1.35 multiplying

factor at 125°C ambient. If the 86°C ambient temperature

is subtracted from the 120°C junction temperature, then

• Use large PCB copper areas for high current paths,

including V , GND, V

and V

. It helps to mini-

IN

OUT1

OUT2

mize the PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the V , PGND and V

pins to minimize

IN

OUT

high frequency noise.

the difference of 34°C divided 5.5W equals a 6.2°C/W Θ

JA

thermal resistance. Table 2 speciﬁes a 7°C/W value which

is pretty close. The airﬂow graphs are more accurate due

to the fact that the ambient temperature environment is

controlled better with airﬂow. As an example in Figure 19,

the load current is derated to ~30A at ~72°C with 200LFM

of airﬂow and the power loss for the 12V to 1.5V at 30A

output is a ~7.9W loss. The 7.9W loss is calculated with

the ~5.9W room temperature loss from the 12V to 1.5V

power loss curve at 22A, and the 1.35 multiplying factor

at 125°C ambient. If the 72°C ambient temperature is

subtracted from the 120°C junction temperature, then

the difference of 48°C divided 7.9W equals a 6.0°C/W

• Place a dedicated power ground layer underneath the

unit.

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put via directly on the pad, unless they are

capped or plated over.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

• For parallel modules, tie the V , V , and COMP pins

θ

thermal resistance. Table 2 speciﬁes a 6.0°C/W value

OUT FB

JA

together. Use an internal layer to closely connect these

pins together. The TRACK pin can be tied a common

capacitor for regulator soft-start.

which is pretty close. Tables 2 and 3 provide equivalent

thermal resistances for 1.0V and 1.5V outputs with and

without airﬂow and heat sinking.

• Bring out test points on the signal pins for monitoring.

The derived thermal resistances in Tables 2 and 3 for the

various conditions can be multiplied by the calculated

power loss as a function of ambient temperature to derive

temperature rise above ambient, thus maximum junction

temperature.Roomtemperaturepowerlosscanbederived

Figure 12 gives a good example of the recommended

layout. LGA and BGA PCB layouts are identical with the

exceptionofcirclepadsforBGA(seePackageDescription).

4630fa

22

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

C

IN1

IN2

V

IN

M

L

K

J

GND

H

G

F

SGND

C

OUT2

OUT1

E

D

C

B

A

1

2

3

4

5

6

7

8

9

10

11

12

V

GND

V

OUT2

OUT1

4630 F12

CNTRL

Figure 12. Recoꢃꢃended PCB Layout (LGA Shown, for BGA Use Circle Pads)

ꢄable 2. 1.0V Output

DERAꢄING CURVE

Figures 15, 16

Figures 17, 18

V

(V)

POWER LOSS CURVE

Figure 13

AIRFLOW (LFꢁ)

HEAꢄ SINK

None

θ

(°C/W)

7

6

5.5

6.5

5

IN

JA

5, 12

0

Figure 13

200

400

0

200

400

None

BGA Heat Sink

Figure 13

4

ꢄable 3. 1.5V Output

DERAꢄING CURVE

Figures 19, 20

V

(V)

POWER LOSS CURVE

Figure 14

AIRFLOW (LFꢁ)

HEAꢄ SINK

None

θ

(°C/W)

IN

JA

5, 12

0

7

6

Figures 19, 20

Figure 14

200

400

0

None

Figures 19, 20

Figure 14

None

5.5

6.5

4

Figures 21, 22

Figure 14

BGA Heat Sink

Figures 21, 22

Figure 14

200

400

Figures 21, 22

Figure 14

3.5

HEAꢄ SINK ꢁANUFACꢄURER

PARꢄ NUꢁBER

WEBSIꢄE

www.aavid.com

Aavid Thermalloy

375424B00034G

4630fa

23

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

ꢄable 4. Output Voltage Response vs Coꢃponent ꢁatriꢂ (Refer to Figure 23) 0A to 7A Load Step ꢄypical ꢁeasured Values

VENDORS

VALUE

PARꢄ NUꢁBER

TDK, C

Murata, C

Ceramic

100µF 6.3V

C4532X5R0J107MZ

GRM32ER60J107M

18126D107MAT

OUT1

Ceramic

OUT1

AVX, C

Ceramic

OUT1

Sanyo POSCAP, C

Bulk

470µF 2R5

470µF 6.3V

56µF 25V

2R5TPD470M5

6TPD470M

OUT2

Sanyo, C Bulk

25SVP56M

IN

P-P

RECOVERY

LOAD

SꢄEP

(A/µs)

V

C

V

DROOP DEVIAꢄION

ꢄIꢁE

(µs)

LOAD SꢄEP

(A)

R

FB

FREQ

(kHz)

OUꢄ

IN

OUꢄ

FF

(pF)

IN

(V) (CERAꢁIC) (BULK) (CERAꢁIC) (BULK)

(V)

(ꢃV)

120

130

140

160

190

170

210

(kΩ)

90.9

60.4

40.2

30.2

1

22uF × 2

150µF

100µF

100µF × 4

100µF

100µF × 4

100µF

100µF × 4

100µF

100µF × 4

470µF

None

470µF

None

470µF

None

470µF

None

None 5, 12

0

25

20

25

20

25

30

25

4.5

450

1.2

1.5

1.8

8

7

6

5

4

3

2

1

0

8

7

6

5

4

3

2

1

0

40

35

30

25

20

15

10

5

V

= 12V

V

= 12V

IN

V

= 5V

V

= 5V

IN

0LFM

200LFM

400LFM

0

70 80

AMBIENT TEMPERATURE (°C)

0

5

10 15 20 25 30 35 40

LOAD CURRENT (A)

0

5

10 15 20 25 30 35 40

LOAD CURRENT (A)

30 40 50 60

90 100 110 120

4630 F13

4630 F14

4630 F15

Figure 13. 1.0V Power Loss Curve

Figure 14. 1.5V Power Loss Curve

Figure 15. 12V to 1V Derating

Curve, No Heat Sink

4630fa

24

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0

70 80

AMBIENT TEMPERATURE (°C)

30 40 50 60

90 100 110 120

30 40 50 60

90 100 110 120

30 40 50 60

90 100 110 120

AMBIENT TEMPERATURE (°C)

4630 F16

4630 F1t

4630 F18

Figure 18. 5V to 1V Derating

Curve, BGA Heat Sink

Figure 16. 5V to 1V Derating

Curve, No Heat Sink

Figure 17. 12V to 1V Derating

Curve, BGA Heat Sink

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

5

0

70 80

30 40 50 60

90 100 110 120

AMBIENT TEMPERATURE (°C)

70 80

AMBIENT TEMPERATURE (°C)

30 40 50 60

90 100 110 120

4630 F19

4630 F20

Figure 19. 12V to 1.5V Derating

Curve, No Heat Sink

Figure 20. 5V to 1.5V Derating

Curve, No Heat Sink

40

35

30

25

20

15

10

5

40

35

30

25

20

15

10

5

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0

70 80

AMBIENT TEMPERATURE (°C)

70 80

AMBIENT TEMPERATURE (°C)

30 40 50 60

90 100 110 120

30 40 50 60

90 100 110 120

4630 F21

4630 F22

Figure 21. 12V to 1.5V Derating

Curve, BGA Heat Sink

Figure 22. 5V to 1.5V Derating

Curve, BGA Heat Sink

4630fa

25

For more information www.linear.com/LTM4630

LTM4630

APPLICATIONS INFORMATION

4630fa

26

For more information www.linear.com/LTM4630

LTM4630

TYPICAL APPLICATIONS

4630fa

27

For more information www.linear.com/LTM4630

LTM4630

TYPICAL APPLICATIONS

4630fa

28

For more information www.linear.com/LTM4630

LTM4630

TYPICAL APPLICATIONS

INTV

CC

C10

4.7µF

R2

5k

CLK1

PGOOD1

MODE_PLLIN CLKOUT INTV

EXTV

PGOOD1

CC

4.5V TO 15V INTERMEDIATE BUS

V

IN

4.5V TO 15V

V

IN

V

OUT1

C3

C2

22µF

25V

C1

22µF

25V

C

OUT2

+

OUT1

R1

R6

TEMP

V

OUTS1

SW1

22µF

25V

100µF

470µF

6.3V

10k

100k

6.3V

RUN1

RUN

V

FB1

RUN2

FB

V

R5

FB2

TRACK1

TRACK2

D1

LTM4630

60.4k

COMP1

COMP2

5.1V ZENER

f

COMP

SET

PHASMD

V

OUTS2

V

OUT2

SW2

C

OUT1

OUT2

R4

121k

100µF

6.3V

470µF

6.3V

PGOOD2

DIFFN DIFFOUT

PGOOD1

SGND GND

DIFFP

V

1.2V

70A

OUT

C16

4.7µF

CLK1

MODE_PLLIN CLKOUT INTV

PGOOD1

EXTV

PGOOD1

CC

4.5V TO 15V INTERMEDIATE BUS

V

OUT1

IN

C12

22µF

25V

C15

22µF

25V

C5

22µF

25V

C

+

OUT1

OUT2

R9

TEMP

V

OUTS1

SW1

100µF

6.3V

470µF

6.3V

100k

RUN1

RUN2

V

FB

FB1

FB2

TRACK1

TRACK2

LTM4630

COMP1

COMP2

COMP

C19

0.22µF

f

SET

PHASMD

V

OUTS2

V

OUT2

SW2

C

OUT1

OUT2

R10

121k

100µF

6.3V

470µF

6.3V

PGOOD2

DIFFN DIFFOUT

PGOOD1

SGND GND

DIFFP

4630 F26

INTV

CC

Figure 26. Lꢄꢁ4630 4-Phase, 1.2V at 70A

4630fa

29

For more information www.linear.com/LTM4630

LTM4630

PACKAGE DESCRIPTION

Lꢄꢁ4630 Coꢃponent LGA and BGA Pinout

PIN ID FUNCꢄION

PIN ID

B1

FUNCꢄION

VOUT1

GND

PIN ID

C1

FUNCꢄION PIN ID FUNCꢄION

PIN ID

E1

FUNCꢄION

GND

PIN ID

F1

FUNCꢄION

GND

A1

A2

VOUT1

GND

VOUT1

VOUT1S

D1

D2

GND

B2

C2

E2

GND

F2

GND

A3

B3

C3

D3

GND

E3

GND

F3

GND

A4

B4

C4

D4

GND

E4

GND

F4

MODE_PLLIN

RUN1

A5

B5

C5

D5

VFB1

SGND

VFB2

TRACK2

GND

E5

TRACK1

COMP1

COMP2

DIFFP

DIFFN

GND

F5

A6

B6

C6

f

D6

E6

F6

SGND

SET

A7

GND

B7

GND

C7

SGND

VOUT2S

VOUT2

D7

E7

F7

SGND

A8

VOUT2

B8

VOUT2

C8

D8

E8

F8

DIFFOUT

RUN2

A9

B9

C9

D9

E9

F9

A10

A11

A12

B10

B11

B12

C10

C11

C12

D10

D11

D12

GND

E10

E11

E12

F10

F11

F12

GND

PIN ID FUNCꢄION

PIN ID

H1

FUNCꢄION

GND

PIN ID

J1

FUNCꢄION PIN ID FUNCꢄION

PIN ID

L1

FUNCꢄION

GND

VIN

PIN ID

M1

FUNCꢄION

GND

VIN

G1

G2

GND

SW1

GND

VIN

K1

K2

GND

VIN

H2

GND

J2

L2

M2

G3

GND

H3

GND

J3

VIN

K3

VIN

L3

VIN

M3

VIN

G4

PHASEMD

CLKOUT

SGND

H4

GND

J4

VIN

K4

VIN

L4

VIN

M4

VIN

G5

H5

GND

J5

GND

TEMP

EXTVCC

GND

VIN

K5

GND

VIN

L5

VIN

M5

VIN

G6

H6

GND

J6

K6

L6

VIN

M6

VIN

G7

SGND

H7

GND

J7

K7

L7

VIN

M7

VIN

G8

PGOOD2

PGOOD1

GND

H8

INTVCC

GND

J8

K8

L8

VIN

M8

VIN

G9

H9

J9

K9

L9

VIN

M9

VIN

G10

G11

G12

H10

H11

H12

GND

J10

J11

J12

VIN

K10

K11

K12

VIN

L10

L11

L12

VIN

M10

M11

M12

VIN

SW2

GND

VIN

GND

4630fa

30

For more information www.linear.com/LTM4630

LTM4630

PACKAGE DESCRIPTION

Please refer to http://www.linear.coꢃ/designtools/packaging/ for the ꢃost recent package drawings.

Z

/ / b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

a a a

Z

4630fa

31

For more information www.linear.com/LTM4630

LTM4630

PACKAGE DESCRIPTION

Please refer to http://www.linear.coꢃ/designtools/packaging/ for the ꢃost recent package drawings.

Z

/ / b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

a a a

Z

4630fa

32

For more information www.linear.com/LTM4630

LTM4630

REVISION HISTORY

REV

DAꢄE

DESCRIPꢄION

PAGE NUꢁBER

A

03/14 Added BGA package

1, 2, 32

4630fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

33

For more information www.linear.com/LTM4630

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTM4630

PACKAGE PHOTO

LGA

BGA

DESIGN RESOURCES

SUBJECꢄ

DESCRIPꢄION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

TechClip Videos

Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management

Linear Technology’s family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user conﬁgurations and fault logging.

RELATED PARTS

PARꢄ NUꢁBER DESCRIPꢄION

COꢁꢁENꢄS

LTM4620

Dual 13A Single 26A µModule Regulator

Pin Compatible with LTM4630; 4.5V ≤ V ≤ 16V, 0.6V ≤ V

≤ 2.5V,

IN

OUT

15mm × 15mm × 4.32mm

LTM4628

Dual 8A, Single 16A µModule Regulator

15A µModule Regulator

Pin Compatible with LTM4630; 4.5V ≤ V ≤ 26.5V, 0.6V ≤ V

≤ 5.5V,

IN

OUT

15mm × 15mm × 4.32mm

LTM4627

LTM4611

LTM4619

LTM4615

LTM4616

4.5V ≤ V ≤ 20V, 0.6V ≤ V

≤ 5.5V, 15mm × 15mm × 4.32mm

OUT

IN

Ultralow V , 15A µModule Regulator

1.5V ≤ V ≤ 5.5V, 0.8V ≤ V

≤ 5V, 15mm × 15mm × 4.32mm

OUT

IN

Dual 26V , 4A DC/DC µModule Regulator

4.5V ≤ V ≤ 26.5V; 0.8V ≤ V

≤ 5V

OUT

IN

Triple Low V , 4A DC/DC µModule Regulator

2.375 ≤ V ≤ 5.5V; Two 4A and One 1.5A Output

IN

Dual 8A, Low V , DC/DC µModule Regulator

2.7V ≤ V ≤ 5.5V; 0.6V ≤ V

≤ 5V

OUT

IN

LTM8062/

LTM8062A

32V , 2A µModule Battery Charger with Maximum Adjustable V

Up to 14.4V (18.8V for the LTM8062A), C/10 or Timer

IN

BATT

Peak Power Tracking (MPPT)

Termination, 9mm × 15mm × 4.32mm LGA Package

LTM8027

LTM4613

60V , 4A DC/DC Step-Down µModule Regulator

4.5V ≤ V ≤ 60V, 2.5V ≤ V ≤ 24V, 15mm × 15mm × 4.32mm LGA Package

IN

OUT

EN55022B Compliant 36V , 8A Step-Down

5V ≤ V ≤ 36V, 3.3V ≤ V

≤ 15V, Synchronizable, Parallelable,

IN

OUT

µModule Regulator

15mm × 15mm × 4.32mm LGA Package

4630fa

LT 0314 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

34

For more information www.linear.com/LTM4630

●

 LINEAR TECHNOLOGY CORPORATION 2013

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4630


型号：	LTM4630EY#PBF
厂家：	Linear
描述：	LTM4630 - Dual 18A or Single 36A DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 144; Temperature Range: -40°C to 85°C 开关
文件：	总34页 (文件大小：630K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4630EY#PBF [Linear]

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