LTC5800IWR-IPRB#PBF_技术文档

LTC5800-IPR

SmartMesh IP Network Manager

2.4GHz 802.15.4e Wireless Manager

neTwork FeaTures

DescripTion

n

SmartMeshIP™wirelesssensornetworksareselfmanag-

ing, low power internet protocol (IP) networks built from

wireless nodes called motes. The LTC^®5800-IPR is the IP

Manager-on-Chip™intheEterna^®*familyofIEEE802.15.4e

system-on-chip (SoC) solutions, featuring a highly inte-

grated, low power radio design by Dust Networks^®as well

as an ARM Cortex-M3 32-bit microprocessor running

Dust’s embedded SmartMesh IP networking software.

Complete Radio Transceiver, Embedded Processor,

and Networking Software for Forming a Self-Healing

Mesh Network

SmartMesh^®Networks Incorporate:

n

Time Synchronized Network-Wide Scheduling

n

Per-Transmission Frequency-Hopping

n

Redundant Spatially Diverse Topologies

n

Network-Wide Reliability and Power Optimization

n

NIST Certified Security

Based on the IETF 6LoWPAN and IEEE-802.15.4e stan-

dards, the LTC5800-IPR SoC runs SmartMesh IP network

management software to monitor and manage network

performance and provide a data ingress/egress point via

a UART interface. The SmartMesh IP software provided

with the LTC5800-IPR is fully tested and validated, and is

readilyconfiguredviaasoftwareApplicationProgramming

Interface. With Dust’s time-synchronized SmartMesh IP

networks, all motes in the network may route, source or

terminate data, while providing many years of battery-

powered operation.

n

SmartMesh Networks Deliver:

n

>99.999% Network Reliability Achieved in the

Most Challenging RF Environments

Sub 50µA Routing Nodes

n

Compliant to 6LoWPAN Internet Protocol (IP) and

IEEE 802.15.4e Standards

lTc5800-ipr FeaTures

n

Provides Network Management Functions and

Security Capabilities

n

Manages Networks of Up to 100 nodes

SmartMesh IP motes deliver a highly flexible network

with proven reliability and low power performance in an

easy-to-integrate platform.

n

Sub 1mA Average Current Consumption Enables

Battery-Powered Network Management

n

PCB Module Versions Available (LTP™5901/2-IPR)

L, LT, LTC, LTM, Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and

Eterna are registered trademarks and LTP, the Dust Networks logo SmartMesh IP and Manager-

on-Chip are trademarks of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217,

7791419, 7881239, 7898322, 8222965.

with RF Modular Certifications

72-Lead 10mm × 10mm QFN Package

n

* Eterna is Dust Networks’ low power radio SoC architecture.

Typical applicaTion

20MHz

LTC5800-IPM

ANTENNA

LTC5800-IPR

ANTENNA

IN+

LTC2379-18 SPI

UART

SENSOR

µCONTROLLER

IN–

HOST

APPLICATION

32kHz

5800IPR TA01

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LTC5800-IPR

Table oF conTenTs

Network Features .......................................... 1

LTC5800-IPR Features .................................... 1

Typical Application ........................................ 1

Description.................................................. 1

SmartMesh Network Overview........................... 3

Absolute Maximum Ratings.............................. 4

Order Information.......................................... 4

Recommended Operating Conditions................... 4

Pin Configuration .......................................... 4

DC Characteristics......................................... 5

Radio Specifications ...................................... 5

Radio Receiver Characteristics.......................... 6

Radio Transmitter Characteristics....................... 6

Digital I/O Characteristics ................................ 7

Temperature Sensor Characteristics.................... 7

System Characteristics ................................... 7

UART AC Characteristics.................................. 8

TIMEn AC Characteristics ................................ 9

RADIO_INHIBIT AC Characteristics ..................... 9

Flash AC Characteristics.................................10

Flash SPI Slave AC Characteristics ....................10

External Bus AC Characteristics ........................11

Typical Performance Characteristics ..................13

Pin Functions..............................................18

Operation...................................................23

Power Supply..........................................................23

Supply Monitoring And Reset.................................24

Precision Timing.....................................................24

Application Time Synchronization ..........................24

Time References.....................................................24

Radio ......................................................................25

UARTS....................................................................25

CLI UART................................................................27

Autonomous Mac ...................................................27

Security ..................................................................27

Temperature Sensor ...............................................28

Radio Inhibit ...........................................................28

Flash Programming ................................................28

Flash Data Retention...............................................28

Networking .............................................................29

State Diagram.........................................................30

Applications Information ................................32

Regulatory And Standards Compliance ..................32

Soldering Information.............................................32

Related Documentation..................................33

Package Description .....................................34

Revision History ..........................................35

Typical Application .......................................36

Related Parts..............................................36

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LTC5800-IPR

smarTmesh neTwork overview

ASmartMeshnetworkconsistsofaself-formingmulti-hop,

mesh of nodes, known as motes, which collect and relay

data, and a network manager that monitors and manages

network performance and security, and exchanges data

with a host application.

The network manager uses health reports to continually

optimizethenetworktomaintain>99.999%datareliability

even in the most challenging RF environments.

The use of TSCH allows SmartMesh devices to sleep in-

between scheduled communications and draw very little

power in this state. Motes are only active in time slots

where they are scheduled to transmit or receive, typically

resulting in a duty cycle of <1%. The optimization soft-

ware in the Network Manager coordinates this schedule

automatically. When combined with the Eterna low power

radio, every mote in a SmartMesh network—even busy

routing ones—can run on batteries for years. By default,

all motes in a network are capable of routing traffic from

other motes, which simplifies installation by avoiding the

complexity of having distinct routers vs non-routing end

nodes. Motesmaybeconfiguredasnon-routingtofurther

reduce that particular mote’s power consumption and to

support a wide variety of network topologies.

SmartMesh networks communicate using a time slotted

channel hopping (TSCH) link layer, pioneered by Dust

Networks. In a TSCH network, all motes in the network

are synchronized to within less than a millisecond. Time

in the network is organized into time slots, which enable

collision-free packet exchange and per-transmission

channel-hopping. In a SmartMesh network, every device

has one or more parents (e.g., mote 3 has motes 1 and 2

as parents) that provide redundant paths to overcome

communicationsinterruptionduetointerference,physical

obstruction or multi-path fading. If a packet transmission

fails on one path, the next retransmission may try on a

different path and different RF channel.

A network begins to form when the network manager

instructs its on-board access point (AP) radio to begin

sendingadvertisements—packetsthatcontaininformation

that enables a device to synchronize to the network and

request to join. This message exchange is part of the secu-

rityhandshakethatestablishesencryptedcommunications

betweenthemanagerorapplication,andmote.Oncemotes

have joined the network, they maintain synchronization

through time corrections when a packet is acknowledged.

ALL NODES ARE ROUTERS.

THEY CAN TRANSMIT AND RECEIVE.

THIS NEW NODE CAN JOIN

ANYWHERE BECAUSE ALL

NODES CAN ROUTE.

HOST

APPLICATION

SNO 02

At the heart of SmartMesh motes and network managers

is the Eterna IEEE 802.15.4e system-on-chip (SoC), fea-

turing Dust Networks’ highly integrated, low power radio

design, plus an ARM Cortex-M3 32-bit microprocessor

runningSmartMeshnetworkingsoftware.TheSmartMesh

networking software comes fully compiled yet is configu-

rable via a rich set of application programming interfaces

(APIs) which allows a host application to interact with

the network, e.g., to transfer information to a device, to

configure data publishing rates on one or more motes,

or to monitor network state or performance metrics. Data

publishing can be uniform or different for each device,

with motes being able to publish infrequently or faster

NETWORK MANAGER

AP

Mote

1

Mote

2

Mote

3

SNO 01

An ongoing discovery process ensures that the network

continually discovers new paths as the RF conditions

change. In addition, each mote in the network tracks per-

formance statistics (e.g., quality of used paths, and lists

of potential paths) and periodically sends that information

to the network manager in packets called health reports.

than once per second as needed.

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LTC5800-IPR

absoluTe maximum raTings

pin conFiguraTion

(Note 1)

Pin functions shown in italics are currently not supported in software.

Supply Voltage on VSUPPLY..................................4.20V

Input Voltage on AI_0/1/2/3 Inputs........................1.80V

Voltage on Any Digital I/O pin..–0.3V to VSUPPLY + 0.3V

Input RF Level......................................................10dBm

Storage Temperature Range (Note 3)..... –55°C to 125°C

Junction Temperature (Note 3) ............................. 125°C

Operating Temperature Range

TOP VIEW

RADIO_INHIBIT 1

CAP_PA_1P 2

CAP_PA_1M 3

CAP_PA_2M 4

CAP_PA_2P 5

CAP_PA_3P 6

CAP_PA_3M 7

CAP_PA_4M 8

CAP_PA_4P 9

VDDPA 10

54 VPP

53 EB_IO_OEn

52 EB_IO_WEn

51 RESERVED / UARTC1_RX

50 RESERVED / UARTC1_TX

49 EB_IO_CSOn

48 EB_DATA_5

47 EB_DATA_2

46 EB_DATA_3

45 IPCS_SSn

44 IPCS_SCK

43 EB_ADDR_0

42 IPCS_MOSI

41 EB_ADDR_1

40 IPCS_MISO

LTC5800I.............................................–40°C to 85°C

LTC5800H.......................................... –55°C to 105°C

CAUTION: This part is sensitive to electrostatic discharge

(ESD). It is very important that proper ESD precautions

be observed when handling the LTC5800-IPR.

EXPOSED PAD

(GND)

LNA_EN 11

RADIO_TX 12

RADIO_TXn 13

ANTENNA 14

AI_0 15

AI_1 16

AI_3 17

AI_2 18

39 EB_IO_LE2

38 UARTCO_RX / EB_DATA_1

37 UARTCO_TX / EB_IO_LE0

WR PACKAGE

72-LEAD PLASTIC QFN

T

= 125°C, Y

= 0.2°C/W, Y

= 0.6°C/W

JMAX

JC top

JCbottom

EXPOSED PAD IS GND, MUST BE SOLDERED TO PCB

orDer inFormaTion

SPECIFIED TEMPERATURE

LEAD FREE FINISH

PART MARKING*

LTC5800WR-IPMA

PACKAGE DESCRIPTION

RANGE

LTC5800IWR-IPMA#PBF

LTC5800HWR-IPMA#PBF

–40°C to 85°C

–55°C to 105°C

72-Lead (10mm × 10mm × 0.85mm) Plastic QFN

For legacy part numbers and ordering information go to: http://www.linear.com/product/LTC5800-IPR#orderinfo.

*The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

The l denotes the specifications which apply

recommenDeD operaTing conDiTions

over the full operating temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

3.76

250

90

UNITS

V

l

VSUPPLY

Supply Voltage

Including Noise and Load Regulation

Requires Recommended RLC Filter, 50Hz to 2MHz

Non-Condensing

2.1

Supply Noise

mV

Operating Relative Humidity

10

% RH

Temperature Ramp Rate While Operating –40°C

≤

Temperature ≤ 85°C

–8

–2

8

2

°C/Min

in Network

Temperature > 85°C or Temperature < –40°C

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LTC5800-IPR

Dc characTerisTics ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

OPERATION/STATE

CONDITIONS

MIN

TYP

MAX

UNITS

Power-On Reset

During Power-On Reset, Maximum 750µs + VSUPPLY Rise Time

from 1V to 1.9V

12

mA

Doze

RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All

Data and State Retained, 32.768kHz Reference Active

1.2

0.8

20

µA

Deep Sleep

RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All

Data and State Retained, 32.768kHz Reference Inactive

In-Circuit Programming

RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz

mA

Peak Operating Current

8dBm

0dBm

System Operating at 14.7MHz, Radio Transmitting, During Flash

Write. Maximum Duration 4.33ms

30

26

mA

Active

ARM Cortex M3, RAM and Flash Operating, Radio and All Other

Peripherals Off. Clock Frequency of CPU and Peripherals Set to

1.3

mA

7.3728MHz, V

= 1.2V

CORE

Flash Write

Flash Erase

Single Bank Flash Write

3.7

2.5

mA

Single Bank Page or Mass Erase

Radio Tx

Current With Autonomous MAC Managing Radio Operation,

CPU Inactive. Clock Frequency of CPU and Peripherals Set to

7.3728MHz.

+0dBm (LTC5800I)

+0dBm (LTC5800H)

+8dBm (LTC5800I)

+8dBm (LTC5800H)

5.4

5.6

9.7

9.9

mA

Radio Rx

LTC5800I

LTC5800H

Current With Autonomous MAC Managing Radio Operation,

CPU Inactive. Clock Frequency of CPU and Peripherals Set to

7.3728MHz.

4.5

4.7

mA

raDio speciFicaTions ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Frequency Band

2.4000

2.4835

GHz

Number of Channels

Channel Separation

Channel Center Frequency

Modulation

15

5

MHz

Where k = 11 to 25, as Defined by IEEE.802.15.4

2405 + 5 •(k – 11)

IEEE 802.15.4 Direct Sequence Spread Spectrum (DSSS)

l

Raw Data Rate

250

kbps

V

Antenna Pin ESD Protection

HBM Per JEDEC JESD22-A114F

1000

Range (Note 4)

Indoor

25°C, 50% RH, 2dBi Omni-Directional Antenna, Antenna 2m

Above Ground

100

300

1200

m

Outdoor

Free Space

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LTC5800-IPR

raDio receiver characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

–93

–95

0

MAX

UNITS

dBm

dBc

Receiver Sensitivity

Saturation

Packet Error Rate (PER) = 1% (Note 5)

PER = 50%

Maximum Input Level the Receiver Will Properly Receive Packets

Adjacent Channel Rejection (High Side)

Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

Above the Desired Signal, PER = 1% (Note 5)

22

Adjacent Channel Rejection (Low Side)

Alternate Channel Rejection (High Side)

Alternate Channel Rejection (Low Side)

Second Alternate Channel Rejection

Co-Channel Rejection

Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

Below the Desired Signal, PER = 1% (Note 5)

19

40

36

42

–6

dBc

Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Above the Desired Signal, PER = 1% (Note 5)

Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Below the Desired Signal, PER = 1% (Note 5)

Desired Signal at –82dBm, Second Alternate Modulated Channel

Either 15MHz Above or Below, PER = 1% (Note 5)

Desired Signal at –82dBm, Undesired Signal is an 802.15.4

Modulated Signal at the Same Frequency, PER = 1%

LO Feed Through

–55

50

dBm

ppm

dBm

Frequency Error Tolerance (Note 6)

Symbol Error Tolerance

50

Received Signal Strength Indicator (RSSI)

Input Range

–90 to –10

RSSI Accuracy

6

1

dB

RSSI Resolution

raDio TransmiTTer characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Power

High Calibrated Setting

Low Calibrated Setting

Delivered to a 50Ω load

8

0

dBm

Spurious Emissions

Conducted Measurement with a 50Ω Single-Ended Load,

8dBm Output Power. All Measurements Made with Max Hold.

RF Implementation Per Eterna Reference Design

30MHz to 1000 MHz

RBW = 120kHz, VBW = 100Hz

RBW = 1MHz, VBW = 3MHz

<–70

–45

–37

–49

–45

dBm

dBc

1GHz to 12.75GHz

2.4GHz ISM Upper Band Edge (Peak)

2.4GHz ISM Upper Band Edge (Average) RBW = 1MHz, VBW = 10Hz

2.4GHz ISM Lower Band Edge

RBW = 100kHz, VBW = 100kHz

Harmonic Emissions

2nd Harmonic

3rd Harmonic

Conducted Measurement Delivered to a 50Ω Load,

Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz.

RF Implementation Per Eterna Reference Design

–50

–45

dBm

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DigiTal i/o characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS (Note 7)

MIN

–0.3

TYP

MAX

0.6

UNITS

l

V

Low Level Input Voltage

High Level Input Voltage

Low Level Output Voltage

High Level Output Voltage

Low Level Output Voltage

High Level Output Voltage

Low Level Output Voltage

High Level Output Voltage

Input Leakage Current

V

IL

(Note 8)

VSUPPLY – 0.3

VSUPPLY + 0.3

0.4

IH

Type 1, I

= 1.2mA

V

OL

OH

OL

OH

OL

OH

OL(MAX)

OH(MAX)

= –0.8mA

VSUPPLY – 0.3

VSUPPLY + 0.3

0.4

V

Type 2, Low Drive, I

= 2.2mA

= –1.6mA

= 4.5mA

= –3.2mA

V

OL(MAX)

OH(MAX)

VSUPPLY + 0.3

0.4

V

Type 2, High Drive, I

V

OL(MAX)

OH(MAX)

VSUPPLY + 0.3

V

Input Driven to VSUPPLY or GND

50

nA

kΩ

Pull-Up/Pull-Down Resistance

TemperaTure sensor characTerisTics ^Thel denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

Offset

CONDITIONS

MIN

TYP

MAX

UNITS

°C

Temperature Offset Error at 25°C

0.25

0.033

Slope Error

°C/°C

sysTem characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

5

MAX

UNITS

µs

Doze to Active State Transition

Doze to Radio Tx or Rx

1.2

4

ms

Q

Charge to Sample RF Channel RSSI

Charge Consumed Starting from Doze State

and Completing an RSSI Measurement

µC

CCA

l

Largest Atomic Charge Operation

RESETn Pulse Width

Flash Erase, 21ms Max Duration

200

µC

µs

MAX

125

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LTC5800-IPR

uarT ac characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Permitted Rx Baud Rate Error

Both Application Programming

Interface (API) and Command Line

Interface (CLI) UARTs

–2

2

%

l

Generated Tx Baud Rate Error

Both API and CLI UARTs

–1

0

1

2

%

t

Assertion of UART_RX_RTSn to Assertion

of UART_RX_CTSn, or Negation of UART_

RX_RTSn to Negation of UART_RX_CTSn

ms

RX_RTS to RX_CTS

l

t

Assertion of UART_RX_CTSn to Start of

Byte

0

20

22

ms

RX_CTS to RX

End of Packet (End of the Last Stop Bit) to

Negation of UART_RX_RTSn

EOP to RX_RTS

Assertion of UART_TX_RTSn to Assertion

of UART_TX_CTSn

ms

BEG_TX_RTS to TX_CTS

END_TX_RTS to TX_CTS

END_TX_CTS to TX_RTS

TX_CTS to TX

Negation of UART_TX_RTSn to Negation Mode 2 Only

of UART_TX_CTSn

ms

Negation of UART_TX_CTSn to Negation Mode 4 Only

of UART_TX_RTSn

2

0

Bit Period

l

Assertion of UART_TX_CTSn to Start of

Byte

2

1

End of Packet (End of the Last Stop Bit) to

Negation of UART_TX_RTSn

EOP to TX_RTS

l

t

Receive Inter-Byte Delay

Receive Inter-Packet Delay

Transmit Inter-Packet Delay

100

ms

RX_INTERBYTE

RX_INTERPACKET

TX_INTERPACKET

TX to TX_CTS

20

1

Bit Period

ns

Start of Byte to Negation of

UART_TX_CTSn

0

t

EOP to RX_RTS

t

RX_INTERPACKET

UART_RX_RTSn

t

RX_RTS to RX_CTS

t

RX_RTS to RX_CTS

UART_RX_CTSn

UART_RX

t

RX_CTS to RX

BYTE 0

t

RX_INTERBYTE

BYTE 1

t

EOP to TX_RTS

t

TX_INTERPACKET

UART_TX_RTSn

UART_TX_CTSn

UART_TX

t

END_TX_CTS to TX_RTS

END_TX_RTS to TX_CTS

TX_RTS to TX_CTS

t

TX to TX_CTS

t

TX_CTS to TX

BYTE 0

BYTE 1

5800IPM F01

Figure 1. API UART Timing

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LTC5800-IPR

The l denotes the specifications which apply over the full operating temperature

Timen ac characTerisTics

range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

125

0

TYP

MAX

UNITS

µs

l

t

TIMEn Signal Strobe Width

STROBE

Delay from Rising Edge of TIMEn to the Start

of Time Packet on API UART

100

ms

RESPONSE

l

t

Delay from End of Time Packet on API UART

to Falling Edge of Subsequent TIMEn

0

ns

TIME_HOLD

l

Timestamp Resolution (Note 9)

1

5

µs

Network-Wide Time Accuracy (Note 10)

t

TIME_HOLD

STROBE

TIMEn

t

RESPONSE

UART_TX

TIME INDICATION PAYLOAD

5800IPR F02

Figure 2. Timestamp Timing

raDio_inhibiT ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

Delay from Rising Edge of

20

ms

RADIO_OFF

RADIO_INHIBIT to Radio Disabled

t

Maximum RADIO_INHIBIT Strobe Width

2

s

RADIO_INHIBIT_STROBE

t

RADIO_INHIBIT_STROBE

RADIO_INHIBIT

t

RADIO_OFF

RADIO STATE

ACTIVE/OFF

OFF

ACTIVE/OFF

5800IPR F03

Figure 3. RADIO_INHIBIT Timing

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Flash ac characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

21

UNITS

µs

l

t

Time to Write a 32-Bit Word (Note 11)

Time to Erase a 2kB Page (Note 11)

Time to Erase 256kB Flash Bank (Note 11)

Data Retention

WRITE

21

ms

PAGE_ERASE

MASS_ERASE

21

ms

25°C

85°C

105°C

100

20

8

Years

Flash spi slave ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

Setup from Assertion of FLASH_P_ENn to

Assertion of RESETn

0

ns

FP_EN_to_RESET

Delay from the Assertion RESETn to the First

Falling Edge of IPCS_SSn

125

10

µs

FP_ENTER

Delay from the Completion of the Last Flash SPI

Slave Transaction to the Negation of RESETn and

FLASH_P_ENn (Note 12)

FP_EXIT

l

t

IPCS_SSn Setup to the Leading Edge of IPCS_SCK

IPCS_SSn Hold from Trailing Edge of IPCS_SCK

IPCS_SCK Period

15

300

15

5

ns

SSS

SSH

CK

IPCS_MOSI Data Setup

DIS

DIH

DOV

OFF

IPCS_MOSI Data Hold

IPCS_MISO Data Valid

3

IPCS_MISO Data Tri-state

0

30

t

FP_EN_TO_RESET

FLASH_P_ENn

RESETn

t

FP_EXIT

FP_ENTER

t

SSH

SSS

IPCS_SSn

IPCS_SCK

t

CK

t

DIS

t

DIH

IPCS_MOSI

5800IRP F04

Figure 4. Flash Programming Interface Timing

5800iprfa

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LTC5800-IPR

exTernal bus ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

100

90

TYP

MAX

UNITS

ns

l

t

EB_IO_LE0, EB_IO_LE1, EB_IO_LE2 Pulse Width

LEPW

AH

EB_DATA_[7:0] Address Hold from the Rising Edge EB_DATA_[7:0] During Address

of EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2

ns

Phase

l

t

EB_ADDR_[1:0] Address Valid Until

EB_DATA_[7:0] Data Latched

90

ns

AV_to_DL

l

t

EB_CS0n Asserted Until EB_OEn Asserted

EB_CS0n Asserted

150

100

50

ns

CSn_to_OEn

CSn

EB_CS0n Negated Between External Bus Transfers

CSn_OFF

SU_to_CSn

EB_ADDR_[1:0], EB_IO_WEn Setup to

EB_CSn Asserted

l

t

EB_ADDR_[1:0], EB_IO_WEn Hold from

EB_CSn Negated

50

ns

H_from_CSn

t

LEPW

EB_IO_LE0

t

LEPW

EB_IO_LE1

EB_IO_LE2

t

LEPW

t

AH

t

AH

t

AH

EB_DATA_[7:0]

EB_ADDR_[1:0]

EB_IO_CSn

A[25:18] A[17:10] A[9:2] D[31:24] D[23:16] D[7:0] D[15:8]

X

t

AV_to_DL

XX

11

10

01

00

CSn_OFF

t

CSn_to_OEn

5800IPR F05

EB_IO_OEn

Figure 5. External Bus Read Timing

t

LEPW

EB_IO_LE0

t

LEPW

EB_IO_LE1

EB_IO_LE2

t

LEPW

t

AH

t

AH

t

AH

EB_DATA_[7:0]

EB_ADDR_[1:0]

X

A[25:18] A[17:10] A[9:2]

D[31:24]

D[23:16]

10

D[7:0]

00

D[15:8]

01

X

XX

11

00

t

H_from_CSn

SU_to_CSn

EB_IO_WEn

EB_IO_CS0n

t

CSn_OFF

CSn

5800IPR F06

Figure 6. External Bus Write Timing

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LTC5800-IPR

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a

frequency tolerance of better than 40 ppm.

Note 7: Per pin I/O types are provided in the Pin Functions section.

Note 8: VIH maximum voltage input must respect the VSUPPLY maximum

voltage specification.

Note 9: See the SmartMesh IP Manager API Guide for the time Indication

notification definition.

Note 10: Network time accuracy is a statistical measure and varies over

the temperature range, reporting rate and the location of the device

relative to the manager in the network. See the Typical Performance

Characteristics section for a more detailed description.

Note 11: Code execution from flash banks being written or erased is

suspended until completion of the flash operation.

Note 12: Following erase or write transfers, the IPCS SPI slave status

register, 0xD7 must be polled to determine the completion time of the

erase or write operation prior to negating either FLASH_P_ENn or RESETn.

Note 2: ESD (electrostatic discharge) sensitive device. ESD protection

devices are used extensively internal to Eterna. However, high electrostatic

discharge can damage or degrade the device. Use proper ESD handling

precautions.

Note 3: Extended storage at high temperature is discouraged, as this

negatively affects the data retention of Eterna’s calibration data. See the

FLASH Data Retention section for details.

Note 4: Actual RF range is subject to a number of installation-specific

variables including, but not restricted to ambient temperature, relative

humidity, presence of active interference sources, line-of-sight obstacles,

and near-presence of objects (for example, trees, walls, signage, and so

on) that may induce multipath fading. As a result, range varies.

Note 5: As Specified by IEEE Std. 802.15.4-2006: Wireless Medium

Access Control (MAC) and Physical Layer (PHY) Specifications for Low-

Rate Wireless Personal Area Networks (LR-WPANs)

Note 13: Guaranteed by design, not production tested.

http://www.standards.ieee.org/findstds/standard/802.15.4-2011.html

5800iprfa

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LTC5800-IPR

Typical perFormance characTerisTics

In mesh networks data can propagate from the manager

to the nodes, downstream, or from the motes to the man-

ager, upstream, via a sequence of transmissions from one

device to the next. As shown in Figure 8, data originating

from mote P1 may propagate to the manager directly or

through P2. As mote P1 may directly communicate with

the manager, mote P1 is referred to as a 1-hop mote. Data

originatingfrommoteD1,mustpropagatethroughatleast

one other mote, P2 or P1, and as a result is referred to as

a 2-hop mote. The fewest number of hops from a mote to

the manager determines the hop depth.

and its descendents therefore propagated down through

the network. The synchronization of the 3-hop and 5-hop

motestothemanagerwasthusaffectedbythetemperature

ramps even though they were at room temperature. For

2°C/minute testing the temperature chamber was cycled

between –40°C and 85°C at this rate for 24 hours. For

8°C/minute testing, the temperature chamber was rapidly

cycled between 85°C and 45°C for 8 hours, followed by

rapid cycling between –5°C and 45°C for 8 hours, and

lastly, rapid cycling between –40°C and 15°C for 8 hours.

MANAGER

As described in Application Time Synchronization, Eterna

provides two mechanisms for applications to maintain a

time base across a network. The synchronization perfor-

mance plots that follow were generated using the more

precise TIMEn input. Publishing rate is the rate a mote ap-

plication sends upstream data. Synchronization improves

as the publishing rate increases. Baseline synchronization

performance is provided for a network operating with a

publishing rate of zero. Actual performance for applica-

tions in network will improve as publishing rates increase.

All synchronization testing was performed with the 1-hop

mote inside a temperature chamber. Timing errors due

to temperature changes and temperature differences both

betweenthemanagerandthismoteandbetweenthismote

P1

P2

1 HOP

P3

2 HOP

D1

3 HOP

D2

5800IPR F08

Figure 8. Example Network Graph

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.5

5 HOPS

2.0

4 HOPS

1.5

3 HOPS

1.0

2 HOPS

0.5

0

1 HOP

0

5

15

20

25

30

10

0

10

15

20

25

30

5

PACKET RATE (PACKETS/s)

REPORTING INTERVAL (SEC)

5800IPR F07a

5800IPR F07b

Figure 7

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LTC5800-IPR

Typical perFormance characTerisTics

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

5 Hops, Room Temperature

14

12

60

30

25

20

15

10

5

µ = –0.2

σ = 1.7

N = 89699

µ = 0.0

µ = –0.2

σ = 3.6

N = 89698

σ = 0.9

50 N = 89700

10

40

30

20

10

8

6

4

2

0

10 20

SYNCHRONIZATION ERROR (µs)

10 20

SYNCHRONIZATION ERROR (µs)

–40 –30 –20 –10

0

30 40

–40 –30 –20 –10

0

30 40

–30 –20

40

–40

–10

0

10 20 30

SYNCHRONIZATION ERROR (µs)

5800IPR G01

5800IPR G02

5800IPR G03

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

1 Hop, 2°C/Min

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

3 Hops, 2°C/Min

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

5 Hops, 2°C/Min

14

12

7

6

20

15

10

5

µ = 1.5

µ = 0.9

µ = 1.0

σ = 3.3

σ = 3.9

σ = 7.7

N = 93812

N = 93846

N = 93845

10

5

8

6

4

2

4

3

2

1

0

–40 –30 –20 –10

0

10 20 30 40

SYNCHRONIZATION ERROR (µs)

–30 –20

40

–30 –20

–40

–10

0

10 20 30

–40

–10

0

10 20 30

SYNCHRONIZATION ERROR (µs)

5800IPR G04

5800IPR G05

5800IPR G06

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

1 Hop, 8°C/Min

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

3 Hops, 8°C/Min

TIMEn Synchronization Error

0 Packets/s Publishing Rate,

5 Hops, 8°C/Min

14

12

7

6

12

10

8

µ = 3.6

µ = 1.1

µ = 1.0

σ = 5.0

σ = 3.8

σ = 7.4

N = 88144

N = 88179

10

5

8

6

4

2

4

3

2

1

6

4

2

0

10 20

SYNCHRONIZATION ERROR (µs)

–40 –30 –20 –10

0

30 40

–30 –20

40

–30 –20

–40

–10

0

10 20 30

–40

–10

0

10 20 30

SYNCHRONIZATION ERROR (µs)

5800IPR G07

5800IPR G08

5800IPR G09

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LTC5800-IPR

Typical perFormance characTerisTics

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, Room Temperature

60

50

40

30

20

10

0

µ = –0.2

σ = 1.2

µ = 0.0

σ = 1.2

µ = –0.2

σ = 1.2

N = 17007

50 N = 22753

50 N = 17008

40

30

20

10

40

30

20

10

0

10 20

–40 –30 –20 –10

0

30 40

–40 –30 –20 –10

0

30 40

–40 –30 –20 –10

0

30 40

SYNCHRONIZATION ERROR (µs)

5800IPR G10

5800IPR G11

5800IPR G12

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 2°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 2°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 2°C/Min

35

30

35

30

45

40

35

30

25

20

15

10

5

µ = 0.5

µ = 0.1

σ = 1.9

σ = 1.5

N = 85860

N = 85855

N = 85858

25

20

15

10

5

20

15

10

5

0

10

–40 –30 –20 –10

20 30 40

–30 –20

40

–30 –20

40

–40

–10

0

10 20 30

–40

–10

0

10 20 30

SYNCHRONIZATION ERROR (µs)

5800IPR G14

5800IPR G13

5800IPR G15

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 8°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 8°C/Min

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 8°C/Min

60

50

40

30

20

10

0

50

40

30

20

10

0

60

50

40

30

20

10

0

µ = –1.0

σ = 1.3

µ = 0.0

µ = 0.2

σ = 1.3

σ = 1.4

N = 33929

N = 33930

N = 33932

10 20

–40 –30 –20 –10

SYNCHRONIZATION ERROR (µs)

10 20

–40 –30 –20 –10

SYNCHRONIZATION ERROR (µs)

0

30 40

0

30 40

10 20

–40 –30 –20 –10

SYNCHRONIZATION ERROR (µs)

0

30 40

5800IPR G17

5800IPR G18

5800IPR G16

5800iprfa

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LTC5800-IPR

Typical perFormance characTerisTics

AsdescribedintheSmartMeshNetworkOverview,devices

in network spend the vast majority of their time inactive

in their lowest power state (doze). On a synchronous

schedule a mote will wake to communicate with another

mote.Regularlyoccurringsequenceswhichwake,perform

a significant function and return to sleep are considered

atomic. These operations are considered atomic as the

sequence of events can not be separated into smaller

events while performing a useful function. For example,

transmission of a packet over the radio is an atomic op-

eration. Atomic operations may be characterized in either

charge or energy. In a time slot where a mote successfully

sends a packet, an atomic transmit includes setup prior

to sending the message, sending the message, receiving

the acknowledgment and the post processing needed as

a result of the message being sent. Similarly in a time slot

when a mote successfully receives a packet, an atomic

receive includes setup prior to listening, listening until the

startofthepackettransition, receivingthepacket, sending

the acknowledgement and post processing required due

to the arrival of the packet.

To ensure reliability each mote in the network is provided

multiple time slots for each packet it nominally will send

and forward. The time slots are assigned to communicate

upstream, towardsthemanager, withatleasttwodifferent

motes. When combined with frequency hopping this pro-

videstemporal,spatialandspectralredundancy.Giventhis

approach a mote will often listen for a message that it will

never receive since the time slot is not being used by the

transmitting mote. It has already successfully transmitted

the packet. Since typically 3 time slots are scheduled for

every1packettobesentorforwarded, moteswillperform

more of these atomic “Idle Listens” than atomic transmit

oratomicreceivesequences.Examplesoftransmit,receive

and idle listen atomic operations are shown in Figure 9.

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LTC5800-IPR

Typical perFormance characTerisTics

Atomic Operation—Maximum Length Transmit with Acknowledge, 7.25ms Time Slot (54.5µC Total Charge at 3.6V)

Atomic Operation—Maximum Length Receive with Acknowledge, 7.25ms Time Slot (32.6µC Total Charge at 3.6V)

Atomic Operation—Idle Listen, 7.25ms Time Slot (6.4µC Total Charge at 3.6V)

Figure 9

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LTC5800-IPR

pin FuncTions ^{Pin functions in italics are currently not supported in software.}

The following table organizes the pins by functional

groups. For those I/O with multiple functions the alternate

functions are shown on the second and third line in their

respective row. The NO column provides the pin number.

The second column lists the function. The TYPE column

lists the I/O type. The I/O column lists the direction of the

signal relative to Eterna. The PULL column shows which

signals have a fixed passive pull-up or pull-down. The

DESCRIPTION column provides a brief signal description.

NO POWER SUPPLY

TYPE

Power

I/O

–

-

PULL DESCRIPTION

P

2

3

4

5

6

7

8

9

GND

–

-

Ground Connection, P = QFN Paddle

CAP_PA_1P

CAP_PA_1M

CAP_PA_2M

CAP_PA_2P

CAP_PA_3P

CAP_PA_3M

CAP_PA_4M

CAP_PA_4P

PA DC/DC Converter Capacitor 1 Plus Terminal

PA DC/DC Converter Capacitor 1 Minus Terminal

PA DC/DC Converter Capacitor 2 Minus Terminal

PA DC/DC Converter Capacitor 2 Plus Terminal

PA DC/DC Converter Capacitor 3 Plus Terminal

PA DC/DC Converter Capacitor 3 Minus Terminal

PA DC/DC Converter Capacitor 4 Minus Terminal

PA DC/DC Converter Capacitor 4 Plus Terminal

Internal Power Amplifier Power Supply, Bypass

Regulated Analog Supply, Bypass

10 VDDPA

30 VDDA

31 VCORE

Regulated Core Supply, Bypass

32 VOSC

Regulated Oscillator Supply, Bypass

54 VPP

Internal Regulator Test Port

56 VPRIME

–

Internal Primary Power Supply, Bypass

57 CAP_PRIME_4P

58 CAP_PRIME_4M

59 CAP_PRIME_3M

60 CAP_PRIME_3P

61 CAP_PRIME_2P

62 CAP_PRIME_2M

63 CAP_PRIME_1M

64 CAP_PRIME_1P

65 VSUPPLY

Primary DC/DC Converter Capacitor 4 Plus Terminal

Primary DC/DC Converter Capacitor 4 Minus Terminal

Primary DC/DC Converter Capacitor 3 Minus Terminal

Primary DC/DC Converter Capacitor 3 Plus Terminal

Primary DC/DC Converter Capacitor 2 Plus Terminal

Primary DC/DC Converter Capacitor 2 Minus Terminal

Primary DC/DC Converter Capacitor 1 Minus Terminal

Primary DC/DC Converter Capacitor 1 Plus Terminal

Power Supply Input to Eterna

NO RADIO

TYPE

I/O

I

PULL DESCRIPTION

1

RADIO_INHIBIT

1 (Note 14)

–

Radio Inhibit

11 LNA_EN

1

–

O

–

External LNA Enable

12 RADIO_TX

13 RADIO_TXn

14 ANTENNA

Radio TX Active (External PA Enable/Switch Control)

Radio TX Active (External PA Enable/Switch Control), Active Low

Single-Ended Antenna Port, 50Ω

5800iprfa

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LTC5800-IPR

pin FuncTions ^{Pin functions in italics are currently not supported in software.}

NO CRYSTALS

TYPE

I/O

0

I

PULL DESCRIPTION

19 OSC_32K_XOUT

20 OSC_32K_XIN

28 OSC_20M_XIN

29 OSC_20M_XOUT

Crystal

–

32kHz Crystal Xout

32kHz Crystal Xin

20MHz Crystal Xin

20MHz Crystal Xout

I

0

NO RESET

TYPE

I/O

PULL DESCRIPTION

22 RESETn

1

0

UP

Reset Input, Active Low

NO JTAG

23 TDI

TYPE

I/O

PULL DESCRIPTION

1

I

O

I

UP

–

JTAG Test Data In

24 TDO

25 TMS

26 TCK

JTAG Test Data Out

JTAG Test Mode Select

UP

I

DOWN JTAG Test Clock

NO SPECIAL PURPOSE

TYPE

I/O

PULL DESCRIPTION

72 TIMEn

1 (Note 14)

I

–

Time Capture Request, Active Low

NO CLI and EXTERNAL MEMORY

33 EB_DATA_7

TYPE

I/O

PULL DESCRIPTION

1

2

–

External Bus Data Bit 7

34 EB_DATA_6

External Bus Data Bit 6

External Bus Data Bit 4

External Bus Data Bit 0

CLI UART 0 Transmit

35 EB_DATA_4

36 EB_DATA_0

37 UARTC0_TX

EB_IO_LE0

O

External Bus I/O Latch Enable 0 for External Address Bits A[25:18]

38 UARTC0_RX

EB_DATA_1

1

I

–

CLI UART 0 Receive

External Bus Data Bit 1

I/O

39 EB_IO_LE2

41 EB_ADDR_1

43 EB_ADDR_0

46 EB_DATA_3

47 EB_DATA_2

48 EB_DATA_5

49 EB_IO_CS0n

50 UARTC1_TX

51 UARTC1_RX

52 EB_IO_WEn

53 EB_IO_OEn

1

2

1

2

1

2

O

–

External Bus I/O Latch Enable 2 for External Address Bits A[9:2]

External Bus Address Bit 1

External Bus Address Bit 0

External Bus Data Bit 3

O

I/O

O

External Bus Data Bit 2

External Bus Data Bit 5

External Bus Chip Select 0

O

CLI UART 1 Transmit

I

CLI UART 1 Receive

O

External Bus Write Enable Strobe

External Bus Output Enable Strobe

O

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LTC5800-IPR

pin FuncTions ^{Pin functions in italics are currently not supported in software.}

NO IPCS SPI/FLASH PROGRAMMING (NOTE 15)

TYPE

I/O

PULL DESCRIPTION

40 IPCS_MISO

2

1

O

I

–

SPI Flash Emulation (MISO) Master In Slave Out Port

42 IPCS_MOSI

SPI Flash Emulation (MOSI) Master Out Slave In Port

SPI Flash Emulation (SCK) Serial Clock Port

SPI Flash Emulation Slave Select, Active Low

44 IPCS_SCK

I

45 IPCS_SSn

I

55 FLASH_P_ENn

EB_IO_LE1

I

O

UP

Flash Program Enable, Active Low

External Bus I/O Latch Enable 1 for External Address Bits A[17:10]

NO API UART

TYPE

I/O

I

PULL DESCRIPTION

66 UART_RX_RTSn

67 UART_RX_CTSn

68 UART_RX

1 (Note 14)

–

UART Receive (RTS) Request to Send, Active Low

1

O

I

UART Receive (CTS) Clear to Send, Active Low

UART Receive

1 (Note 14)

69 UART_TX_RTSn

70 UART_TX_CTSn

71 UART_TX

1

O

I

UART Transmit (RTS) Request to Send, Active Low

UART Transmit (CTS) Clear to Send, Active Low

UART Transmit

1 (Note 14)

2

O

Note 14: These inputs are always enabled and must be driven or pulled to

a valid state to avoid leakage.

Note 15: Embedded programming over the IPCS SPI bus is only avaliable

when RESETn is asserted.

VSUPPLY: System and I/O Power Supply. Provides power

to the chip including the on-chip DC/DC converters. The

digital-interface I/O voltages are also set by this voltage.

Bypasswith2.2µFand0.1µFtoensuretheDC/DCconvert-

ers operate properly.

VBGAP: Bandgap reference output. Used for testing and

calibration. Do not connect anything to this pin.

CAP_PA_1P, CAP_PA_1M Through CAP_PA_4P, CAP_

PA_4M: Dedicated Power Amplifier DC/DC Converter

Capacitor Pins. These pins are used when the radio is

transmitting to efficiently convert VSUPPLY to the proper

voltage for the power amplifier. A 56nF capacitor should

be connected between each P and M pair. Trace length

should be as short as feasible.

VDDPA: PA-Converter Bypass Pin. A 0.47µF capacitor

should be connected from VDDPA to ground with as short

atraceasfeasible.Donotconnectanythingelsetothispin.

VDDA: Analog-Regulator Bypass Pin. A 0.1µF capacitor

should be connected from VDDA to ground with as short a

trace as feasible. Do not connect anything else to this pin.

CAP_PRIME_1P, CAP_PRIME_1M Through

CAP_PRIME_4P, CAP_PRIME_4M: Primary DC/DC Con-

verterCapacitorPins.Thesepinsareusedwhenthedevice

is awake to efficiently convert VSUPPLY to the proper

voltage for the three on-chip low dropout regulators. A

56nF capacitor should be connected between each P and

M pair. Trace length should be as short as feasible.

VCORE: Core-Regulator Bypass Pin. A 56nF capacitor

should be connected from VCORE to ground with as short

atraceasfeasible.Donotconnectanythingelsetothispin.

VOSC: Oscillator-Regulator Bypass Pin. A 56nF capacitor

should be connected from VOSC to ground with as short a

trace as feasible. Do not connect anything else to this pin.

ANTENNA: Multiplexed Receiver Input and Transmitter

Output Pin. The impedance presented to the antenna

pin should be 50Ω, single-ended with respect to paddle

ground. To ensure regulatory compliance of the final

productpleaseseetheEternaIntegrationGuideforfiltering

requirements. The antenna pin should not have a DC path

toground;ACblockingmustbeincludedifaDC-grounded

VPP: Manufacturing Test port for internal regulator. Do

not connect anything to this pin.

VPRIME:Primary-ConverterBypassPin.A0.22µFcapaci-

tor should be connected from VPRIME to ground with as

short a trace as feasible. Do not connect anything else

to this pin.

antenna is used.

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LTC5800-IPR

pin FuncTions

OSC_32K_XOUT: Output Pin for the 32kHz Oscillator.

Connect to 32kHz quartz crystal. The OSC_32K_XOUT

and OSC_32K_XIN traces must be well-shielded from

other signals, both on the same PCB layer and lower PCB

layers, as shown in Figure 10.

OSC_32K_XIN: Input for the 32kHz Oscillator. Con-

nect to 32kHz quartz crystal. The OSC_32K_XOUT and

OSC_32K_XIN traces must be well-shielded from other

signals, both on the same PCB layer and lower PCB layers,

as shown in Figure 10.

OSC_20M_XOUT: Output for the 20MHz Oscillator.

Connect only to a supported 20MHz quartz crystal. The

OSC_20M_XOUT and OSC_20M_XIN traces must be

well-shielded from other signals, both on the same PCB

layer and lower PCB layers, as shown in Figure 10. See

the Eterna Integration Guide for supported crystals.

OSC_20M_XIN: Input for the 20MHz Oscillator. Connect

onlytoasupported20MHzquartzcrystal. TheOSC_20M_

XOUT and OSC_20M_XIN traces must be well-shielded

from other signals, both on the same PCB layer and lower

PCB layers, as shown in Figure 10.

Figure 10. PCB Top Metal Layer Shielding of Crystal Signals

RESETn:Theasynchronousresetsignalisinternallypulled

up. Resetting Eterna will result in the ARM Cortex M3

rebooting and loss of network connectivity. Use of this

signal for resetting Eterna is not recommended, except

during power-on and in-circuit programming.

TMS, TCK, TDI, TDO: JTAG Port Supporting Software

Debug and Boundary Scan. An IEEE Std 1149.1b-1994

compliant boundary scan definition language (BDSL) file

for the WR QFN72 package can be found here.

SLEEPn: The SLEEPn function is not currently supported

in software. The SLEEPn input must either be tied, pulled

or actively driven high to avoid excess leakage.

RADIO_INHIBIT: The radio inhibit function is currently

not supported by software. RADIO_INHIBIT provides a

mechanism for an external device to temporarily disable

radiooperation.Failuretoobservethetimingrequirements

defined in the RADIO_INHIBIT AC Characteristics table

may result in unreliable network operation. In designs

where the RADIO_INHIBIT function is not needed the

input must either be tied, pulled or actively driven low to

avoid excess leakage.

UART_RX,UART_RX_RTSn,UART_RX_CTSn,UART_TX,

UART_TX_RTSn,UART_TX_CTSn:TheAPIUARTinterface

includes bidirectional wake-up and flow control. Unused

inputsignalsmustbedrivenorpulledtotheirinactivestate.

TIMEn: Strobing the TIMEn input is the most accurate

method to acquire the network time maintained by Eterna.

Eternalatchesthenetworktimestampwithsub-microsec-

ond resolution on the rising edge of the TIMEn signal and

produces a packet on the API serial port containing the

timing information.

LNA_ENABLE, RADIO_TX, RADIO_TXn: Control signals

generatedbytheautonomousMACsupportingtheintegra-

tionofanexternalLNA/PA.SeetheEternaExtendedRange

Reference Design for implementation details.

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UARTC0_RX, UARTC0_TX, UARTC1_RX, UARTC1_TX:

The CLI UART provides a mechanism for monitoring,

configuration and control of Eterna during operation. On

the LTC5800-IPR CLI UART 0 is used when Eterna is not

configured to support external RAM and CLI UART 1 is

used when Eterna is configured to support external RAM.

For a complete description of the supported commands

see the SmartMesh IP Manager CLI Guide.

latch signal, EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 will

strobe to latch 8-bits of address from the EB_DATA[7:0]

bus.EB_IO_LE0,EB_IO_LE1,andEB_IO_LE2correspond

to address bits [25:18], [17:10] and [9:2] respectively.

EB_ADDR_0 and EB_ADDR_1 correspond to the lower

two bits of address. For systems with 256kB or less

EB_IO_LE2canbeignored.EB_IO_CS0n,EB_IO_WEnand

EB_IO_OEn provide chip select, write enable and output

enable control of the external RAM.

EB_DATA_0 through EB_DATA_7, EB_ADDR_0, EB_

ADDR_1, EB_IO_LE1 through EB_IO_LE2, EB_IO_CS0n,

EB_IO_WEn, EB_IO_ENn: The external bus provides a

multiplexed address data bus enabling the Cortex-M3

direct access of external byte wide RAM. The additional

RAM is used by network management software enabling

thesupportofalargernetworkofmoteswithhigherpacket

throughput. To support the addressing needed, each

FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,

IPCS_SSn: The in-circuit programming control system

(IPCS)busenablesin-circuitprogrammingofEterna’sflash

memory. IPCS_SCK is a clock and should be terminated

appropriately for the driving source to prevent overshoot

and ringing.

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The LTC5800 is the world’s most energy-efficient IEEE

802.15.4 compliant platform, enabling battery and en-

ergy harvested applications. With a powerful 32-bit ARM

Cortex-M3, best-in-class radio, flash, RAM and purpose-

built peripherals, Eterna provides a flexible, scalable and

robust networking solution for applications demanding

minimal energy consumption and data reliability in even

the most challenging RF environments.

POWER SUPPLY

Eterna is powered from a single pin, VSUPPLY, which

powers the I/O cells and is also used to generate internal

supplies.Eterna’stwoon-chipDC/DCconvertersminimize

energy consumption while the device is awake. To con-

serve power the DC/DC converters are disabled when the

device is in low power state. The integrated power supply

conditioningarchitecture,includingthetwointegratedDC/

DC converters and three integrated low dropout regula-

tors, provides excellent rejection of supply noise. Eterna’s

operating supply voltage range is high enough to support

Shown in Figure 11, Eterna integrates purpose-built

peripherals that excel in both low operating-energy con-

sumption and the ability to rapidly and precisely cycle

between operating and low-power states. Items in the

gray shaded region labeled Analog Core correspond to

the analog/RF components.

direct connection to lithium-thionyl chloride (Li-SOCl )

2

sources and wide enough to support battery operation

over a broad temperature range.

32kHz

DIGITAL CORE

ANALOG CORE

32kHz, 20MHz

TIMERS

SCHED

VOLTAGE REFERENCE

PRIMARY

CORE REGULATOR

CLOCK REGULATOR

ANALOG REGULATOR

DC/DC

SRAM

72kB

CONVERTER

PMU/

RELAXATION

OSCILLATOR

FLASH

512kB

CLOCK

CONTROL

PA

DC/DC

CONVERTER

PoR

20MHz

FLASH

CONTROLLER

802.15.4

MOD

LPF

DAC

AES

PA

CODE

802.15.4

FRAMING

DMA

PLL

AUTO

MAC

802.15.4

DEMOD

BPF

PPF

LNA

ADC

LIMITER

AGC

SYSTEM

RSSI

BAT

LOAD

IPCS

SPI

SLAVE

CLI

UART

(2 PIN)

API

ADC

CTRL

10-BIT

ADC

UART

(6 PIN)

VGA

PTAT

4-BIT

DAC

5800IPR F09

Figure 11. Eterna Block Diagram

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SUPPLY MONITORING AND RESET

APPLICATION TIME SYNCHRONIꢀATION

Eterna integrates a power-on-reset (PoR) circuit. As the

RESETn input pin is nominally configured with an internal

pull-up resistor, no connection is required. For a graceful

shutdown, the software and the networking layers should

be cleanly halted via API commands prior to assertion of

theRESETnpin.SeetheSmartMeshIPManagerAPIGuide

for details on the disconnect and reset commands. Eterna

includes a soft brown-out monitor that fully protects the

flash from corruption in the event that power is removed

while writing to flash. The integrated flash supervisory

functionality,inconjunctionwithafaulttolerantfilesystem,

yields a robust nonvolatile storage solution.

In addition to coordinating time slots across the network,

which is transparent to the user, Eterna’s timing manage-

mentisusedtosupporttwomechanismstosharenetwork

time. Having an accurate, shared, network-wide time base

enables events to be accurately time stamped or tasks to

be performed in a synchronized fashion across a network.

Eterna will send a time packet through its serial interface

when one of the following occurs:

n

Eterna receives an API request to read time

n

The TIMEn signal is asserted

The use of TIMEn has the advantage of being more accu-

rate. The value of the time stamp is captured in hardware

relative to the rising edge of TIMEn. If an API request

is used, due to packet processing, the value of the time

stamp may be captured several milliseconds after receipt

of the packet. See the TIMEn AC Characteristics table for

the TIMEn function’s definition and specifications.

PRECISION TIMING

Eterna’s unique low power dedicated timing hardware and

timing algorithms provide a significant improvement over

competing 802.15.4 product offerings. This functionality

providestimingprecisiontwotothreeordersofmagnitude

better than any other low power solution available at the

timeofpublication.Improvedtimingaccuracyallowsmotes

to minimize the amount of radio listening time required

to ensure packet reception thereby lowering even further

the power consumed by SmartMesh networks. Eterna’s

patented timing hardware and timing algorithms provide

superior performance over rapid temperature changes,

further differentiating Eterna’s reliability when compared

with other wireless products. In addition, precise timing

enablesnetworkstoreducespectraldeadtime, increasing

total network throughput.

TIME REFERENCES

Eterna includes three clock sources: an internal relaxation

oscillator,alowpoweroscillatordesignedfora32.768kHz

crystal, and the radio reference oscillator designed for a

20MHz crystal.

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Relaxation Oscillator

RADIO

Eterna includes the lowest power commercially available

2.4GHz IEEE 802.15.4e radio by a substantial margin.

(Please refer to Radio Specifications section for power

consumption numbers.) Eterna’s integrated power ampli-

fier is calibrated and temperature compensated to con-

sistently provide power at a limit suitable for worldwide

radio certifications. Additionally, Eterna uniquely includes

a hardware-based autonomous MAC that handles precise

sequencing of peripherals, including the transmitter, the

receiver, and advanced encryption standard (AES) pe-

ripherals.Thehardware-basedautonomousmediaaccess

controller (MAC) minimizes CPU activity, thereby further

decreasing power consumption.

The relaxation oscillator is the primary clock source for

Eterna, providing the clock for the CPU, memory subsys-

tems, and all peripherals. The internal relaxation oscillator

is dynamically calibrated to 7.3728MHz. The internal re-

laxation oscillator typically starts up in a few μs, providing

anexpedient, lowenergymethodfordutycyclingbetween

active and low power states. Quick start-up from the doze

state,definedintheStateDiagramsection,allowsEternato

wakeupandreceivedataovertheUARTandSPIinterfaces

by simply detecting activity on the appropriate signals.

32.768kHz Crystal Oscillator

Once Eterna is powered up and the 32.768kHz crystal

source has begun oscillating, the 32.768kHz crystal re-

mains operational while in the Active state, and is used as

thetimingbasiswheninDozestate. SeetheStateDiagram

section, for a description of Eterna’s operational states.

UARTS

The principal network interface is through the application

programming interface (API) UART. A command-line in-

terface (CLI) UART is also provided for support of test and

debug functions. Both UARTs sense activity continuously,

consumingvirtuallynopoweruntildataistransferredover

the port and then automatically returning to their lowest

power state after the conclusion of a transfer. The defini-

tion for packet encoding on the API UART interface can

be found in the SmartMesh IP Manager API Guide and the

CLI command definitions can be found in the SmartMesh

IP Manager CLI Guide.

20MHz Crystal Oscillator

The 20 MHz crystal source provides a frequency refer-

ence for the radio, and is automatically enabled and

disabled by Eterna as needed. Eterna requires specific

characterized 20MHz crystal references. See the Eterna

Integration Guide for a complete list of the currently

supported 20MHz crystals.

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API UART Protocols

packet. Following the transmission of the final byte in the

packet,thecompanionprocessornegatesUART_RX_RTSn

and waits until the negation of UART_RX_CTSn before

asserting UART_RX_RTSn again.

The API UART supports multiple modes with the goal of

supporting a wide range of companion multipoint control

units (MCUs) while reducing power consumption of the

system. Asageneralrule, higherserialdataratestranslate

intolowerenergyconsumptionforbothendpoints.TheAPI

UARTreceiveprotocolincludestwoadditionalsignalsinad-

ditiontoUART_RX:UART_RX_RTSnandUART_RX_CTSn.

The transmit half of the API UART protocol includes two

additionalsignalsinadditiontoUART_TX:UART_TX_RTSn

and UART_TX_CTSn. The two supported protocols are

referred to as UART Mode 2 and UART Mode 4. Mode

setting is controlled via the Fuse Table.

The flow control signals for Eterna’s API transmit path

are shown in Figure 13, UART Mode 2 Transmit Flow

Control. Transfers are initiated by Eterna asserting

UART_TX_RTSn. The companion processor responds

by asserting UART_TX_CTSn when ready to receive data.

After detecting the falling edge of UART_TX_CTSn Eterna

sends the entire packet. Following the transmission of the

final byte in the packet Eterna negates UART_TX_RTSn

and waits until the negation of UART_TX_CTSn before as-

serting UART_TX_RTSn again. The companion processor

may negate UART_TX_CTSn any time after the first byte

is transferred provided the timeout from UART_TX_RTSn

In the Figures accompanying the protocol descriptions,

signals driven by the companion processor are drawn

in black and signals driven by Eterna are drawn in blue.

to UART_TX_CTSn, t , is met.

END_TX_RTS to TX_CTS

UART Mode 2

UART_TX_RTSn

UART_TX_CTSn

UART_TX

UART Mode 2 provides the most energy-efficient method

for operating Eterna’s API UART. UART Mode 2 requires

the use of all six UART signals, but does not require

adherence to the minimum inter-packet delay as defined

in section UART AC Characteristics. UART Mode 2 in-

corporates edge-sensitive flow control, at either 9600

or 115200 baud. Packets are HDLC encoded with one

stop bit and no parity bit. The flow control signals for

Eterna’s API receive path are shown in Figure 12, UART

Mode 2 Receive Flow Control. Transfers are initiated by

the companion processor asserting UART_RX_RTSn.

Eterna then responds by enabling the UART and assert-

ing UART_RX_CTSn. After detecting the assertion of

UART_RX_CTSnthecompanionprocessorsendstheentire

BYTE 0

BYTE 1

5800IRP F13

Figure 13. UART Mode 2 Transmit Flow Control

UART Mode 4

UART Mode 4 incorporates level-sensitive flow control

on the TX channel and requires no flow control on the

RX channel, supporting 115200 baud. The use of level-

sensitive flow control signals enables the option of using

a reduced set of the flow control signals; however, Mode

4 has specific limitations. First, The use of the RX flow

control signals (UART_RX_RTSn and UART_RX_CTSn)

for Mode 4 are optional provided the use is limited to the

industrial temperature range (–40°C to 85°C); otherwise,

the flow control is mandatory. If RX flow control signals

are not used, UART_RX_RTSn should be tied to VSUPPLY

(inactive)andUART_RX_CTSnshouldbeleftunconnected.

UART_RX_RTSn

UART_RX_CTSn

UART_RX

BYTE 0

BYTE 1

5800IRP F12

Figure 12. UART Mode 2 Receive Flow Control

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Second, unless the companion processor is always ready

toreceiveapacket, thecompanionprocessormustnegate

UART_TX_CTSn prior to the end of the current packet.

Failure to negate UART_TX_CTSn prior to the end of a

packet may result in back to back packets. Third, the

AUTONOMOUS MAC

Eterna was designed as a system solution to provide a

reliable, ultralow power, and secure network. A reliable

network capable of dynamically optimizing operation

over changing environments requires solutions that are

far too complex to completely support through hardware

acceleration alone. As described in the Precision Timing

section,propertimemanagementisessentialforoptimizing

a solution that is both low power and reliable. To address

theserequirementsEternaincludestheautonomousMAC,

which incorporates a coprocessor for controlling all of

the time-critical radio operations. The autonomous MAC

provides two benefits: first, preventing variable software

latency from affecting network timing and second, greatly

reducing system power consumption by allowing the CPU

to remain inactive during the majority of the radio activity.

The autonomous MAC provides software-independent

timing control of the radio and radio-related functions,

resultinginsuperiorreliabilityandexceptionallylowpower.

companion processor must wait at least t

RX_INTERPACKET

betweentransmittingpacketsonUART_RX. SeetheUART

AC Characteristics section for complete timing specifica-

tions. Packets are HDLC encoded with one stop bit and no

parity bit. The flow control signals for the TX channel are

showninFigure17.TransfersareinitiatedbyEternaassert-

ing UART_TX_RTSn. The UART_TX_CTSn signal may be

activelydrivenbythecompanionprocessorwhenreadyto

receive a packet or UART_TX_CTSn may be tied low if the

companion processor is always ready to receive a packet.

Afterdetectingalogic‘0’onUART_TX_CTSn,Eternasends

the entire packet. Following the transmission of the final

byte in the packet, Eterna negates UART_TX_RTSn and

waits for t

, defined in the UART AC Charac-

TX_INTERPACKET

teristics section before asserting UART_TX_RTSn again.

For details on the timing of the UART protocol, see section

UART AC Characteristics.

SECURITY

Network security is an often overlooked component of

a complete network solution. Proper implementation of

security protocols is significant in terms of both engineer-

ing effort and market value in an OEM product. Eterna

system solutions provide a FIPS-140 compliant encryp-

tion scheme that includes authentication and encryption

at the MAC and network layers with separate keys for

each mote. This not only yields end-to-end security, but

if a mote is somehow compromised, communication

from other motes is still secure. A mechanism for secure

key exchange allows keys to be kept fresh. To prevent

physical attacks, Eterna includes hardware support for

electronically locking devices, thereby preventing access

to Eterna’s flash and RAM memory and thus the keys and

code stored therein. This lock-out feature also provides

a means to securely unlock a device should support of a

product require access. For details see the Board Specific

Configuration Guide.

UART_TX_RTSn

UART_TX_CTSn

UART_TX

BYTE 0

BYTE 1

5800IRP F14

Figure 14. UART Mode 4 Transmit Flow Control

CLI UART

The command line interface (CLI) UART port is a 2-wire

protocol(TXandRX)thatoperatesatafixed9600baudrate

with one stop bit and no parity. The CLI UART interface is

intendedtosupportcommandlineinstructionsandresponse

activity. The pins used for the CLI UART change when the

Eterna is configured to use external SRAM. The CLI UART

is assigned to UARTC0 when external SRAM is not used

and assigned to UARTC1 when external SRAM is used.

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TEMPERATURE SENSOR

FLASH DATA RETENTION

Eterna includes a calibrated temperature sensor on chip.

The temperature readings are available locally through

Eterna’s serial API, in addition to being available via the

network manager. The performance characteristics of

the temperature sensor can be found in the Temperature

Sensor Characteristics table.

Eterna contains internal flash (non-volatile memory) to

store calibration results, unique ID, configuration settings

and software images. Flash retention is specified over the

operatingtemperaturerange.SeeElectricalCharacteristics

and Absolute Maximum Ratings sections.

Non destructive storage above the operating temperature

range of –55°C to 105°C is possible; however, this may

result in a degradation of retention characteristics.

RADIO INHIBIT

The RADIO_INHIBIT input enables an external control-

ler to temporarily disable the radio software drivers (for

example, to take a sensor reading that is susceptible to

radio interference). When RADIO_INHIBIT is asserted

the software radio drivers will disallow radio operations

including clear channel assessment, packet transmits,

or packet receipts. If the current time slot is active when

RADIO_INHIBIT is asserted the radio will be disabled after

the present operation completes. For details on the timing

associated with RADIO_INHIBIT, see the RADIO_INHIBIT

AC Characteristics table.

Thedegradationinflashretentionfortemperatures>105°C

can be approximated by calculating the dimensionless

acceleration factor using the following equation.

⎡

⎢

⎤

⎥

⎦

⎛

⎞

Ea

k

1

⎛

⎞

•

–

⎜

⎟

⎠

⎜

⎟

AF = e ^⎣⎝

T

_USE+273 T_STRESS+273

⎝

⎠

where:

AF = acceleration factor

Ea = activation energy = 0.6eV

–5

k = 8.625 • 10 eV/°K

FLASH PROGRAMMING

T

= is the specified temperature retention in °C

USE

Thisproductisprovidedwithoutsoftwareprogrammedinto

the device. OEMs will need to program software images

duringdevelopmentandmanufacturing.Eterna’ssoftware

images are loaded via the in-circuit programming control

system (IPCS) SPI interface. Sequencing of RESETn and

FLASH_P_ENn, as described in the Flash SPI Slave A/C

Characteristics table, places Eterna in a state emulating a

serial flash to support in-circuit programming. Hardware

and software for supporting development and produc-

tion programming of devices is described in the Eterna

Serial Programmer Guide. The serial protocol, SPI, and

timing parameters are described in the Flash SPI Slave

A/C Characteristics table.

= actual storage temperature in °C

STRESS

Example: Calculate the effect on retention when storing

at a temperature of 125°C.

T

= 125°C

STRESS

= 85°C

USE

AF = 7.1

So the overall retention of the flash would be degraded

by a factor of 7.1, reducing data retention from 20 years

at 85°C to 2.8 years at 125°C.

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NETWORKING

devices using Eterna’s industry-leading low power radio

technology, deterministic power management enables

over a decade of battery life for network motes.

The LTC5800-IPR network manager provides the ingress/

egress point at the wired to wireless mesh network

boundary via the API UART interface. The complexity of

the mesh network management is handled entirely within

the embedded software, which also provides dynamic

network optimization, deterministic power management,

intelligent routing, and configurable bandwidth allocation

while achieving carrier class data reliability and low power

operation.

Intelligent Routing

Intelligent routing provides each packet with an optimal

path through the network. The shortest distance between

two points is a straight line, but in RF the quickest path is

notalwaystheonewiththefewesthops.Intelligentrouting

finds optimal paths by considering the link quality (one

path may lose more packets than another) and the retry

schedule, in addition to the number of hops. The result

is reduced network power consumption, elimination of

in-network collisions, and unmatched network scalability

and reliability.

Dynamic Network Optimization

DynamicnetworkoptimizationallowsEternatoaddressthe

changing RF requirements in harsh environments result-

ing in a network that is continuously self-monitoring and

self-adjusting. The manager performs dynamic network

optimizationbaseduponperiodicreportsonnetworkhealth

and link quality that it receives from the network motes.

Themanagerusesthisinformationtoprovideperformance

statistics to the application layer and proactively solve

connectivity problems in the network. Dynamic network

optimization not only maintains network health, but also

allowsEternatodeliverdeterministicpowermanagement.

One of the key advantages of SmartMesh networking so-

lutions is the network manager is aware of and tracking

the success or failure of every packet transaction, so not

only can the network be optimized, but the solution can

be rigorously tested to produce a system solution with

better than 99.999% reliability.

Configurable Bandwidth Allocation

SmartMesh networks provide configurations that enable

users to make bandwidth and latency versus power trade-

offs both network wide and on a per device basis. This

flexibility enables solutions that tailored to the application

requirements, such as request/response, fast file trans-

fer, and alerting. Relevant configuration parameters are

described in the SmartMesh IP User’s Guide. The Design

trade-offs between network performance and current

consumption are supported via the SmartMesh Power

and Performance Estimator.

IP Manager Options

The IP Manager can operate with or without external

SRAM, asdescribedintheEternaIntegrationGuide. When

used without external SRAM, the IP manager is limited to

managing networks of 32 motes or fewer and is limited to

a maximum packet throughput of 24 packets per second.

With external SRAM, the IP Manager supports managing

networks of up to 100 motes and the packet throughput

of the IP Manager increases from 24 packets per second

without SRAM to 36 packets per second with SRAM.

Deterministic Power Management

Deterministic power management balances traffic in the

network by diverting traffic around heavily loaded motes

(for example, motes with high reporting rates). In do-

ing so, it reduces power consumption for these motes

and balances power consumption across the network.

Deterministic power management provides predictable

maintenance schedules to prevent down time and lower

the cost of network ownership. When combined with field

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STATE DIAGRAM

Serial Flash Emulation

In order to provide capabilities and flexibility in addition

to ultra low power, Eterna operates in various states, as

shown in Figure 15, and described in this section. State

transitions shown in red are not recommended.

When both RESETn and FLASH_P_ENn are asserted,

Eterna disables normal operation and enters a mode to

emulate the operation of a serial flash. In this mode, its

flash can be programmed.

Fuse Table

Operation

Eterna’s Fuse Table is a 2kB page in flash that contains

two data structures. One structure supports hardware

configuration immediately following power-on reset or

the assertion of RESETn. The second structure supports

configurationofsoftwareboardsupportparameters. Fuse

Tables are generated via the Fuse Table application de-

scribedintheBoardSpecificConfigurationGuide.Hardware

configuration of I/O immediately following power-on reset

providesamethodtominimizeleakageduetofloatingnets

prior to software configuration. I/O leakage can contribute

hundredsofmicroamperesofleakageperinput,potentially

stressing current limited supplies. Examples of software

boardsupportparametersincludesettingofUARTmodes,

clock sources and trim values. Fuse Tables are loaded into

flash using the same software and in-circuit programmer

used to load software images as described in the Eterna

Serial Programmer Guide.

Once Eterna has completed start-up Eterna transitions to

the Operational group of states (active/CPU active, active/

CPU inactive, and Doze). There, Eterna cycles between the

various states, automatically selecting the lowest pos-

sible power state while fulfilling the demands of network

operation.

Active State

IntheActiveState, Eterna’srelaxationoscillatorisrunning

andperipheralsareenabledasneeded.TheARMCortex-M3

cycles between CPU-active and CPU-inactive (referred to

in the ARM Cortex-M3 literature as “Sleep Now” mode).

Eterna’s extensive use of DMA and intelligent peripherals

that independently move Eterna between Active state and

Doze state minimizes the time the CPU is active, signifi-

cantly reducing Eterna’s energy consumption.

Doze State

Start-Up

The Doze state consumes orders of magnitude less cur-

rent than the Active state and is entered when all of the

peripherals and the CPU are inactive. In the Doze state

Eterna’s full state is retained, timing is maintained, and

Eterna is configured to detect, wake, and rapidly respond

to activity on I/Os (such as UART signals and the TIMEn

pin). In the Doze state the 32.768kHz oscillator and as-

sociated timers are active.

Start-upoccurs asaresult ofeither crossingthepower-on

reset threshold or asserting RESETn. After the comple-

tion of power-on reset or the falling edge of an internally

synchronized RESETn, Eterna loads its Fuse Table which,

as described in the previous section, includes configuring

I/O direction. In this state, Eterna checks the state of the

FLASH_P_ENn and RESETn pins and enters the serial

flash emulation mode if both signals are asserted. If the

FLASH_P_ENnpinisnotassertedbutRESETnisasserted,

Eterna automatically reduces its energy consumption to

a minimum until RESETn is released. Once RESETn is

de-asserted, Eterna goes through a boot sequence, and

then enters the Active state.

5800iprfa

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LTC5800-IPR

operaTion

POWER-ON

RESET

VSUPPLY > PoR

RESETn LOW AND

FLASH_P_ENn LOW

LOAD FUSE

SETTINGS

SET RESETn HIGH AND

FLASH_P_ENn HIGH

FOR 125µs, THEN

SERIAL FLASH

EMULATION

SET RESETn LOW

RESETn LOW AND

FLASH_P_ENn HIGH

RESETn HIGH

AND

FLASH_P_ENn

HIGH

RESET

DEASSERT

RESETn

BOOT

START-UP

ASSERT RESETn ASSERT RESETn

ASSERT RESETn

CPU AND

PERIPHERALS

INACTIVE

CPU

ACTIVE

DEEP SLEEP

DOZE

CPU

INACTIVE

LOW POWER SLEEP

COMMAND

HW OR PMU EVENT

OPERATION

INACTIVE

5800IPR F15

Figure 15. Eterna State Diagram

5800iprfa

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For more information www.linear.com/LTC5800-IPR

LTC5800-IPR

applicaTions inFormaTion

REGULATORY AND STANDARDS COMPLIANCE

The RoHS-compliant design features include:

n

RoHS-compliant solder for solder joints

Radio Certification

n

RoHS-compliant base metal alloys

Eterna is suitable for systems targeting compliance with

worldwide radio frequency regulations: ETSI EN 300 328

and EN 300 440 class 2 (Europe), FCC CFR47 Part 15

(US), and ARIB STD-T66 (Japan). Application Program-

ming Interfaces (APIs) supporting regulatory testing are

provided on both the API and CLI UART interfaces. The

Eterna Certification User Guide provides:

n

RoHS-compliant precious metal plating

n

RoHS-compliant cable assemblies and connector

choices

n

Lead-free QFN package

n

Halogen-free mold compound

n

Reference information required for certification

n

RoHS-compliant and 245 °C re-flow compatible

n

Test plans for common regulatory test cases

Note: Customers may elect to use certain types of lead-

free solder alloys in accordance with the European Com-

munity directive 2002/95/EC. Depending on the type of

solder paste chosen, a corresponding process change to

optimize reflow temperatures may be required.

n

Example CLI API calls

Sample manual language and example label

Compliance to Restriction of Hazardous Substances

(RoHS)

SOLDERING INFORMATION

RestrictionofHazardousSubstances(RoHS)isadirective

that places maximum concentration limits on the use of

cadmium (Cd), lead (Pb), hexavalent chromium (Cr ),

mercury (Hg), Polybrominated Biphenyl (PBB), and Poly-

brominated Diphenyl Ethers (PBDE). Linear Technology is

committed to meeting the requirements of the European

Community directive 2002/95/EC.

EternaissuitableforbotheutecticPbSnandRoHS-6reflow.

The maximum reflow soldering temperature is 260 ºC. A

moredetaileddescriptionoflayoutrecommendations, as-

sembly procedures and design considerations is included

in the Eterna Integration Guide.

+6

This product has been specifically designed to utilize

RoHS-compliant materials and to eliminate or reduce the

use of restricted materials to comply with 2002/95/EC.

5800iprfa

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LTC5800-IPR


型号：	LTC5800IWR-IPRB#PBF
厂家：	Linear
描述：	LTC5800-IPM - SmartMesh IP Wireless 802.15.4e System-on-Chip; Package: QFN; Pins: 72; Temperature Range: -40°C to 85°C 无线电信电信集成电路
文件：	总36页 (文件大小：1106K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC5800IWR-IPRB#PBF [Linear]

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