LTC4556EUF [Linear]
Smart Card Interface with Serial Control; 与串行控制智能卡接口
| 型号： | LTC4556EUF |
| 厂家： | 
Linear |
| 描述： | Smart Card Interface with Serial Control |
| 文件： | 总20页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4556
Smart Card Interface
with Serial Control
U
FEATURES
DESCRIPTIO
The LTC®4556 provides all necessary power control, level
translation and supervisory functions for a smart card or
S.A.M.cardinterface.Thepartcontainsalownoisecharge
pump** plus LDO for generating VCC power, as well as all
necessary level shifting circuitry.
■
Electrical Specifications Are ISO7816-3 and EMV
Compatible
■
Control/Status Serial Port May be Daisy-Chained
for Multicard Applications
■
Automatic Shutdown on Electrical Faults
■
Buck Boost Charge Pump Generates 5V, 3V or 1.8V
The card voltage can be set to either 1.8V, 3V or 5V. The
LTC4556includesacarddetectionchannelwithautomatic
debounce circuitry. To reduce wiring costs, the LTC4556
interfaces to a microcontroller via a simple 4-wire serial
interface. Multiple devices may be connected in daisy-
chain fashion so that the number of wires to the card
socket board is independent of the number of sockets.
Status data is returned over the same interface.
Outputs (Smart Card Classes A, B and C)
■
Automatic Level Translation
■
Dynamic Pull-Ups Deliver Fast Signal Rise Times*
■
Supervisory Functions Prevent Smart Card Faults
■
Low Operating Current: 250µA Typical
VIN: 2.7V to 5.5V
Ultralow Shutdown Current
>10kV ESD on Smart Card Pins
Small 24-Pin 4mUm × 4mm QFN Package
■
■
■
Extensive security features ensure proper deactivation
sequencing in the event of a supply fault or a smart card
electrical fault. The smart card pins can withstand greater
than 10kV ESD in-situ with no additional components.
The LTC4556 is available in a small, low profile (0.75mm),
4mm × 4mm QFN package.
■
APPLICATIO S
■
Handheld Payment Terminals
■
Pay Telephones
■
ATM Machines
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
*U.S. Patent No. 6,356,140
**U.S. Patent No. 6,411,531
POS Terminals
■
Computer Keyboards
■
Multiple S.A.M. Sockets
U
TYPICAL APPLICATIO
240k
180k
20
UNDERV
Deactivation Sequence
1
19
DV
PRES
CC
10
V
BATT
INPUT
POWER
0.1µF
1µF
LTC4556
18
17
16
15
14
13
8
6
C8
C4
RST
5V/DIV
GND
I/O
FAULT
RST
CLK
CLK
21
22
23
24
D
D
IN
5V/DIV
SMART CARD
4-WIRE
COMMAND
INTERFACE
V
CC
OUT
SCLK
LD
1µF
I/O
5V/DIV
4556 TA01
V
CC
5V/DIV
2
3
4
5
DATA
4-WIRE
CARD
INTERFACE
R
IN
10µs/DIV
4556 G11.eps
SYNC
ASYNC
+
C
–
C
CPO
11
9
12
1µF
1µF
4556f
1
LTC4556
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
VBATT, DVCC, CPO, FAULT,
UNDERV to GND.......................................–0.3V to 6.0V
PRES, DATA, RIN, SYNC, ASYNC,
LD, DIN, SCLK to GND ............... –0.3V to (DVCC + 0.3V)
I/O, CLK ....................................... –0.3V to (VCC + 0.3V)
ICC (Note 5) .......................................................... 65mA
VCC Short-Circuit Duration............................... Indefinite
Operating Temperature Range (Note 4) .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
LTC4556EUF
24 23 22 21 20 19
DV
1
2
3
4
5
6
18 C8
CC
DATA
C4
17
16
R
I/O
IN
25
SYNC
ASYNC
FAULT
15 RST
14
13
CLK
UF PART
V
CC
MARKING
7
8
9 10 11 12
4556
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS SGND.
MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
V
Operating Voltage
Operating Current
Shutdown Current
●
●
●
●
●
●
2.7
5.5
400
1.75
5.5
V
µA
µA
V
BATT
VBATT
VBATT
I
I
V
= 5V, I = 0µA
250
0.5
CC
CC
No Card Present, V
= 0V
CPO
DV Operating Voltage
1.7
CC
I
I
Operating Current
Shutdown Current
5
25
µA
µA
DVCC
DVCC
0.2
1.5
Charge Pump
5V Mode Open-Loop
Output Resistance
R
OLCP
V
= 3.075V, I
= I = 60mA, (Note 3)
●
●
8.2
0.6
17
Ω
BATT
CPO
CC
CPO Turn On Time
I
= 0mA, 10% to 90%
1.5
ms
CC
4556f
2
LTC4556
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Smart Card Supply
V
Output Voltage
5V Mode, 0 < I < 60mA
●
●
●
4.65
2.75
1.65
5.0
3.0
1.8
5.35
3.25
1.95
V
V
V
CC
CC
3V Mode, 0 < I < 50mA
CC
1.8V Mode, 0 < I < 30mA
CC
V
Turn On-Time
I
= 0mA, 10% to 90%
●
●
●
0.8
–5
1.5
–2.5
150
ms
%
CC
CC
Undervoltage Detection
Overcurrent Detection
Smart Card Detection
Debounce Time ( PRES to
PRES Pull-Up Current
Relative to Nominal Output
–9
60
110
mA
D7)
●
●
●
15
32
1
60
2.5
250
ms
µA
µs
V
= 0
PRES
Deactivation Time ( RST to V = 0.4V)
I
= 0mA, C = 1µF
VCC
100
CC
CC
CLK (Non-Bidirectional Modes)
Low Level Output Voltage (V ), (Note 2) Sink Current = –200µA
●
●
●
●
0.2
16
V
V
OL
High Level Output Voltage (V ), (Note 2) Source Current = 200µA
V
V
– 0.2
CC
OH
Rise/Fall Time, (Note 2)
CLK Frequency, (Note 2)
RST, C4, C8
Loaded with 50pF, 10% to 90%
ns
10
MHz
Low Level Output Voltage (V ), (Note 2) Sink Current = –200µA
●
●
●
0.2
100
0.3
V
V
OL
High Level Output Voltage (V ), (Note 2) Source Current = 200µA
– 0.2
CC
OH
Rise/Fall Time, (Note 2)
I/O, CLK (CLK Specifications in Bidirectional Mode Only)
Low Level Output Voltage (V ), (Note 2) Sink Current = –1mA (V
Loaded with 50pF, 10% to 90%
ns
= 0V or V = 0V)
SYNC
●
●
V
V
OL
DATA
High Level Output Voltage (V ), (Note 2) Source Current = 20µA (V
= V
or
0.85 • V
CC
OH
DATA
DVCC
V
= V
)
SYNC
DVCC
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
= 0V or V = 0V
●
●
500
10
ns
Short Circuit Current, (Note 2)
V
5
mA
DATA
SYNC
DATA, SYNC (SYNC Specifications in Bidirectional Mode Only)
Low Level Output Voltage (V Sink Current = –500µA (V = 0V or V
)
= 0V)
●
●
●
0.3
500
V
V
OL
I/O
CLK
High Level Output Voltage (V
Rise/Fall Time
)
Source Current = 20µA (V = V or V
= V
)
0.8 • DV
CC
OH
I/O
CC
CLK
CC
Loaded with 50pF
ns
R , D , SCLK, LD, SYNC, ASYNC (SYNC Specifications for Non-Bidirectional Mode)
IN IN
Low Input Threshold (V )
●
●
●
0.15 • DV
1
V
V
IL
CC
High Input Threshold (V )
0.85 • DV
–1
IH
CC
Input Current (I /I )
µA
IH IL
D
OUT
Low Level Output Voltage (V
)
Sink Current = –200µA
Source Current = 200µA
●
●
0.3
V
V
OL
High Level Output Voltage (V
UNDERV
)
DV – 0.3
OH
CC
Threshold
●
●
1.17
1.23
1.29
50
V
Leakage Current
V
= 3.3V
nA
UNDERV
4556f
3
LTC4556
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT
Low Level Output Voltage (V
Leakage Current
Serial Port Timing
)
Sink Current = –200µA
●
●
0.005
0.3
1
V
OL
V
C
= 5.5V
µA
FAULT
LOAD
t
D
D
D
Valid to SCLK Setup
Valid to SCLK Hold
8
ns
ns
ns
ns
ns
ns
ns
ns
DS
IN
t
t
t
t
8
DH
DD
L
IN
Output Delay
= 15pF
15
50
50
50
50
0
60
OUT
SCLK Low Time
SCLK High Time
LD Pulse Width
SCLK to LD
H
t
LW
CL
LC
t
t
LD to SCLK
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This specification applies to all three smart card voltage classes:
1.8V, 3V and 5V.
Note 4: The LTC4556E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Based on long term current density limitation.
Note 3: R
≡ (2V
– V )/I ; V
will depend upon total load
OLCP
BATT
CPO CPO CPO
(I ) and minimum supply voltage V
. See Figure 6.
BATT
CC
U W
TYPICAL PERFOR A CE CHARACTERISTICS
I/O and CLK Short-Circuit Current
vs Temperature
(CLK in Bidirectional Mode)
Charge Pump Open-Loop Output
Resistance vs Temperature
(2VBATT – VCPO) / ICPO
No Load Supply Current vs VBATT
500
400
300
200
100
0
6.0
5.5
5.0
4.5
4.0
3.5
10
9
T
I
= 25°C
= 0µA
DV = V
CC
= 3.3V
V
BATT
V
CPO
= 2.7V
= 4.9V
A
CC
CC
BATT
CLK
V
= 5V
V
= 5V
= 3V
CC
8
V
CC
I/O
V
= 1.8V
CC
7
6
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
–40
–15
10
35
60
85
–40
–15
10
35
60
85
V
TEMPERATURE (°C)
TEMPERATURE (°C)
BATT
4556 G01
4556 G02
4556 G03
4556f
4
LTC4556
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VCC Overcurrent Shutdown
Threshold vs Temperature
Card Detection Debounce Time vs
BATT Supply Voltage
Bidirectional Channel (I/O) Low
Output Level vs Temperature
V
200
175
150
125
100
140
130
120
110
100
90
50
45
40
35
30
25
V
= V
= –1mA
= 3V
= 0V
DATA
SYNC
V
= 3.3V
BATT
I
OL
T
= 85°C
V
CC
= 1.8V, CPO = 4V
V
BATT
A
V
= 1.8V
CC
T
T
= 25°C
V
= 5V, CPO = 5.5V
A
A
CC
V
CC
= 3V, 5V
V
CC
= 3V, CPO = 5.5V
= –40°C
80
–40
–15
10
35
60
85
–40
–15
10
35
60
85
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
V
BATT
4556 G06
4556 G04
4556 G05
Extra Input Current vs
Load Current (IBATT – 2ICC
V
BATT Shutdown Current vs
DVCC Shutdown Current vs Supply
Voltage
)
Supply Voltage
6
5
4
3
2
1
0
1.0
0.8
0.6
0.4
0.2
0
3.0
2.5
2.0
1.5
1.0
0.5
0
V
A
= 3.3V
V
BATT
= V
DVCC
BATT
= 25°C
V
= V
BATT
DVCC
T
T
T
= –40°C
A
A
T
= 25°C
A
T
= 25°C
A
T
= –40°C
A
T
= 85°C
= 85°C
A
0.01
0.1
1
10
100
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
LOAD CURRENT (mA)
V
V
BATT
DVCC
4556 G07
4556 G09
4556 G08
Charge Pump and LDO Activation
Deactivation Sequence
Data – I/O Channel
RST
5V/DIV
VCPO
5V/DIV
I/O
2V/DIV
CLK
5V/DIV
VCC
5V/DIV
I/O
5V/DIV
DATA
2V/DIV
I/O
5V/DIV
V
CC
5V/DIV
1ms/DIV
4556 G10
10µs/DIV
4556 G11.eps
100ns/DIV
4556 G12
4556f
5
LTC4556
U
U
U
PI FU CTIO S
DVCC (Pin 1): Power. Reference voltage for the control
CPO (Pin 12): Charge Pump. CPO is the output of the
charge pump. When the smart card requires power, the
charge pump will charge CPO to either 3.7V or 5.35V
depending on what smart card voltage is required. A low
impedance 1µF X5R or X7R ceramic capacitor is required
on CPO.
logic.
DATA (Pin 2): Input/Output. Microcontroller side data I/O
pin. The DATA pin provides the bidirectional communica-
tion path to the smart card. The card may be selected to
communicate via the DATA pin. If several LTC4556s are
connected in parallel, the DATA pin can be made high
impedancebyselectingneithercardsocket.TheC4andC8
synchronous card pins can be selected to connect to the
DATA pin via the serial port (see Table 4).
VCC (Pin 13): Card Socket. The VCC pin should be con-
nected to the VCC pin of the smart card socket. The
activationofthe VCC piniscontrolledbytheserialport(see
Tables 1 and 2) and can be set to 0V, 1.8V, 3V or 5V.
RIN (Pin 3): Input. The RIN pin supplies the RST signal to
the smart card. It is level shifted and transmitted directly
to the RST pin of a selected card. When the card is
deselected, the RST pin is latched at its current state.
CLK (Pin 14): Card Socket. The CLK pin should be con-
nected to the CLK pin of the smart card socket. The CLK
signal can be derived from either the SYNC input or the
ASYNC input depending on which type of card is being
accessed. The card type is selected via the serial port (see
Tables 1 and 3). In bidirectional mode, the CLK pin be-
comes an input/output with the microcontroller side
SYNC pin.
SYNC (Pin 4): Input-Input/Output. The SYNC pin provides
the clock input for synchronous smart cards. When a
synchronous card is selected, its CLK pin follows SYNC
directly. When a synchronous card is deselected, the CLK
pinislatchedatitscurrentstate. Inbidirectionalmode, the
SYNC pin becomes an input/output with the smart card
CLK pin.
RST (Pin 15): Card Socket. This pin should be connected
to the RST pin of the smart card socket. The RST signal is
derived from the RIN pin. When the card is selected, its
RST pin follows RIN. When the card is deselected, the RST
pin holds the current value on RIN.
ASYNC (Pin 5): Input. The ASYNC pin provides the clock
input for asynchronous cards and should be connected to
afreerunningclock. Theclocksignaltothesmartcardcan
be a ÷1, ÷2, ÷4 or ÷8 version of the signal on ASYNC.
Asynchronous cards can also be placed in clock stop
mode with the clock stopped either high or low.
I/O (Pin 16): Card Socket. The I/O pin connects to the I/O
pin of the smart card socket. When the smart card is
selected, its I/O pin connects to the DATA pin. When the
smart card is deselected, its I/O pin returns to the idle
state (H).
FAULT (Pin 6): Output. The FAULT pin can be used as an
interrupt to a microcontroller to indicate when a fault has
occurred. It is an open drain output, which is logically
equivalent to D4 . (See Table 1)
C4, C8 (Pins 17, 18): Card Socket. These pins connect to
the C4 and C8 pins of synchronous memory cards on the
smart card socket. The signal for these pins is unidirec-
tional and can only be sent to the card. Data for C4 and C8
is transmitted via the DATA pin and may be selected in
place of I/O via the serial port (see Table 4). When either
C4 or C8 is selected, it will follow the DATA pin. When it is
deselected, it will remain latched at its current state.
NC (Pin 7): No Connection to chip. May be grounded.
GND (Pin 8): Ground. Power ground for the chip. This pin
should be connected directly to a low impedance ground
plane.
C–, C+ (Pins 9, 11): Charge Pump. Charge pump flying
capacitor pins. A 1µF X5R or X7R ceramic capacitor
should be connected from C+ to C–.
PRES (Pin 19): Card Socket. The PRES pin is used to
detectthepresenceofasmartcard.Itshouldbeconnected
to a normally open detection switch on the smart card
acceptor’s socket. This pin has a pull-up current source
on-chip so no external components are required.
VBATT (Pin 10): Power. Supply voltage for analog and
power sections of the LTC4556.
4556f
6
LTC4556
U
U
U
PI FU CTIO S
UNDERV (Pin 20): Input. The UNDERV pin provides
security by supplying a precision undervoltage threshold
for external supply monitoring. An external resistive volt-
age divider programs the desired undervoltage threshold.
Once UNDERV falls below 1.23V, the LTC4556 automati-
cally begins the deactivation sequence.
SCLK. DOUT canbeconnecteddirectlytoamicrocontroller
or the DIN pin of another LTC4556 or LTC1955 for daisy
chained operation.
SCLK (Pin 23): Input. The SCLK pin clocks the serial port.
Each new data bit is received on the rising edge of SCLK.
SCLK should be left high during idle times and should not
be clocked when LD is low.
If external supply monitoring is not required, the UNDERV
pin should be connected to either VBATT or DVCC.
LD (Pin 24): Input. The falling edge of this pin loads the
current state of the shift register into the command regis-
ter. Command changes to the smart card will be updated
on the falling edge of LD. The rising edge of LD latches
status information into the shift register for the next read/
write cycle.
DIN (Pin 21): Input. Input for the serial port. Command
data is shifted into DIN synchronously with SCLK. DIN can
be connected directly to a microcontroller or the DOUT pin
of another LTC4556 or LTC1955 for daisy chained
operation.
DOUT (Pin 22): Output. Output for the serial port. Smart
card status data is shifted out of DOUT synchronously with
SGND (Pin 25): Exposed Pad. Must be soldered to PCB
Ground.
W
BLOCK DIAGRA
CHARGE PUMP
+
–
C
C
GND
V
CPO
12
BATT
11
9
8
10
CHARGE
PUMP
13
16
17
18
14
15
19
6
LDO
V
CC
I/O
C4
2
5
DATA
SMART
CARD
SOCKET
C8
ASYNC
CLOCK
CONTROL
LOGIC
SMART
CARD
COMMUNICATIONS
4
3
SYNC
CLK
RST
PRES
RESET
CONTROL
LOGIC
R
IN
τ
FAULT
STATUS DATA
21
22
23
24
D
IN
SERIAL PORT
COMMAND/STATUS
DATA
D
DIGITAL
SUPPLY
OUT
1
DV
CC
SHIFT REGISTER
SCLK
LD
20
UNDERV
–
+
COMMAND LATCH
+
1.23V
–
4556 BD
4556f
7
LTC4556
U
OPERATIO
Serial Port
• Clock mode of the card (synchronous, asynchronous
or bidirectional)
The microcontroller compatible serial port provides all of
the command and control inputs for the LTC4556 as well
as the status of the smart card. Data on the DIN input is
loaded on the rising edge of SCLK. D7 is loaded first and
D0 last. At the same time the command bits are being
shifted into the DIN input, the status bits are being shifted
out of the DOUT output. The status bits are presented to
DOUT on the rising edge of SCLK. Once all bits have been
clockedintotheshiftregister, thecommanddataisloaded
into the command latch by bringing LD low. At this time
the command latch is updated and the LTC4556 will begin
to act on the new command set. When LD is low, the shift
register is transparent to the status data of the smart card
channel.Thestatusdataislatchedintotheshiftregisteron
therisingedgeofLD.SCLKshouldbeheldinthehighstate
when idle and should only be clocked when LD is high.
Likewise LD should only be brought high when SCLK is
high. Figure 2 shows the operation of the serial port.
• Operating mode of asynchronous cards (clock stop
high, low, ÷1, ÷2, ÷4 or ÷8)
• Selection of the I/O, C4 or C8 pins
The serial port provides the following status data:
• It indicates the presence or absence of the smart card.
• It indicates the readiness of the smart card VCC supply.
Communication with the smart card is disabled until its
power supply voltage has reached the final value.
• It indicates fault status. In the event of an electrical or
ATR fault, the fault is reported. For electrical faults, the
LTC4556 will automatically deactivate the smart card.
Table 1 illustrates the command inputs and status outputs
associated with each bit of the serial data word.
Three voltage options are available from the LTC4556: 5V,
3V and 1.8V. Bits D0, D1 determine which voltage is
selected. Settingbothcontrolbitsto0deactivatesthecard
and sets the smart card supply voltage to 0V. Table 2
shows the operation of the supply control bits.
Multiple LTC4556s may be daisy chained together by
connecting the DOUT pin of one LTC4556 to the DIN pin of
another. Figure 7 shows an example of an LTC4556 daisy
chained together with LTC1955s.
The CLK pin to the smart card can be programmed for
various modes. Both synchronous and asynchronous
cards are supported. There are several options available
with asynchronous cards. Table 3 shows how all clock
options are obtained using bits D5–D7.
The maximum clock rate for the serial port is 10MHz.
The serial port controls the following parameters of the
smart card socket:
• Selection/deselection of the smart card
• VCC voltage level of the card (5V/3V/1.8V/0V)
t
LC
t
DS
t
DH
t
H
t
t
CL
t
LW
L
t
DD
SCLK
D
IN
X
D7
D6
D2
D1
D0
X
LD
D7 FROM
INPUT
D
OUT
D7
D6
D5
D1
D0
D7
4556 F02
Figure 2. Serial Port Timing Diagram
4556f
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LTC4556
U
OPERATIO
Table 1. Serial Port Commands
Note that current passes from the receiving side of the
channel to the transmitting side. The low output voltage of
thereceivingsidewillbedependentuponthevoltageatthe
transmitting side plus the IR drop of the pass transistor.
STATUS OUTPUT
BIT COMMAND INPUT
0
D0
D1
D2
D3
D4
D5
D6
D7
V
Options
CC
0
(See Table 2)
0
Card Select/Deselect
Card Communications
Options (See Table 4)
Card Clock Options
(See Table 3)
When a card socket is selected, it becomes a candidate to
drive data on the DATA pin and likewise receive data from
the DATA pin. When a card socket is deselected, the
voltage on its I/O pin will return to the idle state (H) and the
DATA side of that channel will become high impedance.
0
Card Electrical Fault
Card ATR Fault
Card V Ready
CC
Card Present
The LTC4556 includes provision for unidirectional com-
munication with the C4 and C8 pins of the smart card. The
C4, C8 and I/O pins are individually multiplexed to the
DATA pin using bits D3 and D4 as shown in Table 4.
Table 2. VCC and Shutdown Options
D1
0
D0 STATUS
0
1
0
1
V
CC
V
CC
V
CC
V
CC
= 0V (Shutdown)
= 1.8V
0
Table 4. Communications Options
1
= 3V
D4
0
D3 COMMUNICATION MODE
1
= 5V
0
1
0
1
Nothing Selected
0
C4 Connected to DATA Pin
C8 Connected to DATA Pin
I/O Connected to DATA Pin
Table 3. Clock Options
1
D7
0
D6
0
D5
0
CLOCK MODE
1
Synchronous Mode
Bidirectional Mode
Asynchronous Stop Low
Asynchronous Stop High
Asynchronous ÷1
Asynchronous ÷2
Asynchronous ÷4
Asynchronous ÷8
0
0
1
Dynamic Pull-Up Current Sources
0
1
0
The current sources on the bidirectional pins (DATA, I/O)
are dynamically activated to achieve a fast rise time with a
relatively small static current. Once a bidirectional pin is
relinquished, a small start up current begins to charge the
node. An edge rate detector determines if the pin is
released by comparing its slew rate with an internal
reference value. If a valid transition is detected, a large
pull-up current enhances the edge rate on the node. The
higher slew rate corroborates the decision to charge the
node thereby affecting a dynamic form of hysteresis.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
To receive status data from the serial port, a read/write
operation must be performed. When polling for the pres-
ence of a smart card, the input word may be set to $00
since this is the shutdown command for the LTC4556.
Data Channel
LOCAL
SUPPLY
V
+
–
REF
The data channel is level shifted to the appropriate VCC
voltages at the I/O pin.
I
START
An NMOS pass transistor performs the level shifting. The
gate of the NMOS transistor is biased such that the
transistor is completely off when both sides have relin-
quished the channel. If one side of the channel asserts an
L, then the transistor will convey the L to the other side.
dv
dt
BIDIRECTIONAL
PIN
4556 F03
Figure 3. Dynamic Pull-Up Current Sources
4556f
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LTC4556
U
OPERATIO
Clock Channel
Additionalsynchronizationcircuitrypreventsglitchesfrom
occurring when switching between synchronous mode
and asynchronous mode. Because of this circuitry, two
edges (a falling edge followed by a rising edge) are
necessary at the CLK pin to switch modes from asynchro-
nous to synchronous. For example, if clock stop mode is
engaged, the clock channel will not change modes until
clock stop mode is disengaged.
As described in the section Serial Port, the LTC4556
supports both synchronous and asynchronous smart
cards. When bits D5-D7 are set to 0s, the clock channel is
in synchronous mode.
In synchronous mode, the CLK pin follows the SYNC pin
for a channel that is selected. If the channel is deselected
(via the serial port) the CLK line is latched at its current
value.
Both SYNC and ASYNC inputs are independently level
shifted to the appropriate voltage for the CLK pin (5V, 3V,
1.8V).
When control bits D7, D6 and D5 are set to 0, 0 and 1
respectively, the clock channel is in bidirectional mode.
This mode permits clock stretching when communicating
with bidirectional cards. The bidirectional level translation
circuit is identical to the I/O-DATA circuit. A low can be
asserted from either the SYNC pin or the CLK pin and the
other pin will follow. The low can be “handed off” to affect
clockstretchingifbothsidesassertatthesametime.Itwill
not run as fast as the unidirectional synchronous or
asynchronous modes but does employ accelerating pull-
up sources on both sides for maximum clock rate.
Reset Channel
Whenthecardisselected,theresetchannelprovidesalevel
shiftedpathfromtheRIN pintotheRSTpin. Whenthecard
is deselected its RST pin is latched at the current value of
RIN.
Smart Card Detection Circuit
The PRES pin is used to detect the presence of a smart
card. An automatic debounce circuit waits until a smart
card has been present for a continuous period of typically
32ms. Once a valid card indication exists, the status bit is
updated and may be polled by cycling data through the
serial port. The DOUT pin (equivalent to D7) of the serial
port can be used to indicate the presence of a card in real
time if LD is held low.
In asynchronous mode the CLK pin follows either the
ASYNC pin (÷1 mode) or a divided version of this pin. The
CLK pin can also be stopped high or low. The available
divider ratios include ÷2, ÷4 and ÷8. When switching
between divider ratios, the internal selection circuitry
ensures that no spikes or glitches appear on the CLK pin.
Consequently,itmaytakeupto8clockpulsesfortheclock
frequency change command to take affect. Synchroniza-
tioncircuitryensuresthatnoglitchesoccurwhenentering
or exiting one of the stop modes. For example, when
entering Stop Low mode, the selection circuitry waits for
the next falling edge of the CLK signal to make the change.
Likewise if Stop High is selected it will occur on the next
rising edge.
The PRES pin has a built-in pull-up current source so no
external components are required for switch detection.
The pull-up current source is designed to have a small
current when the pin voltage is below approximately 1V
butsomewhathighercurrentwhenthepinvoltagereaches
1V. Thishelpsmaintainlowpowerdissipationwhenacard
is present and yet fast response time to a card removal.
Deselection of an asynchronous card does not affect its
CLK pin. Its clock can be started, stopped or its divider
ratio changed at any time.
Activation/Deactivation
For maximum flexibility, the activation sequencing of the
smartcardislefttotheapplicationprogrammer.However,
deactivation can be achieved either manually or automati-
cally.Anelectricalfaultconditionwilltriggertheautomatic
deactivation.
To clean up the duty cycle of the incoming clock in
asynchronousapplications,anyoftheclockdividermodes
÷2, ÷4 or ÷8 will yield a very nearly 50% duty cycle.
4556f
10
LTC4556
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OPERATIO
The built-in deactivation sequence can be executed via the
serial port simply by setting the control bits D0 and D1
to 0. The deactivation sequence is outlined below.
VCC overcurrent faults are detected by comparing the
outputcurrentoftheLDOswithaninternalreferencelevel.
If the current of the LDO is more than 110mA (typ) for the
entire timeout period, the fault is reported and the deacti-
vation sequence is initiated.
1. The RST pin is immediately brought low.
2. The deactivation of the CLK pin depends upon which
type of card is used:
CLKandRSTfaultsaredetectedbycomparingtheoutputs
of these pins with their expected signals. If the signal on
a pin is incorrect for the entire timeout period, the fault is
reported and the deactivation sequence is initiated.
If the smart card was set to asynchronous mode then
the CLK pin will be latched low on its next falling edge.
If no falling edges occur within 5µs (min) then the CLK
line is forced low.
The clock channel is a special case. Since it can have a free
running clock, the error indication is accumulated over a
longer period of time without being cleared. Even though
the clock may be running, an error will still be detected.
If the smart card was set to synchronous mode then the
CLK pin is immediately latched at its current value
(either high or low) and then forced low after a duration
of 5µs (min). During the 5µs timeout period, changes
on SYNC will be ignored.
An overtemperature fault is detected by sensing the junc-
tion temperature of the IC. If the junction temperature
exceeds approximately 150°C for the entire timeout
period, thefaultisreportedbysettingthefaultbit(D4)and
the deactivation sequence is initiated.
3. The I/O, C4 and C8 pins are brought low.
4. The VCC pin is brought low.
AcardremovalfaultisdeterminedassoonasthePRESpin
is high. Once this occurs the fault is reported and the
deactivation sequence is initiated.
Upon activation, to comply with relevant smart card stan-
dards, none of the smart card signal pins will be allowed
to go high before the smart card supply voltage (VCC) has
reached its final value.
Ifnocardispresent,andtheapplicationsoftwareattempts
to power up a card socket, an automatic fault will result.
Electrical Fault Detection
ShortcircuitsontheI/Olinewillnotbedetectedbythefault
detection hardware; however, a short circuit from I/O to
Several types of faults are detected by the LTC4556. They
include VCC undervoltage, VCC overcurrent, CLK, RST, C8,
C4 short circuit, card removal during a transaction, failed
answer to reset (ATR), supply undervoltage or UNDERV
and chip overtemperature. To prevent false errors from
plaguingthemicrocontroller, theelectricalfaultsareacted
upon only after a 5µs (min) timeout period. Card removal
duringtransactionfaultsinitiatethedeactivationsequence
immediately.
V
CC will be compliant with the maximum current limits set
by applicable standards (<15mA). The same is true of the
CLK pin when it is set to bidirectional mode.
Answer to Reset (ATR) Fault Detection
Answer to Reset faults are detected by an internal counter
that is started once the RST line goes high. If the DATA pin
remains high for 40,000 clock cycles, the ATR fault bit is
set in the serial port’s status register (see Table 1).
V
CC undervoltage faults are determined by comparing the
actual output voltage with the internal reference voltage. If
the output is more than ~5% below its set point for the
entire timeout period, the fault is reported and the deacti-
vation sequence is initiated.
An ATR fault can not occur if the clock mode is set to
synchronous. ATRfaultswillonlyoccurforasynchronous
smart cards.
4556f
11
LTC4556
U
OPERATIO
ATR faults are cleared by bringing the RST pin low via RIN.
Using the FAULT Pin
An ATR fault will not automatically deactivate the smart
card. It is the application programmer’s responsibility to
checkthestatusregisterforATRfaultsanddeactivatethe
smart card in accordance with smart card standards.
Generally,theapplicationhas50ms(EMV2.1.3.1,2.1.3.2)
from the 40,000th clock pulse to deactivate the card.
OncetheLTC4556receivesthedeactivationcommand, it
will shut down the smart card in less than 250µs.
The FAULT pin can be used as an interrupt to a microcon-
troller. It is an open-drain output and generally requires a
pull-up resistor. The FAULT pin will go low when an
electrical fault occurs. The FAULT pin is logically equiva-
lent to D4 (see Table 1).
4556f
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LTC4556
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APPLICATIO S I FOR ATIO
10kV ESD Protection
nature of multilayer ceramic chip capacitors will minimize
voltage spikes but only if the power path is kept very short
(i.e., minimum inductance). The VBATT node should be
especially well bypassed. The capacitor for this node
should be directly adjacent to the QFN package. The CPO
and flying capacitors should be very close as well. The
LTC4556 can tolerate more distance between the LDO
capacitor and the VCC pin.
All smart card pins (CLK, RST, I/O, C4, C8 and VCC) can
withstand over 10kV of human body model ESD in-situ. In
order to ensure proper ESD protection, careful board
layout is required. The GND pin should be tied directly
toagroundplane. ThemultilayerceramicchipVCC capaci-
tor should be located very close to the VCC pin and tied
immediately to the ground plane.
Figure 4 shows an example of a tight printed circuit board
layout using single layer copper. For best performance a
multilayer board can be used and should employ a solid
ground plane on at least one layer.
Capacitor Selection
Warning: A polarized capacitor such as tantalum or alumi-
num should never be used for the flying capacitor since its
voltage can reverse upon start up of the LTC4556. Low
ESR ceramic capacitors should always be used for the
flying capacitor.
The following capacitors are recommended for use with
the LTC4556:
TYPE
VALUE CASE SIZE MURATA P/N
A total of four capacitors are required to operate the
LTC4556. An input bypass capacitor is required at VBATT
and DVCC. An output bypass capacitor is required on the
smart card VCC pin. A charge pump flying capacitor is
required from C+ to C– and a charge storage capacitor is
required on the charge pump out pin CPO.
BATT, CPO, X5R
1µF
0603
GRM39 X5R 105K 6.3
C
, V
FLY CC
CDV
X5R
0.1µF
0402
GRM36 X5R 104K 10
CC
To prevent excessive noise spikes due to charge pump
operation, low ESR (equivalent series resistance) multi-
layer ceramic chip capacitors are strongly recommended.
There are several types of ceramic capacitors available
each having considerably different characteristics. For
example,X7R/X5Rceramiccapacitorshaveexcellentvolt-
age and temperature stability but relatively low packing
density. Y5V ceramic capacitors have apparently higher
packing density but poor performance over their rated
voltage or temperature ranges. Under certain voltage and
temperature conditions Y5V and X7R/X5R ceramic ca-
pacitors can be compared directly by case size rather than
specified value for a desired minimum capacitance.
V
CC
CPO
V
BATT
Placementofthecapacitorsiscriticalforcorrectoperation
oftheLTC4556.Becausethechargepumpgenerateslarge
current steps, all of the capacitors should be placed as
close to the LTC4556 as possible. The low impedance
GND
4556 F04
Figure 4. Optimum Single Layer PCB Layout
4556f
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LTC4556
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APPLICATIO S I FOR ATIO
Interfacing to a Microcontroller
Daisy-Chained Operation
The serial port of the LTC4556 can be connected directly
toa68HC11stylemicrocontroller’sserialport. Themicro-
controller should be configured as the master device and
its clock’s idle state should be set to high (MSTR = 1,
CPOL = 1 and CPHA = 0 for the MC68HC11 family).
Figure 5 shows the recommended configuration and di-
rection of data flow. Note that an additional I/O line is
necessaryforLDtoloadthedataonceithasshiftedaround
the loop. Command data is latched into the command
register on the falling edge of the LD signal. The LTC4556
willbegintoactonnewcommanddataassoonasLDgoes
low. Any general purpose microcontroller I/O line can be
configured to control the LD pin.
For applications requiring more than one card socket, the
serial port of the LTC4556 is designed to be easily daisy-
chained. The DOUT pin of one LTC4556 can be connected
directly to the DIN pin of another LTC4556 or LTC1955.
Rather than sending one 8-bit byte before asserting LD,
the microcontroller should send one 8-bit byte per device.
LD should only be asserted after all devices have been
updated. Figure 7 shows an LTC4556 cascaded in daisy
chain fashion with two LTC1955s. In this case the
microcontroller would write five 8-bit bytes before assert-
ing the LD pin.
The status of the LTC4556 is returned over the serial port.
Status data is latched into the shift register on the rising
edge of the LD pin. Whenever the system is waiting for
status data from the LTC4556, its LD pin should be held
low.
µCONTROLLER
LTC4556
MOSI
D
D
IN
MISO
SCK
I/O
OUT
CARD
SCLK
LD
4556 F05
Figure 5. Microcontroller Interface
4556f
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LTC4556
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APPLICATIO S I FOR ATIO
Asynchronous Card Detection
Sincetheoutputvoltageisprogrammedto5V,thecharge
pump will be acting as a voltage doubler. With the card
drawing 60mA, the input current will be 2 • (60mA)
or about 120mA. Allowing the VBATT supply to droop
from 3.1V to 2.7V during the 30us timeout period
the input capacitance would need to be at least
120mA/[(3.1V – 2.7V)/30µs] or 9µF.
Since the shift register is transparent when LD is held
low, DOUT is the same as D7. Recall from Table 1 that D7
indicates the status of the card detection channel. Thus
it is not necessary to perform an entire read/write opera-
tion to determine the card detection status. With LD low,
D
OUT can be used to generate a real time card detection
interrupt.
Zero Shutdown Current
Using the UNDERV Pin
Although the LTC4556 is designed to have very low
shutdown current it can still draw over a microampere on
both DVCC and VBATT when in shutdown. For applications
that require virtually zero shutdown current, the DVCC pin
canbegrounded. ThiswillreducetheVBATT currenttowell
under a single microampere. Internal logic ensures that
the LTC4556 is in shutdown when DVCC is grounded.
Note, however, that all of the logic signals that are refer-
enced to DVCC (DIN, SCLK, LD, DATA, RIN, SYNC and
ASYNC) will have to be at 0V as well to prevent ESD diodes
to DVCC from being forward biased.
The UNDERV pin can be used to add protection against a
supplyundervoltagefault. Byusingtwoexternalprogram-
mingresistors, theundervoltagedetectioncanbesettoan
arbitrary level (Figure 8). To ensure that the smart card is
properly shut down, there must be sufficient energy
available in the input bypass capacitor to run it until the
deactivation cycle begins. It can take approximately 30µs
from the detection of a fault until the deactivation se-
quence begins. It is desirable to maintain the VBATT supply
at 2.7V or greater during this period.
Consider the following (worst-case) example:
Operation at Higher Supplies
1) The UNDERV pin is programmed to trip below 3.1V.
If a 5.5V to 6V supply voltage is available, it is possible to
achieve some power savings by overriding the charge
pump. The higher supply can be connected directly to the
CPO pin. As long as the voltage on CPO is higher than that
at which it ordinarily regulates (5.35V or 3.7V depending
on voltage selections) the charge pump’s oscillator will
not run. This configuration can give considerable power
savings since the charge pump is not being used.
2) It is possible to have the card activated at 5V and
drawing 60mA.
4556f
15
LTC4556
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APPLICATIO S I FOR ATIO
A voltage source is still needed on both DVCC and VBATT in
this configuration. Recall that DVCC sets the logic refer-
ence level for all the control and smart card communica-
tionpins. ThevoltageonVBATT canbeanyconvenientlevel
that meets the parameters in the Electrical Characteristics
table.
VCPO ≥ 2VBATT – (ICC)ROLCP
The LDO has been designed to meet all applicable smart
card standards for VCC with VCPO as low as 5.13V. Given
this information, trade-offs can be made by the user with
regard to total consumption (ICC) and minimum supply
voltage.
The 5.5V to 6V supply can be left permanently connected
to CPO but there will be approximately 5µA of current flow
into CPO when the LTC4556 is in shutdown.
Changing the Smart Card Supply Voltage
Although the LTC4556 control system will allow the smart
card voltage to be changed from one value to the next
without an interim power down, this is not recommended.
When changing from a higher voltage to a lower voltage
there will generally not be a problem; however, changing
from a lower voltage to a higher voltage can result in both
an undervoltage condition or an overcurrent condition.
The likely result is that the LTC4556 will automatically
deactivate. Applicable smart card standards specify that
the smart card supply be powered to zero before applying
a new voltage.
Charge Pump Strength
Under low VBATT conditions, the amount of current avail-
able to the smart card is limited by the charge pump.
Figure 6 shows how the LTC4556 can be modeled as a
Thevenin equivalent circuit to determine the amount of
current available given the effective input voltage, 2VBATT
and the effective open-loop output resistance, ROLCP
.
From Figure 6, the available current is given by:
2VBATT – VCPO
ICC
≤
Compliance Testing
ROLCP
Inductance due to long leads on type approval equipment
can cause ringing and overshooot that leads to testing
problems. Small amounts of capacitance and damping
resistors can be included in the application without com-
promising the normal electrical performance of the
LTC4556 or smart card system. Generally a 100Ω resistor
and a 20pF capacitor will accomplish this as shown in
Figure 9.
ROLCP is dependent on a number of factors including the
switching term, 1/(fOSC • CFLY), internal switch resis-
tances and the nonoverlap period of the switching circuit.
However,foragivenROLCP,theminimumCPOvoltagecan
be determined from the following expression:
R
OLCP
CPO
+
2V
BATT
LDO
V
CC
–
4556 F06
Figure 6. Equivalent Open-Loop Circuit
4556f
16
LTC4556
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APPLICATIO S I FOR ATIO
1µF
1µF
9
11
19
PRES
–
+
C
C
C
C
10
8
V
BATT
INPUT
POWER
SMART CARD
GND
1
DV
CC
20
UNDERV
6
FAULT
FAULT
21
22
23
24
LTC4556
D
D
IN
4-WIRE
COMMAND
INTERFACE
OUT
SCLK
LD
2
3
4
5
12
15
15
DATA
CPO
4-WIRE
CARD
INTERFACE
1µF
R
IN
SYNC
ASYNC
1µF
4.7µF
11
–
14
+
21
2
C
PRES B PRES A
12, 13
9, 10
1
V
BATT
VENDOR CARD
VENDOR CARD
GND
DV
CC
23
UNDERV
24
FAULT
27
28
26
25
LTC1955
D
D
IN
OUT
SCLK
LD
29
30
32
31
DATA
CPO
4.7µF
R
IN
SYNC
ASYNC
1µF
4.7µF
11
–
14
+
21
2
C
PRES B PRES A
12, 13
9, 10
1
V
BATT
VENDOR CARD
VENDOR CARD
GND
DV
CC
23
UNDERV
24
FAULT
27
28
26
25
LTC1955
D
D
IN
OUT
SCLK
LD
29
30
32
31
DATA
CPO
4.7µF
R
IN
SYNC
ASYNC
4556 F07
Figure 7. An LTC4556 and Two LTC1955s Daisy Chained Together
4556f
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LTC4556
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APPLICATIO S I FOR ATIO
MAIN SUPPLY
V
TRIP
= 1.23V (1 + R1/R2)
R1
R2
20
UNDERV
LTC4556
4556 F08
Figure 8. Setting the Undervoltage Trip Point
100Ω
I/O
CLK
RST
C7
C3
C2
C1
100Ω
100Ω
20pF
SMART
CARD
SOCKET
LTC4556
20pF
20pF
V
CC
C5
1µF
0.1µF
4556 F09
Fiugre 9. Additional Components for Improved Compliance Testing
4556f
18
LTC4556
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
23 24
PIN 1
TOP MARK
(NOTE 6)
0.38 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 1103
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4556f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC4556
U
TYPICAL APPLICATIO
Battery-Powered RS232 to Smart Card Interface
0.1µF
FAULT
0.1µF
180k
262k
+
0.1µF
4.7µF
47k
37
47k
RESET
Li-ION
16
17
4
21
45 19
1
20
UNDERV
10
1k
RXEN DREN
V
CC
MOD B
V
DD
V
XIRQ
DV
V
BATT
4
5
3
RH
CC
V
CC18
V
CC3
V
CCA
36
1
6
RST
RST
FAULT
LTC1728ES5-1.8
GND
LTC1348CG
MC68L11E9PB2
LTC4556EUF
18
C8
C4
C7
C2
C3
C1
2
DB9
C8
C4
17
16
15
14
13
RD
TD
2
3
7
8
25
24
40
39
38
42
41
43
44
DR1OUT
DR1IN
PD1 (TXD)
PD0 (RXD)
IRQ
I/O
SMART CARD
21
22
23
24
RX1IN
RX1OUT
(MOSI) PD3
(MISO) PD2
(SCK) PD4
(SS) PD5
D
D
RST
CLK
IN
OUT
GND
5
SCLK
LD
V
CC
1µF
0.1µF
C5
19
5
27
26
+
+
PRES
C1
C3
0.1µF
0.1µF
0.1µF
6
2
–
–
C1
C3
+
C2
24
9
5
3
2
(2MHz) E
PB0
ASYNC
3
–
R
IN
C2
1
(IC3) PA0
PC0
DATA
28
46
29
4
PA7
SYNC
PC1
+
–
–
+
GND
15
V
V
MODA EXTAL XTAL
V
V
C
C
CPO
GND
8
RL SS
1
28
18 20
22
26
27
9
11 12
0.1µF
0.1µF
1µF
10M
1µF
8.000MHz
27pF
27pF
4556 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 2.6V to 6.6V, V
LTC1555L/LTC1555L-1.8 1MHz, SIM Power Supply and Level Translator
for 1.8V/3V/5V SIM Cards
= 1.8V/3V/5V, I = 32µA,
Q
IN
OUT
OUT
I
< 1µA, SSOP16
SD
LTC1555/LTC1556
LTC1755/LTC1756
LTC1955
650kHz, SIM Power Supply and Level Translator
for 3V/5V SIM Cards
V : 2.7V to 10V, V
= 3V/5V, I = 60µA, I < 1µA,
Q SD
IN
SSOP16, SSOP20
850kHz, Smart Card Interface with Serial Control for 3V/5V
Smart Card Applications
V : 2.7V to 7V, V
= 3V/5V, I = 60µA, I < 1µA,
IN
OUT Q SD
SSOP16, SSOP24
Dual Smart Card Interface with Serial Control for 1.8V/3V/5V
Smart Card Applications
V : 3V to 5.5V, V
= 1.8V/3V/5V, I = 200µA,
Q
IN
OUT
I
< 1µA, QFN32
SD
LTC1986
900kHz, SIM Power Supply for 3V/5V SIM Cards
V : 2.6V to 4.4V, V
ThinSOT
= 3V/5V, I = 14µA, I < 1µA,
OUT Q SD
IN
LTC4555
SIM Power Supply and Level Translator
for 1.8V/3V SIM Cards
V : 3V to 6V, V
QFN16
= 1.8V/3V, I = 40µA, I < 1µA,
OUT Q SD
IN
LTC4557
Dual SIM/Smart Card Power Supply and Level Translator
for 1.8V/3V Cards
V : 2.7V to 5.5V, V
QFN16
= 1.8V/3V, I = 250µA, I < 1µA,
OUT Q SD
IN
ThinSOT is a trademark of Linear Technology Corporation.
4556f
LT/TP 0604 1K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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