LTC4556EUF#PBF [Linear]
LTC4556 - Smart Card Interface with Serial Control; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC4556EUF#PBF |
| 厂家： | 
Linear |
| 描述： | LTC4556 - Smart Card Interface with Serial Control; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C |
| 文件： | 总22页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4556
Smart Card Interface
with Serial Control
FeaTures
DescripTion
The LTC®4556 provides all necessary power control, level
translation and supervisory functions for a smart card or
S.A.M.cardinterface.Thepartcontainsalownoisecharge
n
Electrical Specifications Are ISO7816-3 and EMV
Compatible
n
Control/Status Serial Port May be Daisy-Chained
for Multicard Applications
Automatic Shutdown on Electrical Faults
pump plus LDO for generating V power, as well as all
necessary level shifting circuitry.
CC
n
n
Buck Boost Charge Pump Generates 5V, 3V or 1.8V
The card voltage can be set to either 1.8V, 3V or 5V. The
LTC4556includesacarddetectionchannelwithautomatic
debounce circuitry. To reduce wiring costs, the LTC4556
interfaces to a microcontroller via a simple 4‑wire serial
interface.Multipledevicesmaybeconnectedindaisy‑chain
fashion so that the number of wires to the card socket
board is independent of the number of sockets. Status
data is returned over the same interface.
Outputs (Smart Card Classes A, B and C)
n
Automatic Level Translation
n
Dynamic Pull‑Ups Deliver Fast Signal Rise Times
n
Supervisory Functions Prevent Smart Card Faults
n
Low Operating Current: 250µA Typical
n
V : 2.7V to 5.5V
IN
n
n
n
Ultralow Shutdown Current
>10kV ESD on Smart Card Pins
Small 24‑Lead 4mm × 4mm QFN Package
Extensive security features ensure proper deactivation
sequencing in the event of a supply fault or a smart card
electrical fault. The smart card pins can withstand greater
than 10kV ESD in‑situ with no additional components.
The LTC4556 is available in a small, low profile (0.75mm),
4mm × 4mm QFN package.
applicaTions
n
Handheld Payment Terminals
n
Pay Telephones
n
ATM Machines
POS Terminals
Computer Keyboards
Multiple S.A.M. Sockets
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 6356140, 6411531.
n
n
n
Typical applicaTion
240k
180k
20
Deactivation Sequence
UNDERV
1
19
DV
PRES
CC
10
V
BATT
INPUT
POWER
0.1µF
1µF
LTC4556
18
17
16
15
14
13
RST
8
6
C8
C4
GND
5V/DIV
I/O
FAULT
CLK
5V/DIV
RST
CLK
21
22
23
24
D
D
IN
SMART CARD
4-WIRE
COMMAND
INTERFACE
V
CC
OUT
SCLK
1µF
I/O
5V/DIV
LD
4556 TA01
V
2
3
4
5
CC
DATA
5V/DIV
4-WIRE
CARD
INTERFACE
R
IN
4556 G11.eps
10µs/DIV
SYNC
ASYNC
+
C
–
C
CPO
11
9
12
1µF
1µF
4556fb
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For more information www.linear.com/LTC4556
LTC4556
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
V
, DV , CPO, FAULT,
BATT CC
TOP VIEW
UNDERV to GND ....................................... –0.3V to 6.0V
PRES, DATA, R , SYNC, ASYNC,
IN
24 23 22 21 20 19
LD, D , SCLK to GND................ –0.3V to (DV + 0.3V)
IN
CC
DV
1
2
3
4
5
6
18 C8
I/O, CLK ........................................–0.3V to (V + 0.3V)
CC
CC
DATA
C4
17
16
I
(Note 5)............................................................65mA
CC
R
I/O
IN
25
SGND
V
CC
Short‑Circuit Duration............................... Indefinite
SYNC
ASYNC
FAULT
15 RST
Operating Temperature Range (Note 4)....–40°C to 85°C
14
13
CLK
Storage Temperature Range .................. –65°C to 125°C
V
CC
7
8
9 10 11 12
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
T
= 125°C, θ = 160°C/W
JA
JMAX
EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
24‑Lead (4mm x 4mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 85°C
LTC4556EUF#PBF
LTC4556EUF#TRPBF
4556
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
l
l
l
l
l
l
V
Operating Voltage
Operating Current
Shutdown Current
2.7
5.5
400
1.75
5.5
V
µA
µA
V
BATT
VBATT
VBATT
I
I
V
= 5V, I = 0µA
250
0.5
CC
CC
No Card Present, V
= 0V
CPO
DV Operating Voltage
1.7
CC
I
I
Operating Current
Shutdown Current
5
25
µA
µA
DVCC
DVCC
0.2
1.5
Charge Pump
5V Mode Open‑Loop
l
l
R
V
= 3.075V, I
= I = 60mA, (Note 3)
8.2
0.6
17
Ω
OLCP
BATT
CPO
CC
Output Resistance
CPO Turn On Time
I
= 0mA, 10% to 90%
1.5
ms
CC
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For more information www.linear.com/LTC4556
LTC4556
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Smart Card Supply
l
l
l
V
Output Voltage
5V Mode, 0 < I < 60mA
4.65
2.75
1.65
5.0
3.0
1.8
5.35
3.25
1.95
V
V
V
CC
CC
3V Mode, 0 < I < 50mA
CC
1.8V Mode, 0 < I < 30mA
CC
l
l
l
V
Turn On‑Time
I
= 0mA, 10% to 90%
0.8
–5
1.5
–2.5
150
ms
%
CC
CC
Undervoltage Detection
Overcurrent Detection
Smart Card Detection
Debounce Time ( PRES to
PRES Pull‑Up Current
Relative to Nominal Output
–9
60
110
mA
l
15
32
1
60
2.5
250
ms
µA
µs
D7)
l
l
V
I
= 0
PRES
= 0mA, CV = 1µF
100
Deactivation Time ( RST to V = 0.4V)
CC
CC
CC
CLK (Non-Bidirectional Modes)
l
l
l
l
Low Level Output Voltage (V ), (Note 2)
Sink Current = –200µA
0.2
16
V
V
OL
OH
High Level Output Voltage (V ), (Note 2) Source Current = 200µA
V
V
– 0.2
CC
Rise/Fall Time, (Note 2)
CLK Frequency, (Note 2)
RST, C4, C8
Loaded with 50pF, 10% to 90%
Sink Current = –200µA
ns
10
MHz
l
l
l
Low Level Output Voltage (V ), (Note 2)
0.2
100
0.3
V
V
OL
High Level Output Voltage (V ), (Note 2) Source Current = 200µA
– 0.2
CC
OH
Rise/Fall Time, (Note 2)
I/O, CLK (CLK Specifications in Bidirectional Mode Only)
Low Level Output Voltage (V ), (Note 2) Sink Current = –1mA (V
Loaded with 50pF, 10% to 90%
ns
l
l
= 0V or V = 0V)
SYNC
V
V
OL
DATA
High Level Output Voltage (V ), (Note 2) Source Current = 20µA (V
= V
or
0.85 • V
CC
OH
DATA
DVCC
V
= V
)
DVCC
SYNC
l
l
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
= 0V or V = 0V
500
10
ns
Short Circuit Current, (Note 2)
V
5
mA
DATA
SYNC
DATA, SYNC (SYNC Specifications in Bidirectional Mode Only)
Low Level Output Voltage (V Sink Current = –500µA (V = 0V or V
l
l
l
)
OL
= 0V)
0.3
500
V
V
I/O
CLK
High Level Output Voltage (V
Rise/Fall Time
)
OH
Source Current = 20µA (V = V or V
= V
)
0.8 • DV
CC
I/O
CC
CLK
CC
Loaded with 50pF
ns
R , D , SCLK, LD, SYNC, ASYNC (SYNC Specifications for Non-Bidirectional Mode)
IN IN
l
l
l
Low Input Threshold (V )
0.15 • DV
1
V
V
IL
CC
High Input Threshold (V )
0.85 • DV
–1
IH
CC
Input Current (I /I )
µA
IH IL
D
OUT
l
l
Low Level Output Voltage (V
)
Sink Current = –200µA
Source Current = 200µA
0.3
V
V
OL
High Level Output Voltage (V
UNDERV
)
OH
DV – 0.3
CC
l
l
Threshold
1.17
1.23
1.29
50
V
Leakage Current
V
= 3.3V
nA
UNDERV
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LTC4556
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT
l
l
Low Level Output Voltage (V
Leakage Current
Serial Port Timing
)
Sink Current = –200µA
0.005
0.3
1
V
OL
V
= 5.5V
= 15pF
µA
FAULT
t
t
t
t
t
t
t
t
D
D
D
Valid to SCLK Setup
Valid to SCLK Hold
8
ns
ns
ns
ns
ns
ns
ns
ns
DS
DH
DD
L
IN
8
IN
Output Delay
C
LOAD
15
50
50
50
0
60
OUT
SCLK Low Time
SCLK High Time
SCLK to LD
H
CL
LC
LFC
LD to SCLK
LD Falling to SCLK
50
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This specification applies to all three smart card voltage classes:
1.8V, 3V and 5V.
Note 3: R
≡ (2V
– V )/I ; V
will depend upon total load
. See Figure 6.
OLCP
BATT
CPO CPO CPO
(I ) and minimum supply voltage V
CC
BATT
Note 4: The LTC4556E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Based on long term current density limitation.
Typical perForMance characTerisTics
I/O and CLK Short-Circuit Current
vs Temperature
(CLK in Bidirectional Mode)
Charge Pump Open-Loop Output
Resistance vs Temperature
(2VBATT – VCPO) / ICPO
No Load Supply Current vs VBATT
500
400
300
200
100
0
6.0
5.5
5.0
4.5
4.0
3.5
10
9
T
I
= 25°C
= 0µA
DV = V
CC
= 3.3V
V
BATT
V
CPO
= 2.7V
= 4.9V
A
CC
CC
BATT
CLK
V
= 5V
V
= 5V
= 3V
CC
8
V
CC
I/O
V
CC
= 1.8V
7
6
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
–40
–15
10
35
60
85
–40
–15
10
35
60
85
V
BATT
TEMPERATURE (°C)
TEMPERATURE (°C)
4556 G02
4556 G03
4556 G01
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LTC4556
Typical perForMance characTerisTics
VCC Overcurrent Shutdown
Threshold vs Temperature
Card Detection Debounce Time vs
VBATT Supply Voltage
Bidirectional Channel (I/O) Low
Output Level vs Temperature
140
130
120
110
100
90
200
175
150
125
100
50
45
40
35
30
25
V
= V
= –1mA
= 3V
= 0V
SYNC
DATA
V
BATT
= 3.3V
I
OL
T
= 85°C
V
CC
= 1.8V, CPO = 4V
V
BATT
A
V
CC
= 1.8V
T
T
= 25°C
V
CC
= 5V, CPO = 5.5V
A
A
V = 3V, 5V
CC
V
CC
= 3V, CPO = 5.5V
= –40°C
80
–40
–15
10
35
60
85
–40
–15
10
35
60
85
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
V
BATT
4556 G04
4556 G06
4556 G05
Extra Input Current vs
Load Current (IBATT – 2ICC
VBATT Shutdown Current vs
Supply Voltage
DVCC Shutdown Current vs Supply
Voltage
)
3.0
2.5
2.0
1.5
1.0
0.5
0
6
1.0
0.8
0.6
0.4
0.2
0
V
= V
BATT
V
A
= 3.3V
V
= V
BATT
DVCC
BATT
DVCC
T
= 25°C
5
4
3
2
1
0
T
T
= –40°C
= 85°C
A
A
T
= 25°C
A
T
= 25°C
A
T
= –40°C
A
T
= 85°C
A
0.01
0.1
1
10
100
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
LOAD CURRENT (mA)
V
BATT
SUPPLY VOLTAGE (V)
V
DVCC
SUPPLY VOLTAGE (V)
4556 G08
4556 G09
4556 G07
Charge Pump and LDO Activation
Deactivation Sequence
Data – I/O Channel
RST
5V/DIV
V
I/O
2V/DIV
CPO
5V/DIV
CLK
5V/DIV
V
CC
5V/DIV
I/O
5V/DIV
DATA
2V/DIV
I/O
5V/DIV
V
CC
5V/DIV
4556 G11
4556 G10
4556 G12
10µs/DIV
1ms/DIV
100ns/DIV
4556fb
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LTC4556
pin FuncTions
DV (Pin1):Power.Referencevoltageforthecontrollogic.
CPO(Pin12):ChargePump.CPOistheoutputofthecharge
pump. When the smart card requires power, the charge
pump will charge CPO to either 3.7V or 5.35V depending
on what smart card voltage is required. A low impedance
1µF X5R or X7R ceramic capacitor is required on CPO.
CC
DATA (Pin 2): Input/Output. Microcontroller side data I/O
pin. The DATA pin provides the bidirectional communica‑
tion path to the smart card. The card may be selected to
communicate via the DATA pin. If several LTC4556s are
connected in parallel, the DATA pin can be made high
impedance by selecting neither card socket. The C4 and
C8 synchronous card pins can be selected to connect to
the DATA pin via the serial port (see Table 4).
V (Pin13):CardSocket.TheV pinshouldbeconnected
CC
CC
to the V pin of the smart card socket. The activation of
CC
the V pin is controlled by the serial port (see Tables 1
CC
and 2) and can be set to 0V, 1.8V, 3V or 5V.
R (Pin 3): Input. The R pin supplies the RST signal to
CLK (Pin 14): Card Socket. The CLK pin should be con‑
nected to the CLK pin of the smart card socket. The CLK
signal can be derived from either the SYNC input or the
ASYNC input depending on which type of card is being
accessed. The card type is selected via the serial port
(see Tables 1 and 3). In bidirectional mode, the CLK pin
becomes an input/output with the microcontroller side
SYNC pin.
IN
IN
the smart card. It is level shifted and transmitted directly
to the RST pin of a selected card. When the card is dese‑
lected, the RST pin is latched at its current state.
SYNC (Pin 4): Input‑Input/Output. The SYNC pin provides
the clock input for synchronous smart cards. When a
synchronous card is selected, its CLK pin follows SYNC
directly. When a synchronous card is deselected, the CLK
pin is latched at its current state. In bidirectional mode,
the SYNC pin becomes an input/output with the smart
card CLK pin.
RST (Pin 15): Card Socket. This pin should be connected
to the RST pin of the smart card socket. The RST signal
is derived from the R pin. When the card is selected,
IN
its RST pin follows R . When the card is deselected, the
IN
ASYNC (Pin 5): Input. The ASYNC pin provides the clock
input for asynchronous cards and should be connected
to a free running clock. The clock signal to the smart card
can be a ÷1, ÷2, ÷4 or ÷8 version of the signal on ASYNC.
Asynchronouscardscanalsobeplacedinclockstopmode
with the clock stopped either high or low.
RST pin holds the current value on R .
IN
I/O (Pin 16): Card Socket. The I/O pin connects to the
I/O pin of the smart card socket. When the smart card is
selected, its I/O pin connects to the DATA pin. When the
smart card is deselected, its I/O pin returns to the idle
state (H).
FAULT (Pin 6): Output. The FAULT pin can be used as an
interrupt to a microcontroller to indicate when a fault has
occurred. It is an open drain output, which is logically
equivalent to D4 . (See Table 1)
C4, C8 (Pins 17, 18): Card Socket. These pins connect to
the C4 and C8 pins of synchronous memory cards on the
smart card socket. The signal for these pins is unidirec‑
tional and can only be sent to the card. Data for C4 and
C8 is transmitted via the DATA pin and may be selected in
place of I/O via the serial port (see Table 4). When either
C4 or C8 is selected, it will follow the DATA pin. When it
is deselected, it will remain latched at its current state.
NC (Pin 7): No Connection to chip. May be grounded.
GND (Pin 8): Ground. Power ground for the chip. This
pin should be connected directly to a low impedance
ground plane.
–
+
C , C (Pins 9, 11): Charge Pump. Charge pump flying
PRES(Pin19):CardSocket.ThePRESpinisusedtodetect
the presence of a smart card. It should be connected to a
normally open detection switch on the smart card accep‑
tor’s socket. This pin has a pull‑up current source on‑chip
so no external components are required.
capacitorpins.A1µFX5RorX7Rceramiccapacitorshould
+
–
be connected from C to C .
V
(Pin10):Power.Supplyvoltageforanalogandpower
BATT
sections of the LTC4556.
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LTC4556
pin FuncTions
UNDERV (Pin 20): Input. The UNDERV pin provides secu‑
rity by supplying a precision undervoltage threshold for
external supply monitoring. An external resistive voltage
dividerprogramsthedesiredundervoltagethreshold.Once
UNDERV falls below 1.23V, the LTC4556 automatically
begins the deactivation sequence.
SCLK. D
canbeconnecteddirectlytoamicrocontroller
OUT
or the D pin of another LTC4556 or LTC1955 for daisy
IN
chained operation.
SCLK (Pin 23): Input. The SCLK pin clocks the serial port.
Each new data bit is received on the rising edge of SCLK.
SCLK should be left high during idle times and should not
be clocked when LD is low.
If external supply monitoring is not required, the UNDERV
pin should be connected to either V
or DV .
BATT
CC
LD (Pin 24): Input. The falling edge of this pin loads the
current state of the shift register into the command regis‑
ter. Command changes to the smart card will be updated
on the falling edge of LD. The rising edge of LD latches
status information into the shift register for the next read/
write cycle.
D
(Pin 21): Input. Input for the serial port. Command
IN
data is shifted into D synchronously with SCLK. D can
IN
IN
be connected directly to a microcontroller or the D
OUT
pin of another LTC4556 or LTC1955 for daisy chained
operation.
D
(Pin 22): Output. Output for the serial port. Smart
SGND (Pin 25): Exposed Pad. Must be soldered to PCB
Ground.
OUT
card status data is shifted out of D
synchronously with
OUT
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LTC4556
block DiagraM
CHARGE PUMP
+
–
C
C
GND
8
V
CPO
12
BATT
11
9
10
CHARGE
PUMP
13
16
17
18
14
15
19
6
LDO
V
CC
I/O
C4
2
5
DATA
SMART
CARD
SOCKET
C8
ASYNC
CLOCK
CONTROL
LOGIC
SMART
CARD
COMMUNICATIONS
4
3
SYNC
CLK
RST
PRES
RESET
CONTROL
LOGIC
R
IN
τ
FAULT
STATUS DATA
21
22
23
24
D
IN
SERIAL PORT
COMMAND/STATUS
DATA
D
DIGITAL
SUPPLY
OUT
1
DV
CC
SHIFT REGISTER
SCLK
LD
20
UNDERV
–
+
COMMAND LATCH
+
1.23V
–
4556 BD
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LTC4556
operaTion
Serial Port
• Clock mode of the card (synchronous, asynchronous
or bidirectional)
The microcontroller compatible serial port provides all of
the command and control inputs for the LTC4556 as well
• Operating mode of asynchronous cards (clock stop
high, low, ÷1, ÷2, ÷4 or ÷8)
as the status of the smart card. Data on the D input is
IN
loaded on the rising edge of SCLK. D7 is loaded first and
• Selection of the I/O, C4 or C8 pins
D0 last. At the same time the command bits are being
The serial port provides the following status data:
• It indicates the presence or absence of the smart card.
shifted into the D input, the status bits are being shifted
IN
out of the D
OUT
output. The status bits are presented to
on the rising edge of SCLK. Once all bits have been
OUT
D
• It indicates the readiness of the smart card V supply.
CC
clocked into the shift register, the command data is loaded
into the command latch by bringing LD low. At this time
the command latch is updated and the LTC4556 will begin
to act on the new command set. The status data is latched
intotheshiftregisterontherisingedgeofLD.SCLKshould
be low when LD is brought low and should be high when
LD is brought high. This requires a 9th clock cycle per
transaction. Figure 2 shows the recommended operation
of the serial port.
Communication with the smart card is disabled until its
power supply voltage has reached the final value.
• It indicates fault status. In the event of an electrical or
ATR fault, the fault is reported. For electrical faults, the
LTC4556 will automatically deactivate the smart card.
Table 1 illustrates the command inputs and status outputs
associated with each bit of the serial data word.
Three voltage options are available from the LTC4556:
5V, 3V and 1.8V. Bits D0, D1 determine which voltage is
selected. Setting both control bits to 0 deactivates the
card and sets the smart card supply voltage to 0V. Table 2
shows the operation of the supply control bits.
Multiple LTC4556s may be daisy chained together by
connecting the D
pin of one LTC4556 to the D pin of
OUT
IN
another. Figure 7 shows an example of an LTC4556 daisy
chained together with LTC1955s.
The maximum clock rate for the serial port is 10MHz.
The CLK pin to the smart card can be programmed for
various modes. Both synchronous and asynchronous
cards are supported. There are several options available
with asynchronous cards. Table 3 shows how all clock
options are obtained using bits D5–D7.
The serial port controls the following parameters of the
smart card socket:
• Selection/deselection of the smart card
• V voltage level of the card (5V/3V/1.8V/0V)
CC
READ/WRITE CYCLE
t
LC
t
DS
t
DH
t
t
L
t
t
t
CL
H
CL
LFC
t
DD
SCLK
D
IN
X
D7
D6
D2
D1
D0
X
LD
D7 FROM
INPUT
D
OUT
D7
D6
D5
D1
D0
D7
4556 F02
Figure 2. Serial Port Timing Diagram
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Table 1. Serial Port Commands
currentpassesfromthereceivingsideofthechanneltothe
transmitting side. The low output voltage of the receiving
sidewillbedependentuponthevoltageatthetransmitting
side plus the IR drop of the pass transistor.
STATUS OUTPUT
BIT COMMAND INPUT
0
D0
D1
D2
D3
D4
D5
D6
D7
V
Options
CC
(See Table 2)
0
0
Card Select/Deselect
Card Communications
Options (See Table 4)
When a card socket is selected, it becomes a candidate to
drive data on the DATA pin and likewise receive data from
the DATA pin. When a card socket is deselected, the volt‑
age on its I/O pin will return to the idle state (H) and the
DATA side of that channel will become high impedance.
0
Card Electrical Fault
Card ATR Fault
Card Clock Options
(See Table 3)
Card V Ready
CC
Card Present
The LTC4556 includes provision for unidirectional com‑
munication with the C4 and C8 pins of the smart card.
The C4, C8 and I/O pins are individually multiplexed to
the DATA pin using bits D3 and D4 as shown in Table 4.
Table 2. VCC and Shutdown Options
D1
0
D0 STATUS
0
1
0
1
V
CC
V
CC
V
CC
V
CC
= 0V (Shutdown)
= 1.8V
0
Table 4. Communications Options
1
= 3V
D4
0
D3 COMMUNICATION MODE
1
= 5V
0
1
0
1
Nothing Selected
0
C4 Connected to DATA Pin
C8 Connected to DATA Pin
I/O Connected to DATA Pin
Table 3. Clock Options
1
D7
0
D6
0
D5
0
CLOCK MODE
1
Synchronous Mode
Bidirectional Mode
Asynchronous Stop Low
Asynchronous Stop High
Asynchronous ÷1
Asynchronous ÷2
Asynchronous ÷4
Asynchronous ÷8
0
0
1
Dynamic Pull-Up Current Sources
0
1
0
The current sources on the bidirectional pins (DATA, I/O)
are dynamically activated to achieve a fast rise time with
a relatively small static current. Once a bidirectional pin
is relinquished, a small start up current begins to charge
the node. An edge rate detector determines if the pin is
released by comparing its slew rate with an internal refer‑
ence value. If a valid transition is detected, a large pull‑up
current enhances the edge rate on the node. The higher
slew rate corroborates the decision to charge the node
thereby affecting a dynamic form of hysteresis.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
To receive status data from the serial port, a read/write
operation must be performed. When polling for the pres‑
ence of a smart card, the input word may be set to $00
since this is the shutdown command for the LTC4556.
Data Channel
LOCAL
SUPPLY
V
+
–
REF
The data channel is level shifted to the appropriate V
voltages at the I/O pin.
CC
I
START
An NMOS pass transistor performs the level shifting. The
gateoftheNMOStransistorisbiasedsuchthatthetransis‑
tor is completely off when both sides have relinquished
the channel. If one side of the channel asserts an L, then
the transistor will convey the L to the other side. Note that
dv
dt
BIDIRECTIONAL
PIN
4556 F03
Figure 3. Dynamic Pull-Up Current Sources
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As described in the section Serial Port, the LTC4556 sup‑
ports both synchronous and asynchronous smart cards.
When bits D5‑D7 are set to 0s, the clock channel is in
synchronous mode.
Additionalsynchronizationcircuitrypreventsglitchesfrom
occurringwhenswitchingbetweensynchronousmodeand
asynchronous mode. Because of this circuitry, two edges
(a falling edge followed by a rising edge) are necessary
at the CLK pin to switch modes from asynchronous to
synchronous. Forexample, if clockstop modeis engaged,
the clock channel will not change modes until clock stop
mode is disengaged.
Insynchronousmode,theCLKpinfollowstheSYNCpinfor
a channel that is selected. If the channel is deselected (via
the serial port) the CLK line is latched at its current value.
When control bits D7, D6 and D5 are set to 0, 0 and 1
respectively, the clock channel is in bidirectional mode.
This mode permits clock stretching when communicating
with bidirectional cards. The bidirectional level translation
circuit is identical to the I/O‑DATA circuit. A low can be
asserted from either the SYNC pin or the CLK pin and the
other pin will follow. The low can be “handed off” to affect
clock stretching if both sides assert at the same time. It
will not run as fast as the unidirectional synchronous or
asynchronousmodesbutdoesemployacceleratingpull‑up
sources on both sides for maximum clock rate.
Both SYNC and ASYNC inputs are independently level
shifted to the appropriate voltage for the CLK pin (5V, 3V,
1.8V).
Reset Channel
When the card is selected, the reset channel provides a
level shifted path from the R pin to the RST pin. When
IN
the card is deselected its RST pin is latched at the current
value of R .
IN
Smart Card Detection Circuit
In asynchronous mode the CLK pin follows either the
ASYNC pin (÷1 mode) or a divided version of this pin. The
CLK pin can also be stopped high or low. The available di‑
viderratiosinclude÷2,÷4and÷8.Whenswitchingbetween
divider ratios, the internal selection circuitry ensures that
nospikesorglitchesappearontheCLKpin.Consequently,
it may take up to 8 clock pulses for the clock frequency
change command to take affect. Synchronization circuitry
ensures that no glitches occur when entering or exiting
one of the stop modes. For example, when entering Stop
Low mode, the selection circuitry waits for the next falling
edge of the CLK signal to make the change. Likewise if
Stop High is selected it will occur on the next rising edge.
The PRES pin is used to detect the presence of a smart
card. An automatic debounce circuit waits until a smart
card has been present for a continuous period of typically
32ms. Once a valid card indication exists, the status bit
is updated and may be polled by cycling data through the
serial port. The D
pin (equivalent to D7) of the serial
OUT
port can be used to indicate the presence of a card in real
time if LD is held low.
The PRES pin has a built‑in pull‑up current source so no
external components are required for switch detection.
The pull‑up current source is designed to have a small
current when the pin voltage is below approximately 1V
butsomewhathighercurrentwhenthepinvoltagereaches
1V. This helps maintain low power dissipation when a card
is present and yet fast response time to a card removal.
Deselection of an asynchronous card does not affect its
CLK pin. Its clock can be started, stopped or its divider
ratio changed at any time.
To clean up the duty cycle of the incoming clock in asyn‑
chronous applications, any of the clock divider modes ÷2,
÷4 or ÷8 will yield a very nearly 50% duty cycle.
Activation/Deactivation
For maximum flexibility, the activation sequencing of the
smart card is left to the application programmer. However,
deactivation can be achieved either manually or automati‑
cally. Anelectricalfaultconditionwilltriggertheautomatic
deactivation.
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The built‑in deactivation sequence can be executed via the
serial port simply by setting the control bits D0 and D1
to 0. The deactivation sequence is outlined below.
V overcurrentfaultsaredetectedbycomparingtheoutput
CC
current of the LDOs with an internal reference level. If the
current of the LDO is more than 110mA (typ) for the entire
timeout period, the fault is reported and the deactivation
sequence is initiated.
1. The RST pin is immediately brought low.
2. The deactivation of the CLK pin depends upon which
type of card is used:
CLKandRSTfaultsaredetectedbycomparingtheoutputs
of these pins with their expected signals. If the signal on
a pin is incorrect for the entire timeout period, the fault is
reported and the deactivation sequence is initiated.
If the smart card was set to asynchronous mode then
the CLK pin will be latched low on its next falling edge.
If no falling edges occur within 5µs (min) then the CLK
line is forced low.
The clock channel is a special case. Since it can have a free
running clock, the error indication is accumulated over a
longer period of time without being cleared. Even though
the clock may be running, an error will still be detected.
If the smart card was set to synchronous mode then
the CLK pin is immediately latched at its current value
(either high or low) and then forced low after a duration
of 5µs (min). During the 5µs timeout period, changes
on SYNC will be ignored.
An overtemperature fault is detected by sensing the
junction temperature of the IC. If the junction tempera‑
ture exceeds approximately 150°C for the entire timeout
period, the fault is reported by setting the fault bit (D4)
and the deactivation sequence is initiated.
3. The I/O, C4 and C8 pins are brought low.
4. The V pin is brought low.
CC
A card removal fault is determined as soon as the PRES
pin is high. Once this occurs the fault is reported and the
deactivation sequence is initiated.
Upon activation, to comply with relevant smart card stan‑
dards, none of the smart card signal pins will be allowed
to go high before the smart card supply voltage (V ) has
CC
reached its final value.
Ifnocardispresent,andtheapplicationsoftwareattempts
to power up a card socket, an automatic fault will result.
Electrical Fault Detection
Short circuits on the I/O line will not be detected by the
fault detection hardware; however, a short circuit from I/O
Several types of faults are detected by the LTC4556. They
include V undervoltage, V overcurrent, CLK, RST, C8,
CC
CC
to V will be compliant with the maximum current limits
CC
C4 short circuit, card removal during a transaction, failed
answer to reset (ATR), supply undervoltage or UNDERV
and chip overtemperature. To prevent false errors from
plaguing the microcontroller, the electrical faults are acted
upon only after a 5µs (min) timeout period. Card removal
duringtransactionfaultsinitiatethedeactivationsequence
immediately.
set by applicable standards (<15mA). The same is true of
the CLK pin when it is set to bidirectional mode.
Answer to Reset (ATR) Fault Detection
Answer to Reset faults are detected by an internal counter
that is started once the RST line goes high. If the DATA
pin remains high for 40,000 clock cycles, the ATR fault
bit is set in the serial port’s status register (see Table 1).
V
undervoltage faults are determined by comparing the
CC
actual output voltage with the internal reference voltage.
If the output is more than ~5% below its set point for
the entire timeout period, the fault is reported and the
deactivation sequence is initiated.
An ATR fault can not occur if the clock mode is set to
synchronous. ATR faults will only occur for asynchronous
smart cards.
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ATR faults are cleared by bringing the RST pin low via R .
Using the FAULT Pin
IN
An ATR fault will not automatically deactivate the smart
card. It is the application programmer’s responsibility to
check the status register for ATR faults and deactivate
the smart card in accordance with smart card standards.
Generally,theapplicationhas50ms(EMV2.1.3.1,2.1.3.2)
from the 40,000th clock pulse to deactivate the card. Once
the LTC4556 receives the deactivation command, it will
shut down the smart card in less than 250µs.
The FAULT pin can be used as an interrupt to a microcon‑
troller. It is an open‑drain output and generally requires a
pull‑up resistor. The FAULT pin will go low when an elec‑
trical fault occurs. The FAULT pin is logically equivalent
to D4 (see Table 1).
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10kV ESD Protection
nature of multilayer ceramic chip capacitors will minimize
voltage spikes but only if the power path is kept very
All smart card pins (CLK, RST, I/O, C4, C8 and V ) can
CC
short (i.e., minimum inductance). The V
node should
BATT
withstand over 10kV of human body model ESD in‑situ.
In order to ensure proper ESD protection, careful board
layout is required. The GND pin should be tied directly
be especially well bypassed. The capacitor for this node
should be directly adjacent to the QFN package. The CPO
and flying capacitors should be very close as well. The
LTC4556 can tolerate more distance between the LDO
toagroundplane. ThemultilayerceramicchipV capaci‑
CC
tor should be located very close to the V pin and tied
CC
capacitor and the V pin.
CC
immediately to the ground plane.
Figure 4 shows an example of a tight printed circuit board
layout using single layer copper. For best performance a
multilayer board can be used and should employ a solid
ground plane on at least one layer.
Capacitor Selection
Warning: A polarized capacitor such as tantalum or alumi-
num should never be used for the flying capacitor since
its voltage can reverse upon start up of the LTC4556.
Low ESR ceramic capacitors should always be used for
the flying capacitor.
The following capacitors are recommended for use with
the LTC4556:
TYPE
VALUE CASE SIZE MURATA P/N
A total of four capacitors are required to operate the
BATT, CPO,
, V
X5R
1µF
0603
GRM39 X5R 105K 6.3
C
LTC4556. An input bypass capacitor is required at V
FLY CC
BATT
CDV
X5R
0.1µF
0402
GRM36 X5R 104K 10
and DV . An output bypass capacitor is required on the
CC
CC
smart card V pin. A charge pump flying capacitor is
CC
+
–
required from C to C and a charge storage capacitor is
required on the charge pump out pin CPO.
To prevent excessive noise spikes due to charge pump
operation, low ESR (equivalent series resistance) multi‑
layer ceramic chip capacitors are strongly recommended.
Thereareseveraltypesofceramiccapacitorsavailableeach
havingconsiderablydifferentcharacteristics.Forexample,
X7R/X5R ceramic capacitors have excellent voltage and
temperature stability but relatively low packing density.
Y5V ceramic capacitors have apparently higher packing
density but poor performance over their rated voltage or
temperatureranges.Undercertainvoltageandtemperature
conditions Y5V and X7R/X5R ceramic capacitors can be
compared directly by case size rather than specified value
for a desired minimum capacitance.
V
CC
CPO
V
BATT
Placement of the capacitors is critical for correct opera‑
tion of the LTC4556. Because the charge pump generates
large current steps, all of the capacitors should be placed
as close to the LTC4556 as possible. The low impedance
GND
4556 F04
Figure 4. Optimum Single Layer PCB Layout
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Interfacing to a Microcontroller
Daisy-Chained Operation
The serial port of the LTC4556 can be connected directly
to a 68HC11 style microcontroller’s serial port. The mi‑
crocontroller should be configured as the master device
and its clock’s idle state should be set to high (MSTR = 1,
CPOL=1andCPHA=0fortheMC68HC11family).Figure5
shows the recommended configuration and direction of
data flow. Note that an additional I/O line is necessary for
LD to load the data once it has shifted around the loop.
Command data is latched into the command register on
the falling edge of the LD signal. The LTC4556 will begin
to act on new command data as soon as LD goes low. Any
generalpurposemicrocontrollerI/Olinecanbeconfigured
to control the LD pin.
For applications requiring more than one card socket, the
serial port of the LTC4556 is designed to be easily daisy‑
chained. The D
pin of one LTC4556 can be connected
OUT
directly to the D pin of another LTC4556 or LTC1955.
IN
Rather than sending one 8‑bit byte before asserting LD,
the microcontroller should send one 8‑bit byte per device.
LD should only be asserted after all devices have been up‑
dated. Figure7showsanLTC4556cascadedindaisychain
fashionwithtwoLTC1955s.Inthiscasethemicrocontroller
would write five 8‑bit bytes before asserting the LD pin.
The status of the LTC4556 is returned over the serial port.
Status data is latched into the shift register on the rising
edge of the LD pin. Whenever the system is waiting for
statusdatafromtheLTC4556,itsLDpinshouldbeheldlow.
µCONTROLLER
MOSI
LTC4556
D
D
IN
MISO
SCK
I/O
OUT
CARD
SCLK
LD
4556 F05
Figure 5. Microcontroller Interface
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Asynchronous Card Detection
Since the output voltage is programmed to 5V, the charge
pump will be acting as a voltage doubler. With the card
drawing 60mA, the input current will be 2 • (60mA)
Since the shift register is transparent when LD is held
low, D
is the same as D7. Recall from Table 1 that D7
OUT
or about 120mA. Allowing the V
supply to droop
BATT
indicates the status of the card detection channel. Thus it
from 3.1V to 2.7V during the 30us timeout period
the input capacitance would need to be at least
120mA/[(3.1V – 2.7V)/30µs] or 9µF.
is not necessary to perform an entire read/write operation
to determine the card detection status. With LD low, D
OUT
canbeusedtogeneratearealtimecarddetectioninterrupt.
Zero Shutdown Current
Using the UNDERV Pin
Although the LTC4556 is designed to have very low shut‑
down current it can still draw over a microampere on both
The UNDERV pin can be used to add protection against a
supplyundervoltagefault.Byusingtwoexternalprogram‑
ming resistors, the undervoltage detection can be set to
an arbitrary level (Figure 8). To ensure that the smart card
is properly shut down, there must be sufficient energy
available in the input bypass capacitor to run it until the
deactivation cycle begins. It can take approximately 30µs
fromthedetectionofafaultuntilthedeactivationsequence
DV and V
when in shutdown. For applications that
CC
BATT
require virtually zero shutdown current, the DV pin can
CC
be grounded. This will reduce the V
current to well
BATT
under a single microampere. Internal logic ensures that
theLTC4556isinshutdownwhenDV isgrounded.Note,
CC
however, that all of the logic signals that are referenced to
DV (D , SCLK, LD, DATA, R , SYNC and ASYNC) will
CC IN
IN
begins. It is desirable to maintain the V
or greater during this period.
supply at 2.7V
BATT
have to be at 0V as well to prevent ESD diodes to DV
CC
from being forward biased.
Consider the following (worst‑case) example:
Operation at Higher Supplies
1) The UNDERV pin is programmed to trip below 3.1V.
If a 5.5V to 6V supply voltage is available, it is possible
to achieve some power savings by overriding the charge
pump. The higher supply can be connected directly to the
CPO pin. As long as the voltage on CPO is higher than that
at which it ordinarily regulates (5.35V or 3.7V depending
on voltage selections) the charge pump’s oscillator will
not run. This configuration can give considerable power
savings since the charge pump is not being used.
2) It is possible to have the card activated at 5V and draw‑
ing 60mA.
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A voltage source is still needed on both DV and V
in
CC
BATT
VCPO ≥2VBATT –(ICC)ROLCP
thisconfiguration.RecallthatDV setsthelogicreference
CC
level for all the control and smart card communication
The LDO has been designed to meet all applicable smart
pins. ThevoltageonV
canbeanyconvenientlevelthat
card standards for V with V as low as 5.13V. Given
BATT
CC
CPO
meetstheparametersintheElectricalCharacteristicstable.
this information, trade‑offs can be made by the user with
regard to total consumption (I ) and minimum supply
CC
The 5.5V to 6V supply can be left permanently connected
to CPO but there will be approximately 5µA of current flow
into CPO when the LTC4556 is in shutdown.
voltage.
Changing the Smart Card Supply Voltage
Charge Pump Strength
Although the LTC4556 control system will allow the smart
card voltage to be changed from one value to the next
without an interim power down, this is not recommended.
When changing from a higher voltage to a lower voltage
there will generally not be a problem; however, changing
from a lower voltage to a higher voltage can result in both
an undervoltage condition or an overcurrent condition.
The likely result is that the LTC4556 will automatically
deactivate. Applicable smart card standards specify that
the smart card supply be powered to zero before applying
a new voltage.
UnderlowV
conditions,theamountofcurrentavailable
BATT
to the smart card is limited by the charge pump.
Figure 6 shows how the LTC4556 can be modeled as a
Thevenin equivalent circuit to determine the amount of
current available given the effective input voltage, 2V
BATT
and the effective open‑loop output resistance, R
From Figure 6, the available current is given by:
2VBATT – VCPO
.
OLCP
ICC
≤
ROLCP
Compliance Testing
R
is dependent on a number of factors including the
OLCP
Inductance due to long leads on type approval equipment
can cause ringing and overshooot that leads to testing
problems. Small amounts of capacitance and damping
resistorscanbeincludedintheapplicationwithoutcompro‑
mising the normal electrical performance of the LTC4556
or smart card system. Generally a 100Ω resistor and a
20pF capacitor will accomplish this as shown in Figure 9.
switchingterm, 1/(f
•C ), internalswitchresistances
OSC FLY
and the nonoverlap period of the switching circuit. How‑
ever, for a given R , the minimum CPO voltage can be
OLCP
determined from the following expression:
R
OLCP
CPO
+
2V
BATT
LDO
V
CC
–
4556 F06
Figure 6. Equivalent Open-Loop Circuit
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1µF
1µF
1µF
1µF
9
11
+
19
PRES
–
C
C
C
C
10
8
V
BATT
INPUT
POWER
SMART CARD
GND
1
DV
CC
20
UNDERV
6
FAULT
FAULT
21
22
23
24
LTC4556
D
D
IN
4-WIRE
COMMAND
INTERFACE
OUT
SCLK
LD
2
3
4
5
12
15
15
DATA
CPO
4-WIRE
CARD
INTERFACE
1µF
R
IN
SYNC
ASYNC
4.7µF
11
–
14
21
2
+
C
PRES B PRES A
12, 13
9, 10
1
V
BATT
VENDOR CARD
VENDOR CARD
GND
DV
CC
23
UNDERV
24
FAULT
27
28
26
25
LTC1955
D
D
IN
OUT
SCLK
LD
29
30
32
31
DATA
CPO
4.7µF
R
IN
SYNC
ASYNC
4.7µF
11
14
21
2
–
+
C
PRES B PRES A
12, 13
9, 10
1
V
BATT
VENDOR CARD
VENDOR CARD
GND
DV
CC
23
UNDERV
24
FAULT
27
28
26
25
LTC1955
D
D
IN
OUT
SCLK
LD
29
30
32
31
DATA
CPO
4.7µF
R
IN
SYNC
ASYNC
4556 F07
Figure 7. An LTC4556 and Two LTC1955s Daisy Chained Together
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MAIN SUPPLY
V
TRIP
= 1.23V (1 + R1/R2)
R1
R2
20
UNDERV
LTC4556
4556 F08
Figure 8. Setting the Undervoltage Trip Point
100Ω
I/O
CLK
RST
C7
C3
C2
C1
100Ω
100Ω
20pF
SMART
CARD
SOCKET
LTC4556
20pF
20pF
V
CC
C5
1µF
0.1µF
4556 F09
Fiugre 9. Additional Components for Improved Compliance Testing
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LTC4556
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-ꢀ697 Rev B)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05 REV B
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4556fb
20
For more information www.linear.com/LTC4556
LTC4556
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/13 Remove t spec from Serial Port Timing
4
9
4
9
LW
Revised Serial Port Timing section and diagram
B
2/14
Added t parameter to Serial Port Timing electrical parameters.
LFC
Modified Figure 2.
4556fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa‑
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC4556
Typical applicaTion
Battery-Powered RS232 to Smart Card Interface
0.1µF
FAULT
0.1µF
180k
262k
+
0.1µF
4.7µF
10
47k
37
47k
RESET
Li-ION
16
17
4
21
45 19
V
1
20
UNDERV
1k
RXEN DREN
V
CC
MOD B
V
XIRQ
DV
V
BATT
4
5
3
DD
RH
CC
V
V
CC3
V
CCA
CC18
36
1
6
RST
RST
FAULT
LTC1728ES5-1.8
GND
LTC1348CG
MC68L11E9PB2
LTC4556EUF
18
C8
C4
C7
C2
C3
C1
2
DB9
C8
C4
17
16
15
14
13
RD
TD
2
3
7
8
25
24
40
39
38
42
41
43
44
DR1OUT
DR1IN
PD1 (TXD)
PD0 (RXD)
IRQ
I/O
SMART CARD
21
22
23
24
RX1IN
RX1OUT
(MOSI) PD3
(MISO) PD2
(SCK) PD4
(SS) PD5
D
D
RST
CLK
IN
OUT
GND
5
SCLK
LD
V
CC
1µF
0.1µF
C5
19
5
27
26
+
+
PRES
C1
C3
0.1µF
0.1µF
0.1µF
6
2
–
–
C1
C3
+
C2
24
9
5
3
2
(2MHz) E
PB0
ASYNC
3
–
R
IN
C2
1
(IC3) PA0
PC0
DATA
28
46
29
4
PA7
SYNC
PC1
+
–
–
+
GND
15
V
V
MODA EXTAL XTAL
V
V
C
C
CPO
12
GND
8
RL SS
1
28
18 20
22
26
27
9
11
0.1µF
0.1µF
1µF
10M
1µF
8.000MHz
27pF
27pF
4556 TA02
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
V : 2.6V to 6.6V, V
LTC1555L/LTC1555L‑1.8
1MHz, SIM Power Supply and Level Translator
for 1.8V/3V/5V SIM Cards
= 1.8V/3V/5V, I = 32µA,
Q
IN
OUT
OUT
I
< 1µA, SSOP16
SD
LTC1555/LTC1556
LTC1755/LTC1756
LTC1955
650kHz, SIM Power Supply and Level Translator
for 3V/5V SIM Cards
V : 2.7V to 10V, V
= 3V/5V, I = 60µA, I < 1µA,
Q SD
IN
SSOP16, SSOP20
850kHz, Smart Card Interface with Serial Control for 3V/5V
Smart Card Applications
V : 2.7V to 7V, V
= 3V/5V, I = 60µA, I < 1µA,
OUT Q SD
IN
SSOP16, SSOP24
Dual Smart Card Interface with Serial Control for 1.8V/3V/5V
Smart Card Applications
V : 3V to 5.5V, V
SD
= 1.8V/3V/5V, I = 200µA,
Q
IN
OUT
I
< 1µA, QFN32
LTC1986
900kHz, SIM Power Supply for 3V/5V SIM Cards
V : 2.6V to 4.4V, V
= 3V/5V, I = 14µA, I < 1µA,
OUT Q SD
IN
ThinSOT™
LTC4555
SIM Power Supply and Level Translator
for 1.8V/3V SIM Cards
V : 3V to 6V, V
= 1.8V/3V, I = 40µA, I < 1µA,
OUT Q SD
IN
QFN16
LTC4557
Dual SIM/Smart Card Power Supply and Level Translator
for 1.8V/3V Cards
V : 2.7V to 5.5V, V
= 1.8V/3V, I = 250µA, I < 1µA,
OUT Q SD
IN
QFN16
4556fb
LT/TP 0214 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035‑7417
22
(408)432‑1900 FAX: (408) 434‑0507 www.linear.com/LTC4556
●
●
LINEAR TECHNOLOGY CORPORATION 2003
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