LTC4304IMS_技术文档

LTC4304

Hot Swappable 2-Wire

Bus Buffer with Stuck

Bus Recovery

U

FEATURES

DESCRIPTIO

The LTC^®4304 hot swappable 2-wire bus buffer allows I/O

card insertion into a live backplane without corruption of

the data and clock busses. When a connection is made,

the LTC4304 provides bidirectional buffering, keeping the

backplane and card capacitances isolated. If SDAOUT or

SCLOUTislowfor≥30ms(typ),theLTC4304automatically

■

Automatic Disconnect of SDA/SCL Lines when Bus

is Stuck Low for ≥30ms

■

Fault Flag for Stuck Bus

■

Recovers Stuck Busses with Automatic Clocking*

■

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

■

Prevents SDA and SCL Corruption During Live

FAULT

breaks the data and clock bus connection and

will

Board Insertion and Removal from Backplane

pull low. At this time the LTC4304 automatically generates

up to 16 clock pulses on SCLOUT in an attempt to free the

bus. A connection will be enabled automatically when the

bus becomes free. A logic low on the ACC input enables

the LTC4304’s rise-time accelerators. A logic high on ACC

disables the rise-time accelerators, which allows SDA and

■

Allows Bus Pullup Voltages Above and Below V

CC

■

±±1kV ꢀuman Bodꢁ ꢂodel ꢃSD Protection

■

Isolates Input SDA and SCL Lines from Output

2

Compatible with I C^TM, I C Fast-Mode and SMBus

Standards (Up to 400kHz Operation)

READY Open Drain Output

■

SCL bus pull-up voltages below V .

CC

1V Precharge on All SDA and SCL Lines

During insertion, the SDA and SCL lines are precharged

to 1V to minimize bus disturbances. When driven high,

ENABLE allows the LTC4304 to connect after a stop bit or

busidleoccurs.DrivingENABLElowbreakstheconnection

betweenSDAINandSDAOUT,SCLINandSCLOUT.READY

is an open drain output that indicates when the backplane

and card sides are connected together.

High Impedance SDA, SCL Pins for V = 0V

CC

ENABLE Gates Connection from Input to Output

MSOP 10-Pin and DFN (3mm × 3mm) Packages

U

APPLICATIO S

■

Hot Board Insertion

■

Servers

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6356140, 6650174, 7032051.

■

Capacitance Buffer/Bus Extender

RAID Systems

■

U

TYPICAL APPLICATIO

5V 3.3V

Stuck Bus Resolved with

Automatic Clocking

0.01µF

10k 10k

V

CC

10k 10k

LTC4304

SDAOUT

5V/DIV

STUCK LOW > 30ms

RECOVERS

SCLIN

SCLOUT

BACK_SCL

CARD_SCL

CARD_SDA

SDAIN

5V/DIV

DISCONNECT AT TIMEOUT

AUTOMATIC CLOCKING

SDAIN

SDAOUT

READY

SCLOUT

5V/DIV

BACK_SDA

3.3V

FAULT

5V/DIV

ENABLE

ACC

GND

4304 TA01

100k

4304 TA01b

200 s/DIV

BACKPLANE

CONNECTOR CONNECTOR

CARD

STAGGERED

4304fa

1

LTC4304

W W U W

(Notes ±, 2)

ABSOLUTE AXI U RATI GS

V

to GND ..................................................–0.3V to 7V

SDAIN, SCLIN, SDAOUT, SCLOUT,

FAULT READY (Note 3) .........................................30mA

Storage Temperature Range

CC

SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE,

FAULT, ACC ..................................................–0.3V to 7V

Operating Temperature

MSOP ................................................–65°C to 150°C

DFN....................................................–65°C to 125°C

Lead Temperature (Soldering, 10sec)

LTC4304C ................................................ 0°C to 70°C

LTC4304I .............................................–40°C to 85°C

MSOP ............................................................... 300°C

U

W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ENABLE

SCLOUT

SCLIN

ACC

1

2

3

4

5

10

9

V

CC

TOP VIEW

SDAOUT

SDAIN

FAULT

ENABLE

SCLOUT

SCLIN

ACC

1

2

3

4

5

10

9

V

CC

11

8

SDAOUT

SDAIN

FAULT

8

7

6

GND

6

READY

GND

MS10 PACKAGE

10-LEAD PLASTIC MSOP

= 125°C, θ =200°C/W

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

JA

T

= 125°C, θ = 43°C/W

JMAX

JA

EXPOSED PAD (PIN 11)

PCB GND CONNECTION OPTIONAL

ORDER PART NUMBER

DD PART MARKING*

ORDER PART NUMBER

MS PART MARKING*

LTC4304CDD

LTC4304IDD

LBBD

LTC4304CMS

LTC4304IMS

LTBBC

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

ELECTRICAL CHARACTERISTICS

The

●

denotes the speciﬁcations which applꢁ over the full operating

temperature range, otherwise speciﬁcations are at T = 21°C. V = 2.7V to 1.1V, unless otherwise noted.

A

CC

SYꢂBOL

PARAꢂꢃTꢃR

CONDITIONS

ꢂIN

TYP

ꢂAX

UNITS

Power Supplꢁ

V

Positive Supply Voltage

●

2.7

5.5

8

V

CC

I

CC

Supply Current

Supply Current, ENABLE = GND

V

= 5.5V, V

= 5.5V

= V = 0V (Note 7)

SDAOUT

6

1.5

mA

CC

SDAIN

Startup Circuitrꢁ

V

Precharge Voltage

Bus Idle Time

SDA, SCL Floating, V = 5.5V

●

0.8

60

1

1.2

V

PRE

CC

T

95

175

µs

IDLE

V

READY Output Low Voltage

I

= 3mA

= 6mA, V = 4.7V

●

0.4

V

OL_READY

PULLUP

CC

V

ENABLE Threshold

●

0.8

1.6

1.4

0.1

1.8

2

V

THR_ENABLE

ENABLE

I

ENABLE Input Current

ENABLE from 0 to V

1.5

2

µA

CC

V

THR

SDA, SCL Logic Input Threshold Voltage Rising Edge

V

4304fa

2

LTC4304

The

●

denotes the speciﬁcations which applꢁ over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T = 21°C. V = 2.7V to 1.1V, unless otherwise noted.

A

CC

SYꢂBOL

PARAꢂꢃTꢃR

CONDITIONS

ꢂIN

TYP

ꢂAX

UNITS

V

SDA, SCL, Logic Input Threshold Voltage (Note 6)

Hysteresis

50

mV

HYS

t

I

ENABLE Delay On-Off

READY Delay Off-On

V

= 3.3V

CC

300

10

ns

PLH

(Note 6)

ENABLE Delay Off-On

READY Delay On-Off

V

= 3.3V

●

60

2

95

10

175

10

µs

ns

PHL

CC

(Note 6)

Ready Off Leakage Current

µA

OFF_READY

Rise-Time Accelerators

I

Transient Boosted Pull-Up Current

Positive Transition on SDA, SCL, V = 2.7V,

Slew Rate = 0.8V/µs (Note 5)

3.5

5

5.5

mA

PULLUPAC

CC

t

ACC Delay, On/Off

Input High Voltage

Input Low Voltage

ACC Input Current

(Note 6)

ns

V

PDOFF

V

Measured on ACC

●

0.9V

CC

IH

IL

0.1V

V

CC

I

IN

ACC Shorted to GND or V (Note 8)

–100

25

100

µA

CC

Bus Stuck Low Timeout

t

Bus Stuck Low Timer

SDAOUT, SCLOUT = 0V

●

30

35

0.4

10

ms

V

TIMEOUT

V

FAULT Output Low Voltage

I

= 3mA

PULLUP

OLFAULT

I

V

= 5.5V

CC

µA

OFF_FAULT

Input-Output Connection

V

OS

Input-Output Offset Voltage

10k to V on SDA, SCL,

●

40

50

80

100

120

150

mV

CC

2.7k to V on SDA, SCL

CC

V

CC

= 3.3V, V

= 0.2V (Note 4)

SDA/SCL

C

V

Digital Input Capacitance

SDAIN, SDAOUT, SCLIN, SCLOUT

(Note 6)

10

pF

IN

Input Logic Low Voltage

Input Leakage Current

●

0.4

5

V

µA

V

IL, MAX

LEAK

I

SDA, SCL, V = 5.5V

CC

V

Output Low Voltage, Input = 0V

SDA, SCL Pins, I

= 4mA, V = 2.7V

0

0.19

600

0.3

OL

SINK

CC

Timing Characteristics

2

f

t

I C Maximum Operating Frequency

(Note 6)

400

kHz

µs

I2C, MAX

BUF

Bus Free Time Between Stop and Start

Condition

1.3

t

Hold Time After (Repeated)

Start Condition

(Note 6)

100

ns

HD, STA

t

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time Input

(Note 6)

0

ns

SU, STA

SU, STO

HD, DATI

SU, DAT

0

Data Set-Up Time

100

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

voltage than its input. The magnitude of this offset voltage as a function of

the pull-up resistor and V voltage is shown in the Typical Performance

CC

Characteristics section.

Note 1: I

varies with temperature and V voltage, as shown in

PULLUPAC

CC

Note 2: All currents into pins are positive; all voltages are referenced to

the Typical Performance Characteristics section.

GND unless otherwise speciﬁed.

Note 6: Determined by design, not tested in production.

Note 3: Pulsed less than 5µs.

Note 7: I test performed with connection circuitry active.

CC

Note 4: The connection circuitry always regulates the output to a higher

Note 8: When ﬂoating, the ACC pin can tolerate 5µA of leakage.

4304fa

3

LTC4304

U W

T = 21°C unless otherwise indicated.

A

TYPICAL PERFOR A CE CHARACTERISTICS

I

vs Temperature

Input-Output t

vs Temperature

I

vs Temperature

CC

PꢀL

PULLUPAC

140

120

100

80

14

12

10

8

6.2

6.0

C

= C

OUT

PULLUPIN

= 100pF

IN

V

= 5.5V

R

= R

= 10k

PULLUPOUT

CC

V

= 5.5V

= 3.3V

CC

5.8

5.6

V

CC

60

6

5.4

5.2

40

4

V

= 2.7V

25

V

= 2.7V

CC

20

2

0

–50

0

–50

5.0

–50

0

50

75

100

–25

0

25

50

75

100

0

25

50

75

100

–25

TEMPERATURE (°C)

4303 G02

4303 G03

4303 G01

Connection Circuitrꢁ V

- V

Input-Output t

vs C

PꢀL OUT

OUT

IN

180

160

140

120

100

80

250

200

C

= 50pF

PULLUPIN

IN

R

= R

= 10k

PULLUPOUT

V

= 5.5V

= 2.7V

CC

150

100

50

0

V

CC

60

40

20

0

1000

3000

5000

7000

(Ω)

9000

500

1000

1500

2000

R

C

(pF)

PULLUP

OUT

4303 G05

4303 G04

4304fa

4

LTC4304

U

PI FU CTIO S

ꢃNABLꢃ (Pin ±): Connection Enable. This is a digital

thresholdinputpin. FornormaloperationENABLEishigh.

DrivingENABLEbelow0.8VisolatesSDAINfromSDAOUT,

SCLIN from SCLOUT, asserts READY low and disables

automatic clocking. A rising edge on ENABLE after a fault

hasoccurredunconditionallyforcesaconnectionbetween

SDAIN, SDAOUT and SCLIN, SCLOUT.

RꢃADY (Pin 6): Connection Status Flag. READY provides

a digital ﬂag which indicates the status of the connection

circuitry described in the “Connection Circuitry” section.

Connect a resistor of 10k to V to provide the pull-up.

CC

FAULT (Pin 7): Bus Stuck Low Fault. FAULT is an open

drain N-channel MOSFET which pulls low to signal a bus

stuck low condition. In normal operation, FAULT is high.

SCLOUT (Pin 2): Serial Clock Output. Connect this pin to

the SCL bus on the card.

Connect a 10k resistor from this pin to V to provide

CC

the pull-up.

SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL

on the bus backplane.

SDAIN (Pin 8): Serial Data Input. Connect this pin to the

SDA bus on the backplane.

ACC (Pin 4): Rise-Time Accelerator Control. Connect ACC

SDAOUT (Pin 9): Serial Data Output. Connect this pin to

to V to disable all four accelerators. Connect ACC to

the SDA bus on the card.

CC

GND to enable all four accelerators. Float ACC to enable

V

(Pin±0):SupplyVoltageInput. Placeabypasscapaci-

CC

the SDAOUT and SCLOUT accelerators only. For applica-

tor of at least 0.01µF close to V for best results.

CC

tions when V is greater than the bus pull-up voltage,

CC

ꢃxposed Pad (Pin ±±, DFN Onlꢁ): Exposed pad may be

left open or connected to the ground plane.

connect ACC to V .

CC

GND (Pin 1): Device Ground. Connect this pin to a ground

plane for best results.

4304fa

5

LTC4304

W

BLOCK DIAGRA

LTC4304 2-Wire Bus Buffer with Stuck Bus Protection

3.5mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

ACC_IN

ACC_OUT

CONNECT

V

10

8

CC

SDAIN

SDAOUT

200k

9

200k

PC_CONNECT

PRECHARGE

3.5mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

200k

CONNECT

SCLIN

ACC

SCLOUT

3

4

2

ACC_IN

ACC_OUT

ACC

CTRL

+

–

AUTOMATIC

CLOCKING

–

FAULT

7

30ms

TIMER

UVLO

+

–

1.8V

–

+

LOGIC

PC_CONNECT

1.8V

READY

GND

CONNECT

6

ENABLE

1

+

–

95µs

DELAY

UVLO

1.4V

5

4304 BD

4304fa

6

LTC4304

OPERATION

Start-Up

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms, as

described here.

When the LTC4304 ﬁrst receives power on its V pin,

CC

eitherduringpoweruporliveinsertion,itstartsinanunder

voltage lockout (UVLO) state, ignoring any activity on the

Input to Output Offset Voltage

SDA or SCL pins until V rises above 2.5V (typical).

CC

When a logic low voltage, V

, is driven on any of the

LOW1

During this time, the precharge circuitry is active and

forces 1V through 200K nominal resistors to the SDA

and SCL pins. Because the I/O card is being plugged

into a live backplane, the voltage on the backplane SDA

LTC4304’s data or clock pins, the LTC4304 regulates the

voltage on the opposite side of the part (call it V

)

LOW2

to a slightly higher voltage, as directed by the following

equation:

and SCL busses may be anywhere between 0V and V .

CC

V

LOW2

= V + 75mV + (V /R) • 20Ω (typical)

LOW1 CC

Precharging the SCL and SDA pins to 1V minimizes the

worst-case voltage differential these pins will see at the

moment of connection, therefore minimizing the amount

of disturbance caused by the I/O card.

where R is the bus pull-up resistance in ohms. For ex-

ample, if a device is forcing SDAOUT to 10mV where V

CC

= 3.3V and the pull-up resistor R on SDAIN is 10k, then

the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 20

= 91.6mV(typical). See the Typical Performance Charac-

teristics section for curves showing the offset voltage as

Once the LTC4304 comes out of UVLO, it assumes that

SDAIN and SCLIN have been inserted into a live system

and that SDAOUT and SCLOUT are being powered up at

the same time as itself. Therefore, it looks for either a stop

bit or bus idle condition on the input side to indicate the

completion of a data transaction. When either one occurs,

the part also veriﬁes that both the SDAOUT and SCLOUT

voltages are high. When all of these conditions are met,

the input-to-output connection circuitry is activated, join-

ing the SDA and SCL busses on the I/O card with those

on the backplane and READY goes high.

a function of V and R.

CC

Bus Stuck Low Timeout

When SDAOUT or SCLOUT is low, an internal timer starts.

The timer is only reset when SDAOUT and SCLOUT are

both high. If they do not go high within 30ms (typical),

FAULT pulls low indicating a bus stuck condition and the

connection between SDAIN and SDAOUT, and SCLIN

and SCLOUT is broken. After a delay of at least 40µs, the

LTC4304 automatically generates up to 16 clock pulses at

8.5kHz (typical) on SCLOUT in an attempt to unstick the

bus.WhenSDAOUTandSCLOUTgohigh,FAULTiscleared

and reconnection occurs when the conditions described

in the “Start-Up” section above are satisﬁed.

Connection Circuitrꢁ

Oncetheconnectioncircuitryisactivated,thefunctionality

of the SDAIN and SDAOUT pins is identical. A low forced

on either pin at any time results in both pin voltages be-

ing low. For proper operation, logic low input voltages

shouldbenohigherthan0.4Vwithrespecttotheground

pin voltage of the LTC4304. SDAIN and SDAOUT enter

a logic high state only when all devices on both SDAIN

and SDAOUT release high. The same is true for SCLIN

and SCLOUT. This important feature ensures that clock

stretching, clock synchronization, arbitration and the ac-

knowledge protocol always work, regardless of how the

devices in the system are tied to the LTC4304.

When powering up into a bus stuck low condition, the

connection circuitry joining the SDA and SCL busses on

the I/O card with those on the backplane is not activated.

30ms after UVLO, FAULT pulls low indicating a bus stuck

low condition, and automatic clocking takes place as

described above.

Propagation Delaꢁs

During a rising edge, the rise-time on each side is de-

termined by the bus pull-up resistor and the equivalent

capacitance on the line. If the pull-up resistors are the

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

4304fa

7

LTC4304

OPERATION

OUTPUT SIDE

50pF

INPUT SIDE

150pF

0.5V/DIV

INPUT SIDE

50pF

0.5V/DIV

OUTPUT SIDE

150pF

0.5V/DIV

4303 F01

4303 F02

200ns/DIV

20ns/DIV

Figure ±. Input-Output Connection t

Figure 2. Input-Output Connection t

PLꢀ

PꢀL

same, a difference in rise-time occurs which is directly

proportional to the difference in capacitance between the

RꢃADY Digital Output

The READY pin provides a digital ﬂag which indicates the

status of the connection circuitry described previously in

the “Connection Circuitry” section. READY is high when

the connection circuitry is active, and pulls low when

there is not a valid connection. The pin is driven by an

open drain pull-down capable of sinking 3mA while hold-

two sides. This effect is displayed in Figure 1 for a V

CC

= 3.3V and a 10k pull-up resistor on each side (50pF on

one side and 150pF on the other). Since the output side

has less capacitance than the input, it rises faster and the

effective t

is negative.

PLH

There is a propagation delay, t , through the connec-

ing 0.4V on the pin. Connect a resistor of 10k to V to

provide the pull-up.

PHL

CC

tion circuitry for falling waveforms. Figure 2 shows the

falling edge waveforms. An external driver pulls down

the voltage on the side with 50pF capacitance; LTC4304

pulls down the voltage on the opposite side with a delay

of 80ns. This delay is always positive and is a function of

supply voltage, temperature and the pull-up resistors and

equivalent bus capacitances on both sides of the bus. The

FAULT

Digital Output

The FAULT pin provides a digital ﬂag which is low when

SDAOUTandSCLOUThavenotbothbeenhighwithin30ms

(typical). The pin is driven by an open drain pull-down

capable of sinking 3mA while holding 0.4V on the pin.

Typical Performance Characteristics section shows t

PHL

Connect a resistor of 10k to V to provide the pull-up.

CC

as a function of temperature and voltage for 10k pull-up

resistors and 100pF equivalent capacitance on both sides

of the part. Larger output capacitances translate to longer

delays. Users must quantify the difference in propagation

timesforarisingedgeversusafallingedgeintheirsystems

and adjust setup and hold times accordingly.

ꢃNABLꢃ

When the ENABLE pin is driven below 0.8V with respect

to the LTC4304’s ground, the backplane side is discon-

nected from the card side, and the READY pin is internally

pulled low. When the pin is driven above 2V, the part

waits for data transactions on both the backplane and

card sides to be complete (as described in the Start-Up

section) before connecting the two sides. At this time the

internal pulldown on READY releases. When ENABLE is

low, automatic clocking is disabled.

4304fa

8

LTC4304

OPERATION

A rising edge on ENABLE after a stuck bus condition has

occurred forces a connection between SDAIN, SDAOUT

and SCLIN, SCLOUT even if bus idle conditions are not

met. At this time the internal 30ms timer is reset but not

disabled.

reduce power consumption, or bus capacitance beyond

2

that speciﬁed in I C, while still meeting system rise time

requirements.Duringpositivebustransitions,theLTC4304

switches in 3.5mA (typical) of current to quickly slew the

SDA and SCL lines once their DC voltages exceed 0.8V.

Choose a pull-up resistor so that the bus will rise on its

own at a rate of at least 0.8V/µs to guarantee activation

of the accelerators. Rise time accelerators turn off when

Rise Time Accelerators

Once connection has been established, rise time accel-

erator circuits on all four SDA and SCL pins are activated

(assuming accelerators are enabled, see ACC pin descrip-

tion). These allow the use of a large pull-up resistor to

SDA and SCL lines are approximately 1V below V .

CC

Rise time accelerators are automatically disabled during

automatic clocking.

APPLICATIONS INFORMATION

Resistor Pull-Up Selection

The system pull-up resistors must be strong enough

to provide a positive slew rate of 0.8V/µs on the SDA

and SCL pins, in order to activate the rise time accelera-

tors during rising edges. Choose maximum resistor value

the LTC4304 drives the capacitance on the card side and

thebackplanemustdriveonlythedigitalinputcapacitance

of the LTC4304, which is less than 10pF.

In most applications the LTC4304 will be used with a

R

using the formula:

PULL-UP(MAX)

staggered connector where V and GND will be long

CC

pins. SDA and SCL are medium length pins to ensure that

V

– 0.8V •1250[ns/V]

(

)

BUS(MIN)

R_PULLUP(MAX)[kΩ] =

the V and GND pins make contact ﬁrst. This will allow

CC

C_BUS[pF]

the precharge circuitry to be activated on SDA and SCL

before they make contact. ENABLE is a short pin that is

pulleddownwhennotconnected.Thisistoensurethatthe

connection between the backplane and the cards data and

clock busses is not enabled until the transients associated

with live insertion have settled.

where V

ply voltage, and C

tive bus line.

is the minimum operating pull-up sup-

BUS

BUSMIN

the total capacitance on respec-

For example, assume V

= V = 3.3V, and assuming

CC

BUS

10ꢀ supply tolerance, V

= 2.97V. With C

=

BUSMIN

BUS

Figure3showstheLTC4304inaCompactPCI^TMconﬁgura-

100pF, R

= 27.1k. Therefore a smaller pull-up

PULL-UP, MAX

resistor than 27.1k must be used, so 10k works ﬁne.

tion. Connect V and ENABLE to the output of one of the

CC

CompactPCIpowersupplyHotSwapcircuits.Useapull-up

Live Insertion and Capacitance Buffering Application

resistor to ENABLE for a card side enable/disable. V is

CC

Figures 3 through 6 illustrate applications of the LTC4304

that take advantage of both its Hot Swap^TMcontrolling and

capacitancebufferingfeatures. Inalloftheseapplications,

note that if the I/O cards were plugged directly into the

backplanewithouttheLTC4304buffer, allofthebackplane

andcardcapacitanceswouldadddirectlytogether,making

rise-andfall-timerequirementsdifﬁculttomeet. Placinga

LTC4304 on the edge of each card, however, isolates the

card capacitance from the backplane. For a given I/O card,

monitored by a ﬁltered UVLO circuit. With the V voltage

CC

powering up after all the other pins have established con-

nection, the UVLO circuit ensures that the backplane and

the card data and clock busses are not connected until

the transients associated with live insertion have settled.

Owing to their small capacitance, the SDAIN and SCLIN

pins cause minimal disturbance on the backplane busses

when they make contact with the connector.

Hot Swap is a trademark of Linear Technology Corporation.

4304fa

9

LTC4304

APPLICATIONS INFORMATION

BACKPLANE

CONNECTOR

STAGGERED

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

POWER SUPPLY

HOT SWAP

V

CC

R3

10k

R4

10k

R5

10k

R6

10k

0.01µF

R1

R2

10k

CARD

ENABLE/DISABLE

10k

V

CARD1_SDA

CARD1_SCL

BD_SEL

SDA

ENABLE

SDAIN

SCLIN

SDAOUT

CC

SCLOUT

READY

LTC4304

SCL

GND

I/O PERIPHERAL CARD 2

C3

POWER SUPPLY

HOT SWAP

R7

10k

R8

10k

R9

10k

R10

10k

0.01µF

CARD

ENABLE/DISABLE

CARD2_SDA

CARD2_SCL

V

ENABLE

SDAIN

SCLIN

SDAOUT

CC

SCLOUT

READY

LTC4304

GND

I/O PERIPHERAL CARD N

C5

POWER SUPPLY

HOT SWAP

R11

10k

R12

10k

R13

10k

R14

10k

0.01µF

CARD

ENABLE/DISABLE

CARDN_SDA

CARDN_SCL

V

ENABLE

SDAIN

SCLIN

SDAOUT

CC

SCLOUT

READY

LTC4304

GND

4304 F03

Figure 3. Inserting ꢂultiple I/O Cards into a Live Backplane Using the LTC4304 in a CompactPCI Sꢁstem

4304fa

10

LTC4304

APPLICATIONS INFORMATION

Figure 4 shows the LTC4304 in a PCI application where all

of the pins have the same length. In this case, a RC ﬁlter

circuit on the I/O card with a product of 10ms provides a

ﬁltertopreventtheLTC4304frombecomingactivateduntil

the transients associated with live insertion have settled.

Connect the capacitor between ENABLE and GND, and the

resistor from V to ENABLE.

CC

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

V

CC

R3

R4

10k

R5

10k

R6

10k

R11

10k

0.01µF

100k

R1

R2

10k

V

ENABLE

SDAIN

SCLIN

ACC

SDAOUT

CARD1_SDA

CARD1_SCL

CC

SCLOUT

READY

FAULT

SDA

SCL

LTC4304

GND

C2

0.1µF

I/O PERIPHERAL CARD 2

C3

R8

10k

R9

10k

R10

10k

R12

10k

R7

100k

0.01µF

V

CARD2_SDA

CARD2_SCL

ENABLE

SDAIN

SCLIN

ACC

SDAOUT

SCLOUT

READY

FAULT

CC

LTC4304

GND

C4

0.1µF

4304 F04

•

Figure 4. Inserting ꢂultiple I/O Cards into a Live Backplane Using the LTC4304 in a PCI Sꢁstem

4304fa

11

LTC4304

APPLICATIONS INFORMATION

Supplꢁ Independent Operation

celeratorscannotbeused.FloatACCinapplicationswhere

the pull-up voltage on SDAIN and SCLIN is < V and the

CC

Figure5illustratesapplicationsoftheLTC4304withdiffer-

pull-upvoltageonSDAOUTandSCLOUTis≥V .Connect

CC

ent bus pull up and V voltages, demonstrating its ability

CC

ACC to ground in applications where V is ≤ SDA and

CC

to recognize and buffer bus data levels that are above or

SCL pull-up voltages. Connect ACC to V for applications

CC

below its V supply voltage. In applications where V

CC

where SDA and SCL pull-up voltages are ≤ V .

CC

voltage is greater than bus pull-up voltages, rise-time ac-

BACKPLANE

CONNECTOR

STAGGERED

CONNECTOR

5V

C1

0.01µF

R3

10k

R4

10k

3.3V

R1

10k

R2

10k

V

ACC

SDAOUT

SCLOUT

READY

FAULT

CARD_SDA

CARD_SCL

CC

SDAIN

SCLIN

ENABLE

SDA

SCL

LTC4304

GND

5V

R5

10k

STAGGERED

CONNECTOR

BACKPLANE

CONNECTOR

3.3V

C2

0.01µF

R8

10k

R9

10k

5V

R6

10k

R7

10k

V

ACC

SDAOUT

SCLOUT

READY

FAULT

CARD_SDA

CARD_SCL

CC

SDAIN

SCLIN

ENABLE

SDA

SCL

LTC4304

GND

3.3V

R10

10k

STAGGERED

CONNECTOR

BACKPLANE

CONNECTOR

2.5V

3.3V

C3

0.01µF

R13

10k

R14

10k

5V

R11

10k

R12

10k

V

ACC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

CC

SDAIN

SCLIN

ENABLE

SDA

SCL

LTC4304

GND

3.3V

FAULT

R15

10k

4304 F05

Figure 1. Tꢁpical Supplꢁ Independent Applications

4304fa

12

LTC4304

APPLICATIONS INFORMATION

V

CC

ATCA BOARD

C2

SHELF MANAGER

C1

0.01µF

R3

R4

R1

10k 10k

R2

R5

R6

0.01µF

2.7k 2.7k

10k 10k

V

CC

ENABLE

SDAOUT

SDAIN

SCLIN

SDAOUT

SCLOUT

SDAIN

SCLIN

ShMC

IPMC

LTC4304

SCLOUT

IPM

BUS

(1 OF 2)

4304 F06

Figure 6. Simpliﬁed ATCA IPꢂB Application

4304fa

13

LTC4304

U

PACKAGE DESCRIPTIO

DD Package

±0-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 01-08-±699)

R = 0.115

TYP

6

0.38 0.10

10

0.675 0.05

3.50 0.05

2.15 0.05 (2 SIDES)

1.65 0.05

3.00 0.10

(4 SIDES)

1.65 0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

PACKAGE

OUTLINE

(DD10) DFN 1103

5

1

0.25 0.05

0.50 BSC

0.75 0.05

0.200 REF

0.25 0.05

0.50

BSC

2.38 0.10

(2 SIDES)

2.38 0.05

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

4304fa

14

LTC4304

U

PACKAGE DESCRIPTIO

ꢂS Package

±0-Lead Plastic ꢂSOP

(Reference LTC DWG # 01-08-±66±)

0.889 0.127

(.035 .005)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

3.00 0.102

(.118 .004)

(NOTE 3)

(.0197)

0.497 0.076

(.0196 .003)

REF

0.50

0.305 0.038

(.0120 .0015)

TYP

10 9

8

7 6

BSC

RECOMMENDED SOLDER PAD LAYOUT

3.00 0.102

(.118 .004)

(NOTE 4)

4.90 0.152

(.193 .006)

DETAIL “A”

0.254

(.010)

0 – 6 TYP

GAUGE PLANE

1

2

3

4 5

0.53 0.152

(.021 .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.127 0.076

(.005 .003)

MSOP (MS) 0603

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

4304fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC4304

U

TYPICAL APPLICATIO

5V 3.3V

C1

0.01µF

R4

R5

10k 10k

V

CC

R1

R2

10k 10k

LTC4304

SCLIN

SDAIN

SCLOUT

BACK_SCL

BACK_SDA

CARD_SCL

SDAOUT

READY

CARD_SDA

FAULT

FROM

MICROPROCESSOR

ENABLE

ACC

GND

R3

10k

4304 F07

BACKPLANE

CONNECTOR

STAGGERED

CONNECTOR

CARD

Figure 7. Sꢁstem with Active Connection Control

RELATED PARTS

PART NUꢂBꢃR

DꢃSCRIPTION

COꢂꢂꢃNTS

LTC1380/LTC1393

Single-Ended 8-Channel/Differential 4-Channel Analog

Mux with SMBus Interface

Low R_ON: 35Ω Single-Ended/70Ω Differential,

Expandable to 32 Single or 16 Differential Channels

LTC1427-50

Micropower, 10-Bit Current Output DAC

with SMBus Interface

Precision 50µA 2.5ꢀ Tolerance Over Temperature,

4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale

LTC1623

Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability

LTC1663

SMBus Interface 10-Bit Rail-to-Rail Micropower DAC

SMBus Accelerator

DNL < 0.75LSB Max, 5-Lead SOT-23 Package

LTC1694/LTC1694-1

Improved SMBus/I²C Rise-Time,

Ensures Data Integrity with Multiple SMBus/I²C Devices

LT1786F

LTC1695

LTC1840

SMBus Controlled CCFL Switching Regulator

SMBus/I²C Fan Speed Controller in ThinSOT^TM

Dual I²C Fan Speed Controller

1.25A, 200kHz, Floating or Grounded Lamp Conﬁgurations

0.75Ω PMOS 180mA Regulator, 6-Bit DAC

Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0

Isolates Backplane and Card Capacitances

LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer

LTC4300A-3

LTC4301

Hot Swappable 2-Wire Bus Buffer

Provides Level Shifting and Enable Functions

Supply Independent

Supply Independent Hot Swappable 2-Wire Bus Buffer

LTC4301L

Hot Swappable 2-Wire Bus Buffer

with Low Voltage Level Translation

Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN

LTC4302-1/LTC4302-2

LTC4303

Addressable 2-Wire Bus Buffer

Address Expansion, GPIO, Software Controlled

2

Hot Swappable 2-Wire Bus Buffer with Stuck

Bus Recovery

Provides Automatic Clocking to Free Stuck I C Busses

ThinSOT is a trademark of Linear Technology Corporation.

4304fa

LT 0806 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4304IMS
厂家：	Linear
描述：	Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery 热插拔2线总线缓冲器具有阻塞总线恢复
文件：	总16页 (文件大小：637K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4304IMS [Linear]

相关型号：

LTC4304IMS#TR

LTC4305

LTC4305CDHD

LTC4305CDHD#TRPBF

LTC4305CGN

LTC4305CGN#PBF

LTC4305CGN#TR

LTC4305CGN#TRPBF

LTC4305IDHD

LTC4305IDHD#PBF

LTC4305IDHD#TR

LTC4305IDHD#TRPBF