LTC3880IUJ#TRPBF [Linear]
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C;
| 型号： | LTC3880IUJ#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C 控制器 |
| 文件： | 总36页 (文件大小：550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3861-1
Dual, Multiphase Step-Down
Voltage Mode DC/DC Controller
with Accurate Current Sharing
DescripTion
FeaTures
The LTC®3861-1 is a dual PolyPhase® synchronous step-
down switching regulator controller for high current
distributed power systems, digital signal processors, and
othertelecomandindustrialDC/DCpowersupplies.Ituses
aconstant-frequencyvoltagemodearchitecturecombined
with very low offset, high bandwidth error amplifiers and
a remote output sense differential amplifier for excellent
transient response and output regulation.
n
Operates with Power Blocks, DrMOS or External
Gate Drivers and MOSFETs
n
Constant-Frequency Voltage Mode Control with
Accurate Current Sharing
±±0.75 ±0ꢀV Voltage Reference
n
n
Differential Remote Output Voltage Sense Amplifier
Multiphase Capability—Up to 12-Phase Operation
n
n
Programmable Current Limit
n
Safely Powers a Prebiased Load
ThecontrollerincorporateslosslessinductorDCRcurrent
sensingtomaintaincurrentbalancebetweenphasesandto
provide overcurrent protection. The chip operates from a
n
Programmable or PLL-Synchronizable Switching
Frequency Up to 2027MHz
n
Lossless Current Sensing Using Inductor DCR or
V
supply between 3V and 5.5V and is designed for step-
CC
Precision Current Sensing with Sense Resistor
down conversion from V between 3V and 24V to output
IN
n
V
Range: 3V to 5.5V
CC
voltages between 0.6V and V – 0.5V.
CC
n
n
n
n
n
V Range: 3V to 24V
IN
Inductor current reversal is disabled during soft-start to
safely power prebiased loads. The constant operating
frequency can be synchronized to an external clock or
linearly programmed from 250kHz to 2.25MHz. Up to six
LTC3861-1controllerscanoperateinparallelfor1-, 2-, 3-,
4-, 6- or 12-phase operation.
Power Good Output Voltage Monitor
Output Voltage Tracking Capability
Programmable Soft-Start
Available in a 32-Pin 5mm × 5mm QFN Package
applicaTions
TheLTC3861-1ispin-to-pincompatiblewiththeLTC3860.
It is available in a 32-pin 5mm × 5mm QFN package. The
LTC3861is a 36-pin QFN version of the LTC3861-1, which
has dual differential output voltage sense amplifiers.
L, LT, LTC, LTM, PolyPhase, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 6144194, 5055767
n
High Current Distributed Power Systems
n
DSP, FPGA and ASIC Supplies
n
Datacom and Telecom Systems
Industrial Power Supplies
n
Typical applicaTion
V
IN
, 7V TO 14V
LTC4449
GND
180µF
IN
V
V
V
, 7V TO 14V
IN
TG
TS
BG
V
LOGIC
CC
BOOST
CC
V
CC
V
VINSNS
PWM1
CC
0.47µH
2.87k
FREQ
FB2
1µF
28.7k
LTC3861-1
59k
0.22µF
RUN1,2
I
LIM2
I
LIM1
VSNSOUT
VSNSP
ISNS1P
ISNS1N
ISNS2N
ISNS2P
V
1.2V
60A
0.22µF
0.22µF
OUT
V
OUT
VSNSN
330µF
× 6
100µF
× 4
CONFIG
V
IN
2.87k
1nF
LTC4449
PWM2
IN
V
CC
BOOST
GND
TG
20k 221Ω
0.47µH
V
CC
FB1
LOGIC
I
AVG
38611 TA01
V
TS
COMP1,2 SS1,2 SGND CLKIN
BG
1nF
20k
13k 220pF
100pF
0.1µF
0.22µF
38611f
1
LTC3861-1
absoluTe maximum raTings
pin conFiguraTion
(Note 1)
V
CC
Voltage.................................................. –0.3V to 6V
TOP VIEW
VINSNS Voltage ......................................... –0.3V to 30V
RUN Voltage................................................. –0.3V to 6V
ISNS1P, ISNS1N,
32 31 30 29 28 27 26 25
V
1
2
3
4
5
6
7
8
24 RUN1
ISNS2P, ISNS2N........................... –0.3V to (V + 0.1V)
CC
CC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
23
22
21
I
LIM1
All Other Pins................................–0.3V to (V + 0.3V)
CC
ISNS1P
ISNS1N
Operating Junction Temperature Range
33
SGND
(Notes 2, 3)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
20 ISNS2N
ISNS2P
19
18
I
LIM2
17 RUN2
9
10 11 12 13 14 15 16
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 34°C/W
JA
JMAX
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
orDer inFormaTion
LEAD FREE FINISH
LTC3861EUH-1#PBF
LTC3861IUH-1#PBF
TAPE AND REEL
PART MARKING*
38611
PACKAGE DESCRIPTION
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
LTC3861EUH-1#TRPBF
LTC3861IUH-1#TRPBF
38611
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
For more information on soldering profiles, go to: http://cds.linear.com/docs/Packaging/Linear_Technology_Surface_Mount_Products.pdf
38611f
2
LTC3861-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 27°C (Note 3)0 VCC = 7V, VRUN1,2 = 7V, VFREQ = 7V, VCLKIN = ±V,
VFB = ±0ꢀV, fOSC = ±0ꢀMHz, unless otherwise specified0
SYMBOL
PARAMETER
CONDITIONS
MIN
3
TYP
MAX
24
UNITS
l
l
V
V
V
V
Range
V
= 5V
CC
V
V
IN
IN
Voltage Range
3
5.5
CC
CC
I
Q
Input Voltage Supply Current
Normal Operation
Shutdown Mode
UVLO
V
V
V
= 5V
= 0V
UVLO
18
6
mA
µA
mA
RUN1,2
RUN1,2
CC
50
< V
V
RUN
RUN Input Threshold
V
RUN
V
RUN
Rising
Hysteresis
1.95
2.25
250
2.45
V
mV
I
RUN Input Pull-Up Current
V
= 2.4V
1.5
µA
RUN
RUN1,2
l
V
Undervoltage Lockout Threshold
V
V
Rising
3.0
V
UVLO
CC
CC
Hysteresis
100
2.5
1.5
mV
I
t
Soft-Start Pin Output Current
Internal Soft-Start Time
V
= 0V
µA
SS
SS
ms
SS(INTERNAL)
V
Regulated Feedback Voltage
–40°C to 85°C
–40°C to 125°C
595.5
594
600
600
604.5
606
mV
mV
FB
l
∆V /∆V
Regulated Feedback Voltage Line Dependence 3.0V < V < 5.5V
0.05
20
0.2
22
%/V
µA
FB
CC
CC
I
I
Pin Output Current
V
ILIM
= 0.8V
19
LIMIT
LIM
Power Good
V
V
V
PGOOD/V Overvoltage Threshold
V
V
Falling
645
660
mV
mV
FB(OV)
FB
FB
FB
Rising
650
530
670
550
PGOOD/V Undervoltage Threshold
V
V
Falling
Rising
540
555
mV
mV
FB(UV)
FB
FB
FB
PGOOD Pull-Down Resistance
PGOOD Leakage Current
PGOOD Delay
15
60
2
Ω
µA
µs
PGOOD(ON)
PGOOD(OFF)
PGOOD
I
t
V
V
= 5V
PGOOD
PGOOD
High to Low
30
Error Amplifier
I
I
FB Pin Input Current
V
= 600mV
FB
–100
100
nA
FB
COMP Pin Output Current
Sourcing
Sinking
1
5
mA
mA
OUT
A
Open-Loop Voltage Gain
Slew Rate
75
45
40
dB
V/µs
MHz
V(OL)
SR
(Note 4)
(Note 4)
f
COMP Unity-Gain Bandwidth
0dB
Differential Amplifier
l
A
V
Differential Amplifier Voltage Gain
Input Referred Offset
V
V
= 0V
= 0V
1.007
–2
1
0.993
2
V/V
mV
MHz
µA
V
VSNSN
VSNSN
OS
f
I
I
DA Unity-Gain Crossover Frequency
Maximum Sinking Current
Maximum Sourcing Current
Maximum Output Voltage
(Note 4)
40
100
500
4
0dB
DIFFOUT = 1.2V
DIFFOUT = 1.2V
OUT(SINK)
OUT(SOURCE)
µA
V
V
SNSOUT(MAX)
Current Sense Amplifier
V
Maximum Differential Current Sense Voltage
(V -V
50
mV
ISENSE(MAX)
)
ISNSP ISNSN
A
V
Voltage Gain
Input Common Mode Range
18.5
V/V
V
V(ISENSE)
–0.3
V
CC
– 0.5
CM(ISENSE)
38611f
3
LTC3861-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 27°C (Note 3)0 VCC = 7V, VRUN1,2 = 7V, VFREQ = 7V, VCLKIN = ±V,
VFB = ±0ꢀV, fOSC = ±0ꢀMHz, unless otherwise specified0
SYMBOL
PARAMETER
CONDITIONS
= 1.5V
MIN
TYP
MAX
UNITS
nA
I
SENSE Pin Input Current
Current Sense Input Referred Offset
V
100
ISENSE
CM
l
V
OS
–40°C to 125°C
–1.25
1.25
mV
Oscillator and Phase-Locked Loop
f
Oscillator Frequency
V
= 0V
= 0V
= 5V
OSC
CLKIN
l
l
V
V
360
540
400
600
440
660
kHz
kHz
FREQ
FREQ
V
= 5V
CLKIN
R
R
R
R
R
< 24.9k
= 36.5k
= 48.7k
= 64.9k
= 88.7k
200
600
1
1.45
2.1
kHz
kHz
MHz
MHz
MHz
FREQ
FREQ
FREQ
FREQ
FREQ
Maximum Frequency
Minimum Frequency
3
MHz
MHz
0.25
21.5
I
t
t
FREQ Pin Output Current
CLKIN Pulse Width High
CLKIN Pulse Width Low
CLKIN Pull-Up Resistance
CLKIN Input Threshold
V
V
V
= 0.8V
18.5
100
100
20
µA
ns
FREQ
FREQ
= 0V to 5V
= 0V to 5V
CLKIN(HI)
CLKIN(LO)
CLKIN
CLKIN
ns
R
13
kΩ
CLKIN
CLKIN
V
V
V
Falling
Rising
1.2
2
V
V
CLKIN
CLKIN
V
FREQ Input Threshold
V
= 0V
Falling
Rising
FREQ
CLKIN
V
V
1.5
2.5
V
V
FREQ
FREQ
V
V
CLKOUT Low Output Voltage
I
I
= –500µA
= 500µA
= 0V
0.2
V
V
OL(CLKOUT)
OH(CLKOUT)
LOAD
LOAD
CLKOUT High Output Voltage
V
– 0.2
CC
Channel 1-to-Channel 2 Phase Relationship
V
V
V
180
180
120
Deg
Deg
Deg
θ -θ
2
PHSMD
1
= Float
PHSMD
PHSMD
= V
CC
CLKOUT-to-Channel 1 Phase Relationship
V
V
V
= 0V
60
90
240
Deg
Deg
Deg
θ -θ
CLKOUT 1
PHSMD
PHSMD
PHSMD
= Float
= V
CC
PWM/PWMEN Outputs
l
l
PWM
PWM Output High Voltage
I
I
= 500µA
4.5
4.5
V
V
LOAD
PWM Output Low Voltage
= –500µA
0.5
5
LOAD
PWM Output Current in Hi-Z State
PWM Maximum Duty Cycle
PWMEN Output High Voltage
µA
%
V
91.5
l
PWMEN
I
= 1mA
LOAD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
specifications from 0°C to 85°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTC3861-1I is guaranteed over the full –40°C to 125°C
operating junction temperature range. The maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistors and other environmental factors.
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • 34°C/W)
J
A
D
Note 3: The LTC3861-1 is tested under pulsed load conditions such that
T . The LTC3861-1E is guaranteed to meet performance
Note 4: Guaranteed by design.
T
≈
A
J
38611f
4
LTC3861-1
Typical perFormance characTerisTics
Load Step Transient Response
(2-Phase Using D12S1R847A
Power Block)
Load Step Transient Response
(2-Phase Using LTC4449)
Load Step Transient Response
(Single Phase Using LTC4449)
I
LOAD
20A/DIV
I
I
L
I
LOAD
L1
10A/DIV
20A/DIV
10A/DIV
I
L2
10A/DIV
V
OUT
V
OUT
50mV/DIV
50mV/DIV
V
OUT
AC-COUPLED
AC-COUPLED
50mV/DIV
AC-COUPLED
38611 G02
38611 G01
38611 G03
40µs/DIV
20µs/DIV
50µs/DIV
V
V
= 12V
I
f
STEP = 0A TO 20A TO 0A
V
V
= 12V
I
f
STEP = 3A TO 18A TO 3A
V
V
= 12V
I
STEP = 4A TO 20A TO 4A
LOAD
IN
OUT
LOAD
SW
IN
OUT
LOAD
SW
IN
OUT
= 1.2V
= 300kHz
= 1.2V
= 300kHz
= 1.2V
f
= 400kHz
SW
Load Step Transient Response
(3-Phase Using FDMFꢀ.±.B
DrMOS)
Load Step Transient Response
(4-Phase Using TDA2122±
DrMOS)
Line Step Transient Response
(2-Phase Using LTC4449)
V
IN
I
L1
10V/DIV
10A/DIV
I
LOAD
40A/DIV
I
L1
I
L2
10A/DIV
10A/DIV
I
L2
I
10A/DIV
L3
V
10A/DIV
OUT
50mV/DIV
V
V
OUT
OUT
AC-COUPLED
50mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
38611 G04
38611 G06
38611 G05
50µs/DIV
20µs/DIV
40µs/DIV
V
V
= 12V
I
f
STEP = 0A TO 30A TO 0A
V
V
= 7V TO 14V IN 20µs
= 1.2V
I
= 20A
LOAD
V
V
= 12V
= 1V
I
STEP = 40A TO 80A TO 40A
LOAD
IN
OUT
LOAD
SW
IN
OUT
IN
OUT
= 1.2V
= 500kHz EXTERNAL CLOCK
f
= 300kHz
SW
f
= 500kHz EXTERNAL CLOCK
SW
Feedback Voltage VFB
vs Temperature
Efficiency vs Load Current
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
96
94
92
90
88
86
84
82
80
78
76
74
72
70
601.00
600.75
600.50
600.25
600.00
599.75
599.50
V
V
= 12V
IN
OUT
V
IN
= 12V, V
= 1V
OUT
= 1.2V
4-PHASE TDA21220 DrMOS
= 500kHz EXTERNAL CLOCK
2-PHASE, LTC4449
= 300kHz
f
f
SW
SW
20
30
40
50
60
70
0
25 50 75 100 125 150
0
10
–50 –25
20 30 40 50 60
100
0
10
70 80 90
LOAD CURRENT (A)
TEMPERATURE (°C)
LOAD CURRENT (A)
38611 G08
38611 G07
38611 G09
38611f
5
LTC3861-1
Typical perFormance characTerisTics
Start-Up Response
(2-Phase Using LTC4449)
Start-Up Response (3-Phase
Using FDMFꢀ.±.B DrMOS)
Regulated VFB vs Supply Voltage
604
602
600
598
V
RUN
5V/DIV
I
L1
10A/DIV
I
L1
I
L2
10A/DIV
10A/DIV
I
L3
I
L2
10A/DIV
10A/DIV
V
OUT
500mV/DIV
V
OUT
INTERNAL
SOFT-START
INTERNAL
SOFT-START
1V/DIV
38611 G12
38611 G11
500µs/DIV
R = 30mΩ
LOAD
500µs/DIV
R 50mΩ
LOAD
V
V
= 12V
OUT
IN
V
V
= 12V
IN
OUT
= 1V
f
= 500kHz
SW
596
= 1.2V
3
4
5
6
SUPPLY VOLTAGE (V)
38611 G10
Soft-Start Start-Up Response
(2-Phase Using D12S1R847A
Power Block)
Coincident Tracking (Single
Phase Using FDMFꢀ.±.B DrMOS)
Ratiometric Tracking (Single
Phase Using FDMFꢀ.±.B DrMOS)
3.3V TRACKING
SIGNAL
3.3V TRACKING
SIGNAL
V
V
OUT
OUT
500mV/DIV
500mV/DIV
V
OUT
200mV/DIV
38611 G14
38611 G15
38611 G13
2ms/DIV
2ms/DIV
5ms/DIV
V
V
= 12V
f
= 500kHz EXTERNAL CLOCK
V
V
= 12V
f
= 500kHz EXTERNAL CLOCK
SW
V
V
= 12V
0.1µF CAPACITOR ON TRACK/SS1
f = 400kHz
SW
IN
OUT
SW
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.2V
Start-Up Response Into a 3±±mV
Prebiased Output (Single Phase
Using FDMFꢀ.±.B DrMOS)
Initial .-Cycle Nonsynchronous
Start-Up (Single Phase Using
FDMFꢀ.±.B DrMOS)
Start-Up Into a Short (Single
Phase Using FDMFꢀ.±.B DrMOS)
I
PWM
2V/DIV
L
I
L
10A/DIV
10A/DIV
V
OUT
500mV/DIV
PWM
2V/DIV
PWM
2V/DIV
TRACK/SS
500mV/DIV
V
V
OUT
500mV/DIV
OUT
I
L
500mV/DIV
20A/DIV
38611 G16
38611 G17
38611 G18
200µs/DIV
5µs/DIV
10ms/DIV
V
V
= 12V
f
= 500kHz EXTERNAL CLOCK
V
V
= 12V
300mV PREBIASED OUTPUT
SW
V
V
= 12V
f = 500kHz EXTERNAL CLOCK
SW
IN
OUT
SW
IN
OUT
IN
OUT
= 1.8V
= 1.8V
f
= 500kHz EXTERNAL CLOCK
= 1.8V
38611f
6
LTC3861-1
Typical perFormance characTerisTics
128-Cycle Overcurrent Counter
(Single Phase Using FDMFꢀ.±.B
Overcurrent Threshold
vs Temperature
DrMOS)
Oscillator Frequency vs RFREQ
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
40
35
I
= 1.2V
LIM
PWM
2V/DIV
TRACK/SS
200mV/DIV
30
V
OUT
500mV/DIV
25
20
15
10
I
I
= 800mV
L
LIM
20A/DIV
38611 G19
50µs/DIV
V
V
= 12V
f
SW
= 500kHz EXTERNAL CLOCK
IN
OUT
5
= 1.8V
50
100
150
–50
0
0
40
60
(kΩ)
80
100
120
20
R
FREQ
TEMPERATURE (°C)
38611 G20
38611 G21
ꢀ±±kHz Preset Frequency
vs Temperature
ILIM Pin Current vs Temperature
FREQ Pin Current vs Temperature
20.6
20.4
20.2
20.0
19.8
19.6
19.4
19.2
20.6
20.4
20.2
20.0
19.8
19.6
19.4
19.2
19.0
620
615
610
605
600
595
590
585
580
0
50
150
0
50
150
–50
100
–50
100
0
25 50 75 100 125 150
–50 –25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
38611 G22
38611 G23
38611 G24
Shutdown Quiescent Current
vs Temperature
4±±kHz Preset Frequency
vs Temperature
Quiescent Current vs Temperature
395
390
385
380
375
370
365
24
22
20
18
16
14
12
10
34
33
32
31
30
29
28
V
V
= 6V
= 5V
V
V
= 6V
= 5V
IN
CC
IN
CC
RUN1 = RUN2 = 5V
50
100
150
75 100
150
125
–50
0
–50 –25
0
25 50
75 100
150
125
–50 –25
0
25 50
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
38611 G25
38611 G26
38611 G27
38611f
7
LTC3861-1
Typical perFormance characTerisTics
Shutdown Quiescent Current
RUN Threshold vs Temperature
vs Supply Voltage
RUN Pull-Up Current vs Temperature
2.25
2.2
2.0
1.8
1.6
1.4
1.2
1.0
40
35
30
25
20
15
10
5
RISING
2.20
2.15
2.10
2.05
2.00
1.95
FALLING
1.90
0
0
25 50 75 100
TEMPERATURE (°C)
150
50
100
150
–50 –25
125
–50
0
0
1
2
3
4
5
6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
38611 G28
38611 G29
38611 G30
TRACK/SS Current
vs TRACK/SS Voltage
TRACK/SS Pull-Up Current
vs Temperature
0.5
0
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
2
3
4
5
0
1
–50
0
50
100
150
TRACK/SS PIN VOLTAGE (V)
TEMPERATURE (°C)
38611 G31
38611 G32
38611f
8
LTC3861-1
pin FuncTions
V
(Pin 1): Chip Supply Voltage. Bypass this pin to GND
FREQ pin logic state selects an internal 600kHz or 1MHz
preset frequency.
CC
with a capacitor (0.1µF to 1µF ceramic) in close proximity
to the chip.
CLKOUT (Pin 12): Digital Output Used for Daisychain-
ing Multiple LTC3861-1 ICs in Multiphase Systems. The
PHSMD pin voltage controls the relationship between
CH1 and CH2 as well as between CH1 and CLKOUT. When
both RUN pins are driven low, the CLKOUT pin is actively
FB1 (Pin 2), FB2 (Pin 8): Error Amplifier Inverting Input.
FB1 or FB2 can be connected to VSNSOUT via a resistor
divider for remote V
sensing. The bottom of the divider
OUT
should be connected to the SGND pin of the IC. The other
FB, when used, is typically connected to the second V
via a resistor divider, also terminated at the IC SGND pin.
pulled up to V .
OUT
CC
PHSMD (Pin 13): Phase Mode Pin. The PHSMD pin volt-
age programs the phase relationship between CH1 and
CH2 rising PWM signals, as well as the phase relationship
between CH1 PWM signal and CLKOUT. Floating this pin
COMP1 (Pin 3), COMP2 (Pin .): Error Amplifier Outputs.
PWM duty cycle increases with this control voltage. The
error amplifiers in the LTC3861-1 are true operational
amplifiers with low output impedance. As a result, the
outputs of two active error amplifiers cannot be directly
connectedtogether!Formultiphaseoperation,connecting
or connecting it to either V or SGND changes the phase
CC
relationship between CH1, CH2 and CLKOUT.
ISNS1N (Pin 21), ISNS2N (Pin 2±): Current Sense Am-
the FB pin on an error amplifier to V will three-state the
CC
plifier (–) Input. The (–) input to the current amplifier is
output of that amplifier. Multiphase operation can then be
achieved by connecting all of the COMP pins together and
using one channel as the master and all others as slaves.
When the RUN pin is low, the respective COMP pin is
actively pulled down to ground.
normallyconnectedtotherespectiveV
attheinductor.
OUT
ISNS1P (Pin 22), ISNS2P (Pin 19): Current Sense Ampli-
fier (+) Input. The (+) input to the current sense amplifier
is normally connected to the midpoint of the inductor’s
parallel RC sense circuit or to the node between the induc-
tor and sense resistor if using a discrete sense resistor.
VSNSOUT (Pin 4): Differential Amplifier Output. Connect
to FB1 or FB2 with a resistive divider and compensation
I
(Pin 23), I
(Pin 18): Current Comparator Sense
LIM2
network for remote V
sensing.
LIM1
OUT
Voltage Limit Selection Pin. Connect a resistor from this
pin to SGND. This pin sources 20µA. The resultant voltage
sets the threshold for overcurrent protection.
VSNSN(Pin7):DifferentialSenseAmplifierInvertingInput.
Connect this pin to sense ground at the output load.
VSNSP (Pin ꢀ): Differential Sense Amplifier Noninverting
Input. Connect this pin to V
RUN1 (Pin 24), RUN2 (Pin 1.): Run Control Inputs. A
voltage above 2.25V on either pin turns on the IC. How-
ever, forcing either of these pins below 2V causes the
IC to shut down that particular channel. There are 1.5µA
pull-up currents for these pins.
at the output load.
OUT
FREQ(Pin1±):FrequencySet/SelectPin. Thispinsources
20µA current. If CLKIN is high or floating, then a resistor
betweenthispinandSGNDsetstheswitchingfrequency.If
CLKIN is low, the logic state of this pin selects an internal
600kHz or 1MHz preset frequency.
PWM1 (Pin 27), PWM2 (Pin 1ꢀ): (Top) Gate Signal Out-
put. This signal goes to the PWM or top gate input of the
external gate driver or integrated driver MOSFET. This is
a three-state compatible output.
CLKIN (Pin 11): External Clock Synchronization Input.
Applying an external clock between 250kHz to 2.25MHz
will cause the switching frequency to synchronize to the
PWMEN1 (Pin 2ꢀ), PWMEN2 (Pin 17): Enable Pin for
clock. CLKIN is pulled high to V by a 50k internal resis-
CC
Non-Three-State compatible drivers. This pin has an in-
tor. The rising edge of the CLKIN input waveform will align
with the rising edge of PWM1 in closed-loop operation. If
CLKIN is high or floating, a resistor from the FREQ pin to
SGND sets the switching frequency. If CLKIN is low, the
ternal open-drain pull-up to V . An external resistor to
CC
SGND is required. This pin is low when the corresponding
PWM pin is high impedance.
38611f
9
LTC3861-1
pin FuncTions
PGOOD1 (Pin 2.), PGOOD2 (Pin 14): Power Good Indi-
cator Output for Each Channel. Open-drain logic out that
is pulled to SGND when either channel output exceeds a
10% regulation window, after the internal 30µs power
bad mask timer expires.
VINSNS (Pin 31): V Sense Pin. Connects to the V
IN IN
power supply to provide line feedforward compensation.
A change in V immediately modulates the input to the
IN
PWM comparator and changes the pulse width in an in-
verselyproportionalmanner,thusbypassingthefeedback
loop and providing excellent transient line regulation. An
external lowpass filter can be added to this pin to prevent
noisy signals from affecting the loop gain.
I
(Pin 28): Average Current Output Pin. A capacitor
AVG
tied to ground from this pin stores a voltage proportional
to the instantaneous average current of the master when
multiple outputs are paralleled together in a master-slave
configuration. Only the master phase contributes infor-
mation to this average through an internal resistor when
TRACK/SS1 (Pin 32), TRACK/SS2 (Pin 9): Combined
Soft-Start and Tracking Inputs. For soft-start operation,
connecting a capacitor from this pin to ground will control
the voltage ramp at the output of the power supply. An
internal2.5μAcurrentsourcewillchargethecapacitorand
thereby control an extra input on the reference side of the
erroramplifier.Fortrackingoperation,thisinputallowsthe
start-up of a secondary output to track a primary output
according to a ratio established by a resistor divider from
the primary output to the secondary error amplifier track
pin. For coincident tracking of both outputs at start-up,
a resistor divider with values equal to those connected
to the secondary VSNSP pin from the secondary output
should be used to connect the secondary track input
from the primary output. This pin is internally clamped
to 1.2V, and is used to communicate over current events
in a master-slave configuration.
in current sharing mode. The I
pin ignores channels
AVG
configured for independent operation, hence the pin
should be connected to SGND when the controller drives
independent outputs.
SGND (Pin 29, Exposed Pad Pin 33): Signal Ground.
Pins 29 and 33 are electrically connected internally. The
exposed pad must be soldered to the PCB ground for
rated thermal performance. All soft-start, small-signal
and compensation components should return to SGND.
CONFIG (Pin 3±): Line Feedforward Configuration Pin.
This pin allows the user to configure the multiplier to
achieve accurate modulator gain over varying V and
IN
switching frequencies. This pin can be connected to V
CC
or SGND. An internal resistor will pull this pin to SGND
when it is floated.
38611f
10
LTC3861-1
FuncTional Diagram
1
29
30
24
RUN1
17
RUN2
27
PGOOD1
14
PGOOD2
V
CC
SGND CONFIG
VSNSOUT
VSNSP
4
6
V
CC
100k
100k
1.5µA
1.5µA
PGOOD
V
V
CC
DA
VSNSN
COMP1
5
3
V
V
FB2
BG/BIAS
FB1
CC
SD/UVLO
+
+
–
REF
TRACK/SS1
OC1 OC2
EA1
EA2
32
2
+
OV1 OV2
PWM1
PWMEN1
PWM2
FB1
25
26
16
15
NOC1
NOC2
LOGIC
REF
TRACK/SS2
+
+
–
9
8
+
PWMEN2
FB2
V
COMP2
FB1
7
I
MASTER/SLAVE/
INDEPENDENT
LIM1
V
FB2
I
VINSNS
LIM2
RAMP/SLOPE/
FEEDFORWARD
31
V
CC
S
S
20µA
ISNS1P
ISNS1N
22
21
+
–
x18.5
x18.5
OC1
V
CC
NOC1
20µA
ISNS2P
ISNS2N
V
CC
19
20
+
–
21µA
OC2
PLL/VCO
NOC2
I
I
I
LIM1
FREQ PHSMD CLKOUT CLKIN
10 13 12 11
AVG
LIM2
28
18
23
38611 BD
38611f
11
LTC3861-1
(Refer to Functional Diagram)
operaTion
Main Control Architecture
on-time of approximately 20ns and a minimum off-time
of approximately one-twelth the switching period.
The LTC3861-1 is a dual-channel/dual-phase, constant-
frequency, voltage mode controller for DC/DC step-down
applications. It is designed to be used in a synchronous
switchingarchitecturewithexternalintegrated-driverMOS-
FETs or power blocks, or external drivers and N-channel
MOSFETs using single wire three-state PWM interfaces.
Thecontrollerallowstheuseofsenseresistorsorlossless
inductor DCR current sensing to maintain current balance
between phases and to provide overcurrent protection.
The operating frequency is selectable from 250kHz to
2.25MHz. To multiply the effective switching frequency,
multiphase operation can be extended to 3, 4, 6, or 12
phases by paralleling up to six controllers. In single or
3-phase operation, the 2nd or 4th channel can be used
as an independent output.
Current Sharing
Inmultiphaseoperation, theLTC3861-1alsoincorporates
an auxiliary current sharing loop. Inductor current is
sampled each cycle. The master’s current sense amplifier
output is averaged at the I
pin. A small capacitor con-
AVG
nectedfromI toGND(typically100pF)storesavoltage
AVG
correspondingtotheinstantaneousaveragecurrentofthe
master. Each phase integrates the difference between its
current and the master’s. Within eachphase the integrator
output is proportionally summed with the system error
amplifier voltage (COMP), adjusting that phase’s duty
cycle to equalize the currents. When multiple ICs are
daisychained the I
pins must be connected together.
AVG
When the phases are operated independently, the I
AVG
The output of the differential amplifier is connected to
the error amplifier inverting input (FB) through a resistor
divider. The remote sense differential amplifier output
pin should be tied to ground0 Figure 1 shows a transient
load step with current sharing in a 3-phase system.
(V
(V
)providesasignalequaltothedifferentialvoltage
SNSN
SNSOUT
I
L1 (L= 0.47µH)
10A/DIV
– V
) sensed across the output capacitor, but
SNSP
re-referenced to the local ground (SGND). This permits
accuratevoltagesensingattheload,withoutregardtothe
potentialdifferencebetweenitsgroundandlocalground.
I
L2 (L= 0.25µH)
10A/DIV
I
L3 (L= 0.47µH)
10A/DIV
In the main voltage mode control loop, the error ampli-
fier output (COMP) directly controls the converter duty
cycle in order to drive the FB pin to 0.6V in steady state.
Dynamic changes in output load current can perturb the
output voltage. When the output is below regulation,
COMP rises, increasing the duty cycle. If the output rises
above regulation, COMP will decrease, decreasing the
duty cycle. As the output approaches regulation, COMP
will settle to the steady-state value representing the step-
down conversion ratio.
V
OUT
100mV/DIV
AC-COUPLED
38611 F01
50µs/DIV
STEP = 0A TO 30A TO 0A
LOAD
V
V
= 12V
OUT
I
f
IN
= 1V
= 500kHz EXTERNAL CLOCK
SW
Figure 10 Mismatched Inductor Load Step Transient Response
(3-Phase Using FDMFꢀ.±.B DrMOS)
Overcurrent Protection
Thecurrentsenseamplifieroutputsalsoconnecttoovercur-
rent (OC) comparators that provide fault protection in the
case of an output short. When an OC fault is detected for
128 consecutive clock cycles, the controller three-states
the PWM output, resets the soft-start capacitor, and waits
for 32768 clock cycles before attempting to start up again.
The 128 consecutive clock cycle counter has a 7-cycle
hysteresiswindow,afterwhichitwillreset.TheLTC3861-1
also provides negative OC (NOC) protection by preventing
Innormaloperation,thePWM latchissethighatthebegin-
ning of the clock cycle (assuming COMP > 0.5V). When
the (line feedforward compensated) PWM ramp exceeds
the COMP voltage, the comparator trips and resets the
PWM latch. If COMP is less than 0.5V at the beginning
of the clock cycle, as in the case of an overvoltage at the
outputs, the PWM pin remains low throughout the entire
cycle. When the PWM pin goes high it has a minimum
38611f
12
LTC3861-1
(Refer to Functional Diagram)
operaTion
turn-on of the bottom MOSFET during a negative OC fault
condition. In this condition, the bottom MOSFET will be
turned on for 20ns every eight cycles to allow the driver IC
to recharge its topside gate drive capacitor. The negative
OC threshold is equal to –3/4 the positive OC threshold.
See the Applications Information section for guidelines
on setting these thresholds.
Remote Sense Differential Amplifier
The LTC3861-1 includes a low offset, unity gain, high
bandwidth differential amplifier for differential output
sensing.Outputvoltageaccuracyissignificantlyimproved
by removing board interconnection losses from the total
error budget.
The LTC3861-1 differential amplifier has a typical output
slew rate of 45V/µs, bandwidth of 40MHz, input referred
Excellent Transient Response
offset < 2mV and a typical maximum output voltage of V
CC
TheLTC3861-1erroramplifiersaretrueoperationalampli-
fiers,meaningthattheyhavehighbandwidth,highDCgain,
low offset and low output impedance. Their bandwidth,
when combined with high switching frequencies and low-
value inductors, allows the compensation network to be
optimizedforveryhighcontrolloopcrossoverfrequencies
and excellent transient response. The 600mV internal ref-
erence allows regulated output voltages as low as 600mV
without external level-shifting amplifiers.
– 1V. The amplifier is configured for unity gain, meaning
that the differential voltage between V and V is
SNSP
SNSN
translated to V , relative to SGND.
SNSOUT
Shutdown Control Using the RUN Pins
The two channels of the LTC3861-1 can be independently
enabled using the RUN1 and RUN2 pins. When both pins
are driven low, all internal circuitry, including the internal
reference and oscillator, are completely shut down. When
the RUN pin is low, the respective COMP pin is actively
pulled down to ground. In a multiphase operation when
the COMP pins are tied together, the COMP pin is held
low until all the RUN pins are enabled. This ensures a
synchronized start-up of all the channels. A 1.5μA pull-up
current is provided for each RUN pin internally. The RUN
Line Feedforward Compensation
The LTC3861-1 achieves outstanding line transient re-
sponse using a feedforward correction scheme which
instantaneously adjusts the duty cycle to compensate for
changes in input voltage, significantly reducing output
overshoot and undershoot. It has the added advantage
of making the DC loop gain independent of input voltage.
Figure 2 shows how large transient steps at the input have
little effect on the output voltage.
pins remain high impedance up to V .
CC
Undervoltage Lockout
To prevent operation of the power supply below safe in-
put voltage levels, both channels are disabled when V
CC
is below the undervoltage lockout (UVLO) threshold
(2.9V falling, 3V rising). If a RUN pin is driven high, the
LTC3861-1 will start up the reference to detect when
V
IN
10V/DIV
I
L1
10A/DIV
V
rises above the UVLO threshold, and enable the
CC
I
L2
appropriate channel.
10A/DIV
V
Overvoltage Protection
OUT
50mV/DIV
AC-COUPLED
If the output voltage rises to more than 10% above the
set regulation value, which is reflected as a V voltage
38611 F02
20µs/DIV
= 7V TO 14V IN 20µs
OUT
FB
V
IN
V
I
= 20A
LOAD
= 1.2V
f
= 300kHz
SW
of 0.66V or above, the LTC3861-1 will force the PWM
output low to turn on the bottom MOSFET and discharge
the output. Normal operation resumes once the output
is back within the regulation window. However, if the re-
Figure 20
verse current flowing from V
back through the bottom
OUT
38611f
13
LTC3861-1
(Refer to Functional Diagram)
operaTion
power MOSFET to PGND is greater than 3/4 the positive
OC threshold, the NOC comparator trips and shuts off the
bottompowerMOSFETtoprotectitfrombeingdestroyed.
This scenario can happen when the LTC3861-1 tries to
start into a precharged load higher than the OV threshold.
As a result, the bottom switch turns on until the amount
of reverse current trips the NOC comparator threshold.
Internal Soft-Start
By default, the start-up of each channel’s output voltage
is normally controlled by an internal soft-start ramp. The
internal soft-start ramp represents a noninverting input
to the error amplifier. The FB pin is regulated to the lower
of the error amplifier’s three noninverting inputs (the
internal soft-start ramp for that channel, the TRACK/SS
pin or the internal 600mV reference). As the ramp volt-
age rises from 0V to 0.6V over approximately 2ms, the
output voltage rises smoothly from its prebiased value
to its final set value.
Nonsynchronous Start-Up and Prebiased Output Load
The LTC3861-1 will start up with seven cycles of
nonsynchronous operation before switching over to a
forcedcontinuousmodeofoperation.ThePWMoutputwill
be in a three-state condition until start-up. The controller
will start the seven nonsynchronous cycles if it is not in
an overcurrent or prebiased condition, and if the COMP
pin voltage is higher than 500mV, or if the TRACK/SS
pin voltage is higher than 580mV. During the seven
nonsynchronous cycles the PWM latch is set high at the
beginning of the clock cycle, if COMP > 0.5V, causing the
Soft-Start and Tracking Using TRACK/SS Pin
The user can connect an external capacitor greater than
10nF to the TRACK/SS pin for the relevant channel to
increase the soft-start ramp time beyond the internally
set default. The TRACK/SS pin represents a noninverting
input to the error amplifier and behaves identically to the
internalrampdescribedintheprevioussection.Aninternal
2.5µA current source charges the capacitor, creating a
voltage ramp on the TRACK/SS pin. The TRACK/SS pin is
internally clamped to 1.2V. As the TRACK/SS pin voltage
rises from 0V to 0.6V, the output voltage rises smoothly
from 0V to its final value in:
PWM output to transition from three-state to V . The
CC
latch is reset when the PWM ramp exceeds the COMP
voltage, causing the PWM output to transition from V
CC
to three-state followed immediately by a 20ns three-state
to ground pulse. The 7-cycle nonsynchronous mode of
operation is enabled at initial start-up and also during a
restart from a fault condition. In multiphase operation,
where all the TRACK/SS should be connected together,
an overcurrent event on one channel will discharge the
soft-startcapacitor. After32768cycles, itwillsynchronize
the restart of all channels in to the nonsynchronous mode
of operation.
CSSµF •0.6V
seconds
2.5µA
Alternatively, the TRACK/SS pin can be used to force the
start-up of V
to track the voltage of another supply.
OUT
Typically this requires connecting the TRACK/SS pin to
an external divider from the other supply to ground (see
the Applications Information section). It is only possible
to track another supply that is slower than the internal
soft-start ramp. The TRACK/SS pin also has an internal
open-drain NMOS pull-down transistor that turns on to
reset the TRACK/SS voltage when the channel is shut
TheLTC3861-1cansafelystart-upintoaprebiasedoutput
without discharging the output capacitors. A prebias
is detected when the FB pin voltage is higher than the
TRACK/SS or the internal soft-start voltage. A prebiased
condition will force the COMP pin to be held low, and will
three-state the PWM output. The prebiased condition is
clearedwhentheTRACK/SSortheinternalsoft-startvoltage
is higher than the FB pin voltage or 580mV, whichever is
lower. IftheoutputprebiasishigherthantheOVthreshold
thenthePWMoutputwillbelow, whichwillpulltheoutput
back in to the regulation window.
down (RUN = 0V or V < UVLO threshold) or during an
OC fault condition.
CC
Inmultiphaseoperation,onemastererroramplifierisused
to control all of the PWM comparators. The FB pins for
the unused error amplifiers are connected to V in order
CC
to three-state these amplifier outputs and the COMP pins
are connected together. When the FB pin is tied to V ,
CC
the internal 2.5µA current source on the TRACK/SS pin
38611f
14
LTC3861-1
(Refer to Functional Diagram)
operaTion
is disabled for that channel. The TRACK/SS pins should
also be connected together so that the slave phases can
detect when soft-start is complete and to synchronize the
nonsynchronous mode of operation.
single high current output, or even several outputs from
the same input supply.
The PHSMD pin is used to adjust the phase relationship
between channel 1 and channel 2, as well as the phase
relationship between channel 1 and CLKOUT, as sum-
marized in Table 2. The phases are calculated relative to
zero degrees, defined as the rising edge of PWM1. Refer
to Applications Information for more details on how to
create multiphase applications.
Frequency Selection and the Phase-Locked Loop (PLL)
The selection of the switching frequency is a trade-off
between efficiency, transient response and component
size. High frequency operation reduces the size of the
inductor and output capacitor as well as increasing the
maximum practical control loop bandwidth. However,
efficiency is generally lower due to increased transition
and switching losses.
Table 20 Phase Selection
PHSMD PIN
Float
CH-1 to CH-2 PHASE
CH-1 to CLKOUT PHASE
180°
180°
120°
90°
60°
Low
The LTC3861-1’s switching frequency can be set in three
ways: using an external resistor to linearly program the
frequency, synchronizing to an external clock, or simply
selecting one of two fixed frequencies (400kHz and
600kHz). Table 1 highlights these modes.
High
240°
Using the LTC38ꢀ1-1 Error Amplifiers in
Multiphase Applications
Due to the low output impedance of the error amplifiers,
multiphase applications using the LTC3861-1 use one
error amplifier as the master with all of the slaves’
error amplifiers disabled. The channel 1 error amplifier
(phase = 0°) may be used as the master with phases 2
through n (up to 12) serving as slaves. To disable the
slave error amplifiers connect the FB pins of the slaves
Table 10 Frequency Selection
CLKIN PIN
Clocked
High or Float
Low
FREQ PIN
FREQUENCY
250kHz to 2.25MHz
250kHz to 2.25MHz
400kHz
R
FREQ
R
FREQ
to GND
to GND
Low
High
Low
600kHz
to V . This three-states the output stages of the ampli-
CC
No external PLL filter is required to synchronize the
LTC3861-1toanexternalclock.Applyinganexternalclock
signal to the CLKIN pin will automatically enable the PLL
with internal filter.
fiers. All COMP pins should then be connected together
to create PWM outputs for all phases. As noted in the
section on soft-start, all TRACK/SS pins should also be
shorted together. Refer to the Multiphase Operation sec-
tion in Applications Information for schematics of various
multiphase configurations.
Constant-frequency operation brings with it a number
of benefits: inductor and capacitor values can be chosen
for a precise operating frequency and the feedback loop
can be similarly tightly specified. Noise generated by the
circuit will always be at known frequencies.
Theory and Benefits of Multiphase Operation
Multiphase operation provides several benefits over tra-
ditional single phase power supplies:
n
Greater output current capability
Using the CLKOUT and PHSMD Pins in
Multiphase Applications
n
Improved transient response
The LTC3861-1 features CLKOUT and PHSMD pins that
allow multiple LTC3861-1 ICs to be daisychained together
in multiphase applications. The clock output signal on the
CLKOUT pin can be used to synchronize additional ICs in
a 3-, 4-, 6- or 12-phase power supply solution feeding a
n
Reduction in component size
n
Increased real world operating efficiency
Because multiphase operation parallels power stages,
the amount of output current available is n times what it
38611f
15
LTC3861-1
(Refer to Functional Diagram)
operaTion
would be with a single comparable output stage, where n
ThePWMENoutputshaveanopen-drainpull-uptoV and
CC
is equal to the number of phases.
requireanappropriateexternalpull-downresistor.Thispin
is intended to drive the enable pins of the MOSFET driv-
ers that do not have three-state compatible PWM inputs.
PWMEN is low only when PWM is high impedance, and
high at any other PWM state.
The main advantages of PolyPhase operation are ripple
current cancellation in the input and output capacitors, a
faster load step response due to a smaller clock delay and
reduced thermal stress on the inductors and MOSFETs
duetocurrentsharingbetweenphases. Theseadvantages
allow for the use of a smaller size or a smaller number
of components.
Line Feedforward Gain
In a typical LTC3861-1 circuit, the feedback loop consists
of the line feedforward circuit, the modulator, the external
inductor, the output capacitor and the feedback amplifier
with its compensation network. All these components
affect loop behavior and need to be accounted for in the
loop compensation. The modulator consists of the PWM
generator, the external output MOSFET drivers and the
external MOSFETs themselves. The modulator gain varies
linearly with the input voltage. The line feedforward circuit
compensates for this change in gain, and provides a con-
stant gain from the error amplifier output to the inductor
input regardless of input voltage. From a feedback loop
point of view, the combination of the line feedforward
circuitandthemodulatorlookslikealinearvoltagetransfer
function from COMP to the inductor input and has a gain
roughly equal to 12V/V.
Power Good Indicator Pins (PGOOD1, PGOOD2)
Each PGOOD pin is connected to the open drain of an
internal pull-down device which pulls the PGOOD pin
low when the corresponding FB pin voltage is outside
the PGOOD regulation window ( 7.5% entering regula-
tion, 10% leaving regulation). The PGOOD pins are also
pulled low when the corresponding RUN pin is low, or
during UVLO.
When the FB pin voltage is within the 10% regulation
window, theinternalPGOODMOSFETisturnedoffandthe
pin is normally pulled up by an external resistor. When the
FB pin is exiting a fault condition (such as during normal
output voltage start-up, prior to regulation), the PGOOD
pin will remain low for an additional 30μs. This allows
the output voltage to reach steady-state regulation and
prevents the enabling of a heavy load from retriggering
a UVLO condition.
The LTC3861-1 has a wide V and switching frequency
IN
range. The CONFIG pin is used to select the optimum
range of operation for the internal multiplier, in order to
maintain a constant line feedforward gain across a wide
In multiphase applications, one FB pin and error amplifier
are used to control all of the phases. Since the FB pins
V andswitchingfrequencyrange. TheCONFIGisathree-
IN
state pin and can be connected to SGND, V or floated.
CC,
for the unused error amplifiers are connected to V (in
Floating the pin externally is a valid selection as there are
CC
order to three-state these amplifiers), the PGOOD outputs
for these amplifiers will be asserted. In order to prevent
falsely reporting a fault condition, the PGOOD outputs
for the unused error amplifiers should be left open. Only
the PGOOD output for the master control error amplifier
should be connected to the fault monitor.
internal steering resistors. The selection range based on
V and switching frequency is summarized in Table 3.
IN
Table 30 Line Feedforward Range Selection
CONFIG PIN
V
IN
GND (or) FLOAT
< 14V
> 14V
V
CC
PWM and PWMEN Pins
The PWM pins are three-state compatible outputs, de-
signed to drive MOSFET drivers, DrMOSs, power blocks,
etc., which do not represent a heavy capacitive load. An
external resistor divider may be used to set the voltage to
mid-rail while in the high impedance state.
38611f
16
LTC3861-1
applicaTions inFormaTion
Setting the Output Voltage
Table 1 in the Operation section shows how to connect the
CLKIN and FREQ pins to choose the mode of frequency
programming. The frequency of operation is given by the
following equation:
The LTC3861-1 regulates the FB pins to 0.6V. FB is con-
nected to V
or V
(for remote output sensing)
OUT
SNSOUT
via an external resistive divider as shown in Figure 3. The
divider sets the output voltage according to the following
equation:
Frequency = (R
– 17kΩ) • 29Hz/Ω
FREQ
Figure 4 shows operating frequency vs R
.
FREQ
RB
VOUT = 0.6V • 1 +
RA
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
Care should be taken to place the output divider resistors
and the compensation components as close as possible
to the FB pin to minimize switching noise coupling into
the control signal path.
COMP
LTC3861-1
V
OUT
FB
0
40
60
(kΩ)
80
100
120
20
R
B
R
FREQ
38611 F04
R
C
A
OUT
SGND
Figure 40 Oscillator Frequency vs RFREQ
38611 F03
DIVIDER AND COMPENSATION COMPONENTS
PLACED NEAR FB, SGND AND COMP PINS
Frequency Synchronization
Figure 30 Output Divider and Compensation Component Placement
The LTC3861-1 incorporates an internal phase-locked
loop (PLL) which enables synchronization of the internal
oscillator (rising edge of PWM1) to an external clock from
250kHz to 2.25MHz.
Sensing the Output Voltage with a Differential Amplifier
When using the remote sense differential amplifier, care
should be taken to route the V
and V
PCB traces
SNSP
SNSN
Since the entire PLL is internal to the LTC3861-1, simply
applying a CMOS level clock signal to the CLKIN pin will
enable frequency synchronization. A resistor from FREQ
to GND is still required to set the free running frequency
close to the sync input frequency.
parallel to each other all the way to the terminals of the
output capacitor or remote sensing points on the board.
In addition, avoid routing these sensitive traces near any
high speed switching nodes in the circuit. Ideally, they
should be shielded by a low impedance ground plane to
maintain signal integrity.
Choosing the Inductor and Setting the Current Limit
When using a single LTC3861-1 to regulate two output
The inductor value is related to the switching frequency,
which is chosen based on the trade-offs discussed in the
Operation section. The inductor can be sized using the
following equation:
voltages, the negative terminal of V
should be
OUT2
kelvin-connected to SGND and the differential amplifier
should be used to remotely sense V
. This will maxi-
OUT1
mize output voltage accuracy for both channels.
⎛
⎞ ⎛
f • ΔI
L⎠ ⎝
⎞
VOUT
VOUT
Programming the Operating Frequency
L =
• 1−
⎟ ⎜
⎜
⎟
V
⎝
⎠
IN
The LTC3861-1 can be hard wired to one of two fixed fre-
quencies, linearly programmed to any frequency between
250kHzand2.25MHzorsynchronizedtoanexternalclock.
Choosing a larger value of ∆I leads to smaller L, but re-
sults in greater core loss (and higher output voltage ripple
L
38611f
17
LTC3861-1
applicaTions inFormaTion
for a given output capacitance and/or ESR). A reasonable
starting point for setting the ripple current is 30% of the
maximum output current, or:
In multiphase applications only one current limit resistor
should be used per LTC3861-1. The I
pin should be
LIM2
tied to V . Internal logic will then cause channel 2 to use
CC
thesamecurrentlimitlevelsaschannel1. IfanLTC3861-1
∆I = 0.3 • I
L
OUT
has a slave and an independent, then both I pins must
LIM
The inductor saturation current rating needs to be higher
than the peak inductor current during transient condi-
be independently set to the right voltage.
tions. If I
is the maximum rated load current, then
Inductor Core Selection
OUT
the maximum transient current, I
, would normally be
MAX
Once the value of L is known, the type of inductor must be
selected.Highefficiencyconvertersgenerallycannotafford
the core losses found in low cost powdered iron cores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores.Also,corelossesdecreaseasinductanceincreases.
Unfortunately, increased inductance requires more turns
of wire, larger inductance and larger copper losses.
chosen to be some factor (e.g., 60%) greater than I
:
OUT
I
= 1.6 • I
OUT
MAX
The minimum saturation current rating should be set to
allowmarginduetomanufacturingandtemperaturevaria-
tion in the sense resistor or inductor DCR. A reasonable
value would be:
Ferritedesignshaveverylowcorelossandarepreferredat
highswitchingfrequencies.However,thesecorematerials
exhibit“hard”saturation,causinganabruptreductioninthe
inductance when the peak current capability is exceeded.
Do not allow the core to saturate!
I
= 2.2 • I
OUT
SAT
The programmed current limit must be low enough to
ensure that the inductor never saturates and high enough
to allow increased current during transient conditions and
allow margin for DCR variation.
C Selection
IN
For example, if:
TheinputbypasscapacitorinanLTC3861-1circuitiscom-
mon to both channels. The input bypass capacitor needs
to meet these conditions: its ESR must be low enough to
keep the supply drop low as the top MOSFETs turn on, its
RMS current capability must be adequate to withstand the
ripple current at the input, and the capacitance must be
large enough to maintain the input voltage until the input
supply can make up the difference. Generally, a capacitor
(particularly a non-ceramic type) that meets the first two
parameterswillhavefarmorecapacitancethanisrequired
to keep capacitance-based droop under control.
I
= 2.2 • I
OUT
SAT
and
I
= 1.6 • I
OUT
MAX
A reasonable I
would be:
LIMIT
I
= 1.8 • I
OUT
LIMIT
If the sensed inductor current exceeds current limit for
128 consecutive clock cycles, the IC will three-state the
PWM outputs, reset the soft-start timer and wait 32768
switching cycles before attempting to return the output
to regulation.
The input capacitor’s voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
The current limit is programmed using a resistor from the
LIM
a voltage corresponding to the current limit. The current
sense circuit has a voltage gain of 18.5 and a zero current
levelof500mV.Therefore,thecurrentlimitresistorshould
be set using the following equation:
2
occurs not only as I R dissipation in the capacitor itself,
I
pin to SGND. The I pin sources 20µA to generate
LIM
but also in overall battery efficiency. For mobile applica-
tions, the input capacitors should store adequate charge
to keep the peak battery current within the manufacturer’s
specifications.
The input capacitor RMS current requirement is simpli-
fied by the multiphase architecture and its impact on the
18.5 •ILIMIT PHASE • RSENSE + 0.5V
–
RILIM
=
20µA
worst-case RMS current drawn through the input network
38611f
18
LTC3861-1
applicaTions inFormaTion
(battery/fuse/capacitor). It can be shown that the worst-
or aluminum electrolytic capacitors from Panasonic WA
series or Cornell Dubilier SPV series, in parallel with a
couple of high performance ceramic capacitors, can be
used as an effective means of achieving low ESR and high
bulk capacitance.
case RMS current occurs when only one controller is
operating. The controller with the highest (V )(I
)
OUT OUT
productneedstobeusedtodeterminethemaximumRMS
current requirement. Increasing the output current drawn
fromtheotherout-of-phasecontrollerwillactuallydecrease
the input RMS ripple current from this maximum value.
The out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
C
OUT
Selection
The selection of C
is primarily determined by the ESR
OUT
requiredtominimizevoltagerippleandloadsteptransients.
The output ripple ∆V
is approximately bounded by:
OUT
In continuous mode, the source current of the top
N-channel MOSFET is approximately a square wave of
OUT IN
rent is given by:
⎛
⎞
1
ΔVOUT ≤ ΔIL ESR+
duty cycle V / V . The maximum RMS capacitor cur-
⎜
⎝
⎟
8• fSW •COUT
⎠
where ∆I is the inductor ripple current.
L
VOUT V – V
(
)
IN
OUT
IRMS ≈IOUT(MAX)
∆I may be calculated using the equation:
L
V
IN
⎛
⎞
VOUT
L • fSW
VOUT
This formula has a maximum at V = 2V , where
ΔIL =
1–
IN
OUT
⎜
⎟
V
⎝
⎠
IN
I
= I /2. This simple worst-case condition is com-
RMS
OUT
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. The total RMS current is lower
when both controllers are operating due to the interleav-
ing of current pulses through the input capacitors. This is
why the input capacitance requirement calculated above
for the worst-case controller is adequate for the dual
controller design.
Since ∆I increases with input voltage, the output ripple
L
voltage is highest at maximum input voltage. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
Manufacturers such as Sanyo, Panasonic and Cornell Du-
biliershouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has a good (ESR)(size)
product. An additional ceramic capacitor in parallel with
OS-CON capacitors is recommended to offset the effect
of lead inductance.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surfacemountconfigurations.Newspecialpolymersurface
mount capacitors offer very low ESR also but have much
lower capacitive density per unit volume. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
Ceramic,tantalum,OS-CONandswitcher-ratedelectrolytic
capacitors can be used as input capacitors, but each has
drawbacks: ceramics have high voltage coefficients of
capacitance and may have audible piezoelectric effects;
tantalums need to be surge-rated; OS-CONs suffer from
higher inductance, larger case size and limited surface
mount applicability; and electrolytics’ higher ESR and
dryout possibility require several to be used. Sanyo
OS-CON SVP, SVPD series; Sanyo POSCAP TQC series
output capacitor choices include the Sanyo POSCAP TPD,
38611f
19
LTC3861-1
applicaTions inFormaTion
TPE, TPF series, the Kemet T520, T530 and A700 series,
NEC/Tokin NeoCapacitors and Panasonic SP series. Other
capacitor types include Nichicon PL series and Sprague
595D series. Consult the manufacturer for other specific
recommendations.
exactly equal to the L/DCR time constant of the inductor,
the voltage drop across the external capacitor is equal
to the voltage drop across the inductor DCR. Check the
manufacturer’sdatasheetforspecificationsregardingthe
inductor DCR in order to properly dimension the external
filter components. The DCR of the inductor can also be
measured using a good RLC meter.
Current Sensing
To maximizeefficiency,theLTC3861-1isdesignedtosense
current through the inductor’s DCR, as shown in Figure 5
The DCR of the inductor represents the small amount
of DC winding resistance of the copper, which for most
inductorsapplicabletothisapplication,isbetween0.3mΩ
and 1mΩ. If the filter RC time constant is chosen to be
Since the temperature coefficient of the inductor’s DCR is
3900ppm/°C, first order compensation of the filter time
constant is possible by using filter resistors with an equal
butopposite(negative)TC,assumingalowTCcapacitoris
used. That is, as the inductor’s DCR rises with increasing
temperature, the L/DCR time constant drops. Since we
V
IN
VINSNS
12V
5V
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
LTC3861-1
V
V
V
BOOST
TG
CC
LOGIC
CC
L
R
S
ESL
LTC4449
PWM
IN
TS
V
OUT
BG
C • 2R ≤ ESL/R
F
F
S
GND ISNSN ISNSP
GND
POLE-ZERO
CANCELLATION
C
F
R
R
F
F
38611 F05a
FILTER COMPONENTS PLACED NEAR SENSE PINS
(7a) Using a Resistor to Sense Current
V
IN
VINSNS
LTC3861-1
12V
5V
V
CC
V
V
BOOST
TG
LOGIC
INDUCTOR
DCR
CC
LTC4449
L
PWM
IN
TS
V
OUT
BG
GND ISNSN ISNSP
C1*
GND
R1*
38611 F05b
L
DCR
R1 • C1 =
*PLACE R1 NEAR INDUCTOR
PLACE C1 NEAR ISNSP, ISNSN PINS
(7b) Using the Inductor to Sense Current
Figure 70 Two Different Methods of Sensing Current
38611f
20
LTC3861-1
applicaTions inFormaTion
want the filter RC time constant to match the L/DCR time
constant, we also want the filter RC time constant to drop
withincreasingtemperature. Typically, theinductancewill
also have a small negative TC.
Multiphase Operation
WhentheLTC3861-1isusedinasingleoutput,multiphase
application, the slave error amplifiers must be disabled
by connecting their FB pins to V . All current limits
CC
The ISNSP and ISNSN pins are the inputs to the current
comparators. The common mode range of the current
should be set to the same value using only one resistor
to SGND per IC. I
should then be connected to V .
LIM2
CC
comparators is –0.3V to V – 0.5V. Continuous linear
These connections are shown in Table 4. In a multiphase
application all COMP, RUN and TRACK/SS pins must be
connected together.
CC
operation is provided throughout this range, allowing
output voltages between 0.6V (the reference input to the
error amplifiers) and
V
CC
– 0.5V. The maximum output
CC
Table 40 Multiphase Configurations
voltage is lower than V to account for output ripple and
CH1
CH2
FB1
FB2
I
I
LIM2
LIM1
outputovershoot.Themaximumdifferentialcurrentsense
Master
Slave
On
Off
(FB = V
Resistor
to GND
V
CC
input (V
– V
) is 50mV.
ISNSP
ISNSN
)
)
CC
Slave
Slave
Slave
Off
Off
Resistor
to GND
V
The high impedance inputs to the current comparators
allow accurate DCR sensing. However, care must be taken
not to float these pins during normal operation.
CC
(FB = V ) (FB = V
CC
CC
Additional
Output
Off
(FB = V
On
Resistor
to GND
Resistor
to GND
)
CC
Filter components mutual to the sense lines should be
placed close to the LTC3861-1, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 6). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If low value
(<5mΩ) sense resistors are used, verify that the signal
For output loads that demand high current, multiple
LTC3861-1s can be daisychained to run out-of-phase to
provide more output current without increasing input and
outputvoltageripple.TheCLKINpinallowstheLTC3861-1
tosynchronizetotheCLKOUTsignalofanotherLTC3861-1.
The CLKOUT signal can be connected to the CLKIN pin of
thefollowingLTC3861-1stagetolineupboththefrequency
andthephaseoftheentiresystem.TyingthePHSMDpinto
V , SGND or floating it generates a phase difference
CC
across C resembles the current through the inductor,
F
(between CLKIN and CLKOUT) of 240°, 60° or 90°
respectively, and a phase difference (between CH1 and
CH2) of 120°, 180° or 180°. Figure 7 shows the PHSMD
connectionsnecessaryfor3-,4-,6-or12-phaseoperation.
A total of twelve phases can be daisychained to run simul-
taneously out-of-phase with respect to each other.
and reduce R to eliminate any large step associated with
F
the turn-on of the primary switch. If DCR sensing is used
(Figure 5b), sense resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small-signal nodes. The capacitor C1 should be
placed close to the IC pins.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
C
OUT
INDUCTOR OR R
38611 F06
SENSE
Figure ꢀ0 Sense Lines Placement with Inductor or Sense Resistor
38611f
21
LTC3861-1
applicaTions inFormaTion
V
V
CC
V
CC
V
CC
CC
0, 180
90, 270
0, 120
240, 60
LTC3861-1
LTC3861-1
LTC3861-1
LTC3861-1
+90
+240
CLKIN
CLKIN
CLKIN
CLKIN
PHSMD
FB1
CLKOUT
CLKOUT
CLKOUT
CLKOUT
TRACK/SS2
PHSMD
FB1
PHSMD
FB1
PHSMD
FB1
FB1
FB1
FB2
FB2
FB2
FB2
I
I
COMP1
COMP2
I
I
COMP1
COMP2
COMP1
COMP2
COMP1
COMP2
LIM2
LIM2
LIM2
LIM2
I
I
I
I
FB2
LIM1
LIM1
LIM1
LIM1
I
TRACK/SS1,2
I
TRACK/SS1,2
I
TRACK/SS1,2
I
TRACK/SS1
AVG
AVG
AVG
AVG
38611 F07b
38611 F07a
Figure .a0 3-Phase Operation
Figure .b0 4-Phase Operation
V
V
V
CC
CC
CC
0, 180
60, 240
120, 300
LTC3861-1
FB1
LTC3861-1
LTC3861-1
+60
+60
CLKIN
CLKIN
CLKIN
PHSMD
FB1
CLKOUT
CLKOUT
CLKOUT
PHSMD
FB1
PHSMD
FB1
FB2
FB2
FB2
I
I
I
COMP1
COMP2
COMP1
COMP2
COMP1
COMP2
LIM2
LIM2
LIM2
I
I
I
LIM1
LIM1
LIM1
I
TRACK/SS1,2
I
TRACK/SS1,2
I TRACK/SS1,2
AVG
AVG
AVG
38611 F07c
Figure .c0 ꢀ-Phase Operation
V
V
V
CC
CC
CC
0, 180
60, 240
120, 300
LTC3861-1
FB1
LTC3861-1
LTC3861-1
+60
+60
+90
CLKIN
CLKIN
CLKIN
PHSMD
FB1
CLKOUT
CLKOUT
CLKOUT
PHSMD
FB1
PHSMD
FB1
FB2
FB2
FB2
I
I
I
COMP1
COMP2
COMP1
COMP2
COMP1
COMP2
LIM2
LIM2
LIM2
I
I
I
LIM1
LIM1
LIM1
I
TRACK/SS1,2
I
TRACK/SS1,2
I
TRACK/SS1,2
AVG
AVG
AVG
V
210, 30
V
270, 90
V
CC
330, 150
CC
CC
LTC3861-1
LTC3861-1
LTC3861-1-1
+60
+60
CLKIN
PHSMD
FB1
CLKIN
PHSMD
FB1
CLKIN
PHSMD
FB1
CLKOUT
CLKOUT
CLKOUT
FB2
FB2
FB2
I
I
I
COMP1
COMP2
COMP1
COMP2
COMP1
COMP2
LIM2
LIM2
LIM2
I
I
I
LIM1
LIM1
LIM1
I
TRACK/SS1,2
I
TRACK/SS1,2
I
TRACK/SS1,2
AVG
AVG
AVG
38611 F07d
Figure .d0 12-Phase Operation
Figure .0 PHSMD Connections for 3-, 4-, ꢀ- or 12-Phase Operation
38611f
22
LTC3861-1
applicaTions inFormaTion
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is divided by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output volt-
age). The output ripple amplitude is also reduced by the
number of phases used. Figure 8 graphically illustrates
the principle.
design results in peak outputs of 1/4 and 3/4 of input
voltage. When the RMS current is calculated, higher ef-
fective duty factor results and the peak current levels are
divided as long as the current in each stage is balanced.
Refer to Application Note 19 for a detailed description of
howtocalculateRMScurrentforthesinglestageswitching
regulator. Figures 9 and 10 illustrate how the input and
output currents are reduced by using an additional phase.
For a 2-phase converter, the input current peaks drop in
half and the frequency is doubled. The input capacitor
requirement is thus reduced theoretically by a factor of
four!Justimaginethepossibilityofcapacitorsavingswith
even higher number of phases!
The worst-case RMS ripple current for a single stage
design peaks at an input voltage of twice the output volt-
age. The worst case RMS ripple current for a two stage
SINGLE PHASE
SW1 V
DUAL PHASE
SW1 V
SW2 V
I
CIN
I
I
L1
L2
I
COUT
I
CIN
I
COUT
38611 F08
RIPPLE
Figure 80 Single and 2-Phase Current Waveforms
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
1 PHASE
1 PHASE
2 PHASE
2 PHASE
0.1
0.5
0.7 0.8
)
0.1
0.5
0.7 0.8
)
0.2 0.3 0.4
0.6
0.9
0.2 0.3 0.4
0.6
0.9
DUTY FACTOR (V /V
DUTY FACTOR (V /V
OUT IN
OUT IN
38611 F09
38611 F10
Figure 90 Normalized Output Ripple Current
vs Duty Factor [IRMS″ ±03 (DIC(PP))]
Figure 1±0 Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
38611f
23
LTC3861-1
applicaTions inFormaTion
Output Current Sharing
Table 5 shows the I
channel operation.
and EA configuration for dual-
LIM
When multiple LTC3861-1s are daisychained to drive a
commonload,accurateoutputcurrentsharingisessential
toachieveoptimalperformanceandefficiency.Otherwise,
if one stage is delivering more current than another, then
the temperature between the two stages will be different,
Table 70 Dual-Channel Configuration
CH1
CH2
EA1
EA2
I
I
LIM2
LIM1
Independent Independent
On
On
Resistor Resistor
to GND to GND
and that could translate into higher switch R
, lower
DS(ON)
Tracking and Soft-Start (TRACK/SS Pins)
efficiency, and higher RMS ripple. When the COMP and
pins of multiple LTC3861-1s are tied together, the
I
AVG
The start-up of the supply output is controlled by the volt-
age on the TRACK/SS pin for that channel. The LTC3861-1
regulates the FB pin voltage to the lower of the voltage
on the TRACK/SS pin and the internal 600mV reference.
The TRACK/SS pin can therefore be used to program an
external soft-start function or allow the output supply to
track another supply during start-up.
amount of output current delivered from each LTC3861-1
is actively balanced by the I loop. The SGND pins of
AVG
the multiple LTC3861-1s must be kelvined to the same
point for optimal current sharing.
Dual-Channel Operation
TheLTC3861-1cancontroltwoindependentpowersupply
outputs with no channel-to-channel interaction or jitter.
The following recommendations will ensure maximum
performance in this mode of operation:
External soft-start is enabled by connecting a capacitor
from the TRACK/SS pin to SGND. An internal 2.5µA cur-
rentsourcechargesthecapacitor, creatingalinearvoltage
ramp at the TRACK/SS pin, and causing the output sup-
ply to rise smoothly from its prebiased value to its final
regulated value. The total soft-start time is approximately:
n
The output of each channel should be sensed using
the differential sense amplifier. The SGND pins and
exposed pad and all local small-signal GND should
then be a Kelvin connection to the negative terminal of
each channel output. This will provide the best possible
regulation of each channel without adversely affecting
the other channel.
600mV
tSS(milliseconds) = CSSµF •
2.5µA
Alternatively, the TRACK/SS pin can be used to track
another supply during start-up.
n
Due to internal logic used to determine the mode of
operation, separate current limit resistors should be
used for each channel in dual-channel operation, even
when the values are the same.
38611f
24
LTC3861-1
applicaTions inFormaTion
The ramp time for V
value is:
to rise from 0V to its final
For example, Figure 11 shows the start-up of V
OUT2
OUT2
controlled by the voltage on the TRACK/SS2 pin. Nor-
mally this pin is used to allow the start-up of V
to
RTRACKA +RTRACKB
0.6
VOUT1F
OUT2
tSS2 = tSS1
•
•
track that of V
as shown qualitatively in Figures
OUT1
RTRACKA
12a and 12b. When the voltage on the TRACK/SS2 pin
is less than the internal 0.6V reference, the LTC3861-1
regulates the FB2 voltage to the TRACK/SS2 pin voltage
For coincident tracking,
VOUT2F
VOUT1F
instead of 0.6V. The start-up of V
may ratiometrically
OUT2
tSS2 = tSS1
•
track that of V
, according to a ratio set by a resistor
OUT1
divider (Figure 12b):
where V
and V
are the final, regulated values
. V should always be greater than
OUT2 OUT1
OUT1F
and V
OUT2F
VOUT1
RTRACKA +RTRACKB
R2B+R2A
R2A
VOUT2 RTRACKA
of V
OUT1
=
•
V
when using the TRACK/SS2 pin for tracking. If no
OUT2
tracking function is desired, then the TRACK/SS2 pin may
be tied to a capacitor to ground, which sets the ramp time
tofinalregulatedoutputvoltage. Itisonlypossibletotrack
another supply that is slower than the internal soft-start
ramp. At the completion of tracking, the TRACK/SS pin
must be >ꢀ2±mV, so as not to affect regulation accuracy
and to ensure the part is in CCM mode0
For coincident tracking (V
= V
during start-up),
OUT1
OUT2
R2A = R
R2B = R
TRACKA
TRACKB
V
OUT1
V
OUT2
LTC3861-1
R2B
R1B
FB1
FB2
R2A
R1A
R
R
TRACKB
TRACK/SS2
38611 F11
TRACKA
Figure 110 Using the TRACK/SS Pin
V
V
V
OUT1
OUT1
OUT2
V
OUT2
38611 F12b
TIME
TIME
(12a) Coincident Tracking
(12b) Ratiometric Tracking
Figure 120 Two Different Modes of Output Voltage Tracking
38611f
25
LTC3861-1
applicaTions inFormaTion
Feedback Loop Compensation
In a typical LTC3861-1 circuit, the feedback loop consists
of the line feedforward circuit, the modulator, the external
inductor, the output capacitor and the feedback amplifier
with its compensation network. All these components
affect loop behavior and need to be accounted for in the
loop compensation. The modulator consists of the PWM
generator, the output MOSFET drivers and the external
MOSFETs themselves. The modulator gain varies linearly
with the input voltage. The line feedforward circuit com-
pensates for this change in gain, and provides a constant
gain from the error amplifier output to the inductor input
regardless of input voltage. From a feedback loop point of
view, the combination of the line feedforward circuit and
the modulator looks like a linear voltage transfer function
from COMP to the inductor input. It has fairly benign AC
behavior at typical loop compensation frequencies with
significant phase shift appearing at half the switching
frequency.
The LTC3861-1 is a voltage mode controller with a second
dedicatedcurrentsharinglooptoprovideexcellentphase-
to-phase current sharing in multiphase applications. The
current sharing loop is internally compensated.
While Type 2 compensation for the voltage control loop
may be adequate in some applications (such as with the
use of high ESR bulk capacitors), Type 3 compensation,
along with ceramic capacitors, is recommended for opti-
mum transient response. Referring to Figure 13, the error
amplifiers sense the output voltage at V
.
OUT
The positive input of the error amplifier is connected to
an internal 600mV reference, while the negative input is
connectedtotheFBpin.TheoutputisconnectedtoCOMP,
which is in turn connected to the line feedforward circuit
and from there to the PWM generator. To speed up the
overshoot recovery time, the maximum potential at the
COMP pin is internally clamped.
The external inductor/output capacitor combination
makes a more significant contribution to loop behavior.
These components cause a second order LC roll-off at the
output with 180° phase shift. This roll-off is what filters
the PWM waveform, resulting in the desired DC output
voltage, but this phase shift causes stability issues in the
feedback loop and must be frequency compensated. At
higher frequencies, the reactance of the output capacitor
will approach its ESR, and the roll-off due to the capacitor
will stop, leaving –20dB/decade and 90° of phase shift.
Unlike many regulators that use a transconductance (g )
m
amplifier, the LTC3861-1 is designed to use an inverting
summing amplifier topology with the FB pin configured
as a virtual ground. This allows the feedback gain to be
tightly controlled by external components, which is not
possiblewithasimpleg amplifier.Inaddition,thevoltage
m
feedback amplifier allows flexibility in choosing pole and
zero locations. In particular, it allows the use of Type 3
compensation, which provides a phase boost at the LC
polefrequencyandsignificantlyimprovesthecontrolloop
phase margin.
Figure 13 shows a Type 3 amplifier. The transfer function
of this amplifier is given by the following equation:
– 1+sC1R2 1+s(R1+R3)C3
VCOMP
(
)
[
]
=
VOUT sR1 C1+C2 1+s(C1//C2)R2 1+sC3R3
⎡
⎤
(
)
⎣
⎦
C2
V
OUT
C1
R2
C3
R3
–1
R1
GAIN
+1
–1
–
0
FREQ
FB
–90
COMP
PHASE
–180
–270
–380
+
V
REF
BOOST
38611 F13
Figure 130 Type 3 Amplifier Compensation
38611f
26
LTC3861-1
applicaTions inFormaTion
The RC network across the error amplifier and the feed-
forward components R3 and C3 introduce two pole-zero
pairs to obtain a phase boost at the system unity-gain
Required error amplifier gain at frequency f :
C
A
frequency, f . In theory, the zeros and poles are placed
C
2
2
⎛
⎞
⎛
⎞
fC
fC
f
ESR
symmetricallyaroundf ,andthespreadbetweenthezeros
C
≈ 40log 1+
– 20log 1+
– 20log A
(
)
MOD
⎜
⎟
⎜
⎟
and the poles is adjusted to give the desired phase boost
f
⎝
⎠
⎝
⎠
LC
at f . However, in practice, if the crossover frequency
C
⎛
⎞
fP2(RES) fP2(RES) – fZ2(RES)
⎛
⎞
fLC
fC
is much higher than the LC double-pole frequency, this
method of frequency compensation normally generates
a phase dip within the unity bandwidth and creates some
concern regarding conditional stability.
1+
1+
+
⎜
⎟
⎜
⎟
fC
fLC
fESR fESR – fLC
fZ2(RES)
fP2(RES)
⎝
⎠
⎝
⎠
R2
R1
≈20log
•
⎛
⎜
⎞
⎛
⎞
⎟
fC
1+
+
1+
⎟
⎜
fC
⎝
⎠
⎝
⎠
If conditional stability is a concern, move the error ampli-
fier’s zero to a lower frequency to avoid excessive phase
dip. The following equations can be used to compute the
feedback compensation components value:
where AMOD is the modulator and line feedforward gain
and is equal to:
V
IN(MAX) • DCMAX
AMOD
≈
≈ 12V/ V
fSW = Switching frequency
VRAMP
1
fLC
=
where DC
is the maximum duty cycle and V
is
RAMP
MAX
2π LCOUT
the line feedforward compensated PWM ramp voltage.
1
fESR
=
Once the value of resistor R1, poles and zeros location
have been decided, the value of R2, C1, C2, R3 and C3
can be obtained from the previous equations.
2πRESR COUT
choose:
Compensating a switching power supply feedback loop
is a complex task. The applications shown in this data
sheet show typical values, optimized for the power
components shown. Though similar power compon-
ents should suffice, substantially changing even one
major power component may degrade performance
significantly. Stability also may depend on circuit board
layout. To verify the calculated component values, all
new circuit designs should be prototyped and tested
for stability.
fSW
10
fC =Crossover frequency =
1
fZ1(ERR) = fLC =
2πR2C1
fC
5
1
fZ2(RES)
=
=
2π R1+R3 C3
(
)
1
fP1(ERR) = fESR
=
2πR2(C1//C2)
1
fP2(RES) = 5fC =
2πR3C3
38611f
27
LTC3861-1
applicaTions inFormaTion
Inductor
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than one-third of the input voltage. In applications
The inductor in a typical LTC3861-1 circuit is chosen for
a specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the
ripple current. The inductor ripple current in the buck
mode is:
where V >> V , the top MOSFETs’ on-resistance is
IN
OUT
normally less important for overall efficiency than its
input capacitance at operating frequencies above 300kHz.
MOSFET manufacturers have designed special purpose
devices that provide reasonably low on-resistance with
significantlyreducedinputcapacitanceforthemainswitch
application in switching regulators.
⎛
⎞
VOUT
(f)(L)
VOUT
ΔIL =
1–
⎜
⎟
V
⎝
⎠
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at
low frequency with small ripple current. To achieve this
however, requires a large inductor.
Selection criteria for the power MOSFETs include the on-
resistance R
, input capacitance, breakdown voltage
DS(ON)
and maximum output current.
A reasonable starting point is to choose a ripple cur-
rent between 20% and 40% of I
largest ripple current occurs at the highest V . To guar-
For maximum efficiency, on-resistance R
capacitanceshouldbeminimized. LowR
and input
. Note that the
DS(ON)
O(MAX)
minimizes
DS(ON)
IN
conduction losses and low input capacitance minimizes
switchingandtransitionlosses.MOSFETinputcapacitance
is a combination of several components but can be taken
from the typical gate charge curve included on most data
sheets (Figure 14).
antee that ripple current does not exceed a specified
maximum, the inductor in buck mode should be chosen
according to:
⎛
⎞
VOUT
f ΔIL(MAX)
VOUT
V
IN(MAX)
L ≥
1–
⎜
⎟
⎝
⎠
The curve is generated by forcing a constant-input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
Power MOSFET Selection
TheLTC3680requiresatleasttwoexternalN-channelpower
MOSFETs per channel, one for the top (main) switch and
one or more for the bottom (synchronous) switch. The
V
IN
V
MILLER EFFECT
V
GS
a
b
+
–
V
DS
+
GS
–
Q
IN
V
C
= (Q – Q )/V
B A DS
MILLER
38611 F14
Figure 14. Gate Charge Characteristic
38611f
28
LTC3861-1
applicaTions inFormaTion
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
where δ is the temperature dependency of R
, R
DS(ON) DR
is the effective top driver resistance, V is the drain po-
IN
tential and the change in drain potential in the particular
application. V
is the data sheet specified typical gate
TH(IL)
while the curve is flat) is specified for a given V drain
thresholdvoltagespecifiedinthepowerMOSFETdatasheet
at the specified drain current. C is the calculated
DS
voltage, but can be adjusted for different V voltages by
DS
MILLER
multiplying by the ratio of the application V to the curve
capacitanceusingthegatechargecurvefromtheMOSFET
data sheet and the technique previously described.
DS
specified V values. A way to estimate the C
term
DS
MILLER
is to take the change in gate charge from points a and b
The term (1 + δ) is generally given for a MOSFET in the
on a manufacturers data sheet and divide by the stated
formofanormalizedR
vstemperaturecurve.Typical
DS(ON)
V
DS
voltage specified. C
is the most important se-
MILLER
values for δ range from 0.005/°C to 0.01/°C depending
on the particular MOSFET used.
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
and C are specified sometimes but
Multiple MOSFETs can be used in parallel to lower
RSS
OS
definitions of these parameters are not included.
R
and meet the current and thermal requirements
DS(ON)
if desired. Suitable drivers such as the LTC4449 are
capable of driving large gate capacitances without sig-
nificantly slowing transition times. In fact, when driving
MOSFETs with very low gate charge, it is sometimes
helpful to slow down the drivers by adding small gate
resistors (5Ω or less) to reduce noise and EMI caused
by the fast transitions
When the controller is operating in continuous mode
the duty cycles for the top and bottom MOSFETs are
given by:
VOUT
Main Switch Duty Cycle =
V
IN
V – VOUT
IN
Synchronous Switch Duty Cycle =
V
IN
MOSFET Driver Selection
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
Gate driver ICs, DrMOSs and power blocks with an
interface compatible with the LTC3861-1’s three-state
PWM outputsortheLTC3861-1’sPWM/PWMENoutputs
can be used.
VOUT
PMAIN
=
I
(
2(1+δ)RDS(ON)
+
MAX
)
V
IN
2 I
V
MAX (RDR)(CMILLER)•
IN
2
⎡
⎢
⎤
⎥
1
1
+
(f)
V – VTH(IL) VTH(IL) ⎥
⎢ CC
⎣
⎦
V − V
OUT (IMAX)2(1+δ)RDS(0N)
IN
PSYNC
=
V
IN
38611f
29
LTC3861-1
applicaTions inFormaTion
Efficiency Considerations
Design Example
The efficiency of a switching regulator is equal to the
output power divided by the input power. It is often useful
to analyze individual losses to determine what is limiting
the efficiency and which change would produce the most
improvement. Percent efficiency can be expressed as:
As a design example, consider a 2-phase application
where V = 12V, V
= 1.2V, I
= 60A and f
=
IN
OUT
LOAD
SWITCH
300kHz. Assume that a secondary 5V supply is available
for the LTC3861-1 V supply.
CC
The inductance value is chosen based on a 25% ripple
assumption. Each channel supplies an average 30A to the
load resulting in 7.7A peak-peak ripple:
%Efficiency = 100% - (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
⎛
⎝
⎞
⎠
VOUT
V
OUT • 1–
⎜
⎟
V
Although all dissipative elements in the system produce
losses, three main sources usually account for most of
IN
ΔIL =
f •L
2
the losses in LTC3861-1 applications: 1) I R losses, 2)
A 470nH inductor per phase will create 7.7A peak-to-
peak ripple. A 0.47µH inductor with a DCR of 0.67mΩ
typical is selected from the WÜRTH 744355147 series.
Float CLKIN and connect 28kΩ from FREQ to SGND for
topside MOSFET transition losses, 3) gate drive current.
2
1. I R losses occur mainly in the DC resistances of the
MOSFET, inductor, PCB routing, and input and output
capacitor ESR. Since each MOSFET is only on for part
of the cycle, its on-resistance is effectively multiplied
by the percentage of the cycle it is on. Therefore in high
step-downratioapplicationsthebottomMOSFETshould
300kHz operation. Setting I
= 54A per phase leaves
LIMIT
plenty of headroom for transient conditions while still
adequately protecting against inductor saturation. This
corresponds to:
have a much lower R
than the top MOSFET. It
DS(ON)
18.5 • 54A • 0.67mΩ + 0.53V
is crucial that careful attention is paid to the layout of
the power path on the PCB to minimize its resistance.
In a 2-phase, 1.2V output, 60A system, 1mΩ of PCB
resistance at the output costs 5% in efficiency.
RILIM
=
= 58.5kΩ
20µA
Choose 59kΩ.
For the DCR sense filter network, we can choose R = 2.87k
and C = 220nF to match the L/DCR time constant of the
inductor.
2. Transition losses apply only to the topside MOSFET but
in 12V input applications are a very significant source
of loss. They can be minimized by choosing a driver
with very low drive resistance and choosing a MOSFET
A loop crossover frequency of 45kHz provides good tran-
sientperformancewhilestillbeingwellbelowtheswitching
frequency of the converter. Six 330µF 9mΩ POSCAPs and
four 100µF ceramic capacitors are chosen for the output
capacitors to maintain supply regulation during severe
transientconditionsandtominimizeoutputvoltageripple.
with low Q , R and C .
G
G
RSS
3. Gate drive current is equal to the sum of the top and
bottom MOSFET gate charges multiplied by the fre-
quency of operation. However, many drivers employ a
linear regulator to reduce the input voltage to a lower
gate drive voltage. This multiplies the gate loss by that
step down ratio. In high frequency applications it may
be worth using a secondary user supplied rail for gate
drive to avoid the linear regulator.
The following compensation values (Figure 13) were
determined empirically:
R1 = 10k
R2 = 5.9k
R3 = 280Ω
C1 = 4.7nF
C2 = 100pF
Other sources of loss include body or Schottky diode
conduction during the driver dependent non-overlap time
and inductor core losses.
C3 = 3.3nF
38611f
30
LTC3861-1
applicaTions inFormaTion
To set the output voltage equal to 1.2V:
3. The PCB traces for remote voltage and current sense
should avoid any high frequency switching nodes in
the circuit and should ideally be shielded by ground
R
FB1
= 10k, R = 10k
FB2
TheLTC4449gatedriverandexternalMOSFETsarechosen
for the power stage. DrMOSs from Fairchild, Infineon,
Vishay and others can also be used.
planes. Each pair (V
and V
, I
and
SNSP
SNSN SNSP
I
) should be routed parallel to one another with
SNSN
minimum spacing between them. If DCR sensing is
used, place the top resistor (Figure 5b, R1) close to
the switching node.
Printed Circuit Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the converter.
4. The input capacitor should be kept as close as possible
to the power MOSFETs. The loop from the input capaci-
tor’s positive terminal, through the MOSFETs and back
to the input capacitor’s negative terminal should also
be as small as possible.
1. TheconnectionbetweentheSGNDpinontheLTC3861-1
andallofthesmall-signalcomponentssurroundingthe
IC should be isolated from the system power ground.
Place all decoupling capacitors, such as the ones on
5. If using discrete drivers and MOSFETs, check the
stress on the MOSFETs by independently measuring
thedrain-to-sourcevoltagesdirectlyacrossthedevice
terminals.Bewareofinductiveringingthatcouldexceed
the maximum voltage rating of the MOSFET. If this
ringing cannot be avoided and exceeds the maximum
rating of the device, choose a higher voltage rated
MOSFET.
V , between ISNSP and ISNSN etc., close to the IC. In
CC
multiphaseoperationSGNDshouldbeKelvin-connected
to the main ground node near the bottom terminal of
the input capacitor. In dual-channel operation, SGND
should be Kelvin-connected to the bottom terminal of
theoutputcapacitorforchannel2,andchannel1should
be remotely sensed using the remote sense differential
amplifier.
6. When cascading multiple LTC3861-1 ICs, minimize
the capacitive load on the CLKOUT pin to minimize
phase error. Kelvin all the LTC3861-1 IC grounds to
the same point, typically SGND of the IC containing
the master.
2. Place the small-signal components away from high fre-
quency switching nodes on the board. The LTC3861-1
containsremotesensingofoutputvoltageandinductor
current and logic-level PWM outputs enabling the IC to
be isolated from the power stage.
38611f
31
LTC3861-1
Typical applicaTions
Dual Phase 1.2V/45A Converter with Delta 45A Power Block, fSW = 40 0 kHz
100pF
V
IN
7V TO 14V
C
IN
180µF
V
CC
V
CC
5V
100k
SS1
1µF
RUN1
6.8nF
0.22µF
110Ω
10k
1.69k
150pF
1.5nF
TEMP1
45.3k
FB1
RUN1
LIM1
+CS1
–CS1
GND
V
IN
D12S1-
R845A
COMP1
VSNSP
VSNSN
I
V
OUT
V
IN1
V
OUT
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
1.2V/45A
10k
22µF
16V
22µF
16V
4.7µF
PWM1
GND
V
OUT1
C
C
OUT1
OUT2
LTC3861-1
100µF ×4 330µF×6
+7V
VSNSOUT
COMP2
FB2
6.3V
2.5V
22µF
16V
22µF
16V
PWM2
V
OUT2
V
CC
V
IN2
GND
V
I
CC
LIM2
RUN2
+CS2
–CS2
TEMP2
0.22µF
RUN1
C
C
: SANYO 2R5TPE330M9
: MURATA GRM32ER60J107ME20
OUT2
OUT1
SS1
30.9k
38611 TA02
1.5V/30 A and 1.2V/30 A Converter with Discrete Gate Drivers
and MOSFETs, fSW = 30 0 kHz
V
IN
C
IN2
22µF ×2
V
IN
IN
V
V
7V TO 14V
0.1µF
1µF
C
CC
LTC4449
GND
IN1
180µF
BSC050NE2LS
× 2
M1
V
L1
0.47µH
CC
V
OUT1
V
CC
5V
TG
TS
1.5V/30A
LOGIC
4.7µF
RUN1
RUN1
D1
100k
V
CC
BOOST BG
BSC010NE2LS
× 2
M2
2.2nF
C
C
499Ω
30.1k
3.92k
100pF
20k
0.22µF
OUT1
OUT2
2.87k
2.2nF
100µF ×2 330µF ×3
61.9k
6.3V
2.5V
FB1
COMP1
VSNSP
VSNSN
I
LIM1
V
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
OUT1
0.22µF
LTC3861-1
VSNSOUT
0.22µF
V
OUT2
COMP2
FB2
100pF
3.57k
20k
I
2.2nF
LIM2
RUN2
61.9k
D2
499Ω
2.2nF
V
IN
C
RUN2
IN3
2.87k
IN
V
22µF ×2
20k
V
CC
LTC4449
GND
27.4k
100k
BSC050NE2LS
× 2
M3
0.047µF
L2
0.47µH
V
OUT2
V
CC
TG
TS
1.2V/30A
LOGIC
4.7µF
V
CC
BOOST BG
BSC010NE2LS
× 2
M4
C
C
OUT4
OUT3
100µF ×2 330µF ×3
6.3V 2.5V
0.22µF
C
, C
OUT2 OUT4
: SANYO 2R5TPE330M9
: MURATA GRM32ER60J107ME20
C
, C
OUT1 OUT3
L1, L2: WÜRTH ELEKTRONIK 744355147
38611 TA03
38611f
32
LTC3861-1
Typical applicaTions
4-Phase 1V/10 0 A Converter with DrMOS, fSW = 50 0 kHz
SS1
I
AVG1
0.22µF
V
IN
7V TO 14V
100pF
V
IN
0.1µF
C
C
BOOT
PHASE
IN1
180µF
IN2
22µF × 2
16V
V
TDA21220
CC
L1
0.47µH
V
IN
DISB
10k
V
CC
5V
VSWH
PGND
100k
PWM
VDRV
VCIN SMOD CGND
1µF
V
CC
RUN1
2.87k
3.3nF
280Ω
20k
5.62k
470pF
3.3nF
1Ω
2.2µF
16V
53.6k
10k
FB1
RUN1
2.2µF
16V
COMP1
VSNSP
VSNSN
I
LIM1
0.22µF
V
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
OUT
30.1k
V
OUT
1V/100A
LTC3861-1
VSNSOUT
COMP2
FB2
C
OUT2
C
OUT1
330µF
×8
0.22µF
2.87k
V
100µF ×8
6.3V
CC
0.22µF
V
V
IN
I
CC
2.5V
LIM2
C
BOOT
PHASE
VSWH
IN3
RUN2
22µF × 2
16V
TDA21220
V
IN
10k
SS1
DISB
PWM
RUN1
RUN1
RUN2
CLKIN
500kHz EXTERNAL
SYNC INPUT
L2
0.47µH
V
CC
VDRV
VCIN SMOD
PGND
CGND
34k
1Ω
10k
2.2µF
2.2µF
16V
16V
0.22µF
V
IN
C
BOOT
PHASE
IN4
22µF × 2
16V
TDA21220
L3
0.47µH
V
IN
10k
V
CC
VSWH
DISB
PWM
V
IN
5V
1µF
SS1
V
CC
V
PGND
CGND
CC
VDRV
VCIN SMOD
2.87k
1Ω
53.6k
10k
FB1
RUN1
LIM1
2.2µF
16V
2.2µF
16V
COMP1
VSNSP
VSNSN
VSNSOUT
COMP2
FB2
I
0.22µF
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
LTC3861-1
V
CC
0.22µF
2.87k
0.22µF
BOOT
V
V
IN
I
CC
LIM2
PHASE
C
RUN2
IN5
22µF × 2
16V
TDA21220
V
IN
DISB
10k
VSWH
SS1
PWM
VDRV
VCIN SMOD CGND
L4
0.47µH
V
CC
PGND
34k
C
C
: SANYO 2R5TPE330M9
: MURATA GRM32ER60J107ME20
L1, L2, L3, L4: WÜRTH ELEKTRONIK 744355147
1Ω
OUT2
OUT1
10k
2.2µF
16V
2.2µF
16V
38611 TA04
38611f
33
LTC3861-1
Typical applicaTions
Dual-Output Converter: Triple Phase + Single Phase with DrMOS,
Synchronized to an External 50 0 kHz Clock
SS1
0.22µF
BOOT
V
IN
7V TO 14V
100pF
V
IN
0.1µF
C
C
PHASE
VSWH
IN1
180µF
IN2
22µF × 2
16V
V
FDMF6707B
CC
L1
0.47µH
V
IN
10k
V
CC
5V
DISB
100k
PWM
1µF
V
CC
RUN1
PGND
CGND
VDRV
2.87k
3.3nF
280Ω
20k
3.48k
150pF
30.1k
VCIN SMOD
3.3nF
1Ω
2.2µF
16V
53.6k
10k
FB1
RUN1
2.2µF
16V
COMP1
VSNSP
VSNSN
I
LIM1
0.22µF
V
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
OUT1
V
OUT1
1V/75A
LTC3861-1
VSNSOUT
COMP2
FB2
C
OUT2
C
OUT1
330µF
×6
V
0.22µF
2.87k
CC
100µF×6
6.3V
0.22µF
V
V
IN
I
CC
2.5V
LIM2
C
IN3
BOOT
PHASE
RUN2
22µF × 2
16V
FDMF6707B
V
10k
IN
SS1
VSWH
DISB
PWM
VDRV
RUN1
CLKIN
500kHz EXTERNAL
SYNC INPUT
L2
0.47µH
V
CC
PGND
34k
VCIN SMOD CGND
1Ω
10k
2.2µF
16V
2.2µF
16V
0.22µF
V
IN
C
BOOT
PHASE
VSWH
IN4
22µF × 2
16V
FDMF6707B
L3
V
10k
IN
V
5V
0.47µH
CC
DISB
V
IN
PWM
1µF
SS1
V
CC
RUN1
V
CC
PGND
CGND
VDRV
2.87k
VCIN SMOD
1Ω
2.2µF
16V
53.6k
10k
FB1
RUN1
LIM1
2.2µF
16V
COMP1
VSNSP
VSNSN
I
0.22µF
V
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
OUT2
LTC3861-1
VSNSOUT
COMP2
FB2
0.22µF
2.87k
0.22µF
100pF
2.1k
4.99k
10k
V
IN
53.6k
I
1.5nF
LIM2
BOOT
PHASE
C
RUN2
IN5
280Ω
22µF × 2
16V
FDMF6707B
V
3.3nF
V
IN
OUT2
1.8V/25A
10k
RUN2
VSWH
DISB
PWM
L4
0.47µH
C
OUT4
V
CC
PGND
CGND
V
VDRV
34k 100k
CC
C
OUT3
0.1µF
330µF
×3
VCIN SMOD
100µF×2
6.3V
1Ω
2.5V
10k
2.2µF
16V
2.2µF
16V
38611 TA05
C
C
, C
OUT2 OUT4
: SANYO 2R5TPE330M9
: MURATA GRM32ER60J107ME20
, C
OUT1 OUT3
L1, L2, L3, L4: WÜRTH ELEKTRONIK 744355147
38611f
34
LTC3861-1
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 ±0.05
5.00 ±0.10
(4 SIDES)
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ±0.10
3.50 REF
(4-SIDES)
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38611f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3861-1
Typical applicaTion
Dual Phase 1.2V/60 A Converter with Discrete Gate Drivers and MOSFETs, fSW = 30 0 kHz
V
IN
C
IN2
100pF
V
IN
7V TO 14V
IN
LTC4449
22µF×2
V
C
CC
IN1
180µF
BSC050NE2LS
× 2
M1
L1
0.47µH
GND
TG
V
V
OUT
1.2V/60A
CC
V
CC
5V
V
V
LOGIC
CC
4.7µF
RUN1
RUN1
D1
TS
SS1
1µF
BOOST BG
BSC010NE2LS
× 2
100k
M2
1nF
C
C
221Ω
20k
OUT1
13k
0.22µF
OUT2
2.87k
1nF
100µF×4
6.3V
330µF×6
59k
FB1
2.5V
220pF
COMP1
VSNSP
VSNSN
I
LIM1
V
OUT
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
20k
0.22µF
LTC3861-1
VSNSOUT
COMP2
FB2
0.22µF
V
CC
V
I
CC
LIM2
RUN2
V
IN
C
RUN1
IN3
2.87k
IN
LTC4449
22µF×2
SS1
V
CC
28.7k
BSC050NE2LS
× 2
M3
GND
TG
L2
0.47µH
V
V
LOGIC
CC
4.7µF
D2
TS
BOOST BG
BSC010NE2LS
× 2
C
C
: SANYO 2R5TPE330M9
M4
OUT2
OUT1
: MURATA GRM32ER60J107ME20
0.22µF
38611 TA06
L1, L2 : WÜRTH ELEKTRONIK 744355147
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
Up to 24V, 0.5V ≤ V
LTC3880/
Dual Output PolyPhase Step-Down DC/DC Controller with
Digital Power System Management
V
≤ 5.5V, Analog Control Loop,
OUT
IN
2
LTC3880-1
I C/PMBus Interface with EEPROM and 16-Bit ADC
LTC3855
LTC3856
LTC3838
LTC3839
LTC3860
Dual Output, 2-Phase, Synchronous Step-Down DC/DC Controller
with Diffamp and DCR Temperature Compensation
4.5V ≤ V ≤ 38V, 0.8V ≤ V
≤ 12V, PLL Fixed Frequency
≤ 5V, PLL Fixed 250kHz to
≤ 5.5V, PLL, Up to 2MHz
≤ 5.5V, PLL, Up to 2MHz
IN
OUT
OUT
OUT
OUT
250kHz to 770kHz
Single Output 2-Phase Synchronous Step-Down DC/DC Controller
with Diffamp and DCR Temperature Compensation
4.5V ≤ V ≤ 38V, 0.8V ≤ V
IN
770kHz Frequency
Dual Output, 2-Phase, Synchronous Step-Down DC/DC Controller
with Diff Amp and Controlled On-Time
4.5V ≤ V ≤ 38V, 0.8V ≤ V
IN
Switching Frequency
Single Output, 2-Phase, Synchronous Step-Down DC/DC Controller
with Diff Amp and Controlled On-Time
4.5V ≤ V ≤ 38V, 0.8V ≤ V
IN
Switching Frequency
Dual, Multiphase, Synchronous Step-Down DC/DC Controller
with Diffamp and Three-State Output Drive
Operates with Power Blocks, DrMOS Devices or External
MOSFETs, 3V ≤ V ≤ 24V, t = 20ns
IN
ON(MIN)
LTC3869/
LTC3869-2
Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller,
with Accurate Current Share
4V ≤ V ≤ 38V, V
Up to 12.5V, PLL Fixed 250kHz to
IN
OUT3
750kHz Frequency
LTC3866
LTC4449
Single Output, High Power, Current Mode Controller with
Submilliohm DCR Sensing
4.75V ≤ V ≤ 38V, 0.6V≤ V
≤ 3.5V, Fixed 250kHz to
IN
OUT
770kHz Frequency
High Speed Synchronous N-Channel MOSFET Driver
V Up to 38V, 4V ≤ V ≤ 6.5V, Adaptive Shoot-Through
IN CC
Protection, 2mm × 3mm DFN-8 Package
LTC4442/
LTC4442-1
High Speed Synchronous N-Channel MOSFET Driver
V Up to 38V, 6V ≤ V ≤ 9V Adaptive Shoot-Through
IN CC
Protection, MSOP-8 Package
LTC3861
Dual, Multiphase, Synchronous Step-Down DC/DC Controller
with Two Diffamps and Three-State Output Drive
Operates with Power Blocks, DrMOS Devices or External
MOSFETs, 3V ≤ V ≤ 24V, t
= 20ns
IN
ON(MIN)
38611f
LT 0812 PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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