LTC3784_15_技术文档

LTC3784

60V PolyPhase Synchronous

Boost Controller

FeaTures

DescripTion

PolyPhase^®Operation Reduces Required Input and

The LTC^®3784 is a high performance PolyPhase^®single

outputsynchronousboostconvertercontrollerthatdrives

two N-channel power MOSFET stages out-of-phase.

Multiphase operation reduces input and output capacitor

requirements and allows the use of smaller inductors than

the single-phase equivalent. Synchronous rectification in-

creasesefficiency,reducespowerlossesandeasesthermal

requirements, simplifying high power boost applications.

n

Output Capacitance and Power Supply Induced Noise

n

Synchronous Operation for Highest Efficiency and

Reduced Heat Dissipation

n

Wide V Range: 4.5V to 60V (65V Abs Max);

IN

Operates Down to 2.3V After Start-Up

Output Voltage Up to 60V

n

±±1 ±.200V Reference Voltage

R

or Inductor DCR Current Sensing

SENSE

A 4.5V to 60V input supply range encompasses a wide

range of system architectures and battery chemistries.

When biased from the output of the boost converter or

anotherauxiliarysupply, theLTC3784canoperatefroman

input supply as low as 2.3V after start-up. The operating

frequency can be set within a 50kHz to 900kHz range or

synchronized to an external clock using the internal PLL.

PolyPhase operation allows the LTC3784 to be configured

for 2-, 3-, 4-, 6- and 12-phase operation.

±001 Duty Cycle Capability for Synchronous MOSFET

Low Quiescent Current: 28μA

Phase-Lockable Frequency (75kHz to 850kHz)

Programmable Fixed Frequency (50kHz to 900kHz)

Power Good Output Voltage Monitor

Low Shutdown Current, I < 4µA

Q

Internal LDO Powers Gate Drive from VBIAS or EXTV

CC

Thermally Enhanced Low Profile 28-Pin 4mm × 5mm

QFN Package and Narrow SSOP Package

The SS pin ramps the output voltage during start-up. The

PLLIN/MODE pin selects Burst Mode^®operation, pulse-

skipping mode or forced continuous mode at light loads.

L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase

applicaTions

n

Industrial

n

Automotive

are registered trademarks and No R

and ThinSOT are trademarks of Linear Technology

SENSE

Corporation. All other trademarks are the property of their respective owners. Protected by

U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.

n

Medical

Military

n

Typical applicaTion

240W, ±2V to 24V/±0A 2-Phase Synchronous Boost Converter

3.3µH

4mΩ

+

SENSE1

47µF

Efficiency and Power Loss

vs Output Current

–

BG1

BOOST1

100

90

10000

1000

100

10

0.1µF

4.7µF

V

OUT

IN

4.5V TO 60V

VBIAS

24V AT 10A

SW1

TG1

DOWN TO 2.3V AFTER

STARTUP IF VBIAS IS

220µF

80

LTC3784

POWERED FROM V

OUT

70

INTV

CC

V

60

50

OUT

FOLLOWS V

3.3µH

4mΩ

IN

FOR V > 24V

IN

+

SENSE2

40

30

20

10

0

–

BURST EFFICIENCY

BURST LOSS

= 12V

= 24V

Burst Mode OPERATION

FIGURE 10 CIRCUIT

BG2

V

IN

OUT

1

BOOST2

0.1µF

FREQ

OVMODE

PLLIN/MODE

0.1

SW2

TG2

VFB

0.00001 0.0001 0.001 0.01

0.1

1

10

OUTPUT CURRENT (A)

3784 TA01b

ITH

3784 TA01a

SS

SGND PGND

232k

12.1k

15nF

8.66k

100pF

0.1µF

3784fb

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For more information www.linear.com/LTC3784

LTC3784

(Notes ±, 3)

absoluTe MaxiMuM raTings

EXTV ...................................................... –0.3V to 14V

VBIAS ........................................................ –0.3V to 65V

BOOST1 and BOOST2.................................–0.3V to 71V

SW1 and SW2............................................... –5V to 65V

RUN ............................................................. –0.3V to 8V

Maximum Current Sourced into Pin

CC

+

–

+

–

SENSE1 , SENSE1 , SENSE2 , SENSE2 ... –0.3V to 65V

+

–

+

–

(SENSE1 -SENSE1 ), (SENSE2 - SENSE2 )...–0.3Vto 0.3V

ILIM, SS, ITH, FREQ, PHASMD, VFB.....–0.3V to INTV

CC

Operating Junction Temperature

Range (Note 2)........................................–55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) SSOP ........300°C

From Source >8V..............................................100µA

PGOOD, PLLIN/MODE ................................. –0.3V to 6V

INTV , (BOOST1 - SW1), (BOOST2 - SW2)...–0.3V to 6V

CC

pin conFiguraTion

TOP VIEW

1

2

PGOOD

SW1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ILIM

+

SENSE1

–

28 27 26 25 24 23

3

TG1

SENSE1

FREQ

PHASMD

CLKOUT

PLLIN/MODE

SGND

1

2

3

4

5

6

7

8

22

BOOST1

4

BOOST1

BG1

FREQ

PHASMD

CLKOUT

PLLIN/MODE

SGND

21 BG1

5

20 VBIAS

19 PGND

6

VBIAS

PGND

29

GND

7

18 EXTV

CC

8

EXTV

CC

17 INTV

16 BG2

RUN

9

INTV

CC

RUN

SS

10

11

12

13

14

BG2

SS

–

BOOST2

15

SENSE2

–

BOOST2

TG2

SENSE2

9

10 11 12 13 14

UFD PACKAGE

+

SENSE2

SW2

VFB

ITH

OVMODE

28-LEAD (4mm × 5mm) PLASTIC QFN

GN PACKAGE

28-LEAD PLASTIC SSOP

T

JMAX

= 150°C, θ = 43°C/W

JA

EXPOSED PAD (PIN 29) IS GND, MUST BE CONNECTED TO GND

T

= 150°C, θ = 80°C/W

JA

JMAX

orDer inForMaTion

LEAD FREE FINISH

LTC3784EUFD#PBF

LTC3784IUFD#PBF

LTC3784HUFD#PBF

LTC3784MPUFD#PBF

LTC3784EGN#PBF

LTC3784IGN#PBF

LTC3784HGN#PBF

LTC3784MPGN#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3784EUFD#TRPBF

LTC3784IUFD#TRPBF

LTC3784HUFD#TRPBF

3784

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

28-Lead (4mm × 5mm) Plastic QFN

28-Lead Plastic SSOP

LTC3784MPUFD#TRPBF 3784

LTC3784EGN#TRPBF

LTC3784IGN#TRPBF

LTC3784HGN#TRPBF

LTC3784MPGN#TRPBF

LTC3784GN

28-Lead Plastic SSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3784fb

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For more information www.linear.com/LTC3784

LTC3784

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).

SYMBOL

Main Control Loop

VBIAS Chip Bias Voltage Operating Range

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

4.5

2.3

60

V

SENSE Pins Common Mode Range (BOOST

Converter Input Supply Voltage V )

IN

l

V

FB

Regulated Feedback Voltage

Feedback Current

I

= 1.2V (Note 4)

TH

1.188

1.200

5

1.212

50

V

nA

(Note 4)

Reference Line Voltage Regulation

VBIAS = 6V to 60V

Measured in Servo Loop;

0.002

0.01

0.02

0.1

%/V

%

l

Output Voltage Load Regulation

(Note 4)

ΔI Voltage = 1.2V to 0.7V

TH

Measured in Servo Loop;

–0.01

2

–0.1

%

ΔI Voltage = 1.2V to 2V

TH

Error Amplifier Transconductance

I

TH

= 1.2V

mmho

I

Input DC Supply Current

Pulse-Skipping or Forced Continuous Mode

Sleep Mode

(Note 5)

RUN = 5V; V = 1.25V (No Load)

Q

0.9

28

4

mA

µA

FB

RUN = 5V; V = 1.25V (No Load)

45

10

FB

Shutdown

RUN = 0V

SW Pin Current

V

= 12V; V

= 4.5V;

BOOST1,2

700

µA

SW1,2

FREQ = 0V, Forced Continuous or

Pulse-Skipping Mode

l

UVLO

INTV Undervoltage Lockout Thresholds

V

Ramping Up

Ramping Down

4.1

3.8

4.3

V

CC

INTVCC

3.6

l

V

RUN Pin ON Threshold

RUN Pin Hysteresis

V

Rising

1.18

1.28

100

4.5

0.5

10

1.38

V

mV

µA

RUN

RUN Pin Hysteresis Current

RUN Pin Current

V

> 1.28V

RUN

< 1.28V

µA

Soft-Start Charge Current

Maximum Current Sense Threshold

= GND

7

13

µA

SS

l

V

FB

V

FB

V

FB

= 1.1V, I = INTV

90

68

42

100

75

50

110

82

56

mV

SENSE1,2(MAX)

LIM

CC

= 1.1V, I = Float

= 1.1V, I = GND

l

Matching Between V

SENSE2(MAX)

and

V

= 1.1V, I = INTV

–12

–10

–9

0

12

10

9

mV

SENSE1(MAX)

FB

LIM

CC

V

= 1.1V, I = Float

LIM

= 1.1V, I = GND

LIM

+

SENSE Pin Current

V

C

= 1.1V, I = Float

200

300

1

µA

ns

Ω

FB

LIM

–

SENSE Pin Current

= 1.1V, I = Float

LIM

FB

Top Gate Rise Time

Top Gate Fall Time

= 3300pF (Note 6)

20

LOAD

Bottom Gate Rise Time

20

Bottom Gate Fall Time

20

Top Gate Pull-Up Resistance

Top Gate Pull-Down Resistance

Bottom Gate Pull-Up Resistance

1.2

30

Ω

Bottom Gate Pull-Down Resistance

Ω

Top Gate Off to Bottom Gate On Switch-On

Delay Time

C

= 3300pF (Each Driver)

ns

LOAD

Bottom Gate Off to Top Gate On Switch-On

Delay Time

30

ns

Maximum BG Duty Factor

Minimum BG On-Time

96

%

t

(Note 7)

110

ns

ON(MIN)

3784fb

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For more information www.linear.com/LTC3784

LTC3784

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

6V < V < 60V, V = 0V

EXTVCC

MIN

5.2

4.5

TYP

MAX

UNITS

INTV Linear Regulator

CC

Internal V Voltage

5.4

0.5

5.4

0.5

4.8

5.6

2

V

%

V

CC

BIAS

INTV Load Regulation

I

= 0mA to 50mA

CC

Internal V Voltage

6V < V

< 13V

EXTVCC

5.6

2

CC

INTV Load Regulation

I

= 0mA to 40mA, V = 8.5V

EXTVCC

%

V

CC

l

EXTV Switchover Voltage

EXTV Ramping Positive

5

CC

EXTV Hysteresis

250

mV

CC

Oscillator and Phase-Locked Loop

Programmable Frequency

R

= 25k

= 60k

= 100k

105

400

760

kHz

FREQ

335

465

f

Lowest Fixed Frequency

V

= 0V

320

488

75

350

535

380

585

850

kHz

LOW

FREQ

Highest Fixed Frequency

Synchronizable Frequency

= INTV

CC

l

PLLIN/MODE = External Clock

PGOOD Output

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

0.2

0.4

1

V

PGOOD

V

µA

PGOOD

with Respect to Set Regulated Voltage

FB

V

FB

Ramping Negative

–12

8

–10

2.5

–8

12

%

Hysteresis

V

Ramping Positive

Hysteresis

10

2.5

%

FB

PGOOD Delay

PGOOD Going High to Low

45

µs

V

OV Protection Threshold

V

Ramping Positive, OVMODE = 0V

1.296

1.32

1.344

FB

BOOST± and BOOST2 Charge Pump

BOOST Charge Pump Available Output

Current

V

= 12V; V

– V = 4.5V;

SW1,2

55

µA

SW1,2

BOOST1,2

FREQ = 0V, Forced Continuous or

Pulse-Skipping Mode

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

temperature (T , in °C) and power dissipation (P , in Watts) according to

A D

the formula: T = T + (P • θ ), where θ = 43°C/W for the QFN package

J

A

D

JA

and θ = 80°C/W for the SSOP package.

JA

Note 3: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 2: The LTC3784 is tested under pulsed load conditions such that

T ≈ T . The LTC3784E is guaranteed to meet specifications from

J

A

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3784I is guaranteed over the –40°C to 125°C operating junction

temperature range, the LTC3784H is guaranteed over the –40°C to 150°C

operating temperature range and the LTC3784MP is tested and guaranteed

over the full –55°C to 150°C operating junction temperature range. High

junction temperatures degrade operating lifetimes; operating lifetime

is derated for junction temperatures greater than 125°C. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

Note 4: The LTC3784 is tested in a feedback loop that servos V to the

FB

output of the error amplifier while maintaining I at the midpoint of the

TH

current limit range.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: see Minimum On-Time Considerations in the Applications

Information section.

factors. The junction temperature (T , in °C) is calculated from the ambient

J

3784fb

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For more information www.linear.com/LTC3784

LTC3784

Typical perForMance characTerisTics

T_A= 25°C unless otherwise noted.

Efficiency and Power Loss

vs Output Current

Efficiency and Power Loss

vs Output Current

Efficiency vs Load Current

100

90

10000

1000

100

10

100

90

10000

1000

100

10

100

99

98

97

96

95

94

93

92

91

90

V

LOAD

FIGURE 10 CIRCUIT

= 12V

IN

I

= 2A

80

70

V

= 24V

OUT

60

50

60

50

V

OUT

= 12V

40

30

20

10

0

40

30

20

10

0

V

= 12V

IN

OUT

1

V

= 12V

= 24V

IN

OUT

= 24V

Burst Mode OPERATION

FIGURE 10 CIRCUIT

0.1

0

5

15

INPUT VOLTAGE (V)

20

25

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01

0.1

1

10

OUTPUT CURRENT (A)

3784 G03

3784 G02

3784 G01

BURST EFFICIENCY

BURST LOSS

BURST EFFICIENCY BURST LOSS

PULSE-SKIPPING

EFFICIENCY

PULSE-SKIPPING

LOSS

FORCED CONTINUOUS

MODE EFFICIENCY

FORCED CONTINUOUS

MODE LOSS

Load Step

Burst Mode Operation

Load Step

Pulse-Skipping Mode

Load Step

Forced Continuous Mode

LOAD STEP

5A/DIV

LOAD STEP

5A/DIV

LOAD STEP

5A/DIV

INDUCTOR

CURRENT

5A/DIV

INDUCTOR

CURRENT

5A/DIV

INDUCTOR

CURRENT

5A/DIV

V

OUT

V

OUT

500mV/DIV

V

OUT

500mV/DIV

3784 G05

3784 G06

V

= 12V

200µs/DIV

V

= 12V

200µs/DIV

IN

OUT

IN

OUT

= 24V

3784 G04

LOAD STEP FROM 100mA TO 5A

FIGURE 10 CIRCUIT

LOAD STEP FROM 100mA TO 5A

FIGURE 10 CIRCUIT

V

= 12V

200µs/DIV

IN

OUT

= 24V

LOAD STEP FROM 100mA TO 5A

FIGURE 10 CIRCUIT

Regulated Feedback Voltage

vs Temperature

Inductor Currents at Light Load

Soft Start-Up

1.212

1.209

1.206

FORCED

CONTINUOUS

MODE

1.203

1.200

1.197

1.194

1.191

V

OUT

Burst Mode

OPERATION

5A/DIV

PULSE-

SKIPPING

MODE

5V/DIV

0V

1.188

3784 G07

3784 G08

V

LOAD

= 12V

5µs/DIV

V

= 12V

2ms/DIV

–60 –35 –10 15 40 65 90 115 140

TEMPERATURE (°C)

IN

OUT

= 24V

OUT

3784 G09

I

= 200µA

FIGURE 10 CIRCUIT

3784fb

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For more information www.linear.com/LTC3784

LTC3784

Typical perForMance characTerisTics

T_A= 25°C unless otherwise noted.

Soft-Start Pull-Up Current

vs Temperature

Shutdown Current vs Temperature

Shutdown Current vs Input Voltage

11.0

10.5

10.0

9.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

12.5

10.0

7.5

5.0

2.5

0

V

= 12V

V

IN

= 12V

IN

9.0

–60

–35 –10

40 65 90 115 140

TEMPERATURE (°C)

–60 –35 –10 15 40 65 90 115 140

TEMPERATURE (°C)

5

10 15 20 25 30 35 40 45 50 55 60 65

15

INPUT VOLTAGE (V)

3784 G10

3784 G11

3784 G12

Undervoltage Lockout Threshold

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

Quiescent Current vs Temperature

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

3.4

50

45

40

35

30

25

20

15

10

1.40

1.35

1.30

1.25

1.20

1.15

1.10

V

= 12V

IN

FB

= 1.25V

RUN = GND

INTV RISING

CC

RUN RISING

INTV FALLING

CC

RUN FALLING

–35 –10

40 65 90 115 140

–35 –10

40 65 90 115 140

15

TEMPERATURE (°C)

–60

15

–60

–60 –35 –10 15 40 65 90 115 140

TEMPERATURE (°C)

3784 G15

3784 G14

3784 G13

EXTV_CCSwitchover and INTV_CC

Voltages vs Temperature

INTV_CCLine Regulation

INTV_CCvs INTV_CCLoad Current

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

5.50

5.45

5.40

5.35

5.30

5.25

5.20

5.15

5.10

5.05

5.00

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

4.4

4.2

4.0

V

= 12V

IN

EXTV = 0V

INTV

CC

EXTV RISING

CC

EXTV = 6V

CC

EXTV FALLING

CC

40 60 80 100 120 200

140 160 180

0

20

0

5 10 15 20 25 30 35 40 45 50 55 60 65

INPUT VOLTAGE (V)

–35 –10

–60

15

40 65 90 115 140

INTV LOAD CURRENT (mA)

TEMPERATURE (°C)

CC

3784 G17

3784 G18

3784 G16

3784fb

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For more information www.linear.com/LTC3784

LTC3784

Typical perForMance characTerisTics

T_A= 25°C unless otherwise noted.

Oscillator Frequency

vs Temperature

Oscillator Frequency

vs Input Voltage

Maximum Current Sense

Threshold vs I_THVoltage

600

550

500

450

400

350

300

360

358

356

354

352

350

348

346

344

342

340

120

100

80

FREQ = GND

FREQ = INTV

CC

PULSE-SKIPPING MODE

Burst Mode

OPERATION

60

40

20

I

= GND

LIM

0

I

= FLOAT

LIM

I

= INTV

CC

FREQ = GND

–20

–40

–60

FORCED CONTINUOUS MODE

0.8

VOLTAGE (V)

1.2 1.4

0

0.2 0.4 0.6

1.0

–35 –10

40 65 90 115 140

5

10 20 25 30 35 40 45 50 55 60 65

15

–60

15

TEMPERATURE (°C)

INPUT VOLTAGE (V)

I

TH

3784 G20

3784 G21

3784 G19

SENSE Pin Input Current

vs Temperature

SENSE Pin Input Current

vs I_THVoltage

SENSE Pin Input Current

vs V_SENSEVoltage

260

240

220

200

180

160

140

120

100

80

260

240

220

200

180

160

140

120

100

80

260

240

220

200

180

160

140

120

100

80

V

LIM

= 12V

V

= 12V

SENSE

+

SENSE

I

= INTV

CC

I

= INTV

CC

SENSE PIN

LIM

I

= FLOAT

+

SENSE PIN

I

= FLOAT

= GND

I

= FLOAT

= GND

LIM

I

+

SENSE PIN

I

LIM

60

40

20

0

60

40

20

0

60

40

20

0

I

= INTV

CC

= FLOAT

= GND

LIM

I

= INTV

CC

= FLOAT

= GND

LIM

–

SENSE PIN

–35 –10

40 65 90 115 140

TEMPERATURE (°C)

2

3

–60

15

0

1

I

1.5

2.5

5 10 15 20 25 30 35 40 45 50 55 60 65

0.5

VOLTAGE (V)

V

COMMON MODE VOLTAGE (V)

TH

SENSE

3784 G22

3784 G23

3784 G24

Maximum Current Sense

Threshold vs Duty Cycle

Charge Pump Charging Current

vs Operating Frequency

Charge Pump Charging Current

vs Switch Voltage

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

120

100

80

60

40

20

0

FREQ = GND

T = –60°C

I

= INTV

CC

LIM

FREQ = INTV

CC

T = –45°C

T = 25°C

I

= FLOAT

= GND

LIM

I

T = 130°C

T = 155°C

LIM

20 30 40 50 60

100

70 80 90

0

10

50 150 250 350 450 550 650 750

OPERATING FREQUENCY (kHz)

5

15

25

35

45

55

65

DUTY CYCLE (%)

SWITCH VOLTAGE (V)

3784 G26

3784 G27

3784 G25

3784fb

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For more information www.linear.com/LTC3784

LTC3784

pin FuncTions ^(QFN/SSOP)

FREQ (Pin ±/Pin 4): Frequency Control Pin for the Internal

SGND (Pin 5/Pin 8): Signal Ground. All small-signal

components and compensation components should

connect to this ground, which in turn connects to PGND

at a single point.

VCO. Connecting the pin to GND forces the VCO to a fixed

low frequency of 350kHz. Connecting the pin to INTV

CC

forces the VCO to a fixed high frequency of 535kHz. The

frequency can be programmed from 50kHz to 900kHz

by connecting a resistor from the FREQ pin to GND. The

resistor and an internal 20μA source current create a volt-

age used by the internal oscillator to set the frequency.

Alternatively, this pin can be driven with a DC voltage to

vary the frequency of the internal oscillator.

RUN (Pin 6/Pin 9): Run Control Input. Forcing this pin

below 1.28V shuts down the controller. Forcing this pin

below 0.7V shuts down the entire LTC3784, reducing

quiescent current to approximately 4µA. An external

resistor divider connected to V can set the threshold

IN

for converter operation. Once running, a 4.5µA current is

sourced from the RUN pin allowing the user to program

hysteresis using the resistor values.

PHASMD (Pin 2/Pin 5): This pin can be floated, tied to

SGND, ortiedtoINTV toprogramthephaserelationship

CC

between the rising edges of BG1 and BG2, as well as the

SS (Pin 7/Pin ±0): Output Soft-Start Input. A capacitor to

ground at this pin sets the ramp rate of the output voltage

during start-up.

phase relationship between BG1 and CLKOUT.

CLKOUT (Pin 3/Pin 6): A Digital Output Used for Daisy-

chainingMultipleLTC3784ICsinMultiphaseSystems.The

PHASMDpinvoltagecontrolstherelationshipbetweenBG1

–

SENSE2 , SENSE± (Pin 8, Pin 28/Pin ±±, Pin 3): Nega-

tive Current Sense Comparator Input. The (–) input to the

current comparator is normally connected to the negative

terminal of a current sense resistor connected in series

with the inductor.

and CLKOUT. This pin swings between SGND and INTV .

CC

PLLIN/MODE (Pin 4/Pin 7): External Synchronization

Input to Phase Detector and Forced Continuous Mode

Input. When an external clock is applied to this pin, the

phase-locked loop will force the rising edge of BG1 to be

synchronized with the rising edge of the external clock.

When an external clock is applied to this pin, the OVMODE

pinisusedtodeterminehowtheLTC3784operatesatlight

load. When not synchronizing to an external clock, this

input determines how the LTC3784 operates at light loads.

Pulling this pin to ground selects Burst Mode operation.

An internal 100k resistor to ground also invokes Burst

Mode operation when the pin is floated. Tying this pin

+

SENSE2 , SENSE± (Pin 9, Pin 27/Pin ±2, Pin 2): Posi-

tive Current Sense Comparator Input. The (+) input to the

current comparator is normally connected to the positive

terminalofacurrentsenseresistor.Thecurrentsenseresis-

tor is normally placed at the input of the boost controller in

serieswiththeinductor.Thispinalsosuppliespowertothe

current comparator. The common mode voltage range on

+

–

SENSE and SENSE pins is 2.3V to 60V (65V abs max).

VFB (Pin ±0/Pin ±3): Error Amplifier Feedback Input. This

pin receives the remotely sensed feedback voltage from

an external resistive divider connected across the output.

to INTV forces continuous inductor current operation.

CC

Tying this pin to a voltage greater than 1.2V and less than

INTV – 1.3V selects pulse-skipping operation. This can

CC

ITH (Pin ±±/Pin ±4): Current Control Threshold and Error

AmplifierCompensationPoint.Thevoltageonthispinsets

the current trip threshold.

be done by adding a 100k resistor between the PLLIN/

MODE pin and INTV .

CC

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For more information www.linear.com/LTC3784

LTC3784

pin FuncTions ^(QFN/SSOP)

OVMODE (Pin ±2/Pin ±5): Overvoltage Mode Selection

PGND (Pin ±9/Pin 22): Driver Power Ground. Connects

Input. This pin is used to select how the LTC3784 operates

to the sources of bottom (main) N-channel MOSFETs and

when the output feedback voltage (V ) is overvoltage

the (–) terminal(s) of C and C

.

FB

IN

OUT

(>110% of its normal regulated point of 1.2V). It is also

used to determine the light-load mode of operation when

the LTC3784 is synchronized to an external clock through

the PLLIN/MODE pin.

BG2, BG± (Pin ±6, Pin 2±/Pin ±9, Pin 24): Bottom Gate.

Connect to the gate of the main N-channel MOSFET.

INTV (Pin ±7/Pin 20): Output of Internal 5.4V LDO.

CC

Power supply for control circuits and gate drivers. De-

couple this pin to GND with a minimum 4.7μF low ESR

ceramic capacitor.

WhenOVMODEistiedtoground,overvoltageprotectionis

enabled and the top MOSFET gates (TG1, TG2) are turned

on continuously until the overvoltage condition is cleared.

When OVMODE is grounded, the LTC3784 operates in

forced continuous mode when synchronized. There is an

internal weak pull-down resistor that pulls the OVMODE

pin to ground when it is left floating.

EXTV (Pin±8/Pin2±):ExternalPowerInputtoaninternal

CC

LDOConnectedtoINTV .ThisLDOsuppliesINTV power,

CC

bypassing the internal LDO powered from V

whenever

BIAS

EXTV is higher than 4.8V. See EXTV Connection in the

CC

Applications Information section. Do not float or exceed

WhenOVMODEistiedtoINTV ,overvoltageprotectionis

CC

14V on this pin. Connect to ground if not used.

disabledandTG1/TG2arenotforcedonduringanovervolt-

age event. Instead, the state of TG1/TG2 is determined by

themodeofoperationselectedbythePLLIN/MODEpinand

the inductor current. See the Operation section for more

VBIAS (Pin 20/Pin 23): Main Supply Pin. It is normally

tied to the input supply V or to the output of the boost

IN

converter. A bypass capacitor should be tied between this

pin and the signal ground pin. The operating voltage range

on this pin is 4.5V to 60V (65V abs max).

details. When OVMODE is tied to INTV , the LTC3784

CC

operates in pulse-skipping mode when synchronized.

PGOOD(Pin25/Pin28):PowerGoodIndicator.Open-drain

logic output that is pulled to ground when the output volt-

age is more than 10 % away from the regulated output

voltage. To avoid false trips the output voltage must be

outside the range for 45μs before this output is activated.

SW2, SW± (Pin ±3, Pin 24/Pin ±6, Pin 27): Switch Node.

Connect to the source of the synchronous N-channel

MOSFET, the drain of the main N-channel MOSFET and

the inductor.

TG2, TG± (Pin ±4, Pin 23/Pin ±7, Pin 26): Top Gate. Con-

nect to the gate of the synchronous N-channel MOSFET.

ILIM (Pin 26/Pin ±): Current Comparator Sense Voltage

Range Input. This pin is used to set the peak current sense

voltageinthecurrentcomparator.ConnectthispintoSGND,

BOOST2, BOOST± (Pin ±5, Pin 22/Pin ±8, Pin 25): Float-

ingpowersupplyforthesynchronousN-channelMOSFET.

Bypass to SW with a capacitor and supply with a Schottky

leave floating or connect to INTV to set the peak current

CC

sense voltage to 50mV, 75mV or 100mV, respectively.

diode connected to INTV .

CC

GND (Exposed Pad Pin 29) UFD Package: Ground. Must

besolderedtoPCBgroundforratedthermalperformance.

3784fb

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For more information www.linear.com/LTC3784

LTC3784

block DiagraM

INTV

CC

D

INTV

CC

DUPLICATE FOR SECOND CONTROLLER CHANNEL

S

BOOST

TG

B

CLKOUT

Q

R

C

B

PHASMD

SHDN

SWITCHING

LOGIC

V

OUT

SW

AND

20µA

FREQ

CHARGE

PUMP

INTV

CC

C

OUT

CLK2

CLK1

BG

VCO

+

–

0.425V

–

SLEEP

PGND

L

+

PFD

I

REV

CMP

+

–

+

–

2mV

SENSE

OVMODE

2.8V

0.7V

R

SENSE

5M

+

PLLIN/

MODE

SLOPE COMP

SENS LO

V

SYNC

DET

IN

C

+

IN

100k

–

2.3V

ILIM

VFB

CURRENT

LIMIT

–

+

1.2V

EA

VBIAS

EXTV

SS

SHDN

+

–

CC

OV

1.32V

5.4V

LDO

5.4V

LDO

+

–

C

ITH

0.5µA/

4.5µA

EN

3.8V

R

C

PGOOD

C2

+

–

1.32V

10µA

SS

11V

–

4.8V

INTV

CC

SGND

VFB

+

–

SENS

LO

SHDN

RUN

1.08V

3784 BD

C

SS

3784fb

10

For more information www.linear.com/LTC3784

LTC3784

operaTion

Main Control Loop

internal circuits, including the INTV LDOs. In this state,

CC

the LTC3784 draws only 4μA of quiescent current.

The LTC3784 uses a constant-frequency, current mode

step-up architecture with the two controller channels

operating out of phase. During normal operation, each

external bottom MOSFET is turned on when the clock for

that channel sets the RS latch, and is turned off when the

main current comparator, ICMP, resets the RS latch. The

peak inductor current at which ICMP trips and resets the

latch is controlled by the voltage on the ITH pin, which is

the output of the error amplifier EA. The error amplifier

compares the output voltage feedback signal at the VFB

pin (which is generated with an external resistor divider

NOTE:Donotapplyaheavyloadforanextendedtimewhile

the chip is in shutdown. The top MOSFETs are turned off

duringshutdownandtheoutputloadmaycauseexcessive

dissipation in the body diodes.

The RUN pin may be externally pulled up or driven directly

by logic. When driving the RUN pin with a low impedance

source, do not exceed the absolute maximum rating of

8V. The RUN pin has an internal 11V voltage clamp that

allows the RUN pin to be connected through a resistor to

a higher voltage (for example, V ), as long as the maxi-

connected across the output voltage, V , to ground), to

IN

OUT

mum current into the RUN pin does not exceed 100μA.

theinternal1.200Vreferencevoltage. Inaboostconverter,

the required inductor current is determined by the load

An external resistor divider connected to V can set the

IN

threshold for converter operation. Once running, a 4.5μA

current is sourced from the RUN pin allowing the user to

program hysteresis using the resistor values.

current, V and V . When the load current increases,

IN

OUT

it causes a slight decrease in VFB relative to the reference,

which causes the EA to increase the ITH voltage until the

averageinductorcurrentineachchannelmatchesthenew

requirement based on the new load current.

The start-up of the controller’s output voltage V

is

OUT

controlled by the voltage on the SS pin. When the voltage

on the SS pin is less than the 1.2V internal reference, the

LTC3784 regulates the VFB voltage to the SS pin voltage

instead of the 1.2V reference. This allows the SS pin to

be used to program a soft-start by connecting an external

capacitor from the SS pin to SGND. An internal 10μA

pull-up current charges this capacitor creating a voltage

ramp on the SS pin. As the SS voltage rises linearly from

After the bottom MOSFET is turned off each cycle, the

top MOSFET is turned on until either the inductor current

starts to reverse, as indicated by the current comparator,

IREV, or the beginning of the next clock cycle.

INTV /EXTV Power

CC

Power for the top and bottom MOSFET drivers and most

0V to 1.2V (and beyond up to INTV ), the output voltage

other internal circuitry is derived from the INTV pin.

CC

When the EXTV pin is tied to a voltage less than 4.8V,

rises smoothly to its final value.

CC

the VBIAS LDO (low dropout linear regulator) supplies

Light Load Current Operation—Burst Mode Operation,

Pulse-Skipping or Continuous Conduction

(PLLIN/MODE Pin)

5.4V from VBIAS to INTV . If EXTV is taken above

CC

4.8V, the VBIAS LDO is turned off and an EXTV LDO is

CC

turned on. Once enabled, the EXTV LDO supplies 5.4V

CC

from EXTV to INTV . Using the EXTV pin allows the

CC

TheLTC3784canbeenabledtoenterhighefficiencyBurst

Mode operation, constant-frequency, pulse-skipping

mode or forced continuous conduction mode at low

load currents. To select Burst Mode operation, tie the

PLLIN/MODE pin to ground (e.g., SGND). To select

forced continuous operation, tie the PLLIN/MODE pin to

INTV power to be derived from an external source, thus

CC

removing the power dissipation of the VBIAS LDO.

Shutdown and Start-Up (RUN and SS Pins)

The two internal controllers of the LTC3784 can be shut

down using the RUN pin. Pulling this pin below 1.28V

shuts down the main control loops for both phases. Pull-

ing this pin below 0.7V disables both channels and most

INTV . To select pulse-skipping mode, tie the PLLIN/

CC

MODE pin to a DC voltage greater than 1.2V and less

than INTV – 1.3V.

CC

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For more information www.linear.com/LTC3784

LTC3784

operaTion

When the controller is enabled for Burst Mode opera-

tion, the minimum peak current in the inductor is set to

approximately 30% of the maximum sense voltage even

though the voltage on the ITH pin indicates a lower value.

If the average inductor current is higher than the required

current, the error amplifier EA will decrease the voltage

on the ITH pin. When the ITH voltage drops below 0.425V,

the internal sleep signal goes high (enabling sleep mode)

and both external MOSFETs are turned off.

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference as compared to Burst Mode

operation. It provides higher low current efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

In sleep mode much of the internal circuitry is turned off

and the LTC3784 draws only 28μA of quiescent current.

In sleep mode the load current is supplied by the output

capacitor. Astheoutput voltagedecreases, theEA’s output

beginstorise. Whentheoutputvoltagedropsenough, the

sleep signal goes low and the controller resumes normal

operation by turning on the bottom external MOSFET on

the next cycle of the internal oscillator.

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3784’s controllers can

be selected using the FREQ pin.

When the controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator (IREV) turns off the top external

MOSFET just before the inductor current reaches zero,

preventing it from reversing and going negative. Thus,

thecontrolleroperatesindiscontinuouscurrentoperation.

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTV ,orprogrammedthroughanexternalresistor.Tying

CC

FREQ to SGND selects 350kHz while tying FREQ to INTV

CC

selects535kHz.PlacingaresistorbetweenFREQandSGND

allows the frequency to be programmed between 50kHz

and 900kHz, as shown in Figure 7.

In forced continuous operation or when clocked by an

external clock source to use the phase-locked loop (see

theFrequencySelectionandPhase-LockedLoopsection),

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined by the voltage on the ITH pin, just as

in normal operation. In this mode, the efficiency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantages of lower output

voltage ripple and less interference to audio circuitry, as

it maintains constant-frequency operation independent

of load current.

A phase-locked loop (PLL) is available on the LTC3784

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3784’s phase detector adjusts the voltage (through

an internal lowpass filter) of the VCO input to align the

turn-on of the first controller’s external bottom MOSFET

to the rising edge of the synchronizing signal. Thus, the

turn-onofthesecondcontroller’sexternalbottomMOSFET

is 180 or 240 degrees out-of-phase to the rising edge of

theexternalclocksource.Whensynchronized,theLTC3784

will operate in forced continuous mode of operation if the

OVMODE pin is grounded. If the OVMODE pin is tied to

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode,theLTC3784operatesinPWMpulse-skippingmode

at light loads. In this mode, constant-frequency operation

is maintained down to approximately 1% of designed

maximum output current. At very light loads, the current

comparator ICMP may remain tripped for several cycles

and force the external bottom MOSFET to stay off for

INTV , the LTC3784 will operate in pulse-skipping mode

CC

of operation when synchronized.

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

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For more information www.linear.com/LTC3784

LTC3784

operaTion

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of BG1. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

inductor current and V voltage. In forced continuous

IN

mode, the control loop works to keep the top MOSFET on

continuouslyonceV risesaboveV .Theinternalcharge

IN

OUT

pump delivers current to the boost capacitor to maintain

a sufficiently high TG voltage. The amount of current the

charge pump can deliver is characterized by two curves

in the Typical Performance Characteristics section.

The typical capture range of the LTC3784’s PLL is from

approximately 55kHz to 1MHz, and is guaranteed to lock

to an external clock source whose frequency is between

75kHz and 850kHz.

In pulse-skipping mode, if V is between 100% and

IN

110% of the regulated V

voltage, TG turns on if the

OUT

inductor current rises above a certain threshold and turns

off if the inductor current falls below this threshold. This

threshold current is set to approximately 6%, 4% or

3% of the maximum ILIM current when the ILIM pin is

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.2V (falling). The recommended

maximumamplitudeforlowlevelandminimumamplitude

forhighlevelofexternalclockare0Vand2.5V,respectively.

grounded, floating or tied to INTV , respectively. If the

CC

controller is programmed to Burst Mode operation under

PolyPhase Applications (CLKOUT and PHASMD Pins)

this same V window, then TG remains off regardless of

IN

the inductor current.

The LTC3784 features two pins, CLKOUT and PHASMD,

that allow other controller ICs to be daisy-chained with

the LTC3784 in PolyPhase applications. The clock output

signal on the CLKOUT pin can be used to synchronize

additional power stages in a multiphase power supply

solution feeding a single, high current output or multiple

separate outputs. The PHASMD pin is used to adjust the

phase of the CLKOUT signal as well as the relative phases

between the two internal controllers, as summarized in

Table 1. The phases are calculated relative to the zero

degrees phase being defined as the rising edge of the

bottom gate driver output of controller 1 (BG1). Depend-

ing on the phase selection, a PolyPhase application with

multiple LTC3784s can be configured for 2-, 3-, 4- , 6- and

12-phase operation.

If the OVMODE pin is grounded and V rises above 110%

IN

of the regulated V

voltage in any mode, the controller

OUT

turns on TG regardless of the inductor current. In Burst

Mode operation, however, the internal charge pump turns

off if the chip is asleep. With the charge pump off, there

would be nothing to prevent the boost capacitor from

discharging, resultinginaninsufficientTGvoltageneeded

to keep the top MOSFET completely on. To prevent exces-

sive power dissipation across the body diode of the top

MOSFET in this situation, the chip can be switched over

to forced continuous mode to enable the charge pump;

a Schottky diode can also be placed in parallel with the

top MOSFET.

Power Good

Table ±.

V

CONTROLLER 2 PHASE (°)

CLKOUT PHASE (°)

PHASMD

The PGOOD pin is connected to an open drain of an

internal N-channel MOSFET. The MOSFET turns on and

pulls the PGOOD pin low when the VFB pin voltage is not

within 10% of the 1.2V reference voltage. The PGOOD

pin is also pulled low when the corresponding RUN pin

is low (shut down). When the VFB pin voltage is within

the 10% requirement, the MOSFET is turned off and the

pin is allowed to be pulled up by an external resistor to a

source of up to 6V (abs max).

GND

180

240

60

90

Floating

INTV

120

CC

CLKOUT is disabled when the controller is in shutdown

or in sleep mode.

Operation When V > Regulated V

IN

OUT

WhenV risesabovetheregulatedV voltage,theboost

controller can behave differently depending on the mode,

IN

OUT

3784fb

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For more information www.linear.com/LTC3784

LTC3784

operaTion

Overvoltage Mode Selection

Note however that in Burst Mode operation, the LTC3784

isinsleepduringanovervoltagecondition, whichdisables

theinternaloscillatorandBOOST-SWchargepump.Sothe

BOOST-SW voltage may discharge (due to leakage) if the

overvoltage conditions persists indefinitely. If BOOST-SW

discharges, then by definition TG would turn off.

The OVMODE pin is used to select how the LTC3784

operates during an overvoltage event, defined as when

the output feedback voltage (V ) is greater than 110%

of its normal regulated point of 1.2V. It is also used to

determine the light-load mode of operation when the

LTC3784 is synchronized to an external clock through the

PLLIN/MODE pin.

FB

When OVMODE is grounded or left floating, the LTC3784

operates in forced continuous mode when synchronized.

The OVMODE pin is a logic input that should normally be

OVMODEshouldbetiedtogroundorleftfloatingincircuits,

such as automotive applications, where the input voltage

can often be above the regulated output voltage and it is

desirable to turn on TG1/TG2 to “pass through” the input

voltage to the output.

tied to INTV or grounded. Alternatively, the pin can be

CC

left floating, which allow a weak internal resistor to pull

it down to ground.

OVMODE = INTV : An overvoltage event causes the error

CC

amplifier to pull the ITH pin low. In Burst Mode operation,

this causes the LTC3784 to go to sleep and TG1/TG2 and

BG1/BG2areheldoff.Inpulse-skippingmode,BG1/BG2are

held off and TG1/TG2 will turn on if the inductor current is

positive. In forced continuous mode, TG1/TG2 (and BG1/

BG2)willswitchonandoffastheLTC3784willregulatethe

inductor current to a negative peak value (corresponding

to ITH = 0V) to discharge the output.

Operation at Low SENSE Pin Common Mode Voltage

ThecurrentcomparatorintheLTC3784ispowereddirectly

+

from the SENSE pin. This enables the common mode

+

–

voltage of the SENSE and SENSE pins to operate at as

lowas2.3V, whichisbelowtheUVLOthreshold. Thefigure

on the first page shows a typical application in which the

controller’s VBIAS is powered from V

while the V

OUT

IN

+

supply can go as low as 2.3V. If the voltage on SENSE

drops below 2.3V, the SS pin will be held low. When the

SENSE voltage returns to the normal operating range, the

SS pin will be released, initiating a new soft-start cycle.

When OVMODE is tied to INTV , the LTC3784 operates

CC

in pulse-skipping mode when synchronized.

In summary, with OVMODE = INTV , the inductor cur-

CC

rent is not allowed to go negative (reverse from output to

input) except in forced continuous mode, where it does

reversecurrentbutinacontrolledmannerwitharegulated

BOOST Supply Refresh and Internal Charge Pump

EachtopMOSFETdriverisbiasedfromthefloatingbootstrap

negative peak current. OVMODE should be tied to INTV

CC

capacitor, C , which normally recharges during each cycle

B

in applications where the output voltage may sometimes

be above its regulation point (for example, if the output

is a battery or if there are other power supplies driving

the output) and no reverse current flow from output to

input is desired.

through an external diode when the bottom MOSFET turns

on. There are two considerations for keeping the BOOST

supply at the required bias level. During start-up, if the

bottom MOSFET is not turned on within 200μs after UVLO

goes low, the bottom MOSFET will be forced to turn on for

~400ns. This forced refresh generates enough BOOST-SW

voltageto allow the top MOSFET ready to be fullyenhanced

instead of waiting for the initial few cycles to charge up.

Thereisalsoaninternalchargepumpthatkeepstherequired

bias on BOOST. The charge pump always operates in both

forcedcontinuousmodeandpulse-skippingmode.InBurst

Modeoperation,thechargepumpisturnedoffduringsleep

and enabled when the chip wakes up. The internal charge

pump can normally supply a charging current of 55μA.

OVMODE Grounded or Left Floating: When OVMODE is

groundedorleftfloating,overvoltageprotectionisenabled

and the TG1/TG2 are turned on continuously until the

overvoltage condition is cleared, regardless of whether

Burst Mode operation, pulse-skipping mode, or forced

continuous mode is selected by the PLLIN/MODE pin.

This can cause large negative inductor currents to flow

from the output to the input if the output voltage is higher

than the input voltage.

3784fb

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For more information www.linear.com/LTC3784

LTC3784

applicaTions inForMaTion

+

TheTypicalApplicationonthefirstpageisabasicLTC3784

application circuit. The LTC3784 can be configured to use

either inductor DCR (DC resistance) sensing or a discrete

The SENSE pin also provides power to the current com-

parator. It draws ~200μA during normal operation. There

is a small base current of less than 1μA that flows into

–

sense resistor (R

) for current sensing. The choice

SENSE

the SENSE pin. The high impedance SENSE input to the

current comparators allows accurate DCR sensing.

between the two current sensing schemes is largely a

design trade-off between cost, power consumption and

accuracy. DCR sensing is becoming popular because it

does not require current sensing resistors and is more

power-efficient, especially in high current applications.

However, current sensing resistors provide the most

accurate current limits for the controller. Other external

component selection is driven by the load requirement,

Filter components mutual to the sense lines should be

placed close to the LTC3784, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 1). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

programmed current limit unpredictable. If DCR sensing

is used (Figure 2b), sense resistor R1 should be placed

closetotheswitchingnode,topreventnoisefromcoupling

into sensitive small-signal nodes.

and begins with the selection of R

(if R

is used)

SENSE

andinductorvalue.Next,thepowerMOSFETsareselected.

Finally, input and output capacitors are selected. Note

that the two controller channels of the LTC3784 should

be designed with the same components.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

+

–

SENSE and SENSE Pins

+

–

The SENSE and SENSE pins are the inputs to the cur-

rent comparators. The common mode input voltage range

of the current comparators is 2.3V to 60V. The current

sense resistor is normally placed at the input of the boost

controller in series with the inductor.

V

IN

INDUCTOR OR R

3784 F01

SENSE

Figure ±. Sense Lines Placement with

Inductor or Sense Resistor

VBIAS

V

IN

+

SENSE

(OPTIONAL)

C1

R2

DCR

L

–

SENSE

INTV

CC

INDUCTOR

R1

LTC3784

BOOST

TG

V

OUT

SW

BG

SW

BG

OUT

SGND

3784 F02a

3784 F02b

L

DCR

R2

R1 + R2

||

PLACE C1 NEAR SENSE PINS (R1 R2) • C1 =

R

= DCR •

SENSE(EQ)

(2a) Using a Resistor to Sense Current

(2b) Using the Inductor DCR to Sense Current

Figure 2. Two Different Methods of Sensing Current

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Sense Resistor Current Sensing

Inductor DCR Sensing

A typical sensing circuit using a discrete resistor is shown

For applications requiring the highest possible efficiency

at high load currents, the LTC3784 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 2b. The DCR of the inductor can be less than 1mΩ

for high current inductors. In a high current application

requiring such an inductor, conduction loss through a

sense resistor could reduce the efficiency by a few percent

compared to DCR sensing.

in Figure 2a. R

output current.

is chosen based on the required

SENSE

The current comparator has a maximum threshold

V

. When the ILIM pin is grounded, floating or

CC

SENSE(MAX)

tied to INTV , the maximum threshold is set to 50mV,

75mV or 100mV, respectively. The current comparator

threshold sets the peak of the inductor current, yielding

a maximum average inductor current, I

, equal to the

If the external R1||R2 • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external filter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature. Consult

the manufacturers’ data sheets for detailed information.

MAX

peak value less half the peak-to-peak ripple current, ΔI .

L

To calculate the sense resistor value, use the equation:

V_SENSE(MAX)

R_SENSE

=

ΔI_L

I_MAX

+

2

The actual value of I

required output current I

using:

for each channel depends on the

OUT(MAX)

MAX

and can be calculated

I

⎛

⎞ ⎛

⎞

V_OUT

OUT(MAX)

Using the inductor ripple current value from the induct-

or value calculation section, the target sense resistor

value is:

I_MAX

=

•

⎜

⎟ ⎜

⎟

2

V

⎝

⎠ ⎝

⎠

IN

When using the controller in low V and very high voltage

IN

V_SENSE(MAX)

output applications, the maximum inductor current and

correspondingly the maximum output current level will

be reduced due to the internal compensation required to

meet stability criterion for boost regulators operating at

greater than 50% duty factor. A curve is provided in the

Typical Performance Characteristics section to estimate

this reduction in peak inductor current level depending

upon the operating duty factor.

R_SENSE(EQUIV)

=

ΔI_L

I_MAX

+

2

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value for the maximum current sense threshold

(V

).

SENSE(MAX)

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Next, determine the DCR of the inductor. Where provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficient of resistance, which is approximately 0.4%/°C.

Aconservativevalueforthemaximuminductortemperature

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

Inductor Value Calculation

(T

) is 100°C.

L(MAX)

The operating frequency and inductor selection are in-

terrelated in that higher operating frequencies allow the

use of smaller inductor and capacitor values. Why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

of MOSFET gate charge and switching losses. Also, at

higher frequency the duty cycle of body diode conduction

is higher, which results in lower efficiency. In addition to

this basic trade-off, the effect of inductor value on ripple

currentandlowcurrentoperationmustalsobeconsidered.

To scale the maximum inductor DCR to the desired sense

resistor value, use the divider ratio:

R_SENSE(EQUIV)

R_D=

DCR_MAXat T_L(MAX)

C1 is usually selected to be in the range of 0.1μF to 0.47μF.

ThisforcesR1||R2toaround2k, reducingerrorthatmight

–

have been caused by the SENSE pin’s 1μA current.

The equivalent resistance R1|| R2 is scaled to the room

temperature inductance and maximum DCR:

The inductor value has a direct effect on ripple current.

The inductor ripple current ΔI decreases with higher

L

R1||R2=

L

inductance or frequency and increases with higher V :

IN

(DCR at 20°C)•C1

⎛

⎞

V

f•L

V

IN

V_OUT

IN

The sense resistor values are:

ΔI_L=

1−

⎜

⎟

⎝

⎠

R1||R2

R_D

R1•R_D

1−R_D

R1=

; R2 =

Accepting larger values of ΔI allows the use of low

L

inductances, but results in higher output voltage ripple

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at V = 1/2V

and greater core losses. A reasonable starting point for

:

IN

OUT

setting ripple current is ΔI = 0.3(I

ΔI occurs at V = 1/2V .

). The maximum

L

MAX

(V_OUT− V )•V

L

IN

OUT

IN

P

=

LOSS_R1

R1

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

totheextraswitchinglossesincurredthroughR1.However,

25% of the current limit determined by R

. Lower

SENSE

inductor values (higher ΔI ) will cause this to occur at

L

lower load currents, which can cause a dip in efficiency in

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LTC3784

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the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease. Once the value of L is known, an

inductor with low DCR and low core losses should be

selected.

nel takes one half of the total output current, the MOSFET

power dissipations in each channel at maximum output

current are given by:

2

I

⎛

⎞

(V_OUT− V )V

OUT(MAX)

IN

OUT

P_MAIN

=

•

• 1+δ

(

)

⎜

⎟

V²

2

⎝

⎠

IN

Power MOSFET Selection

I_OUT(MAX)

3

• R_DS(ON)+k •V_OUT

• C_MILLER•f

•

Two external power MOSFETs must be selected for each

controller in the LTC3784: one N-channel MOSFET for the

bottom (main) switch, and one N-channel MOSFET for the

top (synchronous) switch.

2•V

IN

2

I

⎛

⎞

V

V_OUT

OUT(MAX)

IN

The peak-to-peak gate drive levels are set by the INTV

voltage. This voltage is typically 5.4V during start-up

CC

P_SYNC

=

•

• 1+δ •R

( )

DS(ON)

⎜

⎟

2

⎝

⎠

(see EXTV pin connection). Consequently, logic-level

threshold MOSFETs must be used in most applications.

CC

where d is the temperature dependency of R

(ap-

DS(ON)

proximately 1Ω). The constant k, which accounts for

the loss caused by reverse recovery current, is inversely

proportional to the gate drive current and has an empirical

value of 1.7.

Pay close attention to the BV

specification for the

DSS

MOSFETs as well; many of the logic level MOSFETs are

limited to 30V or less.

2

Selection criteria for the power MOSFETs include the

BothMOSFETshaveI RlosseswhilethebottomN-channel

on-resistance R

, Miller capacitance C

DS(ON)

, input

MILLER

equation includes an additional term for transition losses,

voltage and maximum output current. Miller capacitance,

which are highest at low input voltages. For high V the

IN

C

, can be approximated from the gate charge curve

MILLER

high current efficiency generally improves with larger

usually provided on the MOSFET manufacturer’s data

MOSFETs, while for low V the transition losses rapidly

IN

increasetothepointthattheuseofahigherR

device

sheet. C is equal to the increase in gate charge

DS(ON)

MILLER

withlowerC

actuallyprovideshigherefficiency.The

along the horizontal axis while the curve is approximately

flat divided by the specified change in VDS. This result

is then multiplied by the ratio of the application applied

VDS to the gate charge curve specified VDS. When the IC

is operating in continuous mode, the duty cycles for the

top and bottom MOSFETs are given by:

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the bottom switch duty factor is low or dur-

ing overvoltage when the synchronous switch is on close

to 100% of the period.

The term (1+ d) is generally given for a MOSFET in the

form of a normalized R

vs Temperature curve, but

DS(ON)

V_OUT− V

IN

Main SwitchDuty Cycle=

d = 0.005/°C can be used as an approximation for low

V_OUT

voltage MOSFETs.

V

V_OUT

IN

Synchronous SwitchDuty Cycle=

IfthemaximumoutputcurrentisI

andeachchan-

OUT(MAX)

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C and C

Selection

The LTC3784 is configured as a 2-phase single output

converter where the outputs of the two channels are

connected together and both channels have the same

duty cycle. With 2-phase operation, the two channels

are operated 180 degrees out-of-phase. This effectively

interleaves the output capacitor current pulses, greatly

reducing the output capacitor ripple current. As a result,

the ESR requirement of the capacitor can be relaxed.

Because the ripple current in the output capacitor is a

squarewave,theripplecurrentrequirementsfortheoutput

capacitor depend on the duty cycle, the number of phases

and the maximum output current. Figure 3 illustrates the

normalized output capacitor ripple current as a function of

duty cycle in a 2-phase configuration. To choose a ripple

current rating for the output capacitor, first establish the

duty cycle range based on the output voltage and range

of input voltage. Referring to Figure 3, choose the worst-

case high normalized ripple current as a percentage of the

maximum load current.

IN

OUT

The input ripple current in a boost converter is relatively

low(comparedwiththeoutputripplecurrent),becausethis

currentiscontinuous.TheinputcapacitorC voltagerating

IN

should comfortably exceed the maximum input voltage.

Although ceramic capacitors can be relatively tolerant of

overvoltage conditions, aluminum electrolytic capacitors

are not. Be sure to characterize the input voltage for any

possible overvoltage transients that could apply excess

stress to the input capacitors.

ThevalueofC isafunctionofthesourceimpedance, and

IN

ingeneral,thehigherthesourceimpedance,thehigherthe

required input capacitance. The required amount of input

capacitance is also greatly affected by the duty cycle. High

output current applications that also experience high duty

cycles can place great demands on the input supply, both

in terms of DC current and ripple current.

Inaboostconverter,theoutputhasadiscontinuouscurrent,

so C

must be capable of reducing the output voltage

OUT

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

ripple.TheeffectsofESR(equivalentseriesresistance)and

the bulk capacitance must be considered when choosing

the right capacitor for a given output ripple voltage. The

steady ripple voltage due to charging and discharging

the bulk capacitance in a single phase boost converter

is given by:

1-PHASE

I_OUT(MAX)•(V_OUT− V

)

IN(MIN)

V_RIPPLE

=

V

2-PHASE

C_OUT•V_OUT•f

0.4 0.5

DUTY CYCLE OR (1-V /V

0.1 0.2 0.3

0.6 0.7 0.8 0.9

where C

is the output filter capacitor.

OUT

)

IN OUT

3784 F03

The steady ripple due to the voltage drop across the ESR

is given by:

Figure 3. Normalized Output Capacitor Ripple

Current (RMS) for a Boost Converter

ΔV

= I

• ESR

ESR

L(MAX)

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LTC3784

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Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefficient.

Capacitors are now available with low ESR and high ripple

current ratings (e.g., OS-CON and POSCAP).

Setting Output Voltage

The LTC3784 output voltage is set by an external feedback

resistordividercarefullyplacedacrosstheoutput,asshown

in Figure 5. The regulated output voltage is determined by:

⎛

⎞

R_B

R_A

V

_OUT=1.2V 1+

⎜

⎟

⎝

⎠

Great care should be taken to route the VFB line away

from noise sources, such as the inductor or the SW line.

Also place the feedback resistor divider close to the VFB

pin and keep the VFB node as small as possible to avoid

noise pickup.

PolyPhase Operation

For output loads that demand high current, multiple

LTC3784s can be cascaded to run out-of-phase to provide

more output current and at the same time to reduce input

andoutputvoltageripple. ThePLLIN/MODEpinallowsthe

LTC3784 to synchronize to the CLKOUT signal of another

LTC3784. The CLKOUT signal can be connected to the

PLLIN/MODE pin of the following LTC3784 stage to line

up both the frequency and the phase of the entire system.

Soft-Start (SS Pin)

The start-up of V

is controlled by the voltage on the

OUT

SS pin. When the voltage on the SS pin is less than the

internal 1.2V reference, the LTC3784 regulates the VFB

pin voltage to the voltage on the SS pin instead of 1.2V.

Tying the PHASMD pin to INTV , SGND or floating

CC

generates a phase difference (between PLLIN/MODE

and CLKOUT) of 240°, 60° or 90°, respectively, and a

phase difference (between CH1 and CH2) of 120°, 180°

or 180°. Figure 4 shows the connections necessary for

3-, 4-, 6- or 12-phase operation. A total of 12 phases can

be cascaded to run simultaneously out-of-phase with

respect to each other.

Soft-startisenabledbysimplyconnectingacapacitorfrom

the SS pin to ground, as shown in Figure 6. An internal

10μA current source charges the capacitor, providing a

linear ramping voltage at the SS pin. The LTC3784 will

regulate the VFB pin (and hence, V ) according to the

OUT

voltage on the SS pin, allowing V

to rise smoothly

OUT

from V to its final regulated value. The total soft-start

IN

time will be approximately:

1.2V

10µA

t

_SS=C_SS•

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0,240

120, CHANNEL 2 NOT USED

PLLIN/MODE CLKOUT

+120

V

PLLIN/MODE CLKOUT

OUT

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

RUN

ITH

RUN

ITH

VFB

INTV

CC

(4a) 3-Phase Operation

0,180

PLLIN/MODE CLKOUT

90,270

PLLIN/MODE CLKOUT

+90

V

OUT

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

RUN

ITH

RUN

ITH

VFB

(4b) 4-Phase Operation

0,180

PLLIN/MODE CLKOUT

60,240

120,300

+60

V

OUT

PLLIN/MODE CLKOUT

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

RUN

ITH

RUN

ITH

RUN

ITH

VFB

(4c) 6-Phase Operation

0,180

PLLIN/MODE CLKOUT

60,240

+60

PLLIN/MODE CLKOUT

120,300

+60

+90

V

PLLIN/MODE CLKOUT

OUT

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

RUN

ITH

RUN

ITH

RUN

ITH

VFB

210,30

PLLIN/MODE CLKOUT

270,90

PLLIN/MODE CLKOUT

330,150

PLLIN/MODE CLKOUT

+60

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

PHASMD

LTC3784

SS

RUN

ITH

RUN

ITH

RUN

ITH

VFB

3784 F04

(4d) 12-Phase Operation

Figure 4. PolyPhase Operation

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LTC3784

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V

exceeded. The INTV current, which is dominated by the

OUT

CC

gate charge current, may be supplied by either the VBIAS

R

B

LTC3784

VFB

LDO or the EXTV LDO. When the voltage on the EXTV

CC

pin is less than 4.8V, the VBIAS LDO is enabled. In this

R

A

case, power dissipation for the IC is highest and is equal

3784 F05

to VBIAS • I

. The gate charge current is dependent

INTVCC

on operating frequency, as discussed in the Efficiency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 2 of the

Electrical Characteristics. For example, at 70°C ambient

Figure 5. Setting Output Voltage

LTC3784

SS

temperature, theLTC3784INTV currentislimitedtoless

CC

than 21mA in the QFN package from a 60V VBIAS supply

C

SS

when not using the EXTV supply:

CC

SGND

3784 F06

T = 70°C + (21mA)(60V)(43°C/W) = 125°C

J

Figure 6. Using the SS Pin to Program Soft-Start

In an SSOP package, the INTV current is limited to

CC

less than 11mA from a 60V supply when not using the

EXTV supply:

CC

INTV Regulators

CC

T = 70°C + (11mA)(60V)(80°C/W) = 125°C

J

The LTC3784 features two separate internal P-channel

low dropout linear regulators (LDO) that supply power at

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (PLLIN/MODE

= INTV ) at maximum V .

the INTV pin from either the VBIAS supply pin or the

CC

EXTV pin depending on the connection of the EXTV

CC

pin. INTV powers the gate drivers and much of the

CC

IN

CC

LTC3784’s internal circuitry. The VBIAS LDO and the

When the voltage applied to EXTV rises above 4.8V, the

CC

EXTV LDO regulate INTV to 5.4V. Each of these can

CC

V LDO is turned off and the EXTV LDO is enabled. The

IN

CC

supplyatleast40mAandmustbebypassedtogroundwith

a minimum of 4.7μF ceramic capacitor. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers and to prevent interaction

between the channels.

EXTV LDO remains on as long as the voltage applied to

CC

EXTV remains above 4.55V. The EXTV LDO attempts

CC

to regulate the INTV voltage to 5.4V, so while EXTV

CC

is less than 5.4V, the LDO is in dropout and the INTV

voltage is approximately equal to EXTV . When EXTV

CC

is greater than 5.4V, up to an absolute maximum of 14V,

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3784 to be

INTV is regulated to 5.4V.

CC

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LTC3784

applicaTions inForMaTion

Significant thermal gains can be realized by powering

Each of the topside MOSFET drivers includes an internal

chargepumpthatdeliverscurrenttothebootstrapcapaci-

tor from the BOOST pin. This charge current maintains

the bias voltage required to keep the top MOSFET on

continuously during dropout/overvoltage conditions. The

Schottky/silicon diodes selected for the topside drivers

shouldhaveareverseleakagelessthantheavailableoutput

current the charge pump can supply. Curves displaying

the available charge pump current under different operat-

ing conditions can be found in the Typical Performance

Characteristics section.

INTV from an external supply. Tying the EXTV pin

CC

to a 5V supply reduces the junction temperature in the

previous example from 125°C to 77°C in a QFN package:

T = 70°C + (32mA)(5V)(43°C/W) = 77°C

J

and from 125°C to 74°C in an SSOP package:

T = 70°C + (15mA)(5V)(80°C/W) = 77°C

J

The following list summarizes possible connections for

EXTV :

CC

EXTV Grounded.ThiswillcauseINTV tobepowered

CC

A leaky diode D in the boost converter can not only

B

fromtheinternal5.4Vregulatorresultinginanefficiency

prevent the top MOSFET from fully turning on but it can

penalty at high input voltages.

also completely discharge the bootstrap capacitor C and

B

create a current path from the input voltage to the BOOST

EXTV Connected to an External Supply. If an external

CC

pin to INTV . This can cause INTV to rise if the diode

supply is available in the 5V to 14V range, it may be

CC

leakage exceeds the current consumption on INTV .

used to provide power. Ensure that EXTV is always

CC

This is particularly a concern in Burst Mode operation

lower than or equal to VBIAS.

where the load on INTV can be very small. The external

CC

Topside MOSFET Driver Supply (C , D )

Schottky or silicon diode should be carefully chosen such

B

that INTV never gets charged up much higher than its

CC

External bootstrap capacitors C connected to the BOOST

B

normal regulation voltage.

pins supply the gate drive voltages for the topside MOS-

FETs. CapacitorC intheBlockDiagramischargedthough

B

Fault Conditions: Overtemperature Protection

external diode D from INTV when the SW pin is low.

B

CC

At higher temperatures, or in cases where the internal

power dissipation causes excessive self heating on-chip

When one of the topside MOSFETs is to be turned on, the

driver places the C voltage across the gate and source

B

(such as an INTV short to ground), the overtemperature

of the desired MOSFET. This enhances the MOSFET and

CC

shutdown circuitry will shut down the LTC3784. When the

turns on the topside switch. The switch node voltage, SW,

junction temperature exceeds approximately 170°C, the

rises to V

and the BOOST pin follows. With the topside

OUT

overtemperaturecircuitrydisablestheINTV LDO,causing

MOSFETon, theboostvoltageisabovetheoutputvoltage:

CC

the INTV supply to collapse and effectively shut down

V

B

= V

+ V

. The value of the boost capacitor

CC

BOOST

OUT

INTVCC

the entire LTC3784 chip. Once the junction temperature

C needstobe100timesthatofthetotalinputcapacitance

dropsbacktoapproximately155°C, theINTV LDOturns

of the topside MOSFET(s). The reverse breakdown of the

CC

back on. Long term overstress (T > 125°C) should be

external Schottky diode must be greater than V

.

J

OUT(MAX)

avoided as it can degrade the performance or shorten

The external diode D can be a Schottky diode or silicon

B

the life of the part.

diode,butineithercaseitshouldhavelowleakageandfast

recovery. Paycloseattentiontothereverseleakageathigh

temperatures, where it generally increases substantially.

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Since the shutdown may occur at full load, beware that

the load current will result in high power dissipation in the

body diodes of the top MOSFETs. In this case, the PGOOD

output may be used to turn the system load off.

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

Phase-Locked Loop and Frequency Synchronization

C

, holds the voltage at the VCO input.

LP

The LTC3784 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the bottom MOSFET of channel 1 to be locked

to the rising edge of an external clock signal applied to

the PLLIN/MODE pin. The turn-on of channel 2’s bottom

MOSFETisthus180degreesout-of-phasewiththeexternal

clock. The phase detector is an edge-sensitive digital type

thatprovideszerodegreesphaseshiftbetweentheexternal

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

Typically,theexternalclock(onthePLLIN/MODEpin)input

highthresholdis1.6V,whiletheinputlowthresholdis1.2V.

Note that the LTC3784 can only be synchronized to an

external clock whose frequency is within range of the

LTC3784’s internal VCO, which is nominally 55kHz to

1MHz.Thisisguaranteedtobebetween75kHzand850kHz.

RapidphaselockingcanbeachievedbyusingtheFREQpin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

If the external clock frequency is greater than the internal

oscillator’sfrequency,f ,thencurrentissourcedcontinu-

OSC

ously from the phase detector output, pulling up the VCO

input. When the external clock frequency is less than f

,

OSC

current is sunk continuously, pulling down the VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

1000

900

800

700

600

500

400

300

200

100

0

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

3784 F07

Figure 7. Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

3784fb

24

For more information www.linear.com/LTC3784

LTC3784

applicaTions inForMaTion

Table 2 summarizes the different states in which the FREQ

Although all dissipative elements in the circuit produce

losses, five main sources usually account for most of the

pin can be used.

losses in LTC3784 circuits: 1) IC VBIAS current, 2) INTV

CC

Table 2.

2

regulatorcurrent,3)I Rlosses,4)bottomMOSFETtransi-

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

tion losses, 5) body diode conduction losses.

0V

1. The VBIAS current is the DC supply current given in the

ElectricalCharacteristicstable,whichexcludesMOSFET

driver and control currents. VBIAS current typically

results in a small (<0.1%) loss.

INTV

DC Voltage

535kHz

CC

Resistor

DC Voltage

50kHz to 900kHz

Any of the Above

External Clock

Phase Locked to

External Clock

2. INTV current is the sum of the MOSFET driver and

CC

Minimum On-Time Considerations

Minimum on-time, t , is the smallest time duration

that the LTC3784 is capable of turning on the bottom

MOSFET. It is determined by internal timing delays and

the gate charge required to turn on the top MOSFET. Low

duty cycle applications may approach this minimum on-

time limit.

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

ON(MIN)

from INTV to ground. The resulting dQ/dt is a current

CC

out of INTV that is typically much larger than the

CC

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

In forced continuous mode, if the duty cycle falls below

what can be accommodated by the minimum on-time,

the controller will begin to skip cycles but the output will

continuetoberegulated.Morecycleswillbeskippedwhen

the topside and bottom side MOSFETs.

2

3. DC I R losses. These arise from the resistances of the

MOSFETs,sensingresistor,inductorandPCboardtraces

andcausetheefficiencytodropathighoutputcurrents.

V increases. Once V rises above V , the loop keeps

IN

OUT

the top MOSFET continuously on. The minimum on-time

4. Transition losses apply only to the bottom MOSFET(s),

and become significant only when operating at low

inputvoltages.Transitionlossescanbeestimatedfrom:

for the LTC3784 is approximately 110ns.

Efficiency Considerations

3

I_OUT(MAX)

V_OUT

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the greatest improvement. Percent efficiency

can be expressed as:

Transition Loss=(1.7)

•

•C_RSS•f

V

2

IN

5. Body diode conduction losses are more significant at

higherswitchingfrequency. Duringthedeadtime, theloss

in the top MOSFETs is I

• V , where V is around

OUT

DS DS

0.7V. At higher switching frequency, the dead time be-

comes a good percentage of switching cycle and causes

the efficiency to drop.

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc., are the individual losses as a percent-

age of input power.

3784fb

25

For more information www.linear.com/LTC3784

LTC3784

applicaTions inForMaTion

to 80% of full-load current having a rise time of 1μs to

10μs will produce output voltage and ITH pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop.

Other hidden losses, such as copper trace and internal

batteryresistances,canaccountforanadditionalefficiency

degradation in portable systems. It is very important to

includethesesystem-levellossesduringthedesignphase.

Placing a power MOSFET and load resistor directly across

the output capacitor and driving the gate with an ap-

propriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

is why it is better to look at the ITH pin signal which is

in the feedback loop and is the filtered and compensated

control loop response.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ΔI

• ESR, where ESR is the effective

LOAD

series resistance of C . ΔI

also begins to charge or

OUT

LOAD

discharge C , generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

return V

to its steady-state value. During this recovery

OUT

The gain of the loop will be increased by increasing R

C

time V

can be monitored for excessive overshoot or

OUT

and the bandwidth of the loop will be increased by de-

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the ITH pin not only allows

optimization of control loop behavior, but it also provides

a DC coupled and AC filtered closed loop response test

point. The DC step, rise time and settling at this test

point truly reflects the closed loop response. Assuming a

predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The ITH

external components shown in the Figure 10 circuit will

provide an adequate starting point for most applications.

creasing C . If RC is increased by the same factor that C

C

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C

, causing a rapid drop in V

. No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

The ITH series R -C filter sets the dominant pole-zero

C

LOAD

to C

is greater than 1:50, the switch rise time

OUT

loop compensation. The values can be modified slightly

to optimize transient response once the final PC layout

is complete and the particular output capacitor type and

value have been determined. The output capacitors must

beselectedbecausethevarioustypesandvaluesdetermine

the loop gain and phase. An output current pulse of 20%

should be controlled so that the load rise time is limited to

approximately 25 • C . Thus, a 10μF capacitor would

LOAD

require a 250μs rise time, limiting the charging current

to about 200mA.

3784fb

26

For more information www.linear.com/LTC3784

LTC3784

applicaTions inForMaTion

Design Example

C

is chosen to filter the square current in the output.

OUT

The maximum output current peak is:

As a design example, assume V = 12V (nominal),

IN

V

= 22V(max),V =24V,I

=8A,V

=

31%

2

⎛

⎝

⎞

IN

OUT

OUT(MAX)

SENSE(MAX)

I_OUT(PEAK)= 8• 1+

= 9.3A

⎜

⎟

⎠

75mV, and f = 350kHz.

The components are designed based on single channel

operation. The inductance value is chosen first based on

a 30% ripple current assumption. Tie the PLLIN/MODE

pin to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:

A low ESR (5mΩ) capacitor is suggested. This capacitor

will limit output voltage ripple to 46.5mV (assuming ESR

dominates the ripple).

PC Board Layout Checklist

⎛

⎞

V

f•L

V

IN

V_OUT

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 8. Figure 9 illustrates the current

waveforms present in the various branches of the 2-phase

synchronousregulatorsoperatinginthecontinuousmode.

Check the following in your layout:

IN

ΔI_L=

1−

⎜

⎟

⎝

⎠

The largest ripple happens when V = 1/2V

where the average maximum inductor current for each

= 12V,

OUT

IN

channel is:

I

⎛

⎞ ⎛

⎞

V_OUT

OUT(MAX)

I_MAX

=

•

= 8A

⎜

⎟ ⎜

⎟

2

V

⎝

⎠ ⎝

⎠

IN

1.PutthebottomN-channelMOSFETsMBOT1andMBOT2

and the top N-channel MOSFETs MTOP1 and MTOP2

A 6.8μH inductor will produce a 31% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 9.25A.

in one compact area with C

.

OUT

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return of

The R

resistor value can be calculated by using the

maximum current sense voltage specification with some

accommodation for tolerances:

SENSE

C

mustreturntothecombinedC (–)terminals.

INTVCC

OUT

The path formed by the bottom N-channel MOSFET

and the capacitor should have short leads and PC trace

lengths. The output capacitor (–) terminals should be

connected as close as possible to the source terminals

of the bottom MOSFETs.

75mV

9.25A

R_SENSE

≤

= 0.008Ω

Choosing 1% resistors: R = 5k and R = 95.3k yields an

output voltage of 24.072V.

A

B

3. Does the LTC3784 VFB pin’s resistive divider connect to

the (+) terminal of C ? The resistive divider must be

OUT

ThepowerdissipationonthetopsideMOSFETineachchan-

nelcanbeeasilyestimated.ChoosingaVishaySi7848BDP

connected between the (+) terminal of C

and signal

OUT

ground and placed close to the VFB pin. The feedback

resistor connections should not be along the high cur-

rent input feeds from the input capacitor(s).

MOSFET results in: R

= 0.012Ω, C

= 150pF.

DS(ON)

MILLER

At maximum input voltage with T (estimated) = 50°C:

(24V –12V)24V

P_MAIN

=

•(4A)²

–

+

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Thefiltercapacitorbetween

(12V)²

+

–

• 1+(0.005)(50°C–25°C) •0.008Ω

[

]

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the sense resistor.

4A

12V

+ (1.7)(24V)³

(150pF)(350kHz)= 0.7W

3784fb

27

For more information www.linear.com/LTC3784

LTC3784

applicaTions inForMaTion

–

SENSE1

ILIM

PGOOD

SW1

+

V

PULL-UP

R

L1

SENSE1

TG1

LTC3784

C

B1

PHSMD

CLKOUT

FREQ

PLLIN/MODE

BOOST1

BG1

M1

+

M2

f

IN

VBIAS

PGND

OVMODE

SGND

RUN

GND

V

IN

EXTV

CC

INTV

CC

VFB

ITH

SS

BG2

M3

+

C

B2

M4

BOOST2

OUT

R

L2

SENSE2

TG2

SW2

+

SENSE2

–

3784 F08

Figure 8. Recommended Printed Circuit Layout Diagram

SW1

L1

R

SENSE1

SW2

V

OUT

V

IN

R

IN

C

IN

C

OUT

R

L

SW4

L2

R

SENSE2

BOLD LINES INDICATE

HIGH SWITCHING

SW3

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

3784 F09

Figure 9. Branch Current Waveforms

3784fb

28

For more information www.linear.com/LTC3784

LTC3784

applicaTions inForMaTion

suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompen-

sation of the loop can be used to tame a poor PC layout

if regulator bandwidth optimization is not required. Only

after each controller is checked for its individual perfor-

mance should both controllers be turned on at the same

time. A particularly difficult region of operation is when

one controller channel is nearing its current comparator

trip point while the other channel is turning on its bottom

MOSFET. This occurs around the 50% duty cycle on either

channel due to the phasing of the internal clocks and may

cause minor duty cycle jitter.

5. Is the INTV decoupling capacitor connected close

CC

to the IC, between the INTV and the power ground

CC

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1μF ceramic capacitor placed

immediately next tothe INTV andPGND pins can help

CC

improve noise performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2) and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from

the opposites channel’s voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and, therefore, should be kept on

the output side of the LTC3784 and occupy a minimal

PC trace area.

Reduce V from its nominal level to verify operation with

IN

high duty cycle. Check the operation of the undervoltage

lockout circuit by further lowering V while monitoring

IN

7. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling.

capacitors with tie-ins for the bottom of the INTV

decouplingcapacitor,thebottomofthevoltagefeedback

resistive divider and the SGND pin of the IC.

CC

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

to the internal oscillator and probe the actual output volt-

age. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 10% of the maximum designed current level in

Burst Mode operation.

An embarrassing problem which can be missed in an oth-

erwiseproperlyworkingswitchingregulator, resultswhen

the current sensing leads are hooked up backwards. The

output voltage under this improper hook-up will still be

maintained, but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

Thedutycyclepercentageshouldbemaintainedfromcycle

to cycle in a well designed, low noise PCB implementa-

tion. Variation in the duty cycle at a subharmonic rate can

3784fb

29

For more information www.linear.com/LTC3784

LTC3784

Typical applicaTions

–

+

SENSE1

ILIM

100k

+

C

PGOOD

TG1

INTV

CC

OUTA1

C

OUTB1

220µF

L1

3.3µH

R

22µF

SENSE1

4mΩ

MTOP1

MBOT1

× 4

PHASMD

CLKOUT

SW1

C

, 0.1µF

B1

OVMODE

PLLIN/MODE

SGND

BOOST1

BG1

LTC3784

EXTV

RUN

CC

D1

VBIAS

INTV

CC

V

OUT

FREQ

V

IN

C

, 0.1µF

24V

SS

C

INT

4.7µF

5V TO 24V

10A*

C

IN

SS

22µF

PGND

BG2

C

, 15nF

× 2

ITH

D2

C

R

, 8.66k

ITH

MBOT2

MTOP2

, 0.1µF

B2

C

, 220pF

ITHA

L2

3.3µH

R

SENSE2

4mΩ

BOOST2

SW2

R , 12.1k

A

TG2

VFB

SENSE2

+

–

3784 F10

R

B

232k

+

C

22µF

× 4

OUTA2

C

OUTB2

220µF

C

, C : TDK C4532X5R1E226M

, C

OUTB1 OUTB2

IN OUTA1 OUTA2

, C : SANYO, 50CE220LX

L1, L2: PULSE PA1494.362NL

MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H

D1, D2: BAS140W

*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.

IN

Figure 10. High Efficiency 2-Phase 24V Boost Converter

–

SENSE1

ILIM

100k

+

C

PGOOD

TG1

INTV

CC

OUTA1

C

OUTB1

220µF

L1

3.3µH

6.8µF

R

MTOP1

MBOT1

SENSE1

4mΩ

× 4

PHASMD

CLKOUT

SW1

C

, 0.1µF

B1

BOOST1

OVMODE

PLLIN/MODE

SGND

BG1

LTC3784

EXTV

RUN

CC

D1

VBIAS

INTV

CC

V

28V

8A

OUT

FREQ

SS

V

IN

C

, 0.1µF

SS

C

INT

4.7µF

5V TO 28V

C

IN

6.8µF

PGND

BG2

C

, 15nF

× 4

ITH

D2

C

R

, 8.66k

ITH

MBOT2

MTOP2

, 0.1µF

B2

C

, 220pF

ITHA

L2

3.3µH

R

SENSE2

4mΩ

BOOST2

SW2

R , 12.1k

A

TG2

VFB

SENSE2

+

–

3784 F11

R

B

271k

+

C

6.8µF

× 4

OUTA2

C

OUTB2

220µF

C

, C : TDK C4532X7RIH685K

, C

OUTB1 OUTB2

IN OUTA1 OUTA2

C

, C : SANYO, 50CE220LX

L1, L2: PULSE PA1494.362NL

MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H

D1, D2: BAS140W

Figure 11. High Efficiency 2-Phase 28V Boost Converter

3784fb

30

For more information www.linear.com/LTC3784

LTC3784

Typical applicaTions

–

SENSE1

100k

+

C

+

OUTA1

PGOOD

INTV

CC

C

OUTB1

6.8µF

L1

10.2µH

R

TG1

MTOP1

MBOT1

SENSE1

5mΩ

220µF

ILIM

× 4

PHASMD

CLKOUT

SW1

C

, 0.1µF

B1

BOOST1

BG1

INTV

OVMODE

PLLIN/MODE

SGND

CC

LTC3784

EXTV

RUN

CC

D1

VBIAS

INTV

CC

V

36V

6A

FREQ

OUT

V

IN

C

, 0.1µF

SS

C

INT

5V TO 36V

C

IN

4.7µF

SS

6.8µF

PGND

BG2

× 4

C

, 15nF

ITH

D2

C

R

, 3.57k

ITH

MBOT2

MTOP2

, 0.1µF

C

, 220pF

B2

ITHA

L2

10.2µH

R

SENSE2

5mΩ

BOOST2

SW2

R , 12.1k

A

TG2

VFB

SENSE2

+

–

3784 F12

R

B

348k

+

C

6.8µF

× 4

OUTA2

C

OUTB2

220µF

C

, C

: TDK C4532X7RIH685K

IN OUTA1 OUTA2

, C

: SANYO, 50CE220LX

OUTB1 OUTB2

L1, L2: PULSE PA2050.103NL

MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJICO652DPB

D1, D2: BAS170W

Figure 12. High Efficiency 2-Phase 36V Boost Converter

3784fb

31

For more information www.linear.com/LTC3784

LTC3784

Typical applicaTions

–

SENSE1

100k

+

C

PGOOD

INTV

CC

OUTA1

C

OUTB1

L1

6.8µF

R

TG1

MTOP1

MBOT1

SENSE1

8mΩ

220µF

ILIM

16µH

× 4

PHASMD

SW1

C

, 0.1µF

B1

CLKOUT

OVMODE

PLLIN/MODE

SGND

EXTV

RUN

INTV

BOOST1

BG1

CC

LTC3784

CC

D1

VBIAS

INTV

CC

V

48V

4A

OUT

FREQ

V

IN

C

SS

, 0.1µF

C

INT

5V TO 48V

C

4.7µF

IN

SS

6.8µF

PGND

BG2

C

ITH

, 10nF

× 4

D2

C

R

, 23.7k

ITH

MBOT2

MTOP2

, 0.1µF

C

, 220pF

B2

ITHA

L2

16µH

R

SENSE2

8mΩ

BOOST2

SW2

R , 12.1k

A

TG2

VFB

SENSE2

+

–

3784 F13

R

B

475k

+

C

6.8µF

× 4

OUTA2

C

OUTB2

220µF

C

, C

: TDK C4532X7RIH685K

IN OUTA1 OUTA2

, C

: SANYO, 63CE220K

OUTB1 OUTB2

L1, L2: PULSE PA2050.163NL

MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0652DPB

D1, D2: BAS170W

Figure 13. High Efficiency 2-Phase 48V Boost Converter

3784fb

32

For more information www.linear.com/LTC3784

LTC3784

Typical applicaTions

R

S2

53.6k

1%

–

SENSE1

+

C

OUTA1

C1

0.1µF

C

OUTB1

R

26.1k

1%

6.8µF

S1

100k

220µF

+

D3

× 4

PGOOD

TG1

INTV

CC

SENSE1

ILIM

C3

MTOP1

0.1µF

PHASMD

CLKOUT

OVMODE

PLLIN/MODE

SGND

SW1

C

, 0.1µF

B1

L1

10.2µH

BOOST1

INTV

CC

MBOT1

MBOT2

BG1

LTC3784

EXTV

RUN

CC

D1

V

24V

8A

OUT

V

R

, 41.2k

IN

FREQ

VBIAS

5V TO 24V

FREQ

SS

+

C

INA

INTV

CC

C

INB

C

, 0.1µF

SS

22µF

C

220µF

INT

× 4

4.7µF

PGND

BG2

C

, 15nF

ITH

D2

R

, 8.87k, 1%

ITH

C

, 0.1µF

B2

C

, 220pF

ITHA

L2

BOOST2

SW2

10.2µH

R

A

12.1k, 1%

TG2

VFB

MTOP2

D4

R

S3

R

S

26.1k

1%

232k

1%

C4

0.1µF

3784 F14

+

–

SENSE2

+

C2

0.1µF

C

OUTA2

C

OUTB2

6.8µF

220µF

× 4

SENSE2

R

S4

53.6k

1%

C

, C

: C4532x7R1H685K

: SANYO 63CE220KX

OUTA1 OUTA2

, C

OUTB1 OUTB2

: TDK C4532X5R1E226M

: SANYO 50CE220AX

INA

INB

L1, L2: SER2918H-103

MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0305

D1, D2: BAS140W

D3, D4: DIODES INC. B340B

Figure 14. High Efficiency 2-Phase 24V Boost Converter with Inductor DCR Current Sensing

3784fb

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For more information www.linear.com/LTC3784

LTC3784

Typical applicaTions

+

–

SENSE1

100k

+

C

PGOOD

TG1

INTV

CC

OUTA1

C

OUTB1

L1

3.3µH

22µF

R

MTOP1

MBOT1

SENSE1

4mΩ

220µF

ILIM

× 4

SW1

PHASMD

OVMODE

PLLIN/MODE

SGND

C

, 0.1µF

B1

INTV

BOOST1

CC

EXTV

RUN

BG1

CC

LTC3784

D1

VBIAS

FREQ

INTV

CC

C

, 0.1µF

SS

C

INT1

4.7µF

SS

PGND

BG2

C

ITH

, 15nF

D2

C

R

, 8.66k

ITH

MBOT2

MTOP2

, 0.1µF

C

, 220pF

B2

ITHA

L2

3.3µH

R

SENSE2

4mΩ

BOOST2

SW2

R , 12.1k

A

TG2

VFB

–

SENSE2

+

C

OUTA2

C

+

OUTB2

R

B

CLKOUT

22µF

220µF

232k

× 4

V

OUT

V

IN

24V

5V to 24V

C

20A*

INA

C

INB

22µF

220µF

× 4

+

–

SENSE1

100k

C

PGOOD

TG1

INTV

CC

OUTA3

C

OUTB3

L3

3.3µH

22µF

R

MTOP3

MBOT3

SENSE3

4mΩ

220µF

ILIM

× 4

PHASMD

OVMODE

SW1

C

, 0.1µF

B3

BOOST1

BG1

PLLIN/MODE

SGND

EXTV

RUN

FREQ

CC

LTC3784

D3

VBIAS

INTV

CC

C

INT2

4.7µF

PGND

BG2

D4

C

SS

MBOT4

MTOP4

, 0.1µF

B4

L4

3.3µH

R

SENSE4

4mΩ

BOOST2

SW2

ITH

TG2

VFB

3784 F15

–

SENSE2

C

+

OUTA4

C

OUTB4

+

CLKOUT

22µF

220µF

× 4

C

, C

: TDK C4532X5R1E226M

: SANYO, 50CE220LX

INA OUTA1 OUTA2 OUTA3 OUTA4

, C

INB OUTB1 OUTB2 OUTB3 OUTB4

L1, L2, L3, L4: PULSE PA1494.362NL

MBOT1, MBOT2, MBOT3, MBOT4, MTOP1, MTOP2, MTOP3, MTOP4: RENESAS HAT2169H

D1, D2, D3, D4: BAS140W

*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.

IN

Figure 15. 4-Phase 480W Single Output Boost Converter

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For more information www.linear.com/LTC3784

LTC3784

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

.386 – .393*

(9.804 – 9.982)

.045 .005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

(0.38 0.10)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 REV B 0212

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

3784fb

35

For more information www.linear.com/LTC3784

LTC3784

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 ±0.05

4.50 ±0.05

3.10 ±0.05

2.50 REF

2.65 ±0.05

3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

3.50 REF

4.10 ±0.05

5.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 ±0.05

4.00 ±0.10

(2 SIDES)

27

28

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 ±0.10

(2 SIDES)

3.50 REF

3.65 ±0.10

2.65 ±0.10

(UFD28) QFN 0506 REV B

0.25 ±0.05

0.200 REF

0.50 BSC

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3784fb

36

For more information www.linear.com/LTC3784

LTC3784

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

04/14 Revised Figure 13 resistors

32

B

07/15 Electrical Characteristics table Conditions V

= 0, changed to V

= 0V

4

EXTVCC

Typical Performance Characteristics section, Soft Start-Up graph, changed time scale from 20ms to 2ms

5

Pin Functions section, EXTV pin description, changed 4.7V to 4.8V

9

CC

Main Control Loop section, changed IR to IREV

11

12

22

23

34

Light Load Current Operation section, changed IR to IREV

INTV Regulators section, changed 50mA to 40mA

CC

INTV Regulators section, changed Note 3 to Note 2

CC

INTV Regulators section, changed less than 10mA to less than 11mA

CC

INTV Regulators section equation, changed 10mA to 11mA

CC

INTV Regulators section equation, changed 90°C/W to 80°C/W

CC

INTV Regulators section, changed 79°C to 77°C

CC

Changed Figure 15 schematic

3784fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

37

For more information www.linear.com/LTC3784

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3784

Typical applicaTion

I

IN

C

IN

12V

I

1

0°

I

PHASMD

BG1

TG1

1

2

BOOST: 24V, 5A

LTC3784

I

2

180°

90°

BG2

TG2

BOOST: 24V, 5A

CLKOUT

+90°

I

3

4

24V, 20A

3

90,270

C

I

COUT

OUT

PLLIN/MODE

PHASMD

BG1

TG1

LTC3784

I

4

I*

IN

270°

BG2

TG2

BOOST: 24V, 5A

I*

COUT

REFER TO FIGURE 15 FOR APPLICATION CIRCUITS

* RIPPLE CURRENT CANCELLATION INCREASES THE RIPPLE

FREQUENCY AND REDUCES THE RMS INPUT/OUTPUT RIPPLE

CURRENT, THUS SAVING INPUT/OUTPUT CAPACITORS

3784 F16

Figure 16. PolyPhase Application

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC3788/LTC3788-1

Multiphase, Dual Output Synchronous Step-Up

Controller

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V

Up to 60V, 50kHz to

OUT

IN

900kHz Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28

LTC3787

LTC3786

2-Phase Single Output Synchronous Boost Controller

4.5V ≤ V ≤ 38V, V

Up to 60V, 50kHz to 900kHz, 4mm × 5mm

OUT

IN

QFN-28 and SSOP-28 Packages

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V Up to 60V, 50kHz to

OUT

Low I Synchronous Step-Up Controller

Q

IN

900kHz Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E

LTC3862/LTC3862-1/

LTC3862-2

Multiphase, Dual Channel Single Output Current

Mode Step-Up DC/DC Controller

4V ≤ V ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating

IN

Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24

LT3757/LT3758

Boost, Flyback, SEPIC and Inverting Controller

2.9V ≤ V ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency,

IN

3mm × 3mm DFN-10 and MSOP-10E

LTC3859AL

Low I , Triple Output Buck/Buck/Boost Synchronous All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to

Q

DC/DC Controller

2.5V After Start-Up) ≤ V ≤ 38V, V

Up to 24V, V

IN

OUT(BUCKS) OUT(BOOST)

Up to 60V, I = 28µA

Q

LTC3789

High Efficiency Synchronous 4-Switch Buck-Boost

DC/DC Controller

4V ≤ V ≤ 38V, 0.8V ≤ V

≤ 38V, 4mm × 5mm QFN-28 and SSOP-28

IN

OUT

LT8705

80V V and V

Synchronous 4-Switch Buck-Boost

V

Range: 2.8V (Need EXTV > 6.4V) to 80V, V

Range: 1.3V to 80V,

IN

OUT

IN

CC

OUT

DC/DC Controller

Four Regulation Loops

LTC3890/LTC3890-1/

60V, Low I , Dual 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,

Q

IN

LTC3890-2/LTC3890-3 DC/DC Controller

0.8V ≤ V

≤ 24V, I = 50μA

OUT Q

3784fb

LT 0715 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

38

For more information www.linear.com/LTC3784

(408)432-1900 FAX: (408) 434-0507 www.linear.com/3784

●

 LINEAR TECHNOLOGY CORPORATION 2014


型号：	LTC3784_15
厂家：	Linear
描述：	60V PolyPhase Synchronous Boost Controller
文件：	总38页 (文件大小：523K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3784_15 [Linear]

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