LTC3726EGN#PBF [Linear]
LTC3726 - Secondary-Side Synchronous Forward Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LTC3726EGN#PBF |
厂家: | Linear |
描述: | LTC3726 - Secondary-Side Synchronous Forward Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
文件: | 总16页 (文件大小:208K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3726
Secondary-Side Synchronous
Forward Controller
U
DESCRIPTIO
FEATURES
The LTC®3726 is a secondary-side controller for synchro-
nous forward converters. When used in conjunction with
the LTC3705/LTC3725 gate driver and primary-side con-
trollers, the part creates a complete isolated power supply
that combines the simplicity of OPTI-LOOP® compensa-
tion with the speed of secondary-side control.
■
Secondary-Side Control for Fast Transient Response
■
Self-Starting Architecture Eliminates Need for
Separate Bias Regulator
■
Proprietary Gate Drive Encoding Scheme Reduces
System Complexity
■
Current Mode Control Ensures Current Sharing
■
PLL Fixed Frequency: 100kHz to 500kHz
±1% Output Voltage Accuracy
OPTI-LOOP Compensation
The LTC3726 has been designed to simplify the design of
highlyefficient,secondary-sideforwardconverters.Work-
inginconcertwiththeLTC3705orLTC3725,theLTC3726
forms a robust, self-starting converter that eliminates the
needfortheseparatebiasregulatorthatiscommonlyused
in secondary-side control applications. In addition, a pro-
prietaryschemeisusedtomultiplexgatedrivesignalsand
DC bias power across the isolation barrier through a
single, tiny pulse transformer.
■
■
■
Available in a NaUrrow 16-Lead SSOP Package
APPLICATIO S
■
Isolated 48V Telecommunication Systems
■
Internet Servers and Routers
■
Distributed Power Step-Down Converters
■
Automotive and Heavy Equipment
The LTC3726 is available in a 16-lead SSOP package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6144194. Other patents pending.
U
TYPICAL APPLICATIO
36V-72V to 3.3V/20A Isolated Forward Converter
+
+
V
V
OUT
IN
T1
L1
1.2µH
•
•
1.2Ω
Si7852DP
MURS120
Si7852DP
CMPSH1-4
5k
1µF
100V
x3
330µF
6.3V
×3
Si7336ADP
MURS120
Si7336ADP
×2
FZT690B
2mΩ
2W
30mΩ
1W
10µF
25V
7.5V
2.2µF
–
–
V
V
OUT
IN
100k
BAS21
102k
1%
FQT7N10
L1: COILCRAFT SER2010-122
T1: PULSE PA0807
0.22µF
T2: PULSE PA0297
FG
SW SG
V
CC
–
+
I
I
S
S
365k
1%
FS/SYNC
1µF
NDRV
UVLO
BOOST TG TS BG IS
T2
+
+
FB/PHASE
ITH
FB/IN
PT
•
•
LTC3726
680pF
LTC3705
V
CC
2.2µF
25V
–
–
FS/IN
PT
SS/FLT
22.6k
1%
GND
PGND
SLP
MODE
RUN/SS
GND PGND VSLMT
15k
1%
20k
162k
33nF
33nF
3726 TA01
3726fb
1
LTC3726
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
VCC ........................................................... –0.3V to 10V
SW............................................................... –5V to 50V
ITH, RUN/SS............................................... –0.3V to 7V
All Other Pins............................................ –0.3V to 10V
Operating Ambient Temperature Range (Note 2)
LTC3726EGN ...................................... – 40°C to 85°C
LTC3726IGN....................................... – 40°C to 85°C
Operating Junction Temperature (Note 3) ........... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
SG
FG
1
16
15
14
13
12
11
10
9
V
CC
+
2
3
4
5
6
7
8
PT
PT
–
MODE
FB/PHASE
ITH
PGND
SW
+
RUN/SS
SLP
IS
–
IS
GND
FS/SYNC
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
ORDER PART NUMBER
LTC3726EGN
LTC3726IGN
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 7V, GND = PGND = 0V, unless otherwise noted.
A
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
0.606
–0.1
UNITS
Main Control Loop
V
Regulated Feedback Voltage
(Note 4) ITH = 1.2V
●
●
0.594
0.600
0.001
–0.01
V
%/V
%
FB
∆V
∆V
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
V
= 5V to 10V, ITH = 1.2V
CC
FB(LINREG)
Measured in Servo Loop,
ITH = 0.5V to 2V
FB(LOADREG)
V
V
Maximum Current Sense Threshold
Over-Current Shutdown Threshold
R
Mode, V = 0V
68
1.15
78
1.28
88
1.4
mV
V
ISMAX
SENSE
IS
CT Mode, V = 0V
IS
R
SENSE
Mode, V = 0V
87
1.45
100
1.65
113
1.85
mV
V
ISOC
IS
CT Mode, V = 0V
IS
g
Transconductance Amplifier g
Soft-Start Charge Current
Soft-Start Discharge Current
RUN/SS Pin ON Threshold
Minimum ON Time
2.40
–4
2.75
–5
3.10
–6
mS
µA
µA
V
m
m
I
I
V
V
= 2V
RUN/SS(C)
RUN/SS(D)
RUN/SS
RUN/SS
3
V
Rising
●
0.4
15
0.45
200
1.5
1.5
1.5
1.5
17
0.5
RUN/SS
ON,MIN
t
ns
Ω
FG, SG R
FG, SG R
FG, SG Driver Pull-Up On Resistance
FG, SG Driver Pull-Down On Resistance
FG, SG Low
FG, SG High
2.3
2.3
2.3
2.3
19
UP
Ω
DOWN
+
–
+
–
+
–
PT , PT R
PT , PT Driver Pull-Up Resistance
PT , PT Low
Ω
UP
+
–
+
–
+
–
PR , PT R
PT , PT Driver Pull-Down Resistance
Output Overvoltage Threshold
PT , PT High
Rising
Ω
DOWN
∆V
V
%
FB(OV)
FB
3726fb
2
LTC3726
ELECTRICAL CHARACTERISTICS
The
●
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 7V, GND = PGND = 0V, unless otherwise noted.
A
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply
CC
V
Operating Voltage Range
5
10
V
CCOP
I
Supply Current
Operating
CC
f
= 200kHz (Note 5)
4.2
mA
OSC
Shutdown
V
= GND
700
µA
RUN/SS
V
V
UV Lockout
V
CC
Rising
●
4.52
4.60
0.4
4.70
V
V
UVLO
HYS
UV Hysteresis
Oscillator and Phase-Locked Loop
I
f
f
FS/SYNC Pin Sourcing Current
Oscillator Low Frequency Set Point
Oscillator High Frequency Set Point
Oscillator Resistor Set Accuracy
Maximum PLL Sync Frequency
Minimum PLL Sync Frequency
20
µA
kHz
kHz
%
FS
V
V
= GND
170
255
–20
200
300
230
345
20
LOW
HIGH
FS/SYNC
= V
FS/SYNC
CC
∆f (R
)
75kΩ < R
< 175kΩ
FS/SYNC
FS
f
f
500
75
kHz
kHz
PLL(MAX)
PLL(MIN)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Operating junction temperature T (in °C) is calculated from the
J
ambient temperature T and the average power dissipation P (in Watts)
A
D
by the formula:
T = T + θ • P
D
J
A
JA
Note 2: The LTC3726E is guaranteed to meet the performance
specifications from 0°C to 85°C junction temperature. Specifications over
the –40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3726I is guaranteed and tested over the full – 40°C to 85°C operating
temperature range.
Refer to the Applications Information section for details.
Note 4: The LTC3726 is tested in a feedback loop that servos V to a
voltage near the internal 0.6V reference voltage to obtain the specified ITH
FB
voltage (V = 1.2V).
ITH
Note 5: Operating supply current is measured in test mode. Dynamic
supply current is higher due to the internal gate charge being delivered at
the switching frequency. See Typical Performance Characteristics.
3726fb
3
LTC3726
TYPICAL PERFOR A CE CHARACTERISTICS
U W
T = 25°C, unless otherwise noted.
A
Maximum Current Sense
Threshold vs ITH Voltage
V
Supply Current vs
Maximum Current Sense
Threshold vs Duty Cycle
CC
Input Voltage
7
6
5
4
3
100
80
60
40
20
0
100
80
60
40
20
0
f
= 200kHz
OSC
ALL GATES: C
= 0
R
= 0
LOAD
SLP
100kΩ
R
= 50k
SLP
6
7
INPUT VOLTAGE (V)
10
20
40
DUTY CYCLE (%)
80
0.5
1.0
ITH VOLTAGE (V)
3.0
5
8
9
0
60
0
1.5
2.0
2.5
3726 G01
3726 G03
3726 G04
IS Pins Source Current
vs Temperature
Maximum Current Sense
Threshold vs Temperature
IS Pins Source Current
400
300
265
260
255
250
245
240
235
230
101.5
101.0
100.5
100.0
99.5
RS-MODE: (I + + I –)
IS IS
V
+ = V – = 0V
IS IS
200
100
CT-MODE: I
+
IS
0
–100
–200
–300
–400
RS-MODE: (I + + I –)
IS
IS
99.0
0
1
5
6
–25
0
125
–25
0
125
–1
2
3
4
–50
25
50
75 100
–50
25
50
75 100
+
–
IS , IS COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3726 G05
3726 G06
3726 G07
RUN/SS ON Threshold
vs Temperature
Oscillator Frequency
vs Temperature
Oscillator Frequency vs R
FS
5
4
600
500
400
300
200
100
0
470
460
450
440
430
420
3
R = 175KΩ
OSC
2
f
= 500kHz
1
0
–1
–2
R = 75KΩ
= 100kHz
f
OSC
75
100
200
–25
0
125
50
125
(kΩ)
150
175
–50
25
50
75 100
–25
0
125
–50
25
50
75 100
R
TEMPERATURE (°C)
TEMPERATURE (°C)
FS
3726 G09
3726 G14
3726 G08
3726fb
4
LTC3726
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Undervoltage Lockout
vs Temperature
FB Voltage vs Temperature
FB Voltage Line Regulation
601.0
600.5
600.0
599.5
599.0
601.0
600.5
600.0
599.5
599.0
4.65
4.60
4.55
4.50
4.45
4.40
4.35
4.30
4.25
V
RISING
CC
–25
0
125
5
10
SUPPLY VOLTAGE (V)
30
–25
0
125
–50
25
50
75 100
0
15
20
25
–50
25
50
75 100
TEMPERATURE (°C)
V
TEMPERATURE (°C)
IN
3726 G15
3726 G11
3726 G16
Gate Driver On-Resistance
vs Temperature
Gate Driver On-Resistance vs V
CC
1.8
1.7
1.6
1.5
1.4
1.3
1.2
2.50
2.25
2.00
1.75
1.50
1.25
1.00
V
= 7V
CC
PULL-DOWN
PULL-UP
6
7
10
–25
0
125
5
8
9
–50
25
50
75 100
V
CC
VOLTAGE (V)
TEMPERATURE (°C)
3726 G12
3726 G13
Efficiency (Figure 5)
Load Step (Figure 5)
95
90
85
80
V
= 36V
IN
V
OUT
100mV/DIV
V
= 72V
IN
I
OUT
10A/DIV
3726 G18
20µs/DIV
V
V
= 48V
IN
OUT
= 3.3V
LOAD STEP = 0A TO 20A
5
10
LOAD CURRENT (A)
25
0
15
20
3726 G17
3726fb
5
LTC3726
U
U
U
PI FU CTIO S
SG (Pin 1): Gate Drive for the “Synchronous” MOSFET.
FS/SYNC (Pin 9): Combination Frequency Set and SYNC
pin. Tie to GND or VCC to run at 200kHz and 300kHz
respec-tively. Place a single resistor to ground at this pin
to set the frequency between 75kHz and 500kHz. To
synchronize, drive this pin with a clock signal to achieve
PLL synchronization from 75kHz to 500kHz. Sources
20µA of current.
IS– (Pin 10): Negative Input to the Current Sense Circuit.
When using current sense transformers, this pin may be
tied to VCC for single-ended sensing with a 1.28V maxi-
mum current trip level.
FG (Pin 2): Gate Drive for the “Forward” MOSFET.
MODE (Pin 3): Tie to either GND or VCC to set the
maximum duty cycle at either 50% or 75% respectively.
Tie to ground through either a 200k or 100k resistor (50%
or 75% maximum duty cycle) to disable pulse encoding.
In this mode, normal PWM signals will be generated at the
PT+ pin, while a clock signal is generated at the PT– pin.
FB/PHASE (Pin 4): Inverting input of the main loop Error
Amplifier and Control Input to the Phase Selector. In
PolyPhase® Slave applications (where voltage feedback is
notneeded)thispinisusedtodeterminethephasingofthe
controller CLK relative to the synchronizing signal at the
FS/SYNC pin.
IS+ (Pin 11): Positive Input to the Current Sense Circuit.
Connect to the positive end of a current sense resistor or
to the output of a current sense transformer.
SW (Pin 12): Connect to the drain of the “synchronous”
MOSFET. This input is used for adaptive shoot-through
prevention and leading edge blanking.
ITH (Pin 5): The Output of the Main Loop Error Amplifier.
Place compensation components between the ITH pin
and GND.
PGND (Pin 13): Gate Driver Ground Pin.
RUN/SS (Pin 6): Combination Run Control and Soft-Start
Inputs. A capacitor to ground sets the ramp time of the
output voltage. Holding this pin below 0.4V causes the IC
to shut down all internal circuitry.
PT–, PT+ (Pins 14, 15): Pulse Transformer Driver Out-
puts. For most applications, these connect to a pulse
transformer (with a series DC blocking capacitor). The
PWM information is multiplexed together with DC power
andsentthroughasinglepulsetransformertotheprimary
side. This information may be decoded by the LTC3705
gate driver and primary-side controller.
SLP (Pin 7): Slope Compensation Input. Place a single
resistor to ground to set the desired amount of slope
compensation.
GND (Pin 8): Signal Ground.
PolyPhase is a registered trademark of Linear Technology Corporation.
VCC (Pin 16): Main VCC Input for all Driver and Control
Circuitry.
3726fb
6
LTC3726
W
BLOCK DIAGRA
+
2×
I
S
11
+
V
V
CC
+
–
FG
2
I
32×
TRP
C
RESET
–
I
S
–
2V
+
DOMINANT
PGND
13
10
WAIT
OVP
R
CC
SG
1
Q
S
WAIT
PWM
0.25V
+
–
DMAX
SKIP
0.2V
+
OVP
C
C
SW
–
I
12
TH
–
ZERO
CROSSING
DETECT
5
BLANK
V
V
CC
CC
+
0.60V
+
–
+
PT
g
= 2.8mS
m
OC
15
C
EA
FB/PHASE
4
DRIVER
2.5V
PGND
3.2V
–
ENCODING
AND
•
•
SLP
7
–
RUN/SS
PT
14
LOGIC
OVERCURRENT
SLOPE
PULSE
XFMR
COMP 1
FS/SYNC
9
DRIVE
TYPE
BLANK
DMAX
OSC
AND
PLL
MODE
3
DRIVE/DMAX
CONTROL
V
CC
19
3726 BD
UVLO
V
CCUV
REG
4V
SB
V
REF
1.24V
4V
SB
RUN/SS
6
FB
SOFT-
START
V
WAIT
CCUV
OC
GND
8
3726fb
7
LTC3726
U
OPERATIO
Main Control Loop
For most forward converter applications, the PT+ and PT–
outputs will contain a pulse-encoded PWM signal. These
outputs are driven in a complementary fashion with an
essentially constant 50% duty cycle. This results in a
stable volt-second balance as well as an efficient transfer
of bias power across the pulse transformer. As shown in
Figure 1, the beginning of the positive half-cycle coincides
withtheturn-onoftheprimary-sideMOSFET(s).Likewise,
the beginning of the negative half-cycle coincides with
the maximum duty cycle (forced turn-off of primary
The LTC3726 is designed to work in a constant frequency,
current mode, one or two transistor forward converter.
During normal operation, the primary-side MOSFET(s)
is (are) “clocked” on with the forward MOSFET on the sec-
ondaryside.Thisappliesthereflectedinputvoltageacross
the inductor on the secondary side. When the current in
the inductor has ramped up to the peak value as com-
manded by the voltage on the ITH pin, the current sense
comparator is tripped, turning off the primary-side and
forward MOSFETs. To avoid turning on the synchronous
MOSFET prematurely and causing shoot-through, the
voltage on the SW pin is monitored. This voltage will
usuallyfallbelow0Vsoonaftertheprimary-sideMOSFETs
have turned completely off. When this condition is de-
tected, the synchronous MOSFET is quickly turned on,
causing the inductor current to ramp back downwards.
The error amplifier senses the output voltage, and adjusts
the ITH voltage to obtain the peak current needed to
maintain the desired main-loop output voltage. The
LTC3726 always operates in a continuous current, syn-
chronous switching mode. This ensures a rapid transient
response as well as a stable bias supply voltage at light
loads. A maximum duty cycle (either 50% or 75%) is
internally set via clock dividers to prevent saturation of the
main transformer. In the event of an overvoltage on the
output, the synchronous MOSFET is quickly turned on to
help protect critical loads from damage.
switch(es)). At the appropriate time during the positive
half-cycle, the end of the “on” time (PWM going LOW) is
signaled by briefly applying a zero volt differential across
the pulse transformer. Figure 1 illustrates the operation of
this multiplexing scheme.
The LTC3705 primary-side controller and gate driver will
decode this PWM information as well as extract the power
needed for primary-side gate drive.
DUTY CYCLE = 15%
150ns
DUTY CYCLE = 0%
150ns
7V
7V
V
+
– V
–
PT1
PT1
3726 F01
–7V
–7V
1 CLK PER
1 CLK PER
Figure 1: Gate Drive Encoding Scheme (V
= GND)
MODE
Self-Starting Architecture
Gate Drive Encoding
WhentheLTC3726isusedinconjunctionwiththeLTC3705/
LTC3725 primary-side controller and gate driver, a com-
plete self-starting isolated supply is formed. When input
voltageisfirstappliedinsuchanapplication,theLTC3705/
LTC3725 will begin switching in an “open-loop” fashion,
causing the main output to slowly ramp upwards. This is
the primary-side soft-start mode. On the secondary side,
the LTC3726 derives its operating bias voltage from a
peak-charged capacitor. This peak-charged voltage will
rise more rapidly than the main output of the converter, so
that the LTC3726 will become operational well before the
output voltage has reached its final value.
Since the LTC3726 controller resides on the secondary
sideofanisolationbarrier,communicationtotheprimary-
side power MOSFETs is generally done through a trans-
former. Moreover, it is often necessary to generate a low
voltage bias supply for the primary-side gate drive cir-
cuitry. In order to reduce the number of isolated windings
present in the system, the LTC3726 uses a proprietary
scheme to encode the PWM gate drive information and
multiplex it together with bias power for the primary-side
drive and control, using a single pulse transformer. Note
that, unlike optoisolators and other modulation tech-
niques, this multiplexing scheme does not introduce a
significant time delay into the system.
3726fb
8
LTC3726
U
OPERATIO
When the LTC3726 has adequate operating voltage, it will
begintheprocedureofassumingcontrolfromtheprimary
side. To do this, it first measures the voltage on the power
supply’s main output and then automatically advances its
own soft-start voltage to correspond to the main output
voltage. This ensures that the output voltage increases
monotonically as the soft-start control is transferred from
primary to secondary. The LTC3726 then begins sending
PWM signals to the LTC3705/LTC3725 on the primary
side through a pulse transformer. When the LTC3705/
LTC3725 has detected a stable signal from the secondary
controller,ittransferscontroloftheprimaryswitchesover
to the LTC3726, beginning the secondary-side soft-start
mode. The LTC3726 continues in this mode until the
output voltage has ramped up to its final value. If for any
reason, the LTC3726 either stops sending (or initially fails
to send) PWM information to the LTC3705/LTC3725, the
LTC3705/LTC3725 will detect a FAULT and initiate a soft-
start retry (see the LTC3705/LTC3725 data sheet).
the inductor (either high side or ground lead sensing), or
in the source of the “forward” switch. If a current sense
–
transformerisused, theIS inputshouldbetiedtoVCC and
the IS+ pin to the output of the current sense transformer.
Thiscausesthegainoftheinternalcurrentsenseamplifier
to be reduced by a factor of 16, so that the maximum
current sense voltage (current limit) is increased from
78mV to 1.28V. An internal, adaptive leading edge blank-
ing circuit ensures clean operation for “switch” current
sensing applications.
Current limit is achieved in the LTC3726 by limiting the
maximum voltage excursion of the error signal (ITH volt-
age). Note that if slope compensation is used, the precise
value at which current limit occurs will be a function of
duty cycle (see Typical Performance Characteristics). If a
short circuit is applied, an independent overcurrent com-
paratormaybetripped.Inthiscase,theLTC3726willenter
a “hiccup” mode using the soft-start circuitry.
Frequency Setting and Synchronization
Slope Compensation
The LTC3726 uses a single pin to set the operating
frequency, or to synchronize the internal oscillator to a
reference clock with an on-chip phase-locked loop (PLL).
TheFSpinmaybetiedtoGND,VCC orhaveasingleresistor
to GND to set the switching frequency. If a clock signal
(>2V) is detected at the FS pin, the LTC3726 will automati-
cally synchronize to the rising edge of the reference clock.
Table 2 summarizes the operation of the FS pin.
For synchronization between multiple LTC3726s, the PT+
pin of one LTC3726 can be used as a master clock
reference and tied to the FS pin of the other LTC3726s.
Slope compensation is added at the input of the PWM
comparator to improve stability and noise margin of the
peak current control loop. The amount of slope compen-
sation can be selected from one of five preprogrammed
valuesusingtheSLPpinasshowninTable1. Notethatthe
amount of slope compensation doubles when the duty
cycle exceeds 50%.
Table 1
SLP PIN
SLOPE (D < 0.5)
0.05 • I • f
SLOPE (D > 0.5)
GND
0.1 • I
• f
SMAX OSC
SMAX OSC
V
None
None
CC
400kΩ to GND
200kΩ to GND
100kΩ to GND
50kΩ to GND
0.1 • I
• f
0.2 • I
0.3 • I
0.5 • I
1.0 • I
• f
Table 2
FS PIN
SMAX OSC
SMAX OSC
0.15 • I
0.25 • I
• f
• f
SMAX OSC
SWITCHING FREQUENCY
200kHz
SMAX OSC
• f
• f
SMAX OSC
GND
SMAX OSC
0.5 • I
• f
• f
V
CC
300kHz
SMAX OSC
SMAX OSC
In Table 1 above, I
is the maximum current limit, and f
is the
R
to GND
f
f
(Hz) = 4R – 200k
FS
SMAX
OSC
FS
OSC
OSC
switching frequency.
Reference Clock
= f (75kHz to 500kHz)
REF
Current Sensing and Current Limit
This will cause all LTC3726s to operate at the same
frequency and phase. The LTC3726 can also be used as a
“Slave” in a PolyPhase application. In this case, the phase
angle of each LTC3726 can be set by using the FB/PHASE
For current sensing, the LTC3726 supports either a cur-
rent sense resistor or a current sense transformer. The
current sense resistor may either be placed in series with
3726fb
9
LTC3726
U
OPERATIO
pin (see Slave Mode Operation). The Phase angle cannot
be adjusted when the FB/PHASE pin is being used for
voltage loop regulation.
lose its bias voltage after a fault has been detected and
before completing a soft-start retry. In this case, the
“hiccup-mode” operation is actually governed by the
LTC3705/LTC3725 soft-start circuitry (see the LTC3705/
LTC3725 data sheets).
Soft-Start
The soft-start circuitry has four functions: 1) to provide a
shutdown, 2) to provide a smooth ramp on the output
voltage during start-up, 3) to limit the output current in a
short-circuit situation by entering a hiccup mode, and
4) to communicate fault and shutdown information
between multiple LTC3726s in a PolyPhase application.
Drive Mode and Maximum Duty Cycle
Although the LTC3726 is primarily intended to be used
with the LTC3705/LTC3725 in forward converter applica-
tions, the MODE pin provides the flexibility to use the
LTC3726 in a wide variety of additional applications. This
pin can be used to defeat the gate drive encoding scheme,
as well as change the maximum duty cycle from its default
value of 50%. The use of the MODE pin is summarized in
Table 3.
When the RUN/SS pin is pulled to GND, the chip is placed
into shutdown mode. If this pin is released, the RUN/SS
pinisinitiallychargedwitha50µAcurrentsource.Afterthe
RUN/SS pin gets above 0.5V, the chip is enabled. At the
instant that the LTC3726 is first enabled, the RUN/SS
voltage is rapidly preset to a voltage that will correspond
to the main output voltage of the DC/DC converter. (See
the Self-Starting Architecture section.) After this preset
interval has completed, the normal soft-start interval
begins and the charging current is reduced to 5µA. The
externalsoft-startvoltageisusedtointernallyrampupthe
0.6V reference (positive) input to the error amplifier.
When fully charged, the RUN/SS voltage remains at 3V.
When the gate drive encoding scheme is defeated, a
standard PWM-style signal will be present at the PT+ pin
and a reference clock (in phase with the PWM signal) will
be present at the PT– pin. These outputs can be used in
“standalone”applications(withouttheLTC3705/LTC3725)
to drive the gates of MOSFETs in a conventional manner.
Table 3
+
–
PT /PT Mode
INTENDED
APPLICATION
MODE PIN
(MAX DUTY CYCLE)
GND
Encoded PWM
2-Switch Forward
with LTC3705
In the event that the sensed switch or inductor current
exceeds the overcurrent trip threshold, an internal fault
latchistripped.Whensuchafaultisdetected,theLTC3726
immediately goes to zero duty cycle and initiates a soft-
start retry. Prior to discharging the soft-start capacitor,
however, the LTC3726 first puts a voltage pulse on the
RUN/SS pin, which trips the fault latch in any other
LTC3726 that shares the RUN/SS. This ensures an orderly
shutdown of all phases in a PolyPhase application. After
the soft-start capacitor is fully discharged, the LTC3726
attempts a restart. If the fault is persistent, the system
enters a “hiccup” mode.
(D
MAX
= 50%)
V
Encoded PWM
(D = 75%)
1-Switch Forward
with LTC3725
CC
MAX
200kΩ to GND
100kΩ to GND
Standard PWM
(D = 50%)
2-Switch Forward
Standalone
MAX
Standard PWM
(D = 75%)
1-Switch Forward
Standalone
MAX
Overvoltage Protection
This circuit monitors the voltage on the FB input. If the
voltage on the FB pin exceeds 117% of 0.6V (0.7V), an
overvoltage(OVP)isdetected. Forovervoltageprotection,
the secondary-side synchronous MOSFET is turned on
while all other MOSFETs are turned off. This protection
mode is not latched, so that the overvoltage detection is
cleared if the FB voltage falls below 115% of 0.6V (0.69V).
Note that in self-starting secondary-side control applica-
tions (with the LTC3705 or LTC3725), the presence of the
LT3726biasvoltageisdependentupontheregularswitch-
ing of the primary-side MOSFETs. Therefore, depending
on the details of the application circuit, the LTC3726 may
3726fb
10
LTC3726
U
OPERATIO
Slave Mode Operation
haveasingleresistortoVCC toactivateSlavemodeandset
the phase angle (delay) of the internal oscillator relative to
the incoming sync signal on the FS/SYNC pin. Any one of
six preset values can be selected as summarized in Table 4.
WhentwoormoreLTC3726devicesareusedinPolyPhase
systems, one device becomes the “Master” controller,
while the others are used as “Slaves.” Slave mode is
activated when the FB/PHASE pin is greater than approxi-
mately 2V. In this mode, the ITH pin becomes a high-
impedance input, allowing it to be driven by the Master
controller. In this way, equal inductor currents are estab-
lished in each of the individual phases. Also, in slave
mode, the soft-start charge/discharge currents are dis-
abled, allowing the Master device to control the charging
and discharging of the soft-start capacitor.
Table 4
FB/PHASE PIN
PHASE DELAY
OPERATING MODE
Master
V
V
< 2V
= V
0°
FB/PHASE
FB/PHASE
180°
60°
Slave
CC
200kΩ to V
100kΩ to V
Slave
CC
CC
90°
Slave
50kΩ to V
120°
Slave
CC
Inslavemode, thephaseangleofeachLTC3726canbeset
by using the FB/PHASE pin. This pin can be tied to VCC, or
W U U
U
APPLICATIO S I FOR ATIO
Start-Up Considerations
Although the exact start-up frequency on the primary side
is not critical, it is generally good practice to set this
approximately equal to the operating frequency on the
secondary side. The FS/IN– start-up resistor for the
LTC3705/LTC3725 may be selected using the following:
In self-starting applications, the LTC3705/LTC3725 will
initially begin the soft-start of the converter in an open-
loop fashion. After bias is obtained on the secondary side,
the LTC3726 assumes control and completes the soft-
start interval. In order to ensure that control is properly
transferred from the LTC3705/LTC3725 (primary-side) to
the LTC3726 (secondary-side), it is necessary to limit the
rate of rise on the primary-side soft-start ramp so that the
LTC3726 has adequate time to wake up and assume
control before the output voltage gets too high. This
condition is satisfied for many applications if the following
relationship is maintained:
3.2•1010
fPRI(Hz) =
RFS/IN– + 10k
In the event that the secondary-side circuitry fails to
properly start up and assume control of switching, there
areseveralfail-safemechanismstohelpavoidovervoltage
conditions. First, the LTC3705/LTC3725 contains a volt-
second clamp that will keep the primary-side duty cycle at
a level that cannot produce an overvoltage condition.
Second, the LTC3705/LTC3725 contains a time-out fea-
ture that will detect a FAULT if the LTC3726 fails to start up
and deliver PWM signals to the primary side. Finally, the
LTC3726hasanindependentovervoltagedetectioncircuit
that will crowbar the output of the DC/DC converter using
the synchronous MOSFET switch.
CSS,SEC ≤ CSS PRI
However, care should be taken to ensure that soft-start
transfer from primary-side to secondary-side is com-
pleted well before the output voltage reaches its target
value.Agooddesigngoalistohavethetransfercompleted
when the output voltage is less than one-half of its target
value. Note that the fastest output voltage rise time during
primary-side soft-start mode occurs with maximum input
voltage and minimum load current.
In the event that a short circuit is applied to the output of
the DC/DC converter prior to start-up, the LTC3726 will
generally not receive enough bias voltage to operate. In
this case, the LTC3705/LTC3725 will detect a FAULT for
Theopen-loopstart-upfrequencyontheLTC3705/LTC3725
is set by placing a resistor from the FB/IN+ pin to GND.
3726fb
11
LTC3726
W U U
U
APPLICATIO S I FOR ATIO
one of two reasons: 1) the start-up time-out feature will be
activated since the LTC3726 never sends signals to the
primary side or 2) the primary-side overcurrent circuit will
be tripped because of current buildup in the output induc-
tor. In either case, the LTC3705/LTC3725 will initiate a
shutdown followed by a soft-start retry. See the LTC3705/
LTC3725 data sheets for further details.
The linear regulator of Figure 2 should be designed to
handle the total expected ICC current. For self-starting
applications with the LTC3705/LTC3725, this regulator
will supply the operating bias current for both primary and
secondary side control circuitry. This current may be
approximated using the following:
ICC = IQ,3726 + MSfOSC G,SEC
Q
Bias Supply Generation
+2 MPfOSCQG,PRI + IQ,3705
(
)
Figure 2 shows a commonly used method of developing a
VCC bias supply for the LTC3726. During start-up, the
circuit of Figure 2 uses a peak detector followed by a
simple linear regulator to rapidly develop a VCC voltage for
the LTC3726. Note that this bias voltage must rise faster
than the open-loop soft-start that is initiated by the
LTC3705/LTC3725. This ensures that the LTC3726 be-
gins switching and assumes control of the soft-start
before the output voltage has risen substantially.
+ICORE + 20CSNUBVCC fOSC
whereIQ,3705 andIQ,3726 aretheoperatingsupplycurrents
oftheLTC3705/LTC3725andLTC3706,MP andMS arethe
number of power MOSFETs used on the primary and
secondary sides, QG,PRI and QG,SEC are the total gate
charge of the primary and secondary MOSFETs, ICORE is
the core loss current associated with the pulse trans-
former, and CSNUB is the snubber capacitor across the
pulse transformer. Note that the current used by the
primary side circuitry is doubled by the 2:1 turns ratio of
the pulse transformer. For the Typical Application circuit
of Figure 5, the total ICC delivered by the linear regulator
is 5mA + 3(50nC)(200kHz) + 2(2(38nC)(200kHz) + 2mA)
+ 3mA + 13mA = 85mA. To accommodate this current, Q1
should have a high Beta (>300), and R2 should be chosen
to supply adequate base current at low VIN (e.g., at 36V on
theconverterinput),whilemaintainingareasonablepower
dissipation in D2 at high VIN (72V).
The value of R1 should be chosen to keep the peak
chargingcurrentbelowthemaximum(non-repetitivepeak)
rating of diode D1, but should otherwise be as small as
CMPSH1-4
R1
1.2Ω D1
R2
5K
•
•
BIAS
C1
10µF
25V
Q1
FZT690B
WINDING
1
N
B
C2
1µF
16V
D2
7.5V
MAIN
TRANSFORMER
The turns ratio (NB) of the bias winding should be chosen
to ensure that there is adequate voltage to operate the
LTC3726 over the entire range for the DC/DC converter’s
input bus voltage (VBUS). This may be calculated using
PEAK CHARGER
LTC3726
REGULATOR
V
CC
3726 F02
R2⋅ICC
βQ1
VCC MIN + 1.2V +
(
)
Figure 2. Typical Bias Supply Configuration
NB =
VBUS MIN
(
)
possible to provide a rapid charging of capacitor C1. This
capacitor serves as a reservoir to provide bias voltage as VCC(MIN) can be as low as 5V (if this provides adequate
the LTC3726 begins switching and assumes control of the gate drive voltage to maintain acceptable efficiency), or as
soft-start from the LTC3705/LTC3725. Care should be high as 7V. For the Figure 2 circuit if VCC(MIN) = 6V, ICC
=
taken to ensure that capacitor C1 is adequately large to 85mA, and VBUS = 36V-72V, this would mean a turns ratio
provide enough hold-up time for the LTC3726 to assume NB = 0.24, or a 9:2 transformer. Generally, if the output
control and establish a firm bias voltage at the main voltage of the DC/DC converter is 3.3V or higher, then the
transformer.
main output of the power transformer (tied to SW node on
3726fb
12
LTC3726
W U U
APPLICATIO S I FOR ATIO
U
the LTC3726) can be used as the input to the peak charge
circuit of Figure 2. For lower output voltages, however, it
is normally necessary to use a dedicated bias winding to
generate adequate bias voltage for the LTC3726.
side or low side) is generally less noisy but dissipates
more power than sensing the switch current (Figures
3a and 3b). High side inductor current sensing pro-
vides a more convenient layout than low side (no split
ground plane), but can only be used for output volt-
ages up to 5.5V, due to the common mode limitations
of the current sense inputs (IS and IS ). For most
applications, low side switch current sensing will be a
good solution (Figure 3c).
Current Sensing
+
–
The LTC3726 provides considerable flexibility in cur-
rent sensing techniques. It supports two main meth-
ods: 1) resistive current sensing and 2) current trans-
former current sensing. Resistive current sensing is
generally simpler, smaller and less expensive, while
current transformer sensing is more efficient and gen-
erally appropriate for higher (>20A) output currents.
For resistive current sensing, the sense resistor may
be placed in any one of three different locations: high
side inductor, low side inductor or low side switch, as
shown in Figure 3. Sensing the inductor current (high
For high current applications where efficiency (power
dissipation) is very important, a current sense trans-
former may be used. As shown in Figure 3d, the IS– pin
shouldbetiedofftoVCC whenacurrentsensetransformer
is used. This causes the IS+ pin to become a single ended
(nondifferential) current sense input with a maximum
current sense voltage of 1.28V. Figure 3d shows a typical
application circuit using a current transformer.
+
I
+
I
•
•
•
•
S
S
LTC3726
78mV MAX
LTC3726
78mV MAX
–
–
I
S
I
S
3726 F03a
3726 F03b
Figure 3a. High Side Inductor:
Easier Layout, Low Noise, Accurate
Figure 3b. Low Side Inductor:
Accurate, Low Noise, High V
Capable
OUT
•
•
•
1.28V MAX
TRIP
+
I
I
S
•
•
LTC3726
–
+
–
I
S
5Ω TO
50Ω
V
CC
S
LTC3726
78mV MAX
•
I
S
3726 F03d
3726 F03c
Figure 3c. Switch Current Sensing: Easy Layout, Accurate,
Higher Efficiency, High V Capable
Figure 3d. Current Transformer:
Highest Efficiency, High V Capable
OUT
OUT
Figure 3. Current Sensing Techniques
3726fb
13
LTC3726
W U U
U
APPLICATIO S I FOR ATIO
PolyPhase Applications
+
+
V
IN
V
BIAS
V
OUT
Figure 4 shows the basic connections for using the
LTC3705/LTC3725 and LTC3726 in PolyPhase applica-
tions. One of the phases is always identified as the “mas-
ter,” while all other phases are “slaves.” For the LTC3705/
LTC3725 (primary side), the master monitors the VIN
voltageforundervoltage, performstheopen-loopstart-up
and supplies the initial VCC voltage for the master and all
slaves. TheLTC3705/LTC3725slavessimplystandbyand
wait for PWM signals from their respective pulse trans-
formers. Since the SS/FLT pins of each master and slave
LTC3705/LTC3725s are interconnected, a FAULT
(overcurrent, etc.) on any one of the phases will perform
a shutdown/restart on all phases together. The LTC3705/
LTC3725isputintoslavemodebyomittingtheresistoron
FS/IN–. For the LTC3726, the master performs soft-start
and voltage-loop regulation by driving all slaves to the
same current as the master using the ITH pins. Faults and
shutdowns are communicated via the interconnection of
the RUN/SS pins. The LTC3726 is put into slave mode by
tying the FB pin to VCC.
V
CC
NDRV
FS/SYNC
+
–
+
–
UVLO FB/IN
PT
PT
•
•
V
FB/PHASE
ITH
CC
FS/IN
SS/FLT
RUN/SS
LTC3726
(MASTER)
LTC3705/25
(MASTER)
–
V
IN
V
CC
RUN/SS FS/SYNC
+
NDRV
+
–
ITH
SS/FLT FB/IN
PT
•
•
V
CC
–
UVLO FS/IN
PT
FB/PHASE
LTC3705/25
(SLAVE)
LTC3726
(SLAVE)
3726 F05
Figure 4. Connections for PolyPhase Operation
3726fb
14
LTC3726
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165
±
.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
×
45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0°
– 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3726fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3726
U
TYPICAL APPLICATIO
+
+
V
IN
V
OUT
L2 1.2µH
10Ω
L1 1µH
MURS120
0.25W
1.2Ω
CMPSH1-4
T1
1nF
100V
•
•
Si7852DP
1nF
10Ω
100V
330µF
6.3V
×3
0.25W
1µF
100V
1µF
100V
x3
Si7336ADP
1µF
×2
9:2
Si7336ADP
Si7852DP
5K
FZT690B
MURS120
7.5V
2.2nF
250V
2mΩ
30mΩ
10µF
25V
2.2µF
16V
2W
1W
–
–
V
OUT
V
IN
CZT3019
100Ω
100k
BAS21
680pF
100Ω 100Ω
102k
1%
FQT7N10
0.22µF
L1: VISHAY IHLP-2525CZ-01
L2: COILCRAFT SER2010-122
T1: PULSE PA0807
1nF
FG SW SG
V
CC
–
I
S
FS/SYNC
365k
1%
T2: PULSE PA0297
+
I
S
NDRV
BOOST TG TS BG IS
FB/PHASE
+
+
T2
FB/IN
PT
LTC3726
PGND
UVLO
•
•
1µF
0.1µF
ITH
100Ω
470pF
1nF
LTC3705
V
CC
5k
–
–
2.2µF
25V
SS/FLT
FS/IN
PT
2:1
GND
SLP
MODE
RUN/SS
GND PGND VSLMT
680pF
20k
15k
1%
162k
22.6k
1%
33nF
33nF
100k
3726 F05
Figure 5. 36V-72V to 3.3V/20A Isolated Forward Converter
(See Typical Performance Characteristics)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1534
Ultralow Noise 2A Switching Regulator
Reduces Conducted and Radiated EMI, Low Switching Harmonics,
20kHz to 250kHz Switching Frequency
LT1619
Low Voltage Current Mode Controller
1.9V ≤ V ≤ 18V, 300kHz Operation, Boost, Flyback, SEPIC
IN
LT1681/LT3781
LT1725
Dual Transistor Synchronous Forward Controller
General Purpose Isolated Flyback Controller
Operation Up to 72V Maximum
No Optoisolator Required, Accurate Regulation Without User Trims,
50kHz to 250kHz Switching Frequency, SSOP-16 Package
LTC1871
LT1910
Wide Input Range, No R
™ Controller
Operation as Low as 2.5V Input, Boost, Flyback, SEPIC
8V to 48V Supply Range, Protected –15V to 60V Supply Transient
25W to 500W; Synchronous Controller
SENSE
Protected High Side MOSFET Driver
Single Switch Forward Controller
LT1952
LTC3440
LTC3704
Micropower Buck-Boost DC/DC Converter
Positive-to-Negative DC/DC Controller
Synchronous, Single Inductor, No Schottky Diode Required
2.5V ≤ V ≤ 36V, No R
Current Mode Operation,
SENSE
IN
Excellent Transient Response
LTC3705
LT3706
Two-Switch Forward Converter Gate Driver and Controller
PolyPhase Secondary Side Controller
Full Bridge Controller
Use with LTC3726, Isolated Power Supplies, High Speed Gate Drivers
Scalable Output Power; Self-Starting Architecture
Synchronous; ZVS Operation; 24-Pin SSOP
LTC3722
LTC3725
Two-Switch Forward Controller
On-Chip Gate-Driver; Fast Startup
No RSENSE is a trademark of Linear Technology Corporation.
3726fb
LT 0207 REV B • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
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