LTC3720 [Linear]
Single Phase VRM8.5 Current Mode Step-Down Controller; 单相VRM8.5电流模式降压型控制器
| 型号： | LTC3720 |
| 厂家： | 
Linear |
| 描述： | Single Phase VRM8.5 Current Mode Step-Down Controller |
| 文件： | 总24页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3720
Single Phase VRM8.5
Current Mode Step-Down Controller
U
FEATURES
DESCRIPTIO
■
5-Bit Programmable Output Voltage:
The LTC®3720 is a synchronous step-down switching
regulator controller for CPU power. An output voltage
between 1.05V and 1.825V is selected by a 5-bit code
(Intel VRM8.5 VID specification). The controller uses a
valley current control architecture to deliver very low duty
cycles without requiring a sense resistor. Operating fre-
quency is selected by an external resistor and is compen-
1.05V to 1.825V (VRM8.5)
■
No Sense Resistor Required
■
2% to 87% Duty Cycle at 200kHz
■
tON(MIN) ≤ 100ns
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Supports Active Voltage Positioning
True Current Mode Control
Stable with Ceramic COUT
sated for variations in VIN and VOUT.
Dual N-Channel MOSFET Synchronous Drive
Power Good Output Voltage Monitor
Wide VIN Range: 4V to 36V
±1% 0.8V Reference
Adjustable Current Limit
Adjustable Switching Frequency
Forced Continuous Control Pin
Programmable Soft-Start
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Micropower Shutdown: IQ < 30µA
Available in 28-LUead Narrow SSOP Package
Discontinuous mode operation provides high efficiency
operation at light loads. A forced continuous control pin
reduces noise and RF interference and can assist second-
ary winding regulation by disabling discontinuous mode
operation when the main output is lightly loaded.
Fault protection is provided by internal foldback current
limiting, an output overvoltage comparator and optional
short-circuitshutdowntimer.Soft-startcapabilityforsup-
ply sequencing is accomplished using an external timing
capacitor. The regulator current limit level is also user
programmable. Wide supply range allows operation from
4V to 36V at the input.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
APPLICATIO S
■
Power Supplies for Pentium® Processors
Notebook Computers and Servers
■
U
TYPICAL APPLICATIO
LTC3720
PGOOD
330k
Efficiency vs Output Current
I
ON
100
V
IN
V
= 1.45V
OUT
L1 = 1µH
0.1µF
V
IN
5V TO 24V
95
90
85
80
75
70
65
60
55
10µF
×5
IRF7811W
RUN/SS
TG
×2
L1
470pF
1µH
V
= 5V
V
OUT
I
SW
IN
V
TH
1.05V TO 1.825V
20A
20k
0.33µF
C
OUT
SGND BOOST
+
= 15V
IN
270µF
2V
V
CMDSH-3
CC
INTV
CC
×4
UPS840
+
+
VID4
VID3
VID2
VID1
VID0
SENSE
BG
4.7µF
IRF7811W
×3
C
OUT
: CORNELL DUBILIER
ESRE271M02B
L1: SUMIDA CEP125-IROMC
5-BIT VID
PGND
SENSE¯
3720 F01a
V
OSENSE
0.01
1
10
100
0.1
OUTPUT CURRENT (A)
3720 F01b
Figure 1. High Efficiency Step-Down Converter
3720f
1
LTC3720
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
TOP VIEW
Input Supply Voltage
VIN, ION ..................................................36V to –0.3V
Boosted Topside Driver Supply Voltage
1
2
BOOST
TG
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN/SS
V
ON
LTC3720EGN
3
SW
PGOOD
BOOST.................................................. 42V to –0.3V
SW, SENSE+ Voltages ................................. 36V to –5V
EXTVCC, (BOOST – SW), RUN/SS, VCC
VID0-VID4, PGOOD Voltages..................... 7V to –0.3V
FCB, VON, VRNG Voltages .......... INTVCC + 0.3V to –0.3V
ITH, VFB, VOSENSE Voltages....................... 2.7V to –0.3V
TG, BG, INTVCC, EXTVCC Peak Currents.................... 2A
TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA
Operating Ambient Temperature Range
LTC3720EGN (Note 2) ........................ –40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
+
4
SENSE
SENSE
PGND
BG
V
RNG
FCB
–
5
6
I
TH
7
SGND
8
INTV
I
CC
ON
9
V
IN
V
FB
10
11
12
13
14
EXTV
SGND
CC
V
CC
V
FB
VID4
VID3
VID2
V
OSENSE
VID0
VID1
GN PACKAGE
28-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
Input DC Supply Current
Normal
Shutdown Supply Current
Q
900
15
2000
30
µA
µA
V
Feedback Reference Voltage
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Feedback Pin Input Current
Error Amplifier Transconductance
Forced Continuous Threshold
Forced Continuous Pin Current
On-Time
I
= 1.2V (Note 4)
TH
●
●
0.792
0.800
0.002
–0.05
–5
0.808
V
%/V
%
FB
∆V
∆V
V
= 4V to 30V, I = 1.2V (Note 4)
FB(LINEREG)
IN
TH
I
I
= 0.5V to 1.9V (Note 4)
–0.3
±50
2
FB(LOADREG)
TH
I
nA
FB
g
= 1.2V (Note 4)
1.4
1.7
mS
V
m(EA)
TH
V
●
0.76
0.8
0.84
–2
FCB
I
t
V
= 0.8V
FCB
–1
µA
FCB
ON
I
I
= 60µA, V = 1.5V
200
425
250
500
300
575
ns
ns
ON
ON
ON
= 30µA, V = 1.5V
ON
t
t
Minimum On-Time
I
I
= 180µA, V = 0V
50
100
400
ns
ns
ON(MIN)
OFF(MIN)
ON
ON
ON
Minimum Off-Time
= 60µA, V = 1.5V
250
ON
V
Maximum Current Sense Threshold
V
V
V
= 1V, V = 0.76V
●
●
●
113
79
158
133
93
186
153
107
214
mV
mV
mV
SENSE(MAX)
RNG
RNG
RNG
FB
–
+
V
– V
= 0V, V = 0.76V
SENSE
SENSE
FB
= INTV , V = 0.76V
CC FB
V
Minimum Current Sense Threshold
V
V
V
= 1V, V = 0.84V
–67
–47
–93
mV
mV
mV
SENSE(MIN)
RNG
RNG
RNG
FB
–
+
V
– V
= 0V, V = 0.84V
SENSE
SENSE
FB
= INTV , V = 0.84V
CC FB
∆V
Output Overvoltage Fault Threshold
Output Undervoltage Fault Threshold
RUN Pin Start Threshold
5.5
520
0.8
7.5
600
1.5
9.5
680
2
%
FB(OV)
V
V
mV
FB(UV)
RUN/SS(ON)
●
V
3720f
2
LTC3720
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
4
MAX
UNITS
V
V
V
RUN Pin Latchoff Enable Threshold
RUN Pin Latchoff Threshold
Soft-Start Charge Current
Soft-Start Discharge Current
Undervoltage Lockout
RUN/SS Pin Rising
RUN/SS Pin Falling
4.5
RUN/SS(LE)
RUN/SS(LT)
RUN/SS(C)
RUN/SS(D)
3.5
–1.2
1.8
V
I
I
–0.5
0.8
–3
3
µA
µA
V
(UVLO)
V
V
Falling
Rising
●
●
3.4
3.5
3.9
4.0
V
V
IN
IN
IN
TG R
TG R
BG R
BG R
TG Driver Pull-Up On Resistance
TG Driver Pull-Down On Resistance
BG Driver Pull-Up On Resistance
BG Driver Pull-Down On Resistance
TG Rise Time
TG High
TG Low
BG High
BG Low
2
2
3
3
4
2
Ω
Ω
UP
DOWN
UP
3
Ω
1
Ω
DOWN
TG t
TG t
C
C
C
C
= 3300pF
= 3300pF
= 3300pF
= 3300pF
20
20
20
20
ns
ns
ns
ns
r
f
LOAD
LOAD
LOAD
LOAD
TG Fall Time
BG t
BG t
BG Rise Time
r
f
BG Fall Time
Internal V Regulator
CC
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
●
●
4.7
4.5
5
5.3
V
%
INTVCC
CC
IN
∆V
Internal V Load Regulation
I
I
I
= 0mA to 20mA, V = 4V
EXTVCC
–0.1
4.7
±2
LDO(LOADREG)
CC
CC
CC
CC
V
EXTV Switchover Voltage
= 20mA, V
= 20mA, V
Rising
= 5V
V
EXTVCC
CC
EXTVCC
EXTVCC
∆V
∆V
EXTV Switch Drop Voltage
150
200
300
mV
mV
EXTVCC
CC
EXTV Switchover Hysteresis
EXTVCC(HYS)
CC
PGOOD Output
∆V
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising
5.5
7.5
–7.5
1
9.5
–9.5
2
%
%
%
V
FBH
FB
Falling
–5.5
FBL
FB
Returning
FB(HYS)
FB
V
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGL
PGOOD
VID DAC
V
V
V
Operating Supply Voltage Range
VID0-VID4 Logic Threshold Voltage
VID0-VID4 Leakage Current
DAC Output Accuracy
3.1
0.4
5.5
2
V
V
CC
V
V
V
= 3.3V
CC
1.2
0.01
0
VID(T)
VID(LEAK)
-V
= V
±1
µA
%
VID0 VID4
CC
∆V
Programmed from
OSENSE
1.05V to 1.825V (Note 5), V = 5V
–0.25
0.25
OSENSE
CC
R
R
Pull-Up Resistance on VID
V
= 0.6V (Note 6)
DIODE
28
6
40
10
1
56
14
10
kΩ
kΩ
µA
PULLUP
Resistance from V
Supply Current
to V
FB
VID
OSENSE
I
(Note 7)
VCC
Note 1: Absolute Maximum Ratings are those values beyond which the life of
Note 5: The LTC3720 VID DAC is tested in a feedback loop that adjusts
toachieveaspecifiedfeedbackvoltage(V =0.8V)foreachDACVID
a device may be impaired.
V
OSENSE
code.
FB
Note2:TheLTC3720Eisguaranteedtomeetperformancespecificationsfrom
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.
Note 6: Each built-in pull-up resistor attached to VID inputs also has a series
diode connected to V to allow input voltages higher than the V supply
CC
CC
without damage or clamping. (See Operation section for further details.)
Note 3: T is calculated from the ambient temperature T and power
Note 7: Supply current is specified with all VID inputs floating. Due to the
internal pull-ups on the VID pins, the supply current will increase depending
on the number of grounded VID lines. Each grounded VID line will draw
J
A
dissipation P as follows:
D
LTC3720EGN: T = T + (P • 95°C/W)
J
A
D
approximately (V – 0.6V)/40k mA. (See Operation section for further
CC
Note 4: The LTC3720 is tested in a feedback loop that adjusts V to achieve
FB
details.)
a specified error amplifier output voltage (I ).
TH
3720f
3
LTC3720
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
On-Time vs ION Current
On-Time vs VON Voltage
10k
1k
300
200
100
0
1000
800
600
400
200
0
V
= 0V
2V
VON
I
= 30µA
V
=
ION
RNG
1.4V
1V
0.7V
0.5V
100
10
–100
–200
1
10
100
0
1.0
I
1.5
2.0
2.5
3.0
0.5
0
1
2
3
I
CURRENT (µA)
VOLTAGE (V)
ON
V
VOLTAGE (V)
TH
ON
3720 G02
3720 G01
3720 G02
Maximum Current Sense
Threshold vs VRNG Voltage
On-Time vs Temperature
Current Limit Foldback
150
125
300
250
200
150
100
50
300
250
200
150
V = 1V
RNG
I
= 30µA
VON
ION
V
= 0V
100
75
50
25
0
100
50
0
0
0
0.2
0.4
(V)
0.6
0.8
50
TEMPERATURE (°C)
100 125
0.5
0.75
1.0
V
1.25
1.5
1.75
2.0
–50 –25
0
25
75
V
VOLTAGE (V)
FB
RNG
3720 G05
3720 G06
3720 G04
Maximum Current Sense
Threshold vs RUN/SS Voltage
Maximum Current Sense
Threshold vs Temperature
Feedback Reference Voltage
vs Temperature
150
125
150
140
130
120
110
100
0.82
0.81
0.80
0.79
V
RNG
= 1V
V
RNG
= 1V
100
75
50
25
0
0.78
1.5
2
2.5
3
3.5
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
RUN/SS VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3729 G07
3720 G08
3720 G09
3720f
4
LTC3720
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input and Shutdown Currents
vs Input Voltage
Error Amplifier gm vs Temperature
INTVCC Load Regulation
2.0
1.8
1.6
1.4
1.2
1.0
1200
1000
800
60
50
40
30
20
10
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
EXTV OPEN
CC
SHUTDOWN
600
400
200
0
EXTV = 5V
CC
–50 –25
0
25
50
75 100 125
0
5
10
15
20
25
30
35
0
10
20
30
40
50
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INTV LOAD CURRENT (mA)
CC
3720 G10
3720 G11
3720 G12
EXTVCC Switch Resistance
vs Temperature
RUN/SS Pin Current
vs Temperature
FCB Pin Current vs Temperature
10
8
3
2
0
–0.25
–0.50
–0.75
PULL-DOWN CURRENT
6
1
4
0
–1.00
–1.25
–1.50
PULL-UP CURRENT
2
–1
0
–2
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3720 G13
3720 G14
3720 G15
RUN/SS Latchoff Thresholds
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
5.0
4.5
4.0
3.5
4.0
3.5
3.0
2.5
LATCHOFF ENABLE
LATCHOFF THRESHOLD
3.0
2.0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (C)
3720 G16
3720 G17
3720f
5
LTC3720
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
(Forced Continuous Mode)
Transient Response
(Discontinuous Mode)
VOUT
50mV/DIV
VOUT
50mV/DIV
IL
IL
10A/DIV
10A/DIV
20µs/DIV
LOAD STEP = 0A TO 15A
3720 G18
20µs/DIV
3720 G19
LOAD STEP = 1A TO 15A
V
IN = 15V
VIN = 15V
VOUT = 1.5V
VOUT = 1.5V
FCB = 0V
FIGURE 7 CIRCUIT
FCB = INTVCC
FIGURE 7 CIRCUIT
U
U
U
PI FU CTIO S
ITH (Pin 6): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
VON (Pin 2): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to VOUT. The
comparatorinputdefaultsto0.7Vwhenthepinisgrounded,
2.4V when the pin is tied to INTVCC.
SGND(Pin7, 10):SignalGround. Allsmall-signalcompo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
ION (Pin 8): On-Time Current Input. Tie a resistor from VIN
tothispintosettheone-shottimercurrentandtherebyset
the switching frequency.
PGOOD (Pin 3): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±7.5% of the regulation point.
VFB (Pin 9, 11): Error Amplifier Feedback Input. This pin
connectstoboththeerroramplifierinputandtotheoutput
of the internal resistive divider. It can be used to attach
additional compensation components if desired.
V
RNG (Pin 4): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi-
mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
VOSENSE (Pin 12): Output Voltage Sense. The output
voltage connects here to the input of the internal resistive
feedback divider.
VID0-VID4 (Pins 13, 14, 15, 16, 17): VID Digital Inputs.
The voltage identification (VID) code sets the internal
feedbackresistordividerratiofordifferentoutputvoltages
as shown in Table 1. If unconnected, the pins are pulled
high by internal 40k pull-up resistors.
FCB (Pin 5): Forced Continuous Input. Tie this pin to
ground to force continuous synchronous operation at low
loadortoINTVCC toenablediscontinuousmodeoperation
at low load.
3720f
6
LTC3720
U
U
U
PI FU CTIO S
VCC (Pin18):PowerSupplyVoltageforVID.Rangeisfrom
SENSE– (Pin 24): Current Sense Comparator Input. The
(–) input is normally connected to PGND.
3.1V to 5.5V.
EXTVCC (Pin 19): External VCC Input. When EXTVCC ex-
ceeds 4.7V, an internal switch connects this pin to INTVCC
and shuts down the internal regulator so that controller
andgatedrivepowerisdrawnfromEXTVCC.Donotexceed
7V at this pin and ensure that EXTVCC < VIN.
SENSE+ (Pin 25): Current Sense Comparator Input. The
(+) input to the current comparator is normally connected
to the SW node unless using a sense resistor (see Appli-
cations Information).
SW (Pin 26): Switch Node. The (–) terminal of the boot-
strap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to VIN.
VIN (Pin 20): Main Input Supply. Decouple this pin to
PGND with an RC filter (1Ω, 0.1µF).
INTVCC (Pin 21): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. De-
couple this pin to power ground with a minimum of 4.7µF
low ESR tantalum capacitor.
TG (Pin 27): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim-
posed on the switch node voltage SW.
BOOST (Pin 28): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
BG (Pin 22): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
PGND (Pin 23):Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of CVCC and the (–) terminal of CIN.
3720f
7
LTC3720
U
U
W
FU CTIO AL DIAGRA
R
ON
V
IN
20
V
IN
2
V
8
I
ON
5
FCB
19 EXTV
CC
ON
4.7V
+
C
IN
1µA
+
–
0.7V
2.4V
0.8V
REF
0.8V
1
t
5V
REG
+
–
OST
BOOST
28
F
V
VON
=
ION
(10pF)
R
S
ON
C
B
TG
I
Q
FCNT
M1
27
SW
26
ON
20k
+
–
+
–
+
L1
SENSE
25
SWITCH
LOGIC
I
I
D
B
CMP
REV
INTV
21
CC
SHDN
OV
+
+
C
OUT
C
VCC
1.4V
BG
22
M2
V
RNG
PGND
23
4
×
–
SENSE
24
0.7V
PGOOD
3
3.3µA
V
OSENSE
12
1
R2
10k
0.74V
240k
+
–
1V
×5 (ALL VID PINS)
Q2 Q4
UV
OV
V
CC
Q6
40k
13
I
THB
VID0
Q3
Q1
+
–
VID1
VID2
VID3
VID4
14
15
16
Q5
+
–
0.86V
VID
DAC
0.8V
RUN
SHDN
SS
–
+
17
18
1.2µA
6V
EA
×4
–
+
V
CC
0.6V
R1
SGND
C
C1
C
SS
I
TH
RUN/SS
1
SGND
6
V
FB
11
9
V
FB
10
7
0.8V
0.6V
R
C
3711 FD
3720f
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LTC3720
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±7.5% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned
off and M2 is turned on and held on until the overvoltage
condition clears.
The LTC3720 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current com-
parator ICMP trips, restarting the one-shot timer and Foldback current limiting is provided if the output is
initiating the next cycle. Inductor current is determined shorted to ground. As VFB drops, the buffered current
by sensing the voltage between the SENSE– and SENSE+
thresholdvoltageITHB ispulleddownbyclampQ3toa1V
pins using either the bottom MOSFET on-resistance or a level set by Q4 and Q6. This reduces the inductor valley
separate sense resistor. The voltage on the ITH pin sets current level to one sixth of its maximum value as VFB
the comparator threshold corresponding to inductor approaches 0V.
valley current. The error amplifier EA adjusts this voltage
Pulling the RUN/SS pin low forces the controller into its
by comparing the feedback signal VFB from the output
shutdown state, turning off both M1 and M2. Releasing
voltage with an internal 0.8V reference. The feedback
the pin allows an internal 1.2µA current source to charge
upanexternalsoft-startcapacitorCSS. Whenthisvoltage
voltage is derived from the output voltage by a resistive
divider DAC that is set by the VID code pins VID0-VID4.
reaches 1.5V, the controller turns on and begins switch-
If the load current increases, it causes a drop in the
ing, but with the ITH voltage clamped at approximately
feedbackvoltagerelativetothereference. TheITH voltage
0.6V below the RUN/SS voltage. As CSS continues to
thenrisesuntiltheaverageinductorcurrentagainmatches
charge, the soft-start current limit is removed.
the load current.
INTVCC/EXTVCC Power
Atlowloadcurrents,theinductorcurrentcandroptozero
andbecomenegative.Thisisdetectedbycurrentreversal
comparator IREV which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.8V) to
initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.8V, forcing continuous synchronous operation.
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re-
chargedfromINTVCC throughanexternalSchottkydiode
DB when the top MOSFET is turned off. When the EXTVCC
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VIN. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
ahighefficiencysourceconnectedtoEXTVCC, suchasan
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the input voltage is low and INTVCC drops below 3.5V,
undervoltage lockout circuitry prevents the power
switches from turning on.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintainregulation. Theone-shottimergeneratesanon-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN and VOUT. The nominal frequency can be adjusted
with an external resistor RON.
3720f
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LTC3720
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APPLICATIO S I FOR ATIO
The basic LTC3720 application circuit is shown in
Figure 1. External component selection is primarily de-
termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3720 can use either a sense resistor or
theon-resistanceofthesynchronouspowerMOSFETfor
determining the inductor current. The desired amount of
ripple current and operating frequency largely deter-
mines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and COUT is chosen with low enough ESR to meet the
output voltage ripple and transient specification.
between the SENSE+ and SENSE– pins. Kelvin connec-
tions at the sense resistor ensure accurate current sens-
ing. Using a sense resistor provides a well defined current
limit, but adds cost and reduces efficiency. Alternatively,
one can eliminate the sense resistor and use the bottom
MOSFET as the current sense element by simply connect-
ing the SENSE+ pin to the switch node SW at the drain of
the bottom MOSFET and keep SENSE– connected to
PGND. This improves efficiency, but one must carefully
choose the MOSFET on-resistance as discussed below.
Power MOSFET Selection
The LTC3720 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage
acrossasenseresistancethatappearsbetweentheSENSE–
and SENSE+ pins. The maximum sense voltage is set by
the voltage applied to the VRNG pin and is equal to
approximately (0.133)VRNG. The current mode control
loop will not allow the inductor current valleys to exceed
(0.133)VRNG/RSENSE. In practice, one should allow some
margin for variations in the LTC3720 and external compo-
nent values and a good guide for selecting the sense
resistance is:
the power MOSFETs are the breakdown voltage V(BR)DSS
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfercapacitanceCRSS andmaximumcurrentIDS(MAX)
,
.
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3720 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-
resistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
VRNG
10•IOUT(MAX)
RSENSE
=
An external resistive divider from INTVCC can be used to
set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.
RSENSE
RDS(ON)(MAX)
=
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum temperature of 100°C, using a
value ρT = 1.3 is reasonable.
Connecting the SENSE+ and SENSE– Pins
TheLTC3720canbeusedwithorwithoutasenseresistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect
the SENSE+ pin to the source of the bottom MOSFET and
the SENSE– pin to PGND so that the resistor appears
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
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2.0
1.5
1.0
0.5
0
TheoperatingfrequencyofLTC3720applicationsisdeter-
mined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the VON
pin according to:
V
tON
=
VON (10pF)
I
ION
Tying a resistor RON from VIN to the ION pin yields an on-
time inversely proportional to VIN. For a step-down con-
verter, this results in approximately constant frequency
operation as the input supply varies:
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3720 F02
Figure 2. RDS(ON) vs. Temperature
VOUT
VVON RON(10pF)
f =
Hz
[ ]
the load current. When the LTC3720 is operating in
continuous mode, the duty cycles for the MOSFETs are:
Toholdfrequencyconstantduringoutputvoltagechanges,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V.
VOUT
DTOP
DBOT
=
=
V
IN
V – VOUT
IN
V
IN
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
Because the voltage at the ION pin is about 0.7V, the
currentintothispinisnotexactlyinverselyproportionalto
VIN, especially in applications with lower input voltages.
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
PTOP = DTOP OUT(MAX)
I
2 ρT(TOP) RDS(ON)(MAX)
+ k VIN IOUT(MAX) CRSS
PBOT = DBOT OUT(MAX)
2 ρT(BOT) RDS(ON)(MAX)
2
f
I
Both MOSFETs have I2R losses and the top MOSFET
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottomMOSFETlossesaregreatestwhenthebottomduty
cycle is near 100%, during a short-circuit or at high input
voltage.
5V
0.7V
RON2
=
RON
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
loadcurrentincreases.Bylengtheningtheon-timeslightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
3720f
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LTC3720
APPLICATIO S I FOR ATIO
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R
R
VON1
3k
VON1
30k
V
V
ON
V
OUT
V
OUT
ON
C
R
VON
C
VON2
VON
R
0.01µF
VON2
100k
10k
10k
0.01µF
LTC3720
TH
LTC3720
TH
INTV
CC
R
R
C
C
Q1
2N5087
I
I
C
C
C
C
3720 F03a
3720 F03b
(3a)
(3b)
Figure 3. Correcting Frequency Shift with Load Current Changes
shown in Figure 3a. Place capacitance on the VON pin to
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b.
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
orKoolMµ® cores.Avarietyofinductorsdesignedforhigh
current, lowvoltageapplicationsareavailablefrommanu-
facturerssuchasSumida,Panasonic,Coiltronics,Coilcraft
and Toko.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
ofthebottomMOSFETfromturningonandstoringcharge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to be
effective,theinductancebetweenitandthebottomMOSFET
must be as small as possible, mandating that these
components be placed adjacently. The diode can be omit-
ted if the efficiency loss is tolerable.
VOUT
fL
VOUT
V
IN
∆IL =
1−
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
VOUT
f∆IL(MAX)
VOUT
V
IN(MAX)
L =
1−
VOUT
V
IN
V
IN
VOUT
IRMS IOUT(MAX)
– 1
Kool Mµ is a registered trademark of Magnetics, Inc.
3720f
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This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
basedononly2000hoursoflifewhichmakesitadvisable
to derate the capacitor.
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom-
mended to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (CB, DB)
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple ∆VOUT is approximately
bounded by:
1
∆VOUT ≤ ∆IL ESR +
8fCOUT
Discontinuous Mode Operation and FCB Pin
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.8V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which
current reverses and discontinuous operation begins de-
pends on the amplitude of the inductor ripple current and
will vary with changes in VIN. Tying the FCB pin below the
0.8Vthresholdforcescontinuoussynchronousoperation,
allowing current to reverse at light loads and maintaining
high frequency operation.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESRcharacteristicsbutcanhaveahighvoltagecoefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to signifi-
cant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output VSEC is nor-
mally set as shown in Figure 4 by the turns ratio N of the
transformer. However, if the controller goes into discon-
tinuous mode and halts switching due to a light primary
load current, then VSEC will droop. An external resistor
divider from VSEC to the FCB pin sets a minimum voltage
VSEC(MIN) below which continuous operation is forced
until VSEC has risen above its minimum.
R4
R3
VSEC(MIN) = 0.8V 1+
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APPLICATIO S I FOR ATIO
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To further limit current in the event of a short circuit to
ground, the LTC3720 includes foldback current limiting. If
the output falls by more than 25%, then the maximum
sense voltage is progressively lowered to about one sixth
of its full value.
V
IN
+
C
V
IN
SEC
V
IN
1N4148
TG
•
OPTIONAL
EXTV
+
LTC3720
EXTV
C
SEC
CC
SW
1µF
CC
CONNECTION
5V < V < 7V
V
OUT
R4
R3
•
SEC
T1
1:N
+
+
SENSE
C
OUT
FCB
Minimum Off-time and Dropout Operation
BG
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3720 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 350ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON +tOFF(MIN)).Ifthemaximumdutycycleisreached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
SGND
PGND
3720 F04
Figure 4. Secondary Output Loop and EXTVCC Connection
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3720, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
t
ON + tOFF(MIN)
V
= VOUT
IN(MIN)
tON
Output Voltage Programming
The output voltage is digitally set to levels between 1.05V
and 1.825V using the voltage identification (VID) inputs
VID0-VID4. An internal 5-bit DAC configured as a preci-
sion resistive voltage divider sets the output voltage in
increments according to Table 1. The VID codes are com-
patible with Intel VRM8.5 processor specifications. Each
VID input is pulled up by an internal 40k pull-up resistor
from the INTVCC supply and includes a series diode to
prevent damage from VID inputs that exceed the supply.
VSNS(MAX)
R
1
ILIMIT
=
+ ∆IL
DS(ON) ρT* 2
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3720. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF low ESR capacitor. Good bypassing is
necessary to supply the high transient currents required
by the MOSFET gate drivers. Applications using large
MOSFETs with a high input voltage and high frequency of
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
liesaboveit.ConsulttheMOSFETmanufacturerforfurther
guidelines.
*Use RSENSE value if a sense resistor is connected between SENSE+ and SENSE–.
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Table 1. VID Output Voltage Programming
operation may cause the LTC3720 to exceed its maximum
junction temperature rating or RMS current rating. Most
of the supply current drives the MOSFET gates unless an
external EXTVCC source is used. In continuous mode
operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)).
The junction temperature can be estimated from the
equations given in Note 3 of the Electrical Characteristics.
For example, the LTC3720EGN is limited to less than
19mA from a 30V supply:
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
(V)
OUT
1.250V
1.275V
1.200V
1.225V
1.150V
1.175V
1.100V
1.125V
1.050V
1.075V
1.800V
1.825V
1.750V
1.775V
1.700V
1.725V
1.650V
1.675V
1.600V
1.625V
1.550V
1.575V
1.500V
1.525V
1.450V
1.475V
1.400V
1.425V
1.350V
1.375V
1.300V
1.325V
TJ = 70°C + (19mA)(30V)(95°C/W) = 125°C
Forlargercurrents, considerusinganexternalsupplywith
the EXTVCC pin.
EXTVCC Connection
The EXTVCC pin can be used to provide MOSFET gate drive
and control power from an external source during normal
operation. Whenever the EXTVCC pin is above 4.7V the
internal 5V regulator is shut off and an internal 50mA P-
channelswitchconnectstheEXTVCC pintoINTVCC.INTVCC
power is supplied from EXTVCC until this pin drops below
4.5V. Do not apply more than 7V to the EXTVCC pin and
ensure that EXTVCC ≤ VIN. The following list summarizes
the possible connections for EXTVCC:
1. EXTVCC grounded. INTVCC is always powered from the
internal 5V regulator.
2. EXTVCC connected to an external supply. A high effi-
ciency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
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INTV
External Gate Drive Buffers
CC
R
*
SS
The LTC3720 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
higher frequencies requiring greater RMS currents will
benefit from using external gate drive buffers such as the
LTC1693. Alternately, the external buffer circuit shown in
Figure 5 can be used. Note that the bipolar devices reduce
the signal swing at the MOSFET gate and benefit from an
increased EXTVCC voltage of about 6V.
V
IN
RUN/SS
3.3V OR 5V
RUN/SS
*
D2*
R
SS
D1
C
SS
C
SS
3720 F06
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(6a)
(6b)
Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
BOOST
Q1
INTV
CC
backuntiltheoutputreaches75%ofitsfinalvalue. Thepin
can be driven from logic as shown in Figure 6. Diode D1
reduces the start delay while allowing CSS to charge up
slowly for the soft-start function.
Q3
FMMT619
FMMT619
10Ω
10Ω
GATE
OF M1
GATE
OF M2
TG
BG
Q2
FMMT720
Q4
FMMT720
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the con-
troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
SW
PGND
3720 F05
Figure 5. Optional External Gate Driver
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3720 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3720 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:
The overcurrent protection timer requires that the soft-
start timing capacitor CSS be made large enough to guar-
antee that the output is in regulation by the time CSS has
reachedthe4Vthreshold.Ingeneral,thiswilldependupon
the size of the output capacitance, output voltage and load
currentcharacteristic.Aminimumsoft-startcapacitorcan
be estimated from:
1.5V
tDELAY
=
CSS = 1.3s/µF CSS
(
)
1.2µA
CSS > COUT VOUT RSENSE (10–4 [F/V s])
When the voltage on RUN/SS reaches 1.5V, the LTC3720
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a short-
circuit by the current foldback circuitry and latchoff
3720f
16
LTC3720
W U U
APPLICATIO S I FOR ATIO
U
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5µA to the RUN/SS pin. The additional
current prevents the discharge of CSS during a fault and
also shortens the soft-start period. Using a resistor to VIN
as shown in Figure 6a is simple, but slightly increases
shutdown current. Connecting a resistor to INTVCC as
shown in Figure 6b eliminates the additional shutdown
current, but requires a diode to isolate CSS. Any pull-up
network must be able to pull RUN/SS above the 4.5V
maximum threshold that arms the latchoff circuit and
overcome the 4µA maximum discharge current.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply-
ing INTVCC current through the EXTVCC pin from a high
efficiency source, such as an output derived boost net-
work or alternate supply if available.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3720 circuits:
Whenmakingadjustmentstoimproveefficiency,theinput
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
resistances of L and the board traces to obtain the DC I2R
loss.Forexample,ifRDS(ON) =0.01ΩandRL =0.005Ω,the
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
aloadstepoccurs,VOUT immediatelyshiftsbyanamount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
Figure 7 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
2
Transition Loss (1.7A–1) VIN IOUT CRSS
f
3720f
17
LTC3720
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U
APPLICATIO S I FOR ATIO
Design Example
186mV
1
2
ILIMIT
≥
+
4.7A = 18A
(
)
As a design example, take a supply with the following
specifications:VIN =7Vto24V(15Vnominal),VOUT=1.05V
to1.825Vwithtypicalat1.5V, IOUT(MAX) =15A, f=300kHz.
0.5 1.6 0.012Ω
(
)( )(
)
and double check the assumed TJ in the MOSFET:
First, calculate the timing resistor with VON = VOUT
:
2
24V – 1.5V 21.7A
1
PBOT
=
1.6 0.012Ω = 2.12W
(
)(
)
RON
=
= 330k
24V
2
300kHz 10pF
(
)(
)
TJ = 50°C + (2.12W)(50°C/W) = 156°C
and choose the inductor for about 40% ripple current at
the maximum VIN:
Because the top MOSFET is on for such a short time, a
single IRF7811A will be sufficient. Checking its power
dissipation at current limit with ρ90°C = 1.3:
1.5V
1.5V
24V
L =
1−
= 0.8µH
300kHz 0.4 15A
(
)( )(
)
2
1.5V
P
BOT
=
21.7A 1.3 0.012Ω +
(
) ( )(
)
Selecting a standard value of 1µH results in a maximum
ripple current of:
24V
2
) (
1.7 24V 21.7A 60pF 300kHz
(
)(
)(
)(
)
1.5V
1.5V
24V
= 0.46W + 0.38W = 0.84W
∆IL =
1–
= 4.7A
300kHz 1µH
(
)(
)
TJ = 50°C + (0.84W)(50°C/W) = 92°C
Next, choose the synchronous MOSFET switch. Because
of the narrow duty cycle and large current, a single SO-8
MOSFETwillhavedifficultydissipatingthepowerlostinthe
switch. Choosing two IRF7811A (RDS(ON) = 0.013Ω, CRSS
= 60pF, θJA = 50°C/W) yields a nominal sense voltage of:
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
VSNS(NOM) = (15A)(0.5)(1.3)(0.012Ω) = 117mV
Tying VRNG to INTVCC will set the current sense voltage
range for a nominal value of 140mV with current limit
occurring at 186mV. To check if the current limit is
acceptable,assumeajunctiontemperatureofabout100°C
above a 50°C ambient with ρ150°C = 1.6:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (4.7A) (0.005Ω) = 24mV
3720f
18
LTC3720
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APPLICATIO S I FOR ATIO
U
However, a 0A to 15A load step will cause an output
error budget for the load step. This allows one to reduce
the number of output capacitors by relaxing the ESR
requirement.
change of up to:
∆VOUT(STEP) = ∆ILOAD (ESR) = (15A) (0.005Ω) = 75mV
In the design example, Figure 7, five 0.025Ω capacitors
are required in parallel to keep the output voltage within
tolerance. Using active voltage positioning, the same
specification can be met with only three capacitors. In this
case, the load step will cause an output voltage change of:
The complete circuit is shown in Figure 7.
Active Voltage Positioning
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage above the regulation point at zero load, and below
the regulation point at full load, one can use more of the
1
∆VOUT(STEP) = 15A
0.025Ω = 125mV
(
)
(
)
3
V
INT V
IN
CC
7V TO 24V
100k
POWER GOOD
R
F
C
IN
10Ω
10µF
50V
×3
C
B
0.33µF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
M1
IRF7811A
RUN/SS
BOOST
TG
C
SS
V
ON
0.1µF
PGOOD
SW
C
+
C2
INT V
V
RNG
SENSE
L1
1µH
CC
100pF
V
OUT
–
1.05V TO 1.825V
15A
FCB
SENSE
D
B
C
500pF
C1
CMDSH-3
UPS840
I
TH
PGND
BG
R
C
20k
LTC3720
SGND
C
OUT
+
270µF
M2
I
ON
INTV
CC
2V
×5
IRF7811A
C
FB
100pF
×2
C
ION
0.01µF
330k
V
FB
1Ω
V
IN
10
11
12
13
14
SGND
4.7µF
6.3V
EXTV
V
CC
CC
C2 6.8nF
SGND
V
IN
V
FB
C
F
0.1µF
V
VID4
VID3
VID2
OSENSE
VID0
VID1
3720 F07
Figure 7. 15A CPU Core Voltage Regulator at 300kHz
3720f
19
LTC3720
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U
APPLICATIO S I FOR ATIO
Solving for this resistance value:
By positioning the output voltage 60mV above the regula-
tion point at no load, it will only drop 65mV below the
regulationpointaftertheloadstep,wellwithinthe±100mV
tolerance.
V
OUT ∆ITH
RVP
=
=
(0.8V)gm ∆VOUT
(1.5V)(1.08V)
(0.8V)(1.7mS)(125mV)
Implementingactivevoltagepositioningrequiressettinga
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resis-
tance, it is prudent to use a sense resistor with active
voltage positioning. In order to minimize power lost in this
resistor, a low value is chosen of 0.003Ω. The nominal
sense voltage will now be:
= 9.53k
The gain setting resistance RVP is implemented with two
resistors, RVP1 connected from ITH to ground and RVP2
connectedfromITH toINTVCC. Theparallelcombinationof
these resistors must equal RVP and their ratio determines
nominal value of the ITH pin voltage when the error
amplifier input is zero. To center the load line around the
regulation point, the ITH pin voltage must be set to corre-
spond to half the output current. The relation between ITH
voltage and the output current is:
V
SNS(NOM) = (0.003Ω)(15A) = 45mV
To maintain a reasonable current limit, the voltage on the
VRNG pin is reduced to its minimum value of 0.5V, corre-
sponding to a 50mV nominal sense voltage.
Next, the gain of the LTC3720 error amplifier must be
determined. ThechangeinITH voltageforacorresponding
change in the output current is:
12V
VRNG
1
ITH(NOM)
=
=
RSENSE OUT
I
– ∆IL + 0.8V
2
1
12V
0.5V
12V
0.003Ω 7.5A – 4.7A + 0.8V
∆ITH
=
RSENSE ∆IOUT
(
)
2
VRNG
= 1.17V
= 24 0.003Ω 15A = 1.08V
( )(
)(
)
Solving for the required values of the resistors:
The corresponding change in the output voltage is deter-
mined by the gain of the error amplifier and feedback
divider. The LTC3720 error amplifier has a transconduc-
tancegm thatisconstantoverbothtemperatureandawide
± 40mV input range. Thus, by connecting a load resis-
tance RVP to the ITH pin, the error amplifier gain can be
precisely set for accurate active voltage positioning.
5V
5V
RVP1
=
RVP
=
9.53k
5V – ITH(NOM)
5V – 1.17V
= 12.44k
5V
ITH(NOM)
5V
RVP2
=
RVP
=
9.53k = 40.73k
1.17V
0.8V
VOUT
∆ITH = gmRVP
∆VOUT
3720f
20
LTC3720
W U U
APPLICATIO S I FOR ATIO
U
The modified circuit is shown in Figure 8. Figures 9 and 10
show the transient response without and with active
voltagepositioning.Bothcircuitseasilystaywithin±100mV
of the 1.5V output. However, the circuit with active voltage
positioning accomplishes this with only three output ca-
pacitors rather than five. Refer to Linear Technology
Design Solutions 10 for additional information about
active voltage positioning.
V
INT V
IN
CC
5V TO 24V
R
100k
POWER GOOD
F
C
IN
1Ω
C
10µF
35V
×3
SS
0.1pF
C
0.33µF
B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
RUN/SS
BOOST
TG
M1
IRF7811A
V
ON
R
R
RNG1
4.99k
RNG2
45.3k
PGOOD
SW
+
INT V
CC
V
L1
1µH
SENSE
RNG
R
VP2
40.2k
V
OUT
–
1.05V TO 1.825V
15A
FCB
SENSE
D
B
CMDSH-3
C
180pF
C
R
12.4k
VP1
I
PGND
BG
TH
M2
LTC3720
IRF7811A
SGND
C
OUT
+
×2
270µF
I
INTV
CC
2V
×3
ON
+
C
ION
0.01µF
UPS840
4.7µF
6.3V
V
330k
V
FB
R
SENSE
0.003Ω
IN
10
11
12
13
14
SGND
EXTV
V
CC
CC
SGND
V
IN
V
FB
C
FB
100pF
C
F
0.1µF
V
VID4
VID3
VID2
OSENSE
VID0
VID1
3720 F08
Figure 8. 15A CPU Core Voltage Regulator with Active Voltage Positioning at 300kHz
VOUT
100mV/DIV
1.5V
VOUT
100mV/DIV
1.5V
IL
IL
10A/DIV
10A/DIV
COUT = 5 × 270µF
VIN = 15V
FIGURE 7 CIRCUIT
20µs/DIV
3720 F09
COUT = 3 × 270µF
VIN = 15V
FIGURE 8 CIRCUIT
20µs/DIV
3720 F10
Figure 9. Normal Transient Response (COUT = 5 × 270µF)
Figure 10. Transient Response with Active
Voltage Positioning (COUT = 3 × 270µF)
3720f
21
LTC3720
W U U
U
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the controller.
These items are also illustrated in Figure 11.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
onepointwhichisthentiedtothePGNDpinclosetothe
source of M2.
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Connect the VIN pin decoupling capacitor CF closely to
the VIN and PGND pins.
• Place M2 as close to the controller as possible, keeping
the SENSE–, BG and SENSE+ traces short.
• VID0-VID4 interface circuitry must return to SGND.
•
Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current. Minimize the loop area formed by CIN, M1 and
M2.
V
INT V
IN
CC
R
F
10Ω
POWER GOOD
C
IN
C
B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
RUN/SS
BOOST
TG
M1
C
C
SS
V
ON
PGOOD
SW
+
V
SENSE
L1
RNG
C2
INT V
1µH
CC
–
V
FCB
SENSE
OUT
C
C1
D
B
I
PGND
BG
TH
M2
R
C
LTC3720
SGND
D1
C
+
ION
C
OUT
I
INTV
CC
ON
+
R
ON
V
V
FB
IN
10
11
12
13
14
SGND
EXTV
V
CC
CC
SGND
V
IN
V
FB
C
F
V
VID4
VID3
VID2
OSENSE
VID0
VID1
3720 F11
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 11. LTC3720 Layout Diagram
3720f
22
LTC3720
U
PACKAGE DESCRIPTIO
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14
.004 – .009
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.053 – .069
(1.351 – 1.748)
× 45°
(0.102 – 0.249)
.0075 – .0098
(0.191 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN28 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3720f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
23
LTC3720
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1628-PG
Dual, 2-Phase Synchronous Step-Down Controller
Power Good Output, Minimum Input/Output Capacitors,
3.5V ≤ V ≤ 36V
IN
LTC1628-SYNC
Dual, 2-Phase Synchronous Step-Down Controller
Synchronizable 150kHz to 300kHz
LTC1709-7/-8/-8.5/-9 2-Phase Synchronous Step-Down Controllers
with 5-Bit VID
Up to 42A Outputs, Various VID Tables, Mobile, Desktop,
Server, 3.5V ≤ V ≤ 36V
IN
LTC1735
Synchronous Step-Down Controller
Burst ModeTM Operation, 16-Pin Narrow SSOP,
3.5V ≤ V ≤ 36V
IN
LTC1736
LTC1772
LTC1773
Synchronous Step-Down Controller with 5-Bit VID
SOT-23 Step-Down Controller
Mobile VID, 0.925V ≤ V
≤ 2V, 3.5V ≤ V ≤ 36V
OUT IN
Current Mode, 550kHz, Very Small Solution Size
Up to 95% Efficiency, 550kHz, 2.65V ≤ V ≤ 8.5V,
Synchronous Step-Down Controller
IN
0.8V ≤ V
≤ V , Synchronizable to 750kHz
OUT
IN
LTC1778/LTC1778-1 No R
LTC3778
Synchronous Step-Down Controllers
No Sense Resistor Required, 4V ≤ V ≤ 36V,
IN
SENSE
0.8V ≤ V
≤ (0.9) V
OUT
IN
LTC1876
2-Phase, Dual Synchronous Step-Down Controller with
Step-Up Regulator
2.6V ≤ V ≤ 36V, Power Good Output, 300kHz Operation
IN
LTC3701
LTC3711
Dual, 2-Phase Step-Down Controller
Current Mode,550kHz, Small 16-Pin SSOP, 2.5V ≤ V < 9.8V
IN
5-Bit Adjustible, Low Duty Cycle Step-Down Controller
Dual, 550kHz, 2-Phase Synchronous Step-Down Controllers
0.925V ≤ V ≤ 2V, V up to 36V, 24-Pin GN
OUT IN
LTC3728LX
LTC3728/LTC3728L
Phase Lockable Fixed Frequency from 250kHz to 550kHz,
5mm × 5mm QFN and SSOP Packages, Small Inductors and
Capacitors, Integrated MOSFET Drivers
LTC3730/LTC3732
LTC3831
3-Phase Synchronous DC/DC Step-Down Controllers
DDR Memory Termination Power Supply
IMVP III and VRM 9.0/9.1 Compliant, 600kHz per Phase,
I
≤ 60A, Integrated MOSFET Drivers
OUT
V
= 1/2 V , I
up to 15A, 3V ≤ V ≤ 8V, 700µA Supply
OUT
IN OUT IN
Current, 16-Pin SSOP Package
Burst Mode is registered trademark of Linear Technology Corporation.
3720f
LT/TP 0203 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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