LTC3709EUH#PBF [Linear]
LTC3709 - Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C;
| 型号： | LTC3709EUH#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3709 - Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总24页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3709
TM
SENSE
Fast 2-Phase, No R
,
Synchronous DC/DC Controller
with Tracking/Sequencing
U
FEATURES
DESCRIPTIO
PolyPhase® Valley Current Mode Controller
TheLTC®3709isasingleoutput,dualphase,synchronous
step-down switching regulator. The controller uses a
constant on-time, valley current control architecture to
deliver very low duty cycles without requiring a sense
resistor. Operating frequency is selected by an external
resistor and is compensated for variations in input supply
voltage. An internal phase-lock loop allows the LTC3709
to be synchronized to an external clock.
■
■
Synchronizable to an External Clock with PLL
■
Coincident or Ratiometric Tracking
■
Sense Resistor Optional
■
2% to 90% Duty Cycle at 200kHz
■
tON(MIN) < 100ns
■
True Remote Sensing Differential Amplifier
■
High Efficiency at Both Light and Heavy Loads
■
Power Good Output Voltage Monitor
A TRACK pin is provided for tracking or sequencing the
output voltage among several LTC3709 chips or an
LTC3709 and other DC/DC regulators. Soft-start is ac-
■
0.6V ±1% Reference
Adjustable Current Limit
■
■
Programmable Soft-Start and Operating Frequency
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Available in 32-Lead (5mm × 5mm) QFN and 36-Lead
complished using an external timing capacitor.
■
■
■
Faultprotectionisprovidedbyanoutputovervoltagecom-
parator and an optional short-circuit shutdown timer. The
current limit level is user programmable. A wide supply
range allows voltages as high as 31V to step down as low
SSOP Packages U
as 0.6V.
APPLICATIO S
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
■
No R
is a trademark of Linear Technology Corporation.
Notebook Computers
Power Supply for DSP, ASIC, Graphic Processors
SENSE
PolyPhase is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178, 6476589, 6144194, 5847554, 6100678,
6304066, 6580258, 6674274, 6462525, 6593724.
■
U
TYPICAL APPLICATIO
High Efficiency Dual Phase 1.5V/30A Step-Down Converter
5V
4.7µF
324k
10Ω
V
IN
4.5V TO 28V
10µF
35V
×3
1µF
V
DRV
I
47.5k
CC
CC ON
TG1
HAT2168H
HAT2165H
TRACK
Efficiency and Power Loss
V
RNG
0.22µF
FCB
100
95
90
85
80
75
70
65
60
55
50
10
9
8
7
6
5
4
3
2
1
0
BOOST1
SW1
1.22µH
10k
V
= 12V
IN
100k
+
0.1µF
SENSE1
PGOOD
EFFICIENCY
RUN/SS
BG1
–
EXTLPF
INTLPF
SENSE1
3.32k
PGND1
100nF
680pF
LTC3709
I
TH
V
IN
20k
HAT2168H
HAT2165H
SGND
TG2
BOOST2
SW2
0.22µF
POWER LOSS
10k
1.22µH
V
1.5V
30A
OUT
V
FB
+
DIFFOUT
SENSE2
15k
BG2
–
0.01
0.1
1
10
100
–
330µF
2.5V
×4
+
V
V
LOAD CURRENT (A)
OS
SENSE2
PGND2
+
3709 TA01b
OS
3709 TA01a
3709fb
1
LTC3709
ABSOLUTE AXI U RATI GS
Input Supply Voltage (VCC, DRVCC) ............ 7V to –0.3V
Boosted Topside Driver Supply Voltage
W W
U W
(Note 1)
ITH Voltage............................................... 2.7V to –0.3V
FB Voltage .............................................. 2.7V to –0.3V
V
(BOOST1, BOOST2) .................................. 37V to –0.3V
Switch Voltage (SW1, 2) ............................. 31V to –1V
SENSE1+, SENSE2+ Voltages....................... 31V to –1V
SENSE1–, SENSE2– Voltages.................... 10V to –0.3V
INTLPF, EXTLPF Voltages ........................ 2.7V to –0.3V
VOS+, VOS– Voltages ................................... 7V to –0.3V
FCB Voltage ................................................ 7V to –0.3V
Operating Temperature Range (Note 4) .. –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range
I
ON Voltage ............................................... 31V to –0.3V
(BOOST – SW) Voltages ..............................7V to –0.3V
RUN/SS, PGOOD Voltages.......................... 7V to –0.3V
TRACK Voltage ............................................7V to –0.3V
VRNG Voltage ................................. VCC + 0.3V to –0.3V
UH Package ..................................... –65°C to 125°C
G Package ....................................... –65°C to 150°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
1
2
BOOST1
TG1
36
25
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
TOP VIEW
PGOOD
3
SW1
I
ON
+
4
SENSE1
SENSE1
PGND1
BG1
FCB
RNG
–
32 31 30 29 28 27 26 25
–
5
V
RUN/SS
1
2
3
4
5
6
7
8
24 SENSE1
23 PGND1
6
RUN/SS
I
TH
7
I
TH
V
BG1
DRV
22
21
FB
8
DRV
CC
V
FB
TRACK
SGND
CC
9
BG2
TRACK
SGND
33
20 BG2
PGND2
10
11
12
13
14
15
16
17
18
PGND2
SENSE2
SGND
–
19
18 SENSE2
17
–
+
SGND
–
–
V
OS
V
V
CC
OS
DIFFOUT
V
CC
SENSE2
SW2
DIFFOUT
+
9
10 11 12 13 14 15 16
V
OS
TG2
EXTLPF
INTLPF
NC
BOOST2
NC
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
NC
NC
EXPOSED PAD IS SGND (PIN 33)
MUST BE SOLDERED TO PCB
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 34°C/ W
TJMAX = 125°C, θJA = 95°C/ W
ORDER PART NUMBER
UH PART MARKING
3709
LTC3709EG
ORDER PART NUMBER
LTC3709EUH
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3709fb
2
LTC3709
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = DRV = 5V, unless otherwise noted.
A
CC
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
Input DC Supply Current
Normal
Shutdown
Q
2.4
25
3
65
mA
µA
I
FB Pin Input Current
I
I
= 1.2V (Note 3)
–35
0.600
0.02
–60
nA
V
FB
TH
TH
V
Feedback Voltage
= 1.2V (Note 3)
●
0.594
1.3
0.606
FB
∆V
∆V
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Error Amplifier Transconductance
On-Time
V
= 4.5V to 6.5V (Note 3)
= 0.5V to 2V (Note 3)
= 1.2V (Note 3)
%/V
%
FB(LINEREG)
FB(LOADREG)
CC
I
I
–0.12
1.45
–0.2
1.6
TH
g
mS
m(EA)
TH
t
I
I
= 180µA, V = 0V
FCB
90
180
116
233
140
280
ns
ns
ON
ON
ON
= 90µA, V = 0V
FCB
t
t
Minimum On-Time
I
I
= 540µA
= 90µA
45
100
350
ns
ns
ON(MIN)
OFF(MIN)
ON
ON
Minimum Off-Time
250
V
Maximum Current Sense Threshold
V
V
V
= 1V
= 0V
124
86
177
144
101
202
166
119
234
mV
mV
mV
SENSE(MAX)
RNG
RNG
RNG
= V
CC
V
Minimum Current Sense Threshold
V
V
V
= 1V
= 0V
–60
–40
–80
mV
mV
mV
SENSE(MIN)
RNG
RNG
RNG
= V
CC
∆V
∆V
Overvoltage Fault Threshold
Undervoltage Fault Threshold
RUN Pin Start Threshold
8.5
–8.5
0.8
10
–10
1.4
3
12.5
–12.5
2
%
%
V
FB(OV)
FB(UV)
V
V
V
●
RUN/SS(ON)
RUN/SS(LE)
RUN/SS(LT)
RUN/SS(C)
RUN/SS(D)
RUN Pin Latchoff Enable Threshold
RUN Pin Latchoff Threshold
Soft-Start Charge Current
RUN/SS Pin Rising
RUN/SS Pin Falling
V
2.3
–1.2
2
V
I
I
–0.5
0.8
–3
4
µA
µA
V
Soft-Start Discharge Current
Undervoltage Lockout
UVLO
UVLO
V
Falling
3.9
0.2
2
4.2
0.35
CC
Undervoltage Lockout Hysteresis
TG Driver Pull-Up On-Resistance
TG Driver Pull-Down On-Resistance
BG Driver Pull-Up On-Resistance
BG Driver Pull-Down On-Resistance
Measured at V Pin
V
(HYS)
CC
TG R
TG R
BG R
BG R
TG High (Note 5)
TG Low (Note 5)
BG High (Note 5)
BG Low (Note 5)
Ω
Ω
Ω
Ω
UP
1.5
3
DOWN
UP
1.5
DOWN
Tracking
I
TRACK Pin Input Current
I
= 1.2V, V = 0.2V (Note 3)
TRACK
–100
–150
nA
TRACK
TH
V
Feedback Voltage at Tracking
V
V
V
= 0.1V, I = 1.2V (Note 3)
90
290
490
100
300
500
110
310
510
mV
mV
mV
FB(TRACK)
TRACK
TRACK
TRACK
TH
= 0.3V, I = 1.2V (Note 3)
TH
= 0.5V, I = 1.2V (Note 3)
TH
PGOOD Output
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Delay
V
V
V
V
V
Rising
8.5
–8.5
100
10
12.5
%
%
µs
%
µA
V
FBH
FBL
FB
Falling
–10
–12.5
FB
PG Delay
∆V
Rising
FB
PGOOD Hysteresis
Returning
3.5
0.2
FB(HYS)
FB
I
PGOOD Leakage Current
PGOOD Low Voltage
= 7V
±1
PGOOD
PGOOD
PGOOD
V
I
= 5mA
0.4
PGL
3709fb
3
LTC3709
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = DRV = 5V, unless otherwise noted.
A
CC
CC
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Phase-Lock Loop
I
I
I
I
Internal PLL Sourcing Current
Internal PLL Sinking Current
External PLL Sourcing Current
External PLL Sinking Current
Forced Continuous Threshold
Clock Input Threshold
20
–20
20
µA
µA
µA
µA
V
INTPLL_SOURCE
INTPLL_SINK
EXTPLL_SOURCE
EXTPLL_SINK
–20
2.1
1.5
V
V
Measured with a DC Voltage at FCB Pin
Measured with a AC Pulse at FCB Pin
1.9
1
2.3
2
FCB(DC)
FCB(AC)
V
t
t
Modulation Range by External PLL
ON1
ON(PLL)1
Up Modulation
I
I
= 180µA, V
= 180µA, V
= 1.8V
= 0.6V
186
186
233
58
ns
ns
ON1
ON1
EXTPLL
EXTPLL
Down Modulation
80
80
t
t
Modulation Range by Internal PLL
ON2
Up Modulation
Down Modulation
ON(PLL)2
I
I
= 180µA, V
= 180µA, V
= 1.8V
= 0.6V
233
58
ns
ns
ON2
ON2
INTPLL
INTPLL
Differential Amplifier
A
V
Differential Gain
0.995
1.000
0.5
1.005
7
V/V
mV
V
+
–
Input Offset Voltage
IN = IN = 1.2V, I
= 1mA,
OS
OUT
Input Referred; Gain = 1
CM
Common Mode Input Voltage Range
Common Mode Rejection Ratio
I
= 1mA
0
5
V
OUT
+
–
CMRR
0V < IN = IN < 5V, I
Input Referred
= 1mA,
45
70
dB
OUT
I
Output Current
10
40
2
mA
MHz
V/µs
V
CL
GBP
SR
Gain Bandwidth Product
Slew Rate
I
= 1mA
OUT
R = 2k
5
L
V
Maximum High Output Voltage
Input Resistance
I
= 1mA
V
– 1.2 V – 0.8
O(MAX)
OUT
CC
CC
+
R
Measured at IN Pin
80
kΩ
IN
Note 3: The LTC3709 is tested in a feedback loop that adjusts V to
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
FB
achieve a specified error amplifier output voltage (I ).
TH
Note 4: The LTC3709E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P as follows:
D
Note 5: R
test.
limit is guaranteed by design and/or correlation to static
LTC3709EUH: T = T + (P • 34°C/W)
DS(ON)
J
A
D
LTC3709EG: T = T + (P • 95°C/W)
J
A
D
3709fb
4
LTC3709
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up
Continuous Current Mode (CCM)
Discontinuous Current Mode (DCM)
V
RUN/SS
5V/DIV
V
OUT
1V/DIV
SW1
5V/DIV
SW1
5V/DIV
I
L1
10A/DIV
SW2
1V/DIV
SW2
5V/DIV
I
L2
10A/DIV
3709 G01
3709 G02
3709 G03
1ms/DIV
2µs/DIV
10µs/DIV
Transient Response (CCM)
Transient Response (DCM)
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
V
V
= 12V
IN
OUT
I
I
LOAD
LOAD
3A-18A
= 1.5V
3A-18A
f = 220kHz
V
V
OUT
OUT
50mV/DIV
50mV/DIV
V
V
SW1
20V/DIV
SW1
20V/DIV
V
V
SW2
SW2
20V/DIV
20V/DIV
3709 G04
3709 G05
20µs/DIV
20µs/DIV
10
100
1000
10000
100000
LOAD (mA)
3709 G06
Power Loss vs Load Current
Efficiency vs V
Quiescent Current at V = 5V
CC
IN
3.0
2.8
2.6
2.4
2.2
2.0
10
1
100
95
90
85
80
V
V
= 12V
V
I
= 1.5V
= 10A
IN
OUT
OUT
LOAD
f = 220kHz
= 1.5V
f = 220kHz
0.1
0.01
0.001
10
100
1000
10000
100000
–40
–20
0
20
40
60
80
4
8
12
16
(V)
20
24
LOAD CURRENT (mA)
TEMPERATURE (°C)
V
IN
3709 G07
3709 G09
3709 G08
3709fb
5
LTC3709
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Shutdown Current at V = 5V
Error Amplifier g
EA Load Regulation
CC
m
45
40
35
30
25
20
15
1.6
1.5
1.4
1.3
1.2
0.4
0.3
0.2
0.1
0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3709 G10
3709 G11
3709 G12
V
Pin Input Current
RUN/SS Threshold
Armed Threshold
FB
–20
–25
–30
–35
–40
–45
–50
1.8
1.6
1.4
1.2
1.0
0.8
4.0
3.5
3.0
2.5
2.0
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3709 G13
3709 G14
3709 G15
Current Sense Threshold
UVLO Threshold
On-Time vs I Current
ON
vs I Voltage
TH
4.5
4.3
4.1
3.9
3.7
3.5
300
250
200
150
100
50
10000
1000
100
V
= 2V
RNG
V
= V
RNG
CC
V
= 1V
RNG
V
= 0V
RNG
V
= 0.5V
RNG
1.8
0
–50
–100
–150
10
1.2
VOLTAGE (V)
0
0.6
2.4
–40
–20
0
20
40
60
80
10
100
1000
I
ON
CURRENT (µA)
I
TH
TEMPERATURE (°C)
3709 G17
3709 G18
3709 G16
3709fb
6
LTC3709
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense
Minimum Current Sense
Threshold Voltage vs V
Threshold Voltage vs V
RNG
RNG
350
300
0
–20
250
200
150
100
50
–40
–60
–80
–100
–120
–140
0
0.5
0.8
1.1
V
1.4
(V)
2.0
0.8
1.1
V
1.4
(V)
2.0
1.7
0.5
1.7
RNG
RNG
3709 G19
3709 G20
U
U
U
PI FU CTIO S
(QFN/SSOP)
RUN/SS (Pin 1/Pin 6): Run Control and Soft-Start Input.
A capacitor to ground at this pin sets the ramp rate of the
output voltage (approximately 0.5s/µF) and the time delay
for overcurrent latch-off (see Applications Information).
Forcing this pin below 1.4V shuts down the device.
SGND (Pins 5, 6, 33/Pins 10, 11): Signal Ground. All
small-signal components such as CSS and compensation
componentsshouldconnecttothisgroundandeventually
connecttoPGNDatonepoint.TheExposedPadoftheQFN
package must be soldered to PCB ground.
–
ITH(Pin2/Pin7):ErrorAmplifierCompensationPoint. The
current comparator threshold increases with this control
voltage. The voltage ranges from 0V to 2.4V with 0.8V
corresponding to zero sense voltage (zero current).
VOS (Pin 7/Pin 12): The (–) Input to the Differential
Amplifer.
DIFFOUT (Pin 8/Pin 13): The Output of the Differential
Amplifier.
VFB (Pin 3/Pin 8): Error Amplifier Feedback Input. This pin
connects to the error amplifier input. It can be used to
attach additional compensation components if desired.
+
VOS (Pin 9/Pin 14): The (+) Input to the Differential
Amplifier.
EXTLPF (Pin 10/Pin 15): Filter Connection for the PLL.
This PLL is used to synchronize the LTC3709 with an
external clock.
TRACK (Pin 4/Pin 9): Tie the TRACK pin to a resistive
divider connected to the output of another LTC3709 for
eithercoincidentorratiometricoutputtracking(seeAppli-
cations Information). To disable this feature, tie the pin to
VCC. Do Not Float this pin.
INTLPF (Pin 11/Pin 16): Filter Connection for the PLL.
This PLL is use to phase shift the second channel to the
first channel by 180°.
3709fb
7
LTC3709
U
U
U
PI FU CTIO S
(QFN/SSOP)
NC (Pin 12/Pins 1, 17, 18, 19, 20): No Connect.
TG1, TG2 (Pins 27, 14/Pins 35, 22): Top Gate Drive.
Drives the top N-channel MOSFET with a voltage swing
equal to DRVCC superimposed on the switch node voltage
SW.
V
CC (Pin 17/Pin 25): Main Input Supply. Decouple this pin
to SGND with an RC filter (1Ω, 0.1µF).
DRVCC (Pin 21/Pin 29): Driver Supply. Provides supply to
the driver for the bottom gate. Also used for charging the
bootstrap capacitor.
BOOST1, BOOST2 (Pins 28, 13/Pins 36, 21): Boosted
Floating Driver Supply. The (+) terminal of the bootstrap
capacitor CB connects here. This pin swings from a diode
voltage drop below DRVCC up to VIN + DRVCC.
BG1, BG2 (Pins 22, 20/Pins 30, 28): Bottom Gate Drive.
Drives the gate of the bottom N-channel MOSFET between
ground and DRVCC.
PGOOD (Pin 29/Pin 2): Power Good Output. Open-drain
logic output that is pulled to ground when output voltage
is not within ±10% of the regulation point. The output
voltage must be out of regulation for at least 100µs before
the power good output is pulled to ground.
PGND1,PGND2(Pins23,19/Pins31,27):PowerGround.
Connect this pin closely to the source of the bottom N-
channelMOSFET,the(–)terminalofCDRVCCandthe(–)ter-
minal of CIN.
SENSE1–, SENSE2– (Pins 24,18/Pins 32, 26): Current
Sense Comparator Input. The (–) input to the current
comparator is used to accurately Kelvin sense the bottom
side of the sense resistor or MOSFET.
SENSE1+, SENSE2+ (Pins 25,16/Pins 33, 24): Current
Sense Comparator Input. The (+) input to the current
comparator is normally connected to the SW node unless
using a sense resistor (see Applications Information).
I
ON (Pin 30/Pin 3): On-Time Current Input. Tie a resistor
from VIN to this pin to set the one-shot timer current and
thereby set the switching frequency.
FCB(Pin31/Pin4):ForcedContinuousandExternalClock
Input. Tie this pin to ground to force continuous synchro-
nous operation or to VCC to enable discontinuous mode
operation at light load. Feeding an external clock signal
into this pin will synchronize the LTC3709 to the external
clock and enable forced continuous mode.
SW1, SW2 (Pins 26, 15/Pins 34, 23): Switch Node. The
(–) terminal of the bootstrap capacitor CB connects here.
This pin swings from a Schottky diode voltage drop below
ground up to VIN.
VRNG (Pin32/Pin5):SenseVoltageRangeInput. Thevolt-
ageatthispinistentimesthenominalsensevoltageatmaxi-
mumoutputcurrentandcanbeprogrammedfrom0.5Vto
2V.Thesensevoltagedefaultsto70mVwhenthispinistied
to ground, 140mV when tied to VCC.
3709fb
8
LTC3709
U
U
W
FU CTIO AL DIAGRA
I
ON
INTLPF
R
ON
V
IN
+
FCB
C
IN
CLOCK DETECTOR
V
CC
0.6V
REF
FROM CHANNEL 2
TG
+
C
VCC
EXTLPF
PLL2
PLL1
BOOST
TO CHANNEL 2 OST
C
TG
B
OST
0.7
ION
FCNT
ON
M1
R
S
t
=
(30pF)
ON
I
Q
SW
L1
V
+
OUT
D
SWITCH
LOGIC
B
SENSE
20k
+
+
–
+
5V
C
OUT
DRV
CC
I
I
CMP
REV
–
SHDN
OV
C
DRVCC
BG
DUPLICATE FOR
M2
SECOND CHANNEL
PGND
SENSE
1.4V
–
SHDN TO
V
RNG
CHANNEL 2
SWITCH LOGIC
×
0.7V
–
3.3µA
0.66V
R2
OV
UV
V
FB
+
–
+
R1
1
240k
SGND
EA
Q4
–
+
I
TH
PGOOD
C
C
0.54V
R
C
100µs
BLANKING
SHED
40k
40k
+
RUN
SHDN
V
V
OS
DISABLE
40k
I
+
–
THB
DIFFOUT
1.2µA
–
TRACK
6V
OS
40k
Q1 Q2
0.6V Q3
REF
+
–
1.4V
V
RUN/SS
1.4V
C
SS
+
–
3709 FD
3709fb
9
LTC3709
U
(Refer to Functional Diagram)
OPERATIO
MAIN CONTROL LOOP
Output Overvoltage Protection
The LTC3709 is a constant on-time, current mode step-
down controller with two channels operating 180 degrees
out of phase. In normal operation, each top MOSFET is
turned on for a fixed interval determined by its own one-
shot timer OST. When the top MOSFET is turned off, the
bottom MOSFET is turned on until the current comparator
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In this condition,
the top MOSFET is turned off and the bottom MOSFET is
turned on and held on until the condition is cleared.
Power Good (PGOOD) Pin
ICMP trips, restarting the one-shot timer and repeating the
cycle. The trip level of the current comparator is set by the
ITH voltage, which is the output of error amplifier EA.
Inductor current is determined by sensing the voltage
between the SENSE– and SENSE+ pins using either the
bottom MOSFET on-resistance or a separate sense resis-
tor. At light load, the inductor current can drop to zero and
become negative. This is detected by current reversal
comparatorIREV,whichthenshutsoffthebottomMOSFET,
resulting in discontinuous operation. Both switches will
remain off with the output capacitor supplying the load
current until the ITH voltage rises above the zero current
level (0.8V) to initiate another cycle. Discontinuous mode
operation is disabled when the FCB pin is tied to ground,
forcing continuous synchronous operation.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point. In
addition, the output feedback voltage must be out of this
window for a continuous duration of at least 100µs before
the PGOOD is pulled low. This is to prevent any glitch on
the feedback voltage from creating a false power bad
signal.ThePGOODwillindicateagoodpowerimmediately
when the feedback voltage is in regulation.
Short-Circuit Detection and Protection
After the controller has been started and been given
adequatetimetochargetheoutputcapacitor,theRUN/SS
capacitor is used in a short-circuit time-out circuit. If the
output voltage falls to less than 67% of its nominal output
voltage, the RUN/SS capacitor begins discharging on the
assumption that the output is in an overcurrent and/or
short-circuit condition. If the condition lasts for a long
enough period, as determined by the size of the RUN/SS
capacitor, the controller will be shut down until the
RUN/SS pin voltage is recycled. This built-in latch off can
be overridden by providing a >5µA pull-up at a compli-
ance of 5V to the RUN/SS pin. This current shortens the
soft-start period but also prevents net discharge of the
RUN/SS capacitor during an overcurrent and/or short-
circuit condition.
The main control loop is shut down by pulling the RUN/SS
pinlow,turningoffbothtopMOSFETandbottomMOSFET.
Releasing the pin allows an internal 1.2µA current source
to charge an external soft-start capacitor CSS. When this
voltage reaches 1.4V, the LTC3709 turns on and begins
operating with a clamp on the noninverting input of the
error amplifier. This input is also the reference input of the
error amplifier. As the voltage on RUN/SS continues to
rise, the voltage on the reference input also rises at the
same rate, effectively controlling output voltage slew rate.
Operating Frequency
The operating frequency is determined implicitly by the
top MOSFET on time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holdingthefrequencyapproximatelyconstantwithchanges
in VIN. The nominal frequency can be adjusted with an
external resistor RON.
DRVCC
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
DRVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is normally
recharged from DRVCC through an external Schottky di-
ode DB when the top MOSFET is turned off.
3709fb
10
LTC3709
U
(Refer to Functional Diagram)
OPERATIO
Differential Amplifier
of the top MOSFET of channel 1 to the rising edge of the
external clock. Compensation for PLL2 is through the
EXTLPF pin.
This amplifier provides true differential output voltage
sensing. Sensing both VOUT+ and VOUT– benefits regula-
tion in high current applications and/or applications hav-
ing electrical interconnection losses. This sensing also
isolates the physical power ground from the physical
signal ground, preventing the possibility of troublesome
“ground loops” on the PC layout and preventing voltage
errors caused by board-to-board interconnects.
The loop filter components tied to the INTLPF and EXTLPF
pins are used to compensate the internal PPL and external
PLL respectively. The typical value ranges are:
INTLPF: RIPLL = 2kΩ to 10kΩ, CIPLL = 10nF to 100nF
EXTLP: REPLL ≤ 1kΩ, CEPLL= 10nF to 100nF
For noise suppression, a capacitor with a value of 1nF or
less should be placed from INTLPF to ground and EXTLPF
to ground.
Dual Phase Operation
An internal phase-lock loop (PLL1) ensures that channel
2 operates exactly at the same frequency as channel 1 and
is also phase shifted by 180°, enabling the LTC3709 to
operateoptimallyasadualphasecontroller. Theloopfilter
connected to the INTLPF pin provides stability to the PLL.
For external clock synchronization, a second PLL (PLL2)
is incorporated into the LTC3709. PLL2 will adjust the on-
time of channel 1 until its frequency is the same as the
external clock. When locked, the PLL2 aligns the turn on
Second Channel Shutdown During Light Loads
When FCB is tied to VCC, discontinuous mode is selected.
In this mode, no reverse current is allowed. The second
channel is off when ITH is less than 0.8V for better
efficiency. When FCB is tied to ground, forced continuous
mode is selected, both channels are on and reversed
current is allowed.
U
W U U
APPLICATIO S I FOR ATIO
theSENSE+ pins.Themaximumsensevoltageissetbythe
voltage applied to the VRNG pin and is equal to approxi-
mately VRNG/7.5. The current mode control loop will not
allow the inductor current valleys to exceed VRNG/(7.5 •
RSENSE). In practice, one should allow some margin for
variationsintheLTC3709andexternalcomponentvalues.
A good guide for selecting the sense resistance for each
channel is:
The basic LTC3709 application circuit is shown on the
first page of this data sheet. External component selec-
tion is primarily determined by the maximum load cur-
rent and begins with the selection of the power MOSFET
switches and/or sense resistor. The inductor current is
determined by the RDS(ON) of the synchronous MOSFET
while the user has the option to use a sense resistor for
a more accurate current limiting. The desired amount of
ripple current and operating frequency largely deter-
mines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and COUT is chosen with low enough ESR to meet the
output voltage ripple specification.
2 • VRNG
10 •IOUT(MAX)
RSENSE
=
The voltage of the VRNG pin can be set using an external
resistive divider from VCC between 0.5V and 2V resulting
in nominal sense voltages of 50mV to 200mV. Addition-
ally, the VRNG pin can be tied to ground or VCC, in which
case the nominal sense voltage defaults to 70mV or
140mV, respectively. The maximum allowed sense volt-
age is about 1.3 times this nominal value.
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage
acrosstheRDS(ON) ofthesynchronousMOSFETorthrough
a sense resistance that appears between the SENSE– and
3709fb
11
LTC3709
W U U
U
APPLICATIO S I FOR ATIO
2.0
1.5
1.0
0.5
0
Connecting the SENSE+ and SENSE– Pins
TheLTC3709providestheuserwithanoptionalmethodto
sensecurrentthroughasenseresistorinsteadofusingthe
R
DS(ON) ofthesynchronousMOSFET. Whenusingasense
resistor, it is placed between the source of the synchro-
nous MOSFET and ground. To measure the voltage across
this resistor, connect the SENSE+ pin to the source end of
the resistor and the SENSE– pin to the other end of the
resistor. The SENSE+ and SENSE– pin connections pro-
vide the Kelvin connections, ensuring accurate voltage
measurement across the resistor. Using a sense resistor
provides a well-defined current limit, but adds cost and
reduces efficiency. Alternatively, one can use the synchro-
nous MOSFET as the current sense element by simply
connecting the SENSE+ pin to the switch node SW and the
SENSE– pin to the source of the synchronous MOSFET,
eliminating the sense resistor. This improves efficiency,
but one must carefully choose the MOSFET on-resistance
as discussed in the Power MOSFET Selection section.
–50
50
100
150
0
JUNCTION TEMPERATURE (°C)
3709 F01
Figure 1. R
vs Temperature
DS(ON)
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C. Junction-to-
case temperature is about 20°C in most applications. For
a maximum junction temperature of 100°C, using a value
ρ
100°C = 1.3 is reasonable (Figure 1).
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. When the LTC3709 is operating in
continuous mode, the duty cycles for the MOSFETs are:
Power MOSFET Selection
The LTC3709 requires four external N-channel power
MOSFETs, two for the top (main) switches and two for the
bottom (synchronous) switches. Important parameters
for the power MOSFETs are the breakdown voltage
VOUT
DTOP
DBOT
=
=
V(BR)DSS,thresholdvoltageV(GS)TH,on-resistanceRDS(ON)
reverse transfer capacitance CRSS and maximum current
IDS(MAX)
,
V
IN
V – VOUT
IN
.
V
IN
The gate drive voltage is set by the 5V DRVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3709 applications. If the driver’s voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be used.
The maximum power dissipation in the MOSFETs per
channel is:
2
⎛
⎞
IOUT(MAX)
PTOP = DTOP
•
• ρT(TOP) •RDS(ON)(MAX) +
⎜
⎟
2
⎝
⎠
When the bottom MOSFETs are used as the current sense
elements, particular attention must be paid to their on-
resistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
⎛
2
⎞
IOUT
2
(0.5)• V
•
•CRSS • f •
IN
⎜
⎟
⎝
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1
1
RDS(ON)_DRV
+
VGS(TH)
DRV – V
(
)
CC
GS(TH)
2
RSENSE
⎛
⎞
RDS(ON)(MAX)
=
IOUT(MAX)
PBOT = DBOT
•
• ρT(BOT) •RDS(ON)(MAX)
ρT
⎜
⎟
2
⎝
⎠
3709fb
12
LTC3709
W U U
APPLICATIO S I FOR ATIO
U
BothtopandbottomMOSFETshaveI2Rlossesandthetop
MOSFET includes an additional term for transition losses,
which are the largest at maximum input voltages. The
bottom MOSFET losses are the greatest when the bottom
duty cycle is near 100%, during a short circuit or at high
input voltage. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET
in applications that have an output voltage that is less than
locking and phase separation between the two channels
while the second PLL is for locking onto an external clock.
Since the LTC3709 is a constant on-time architecture, the
error signal generated by the phase detector of the PLL is
used to vary the on-time to achieve frequency locking and
180° phase separation.
The synchronization is set up in a “daisy chain” manner
whereby channel 2’s on-time will be varied with respect to
channel 1. If an external clock is present, then channel 1’s
on-time will be varied and channel 2 will follow suit. Both
PLLs are set up with the same capture range and the fre-
quencyrangethattheLTC3709canbeexternallysynchro-
nized to is between 2 • fC and 0.5 • fC, where fC is the initial
frequency setting of the two channels. It is advisable to set
initialfrequencyasclosetoexternalfrequencyaspossible.
1/3oftheinputvoltage. InapplicationswhereVIN >>VOUT
,
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
inputcapacitanceforthemainswitchapplicationinswitch-
ing regulators.
AlimitationofbothPLLsiswhentheon-timeisclosetothe
minimum (100ns). In this situation, the PLL will not be
able to synchronize up in frequency.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage.
Toensureproperoperationoftheinternalphase-lockloop
when no external clock is applied to the FCB pin, the
INTLPF pin may need to be pulled down while the output
voltage is ramping up. One way to do this is to connect the
anode of a silicon diode to the INTLPF pin and its cathode
to the PGOOD pin and connect a pull-up resistor between
the PGOOD pin and VCC. Refer to Figure 9 for an example.
TheoperatingfrequencyofLTC3709applicationsisdeter-
mined implicitly by the one-shot timer that controls the on
time, tON, of the top MOSFET switch. The on-time is set by
the current into the ION pin according to:
Inductor Selection
0.7
IION
Given the desired input and output voltages, the inductor
valueandoperatingfrequencydeterminetheripplecurrent:
tON
=
30pF
(
)
Tying a resistor from VIN to the ION pin yields an on-time
inversely proportional to VIN. For a down converter, this
results in approximately constant frequency operation as
the input supply varies:
⎛
⎞⎛
⎞
VOUT
f •L
VOUT
∆IL =
1–
⎜
⎟⎜
⎟
V
⎝
⎠⎝
⎠
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
VOUT
f =
Per Phase
(
)
0.7 •RON 30pF
(
)
PLL and Frequency Synchronization
In the LTC3709, there are two on-chip phase-lock loops
(PLLs). One of the PLLs is used to achieve frequency
3709fb
13
LTC3709
W U U
U
APPLICATIO S I FOR ATIO
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX)/2. Note that the largest
ripple current occurs at the highest VIN. To guarantee that
ripple current does not exceed a specified maximum, the
inductance should be chosen according to:
In the Figure 2 graph, the local maximum input RMS
capacitor currents are reached when:
VOUT 2k – 1
=
where k = 1, 2
V
4
IN
These worst-case conditions are commonly used for
design because even significant deviations do not offer
muchrelief.Notethatripplecurrentratingsfromcapacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to derate the capacitor. Several
capacitors may also be paralleled to meet size or height
requirements in the design. Always consult the capacitor
manufacturer if there is any question.
⎛
⎞⎛
⎟⎜
⎞
VOUT
f • ∆I
VOUT
L =
1–
⎜
⎟
V
⎝
L(MAX) ⎠⎝
⎠
IN(MAX)
Once the value for L is known, the inductors must be
selected (based on the RMS saturation current ratings). A
variety of inductors designed for high current, low voltage
applications are available from manufacturers such as
Sumida, Toko and Panasonic.
It is important to note that the efficiency loss is propor-
tional to the input RMS current squared and therefore a
2-stage implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the re-
ductionoftheinputripplecurrentina2-phasesystem.The
requiredamountofinputcapacitanceisfurtherreducedby
the factor 2 due to the effective increase in the frequency
of the current pulses.
Schottky Diode Selection
The Schottky diodes conduct during the dead time be-
tween the conduction of the power MOSFET switches. It is
intended to prevent the body diode of the bottom MOSFET
from turning on and storing charge during the dead time,
which causes a modest (about 1%) efficiency loss. The
diode can be rated for about one-half to one-fifth of the full
load current since it is on for only a fraction of the duty
cycle. In order for the diode to be effective, the inductance
between the diode and the bottom MOSFET must be as
small as possible, mandating that these components be
placed adjacently. The diode can be omitted if the effi-
ciency loss is tolerable.
0.6
0.5
0.4
1-PHASE
2-PHASE
CIN and COUT Selection
0.3
In continuous mode, the current of each top N-channel
MOSFET is a square wave of duty cycle VOUT/VIN. A low
ESR input capacitor sized for the maximum RMS current
must be used. The details of a close form equation can be
found in Application Note 77. Figure 2 shows the input
capacitor ripple current for a 2-phase configuration with
theoutputvoltagefixedandinputvoltagevaried. Theinput
ripple current is normalized against the DC output current.
Thegraphcanbeusedinplaceoftediouscalculations.The
minimum input ripple current can be achieved when the
input voltage is twice the output voltage.
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V /V
)
OUT IN
3709 F02
Figure 2. RMS Input Current Comparison
3709fb
14
LTC3709
W U U
APPLICATIO S I FOR ATIO
U
The selection of COUT is primarily determined by the ESR Discontinuous Mode Operation and FCB Pin
requiredtominimizevoltagerippleandloadsteptransients.
The FCB pin determines whether the bottom MOSFET
The output ripple ∆VOUT is approximately bounded by:
remains on when current reverses in the inductor. Tying
this pin to VCC enables discontinuous operation where the
⎛
⎞
1
bottomMOSFETturnsoffwheninductorcurrentreverses.
The load current at which inductor current reverses and
discontinuousoperationbeginsdependsontheamplitude
of the inductor ripple current. The ripple current depends
onthechoiceofinductorvalueandoperatingfrequencyas
well as the input and output voltages.
∆VOUT ≤ ∆IL ESR +
⎜
⎟
8fCOUT
⎝
⎠
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Tying the FCB pin to ground forces continuous synchro-
nous operation, allowing current to reverse at light loads
and maintaining high frequency operation.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long-
term reliability. Ceramic capacitors have excellent low
ESRcharacteristicsbutcanhaveahighvoltagecoefficient
and audible piezoelectric effects. High performance
through-hole capacitors may also be used, but an addi-
tional ceramic capacitor in parallel is recommended to
reduce the effect of their lead inductance.
Besides providing a logic input to force continuous opera-
tion, the FCB pin acts as the input for external clock syn-
chronization. Upon detecting a TTL level clock and the fre-
quency is higher than the minimum allowable, channel 1
will lock on to this external clock. This will be followed by
channel 2 (see PLL and Frequency Synchronization). The
LTC3709 will be forced to operate in forced continuous
mode in this situation.
Fault Conditions: Current Limit
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3709, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
Top MOSFET Driver Supply (CB, DB)
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
This capacitor is charged through diode DB from DRVCC
when the switch node is low. Note that the average voltage
acrossCB isapproximatelyDRVCC. WhenthetopMOSFET
turns on, the switch node rises to VIN and the BOOST pin
rises to approximately VIN + DRVCC. The boost capacitor
needstostoreabout100timesthegatechargerequiredby
the top MOSFET. In most applications 0.1µF to 0.47µF is
adequate.
⎛
⎞
VSNS(MAX)
1
2
ILIMIT
=
+ • ∆IL • 2
⎟
⎜
RDS(ON) • ρT
⎝
⎠
The current limit value should be checked to ensure that
ILIMIT(MIN)>IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
enttemperature,conditionswhichcausethelargestpower
loss in the converter. Note that it is important to check for
3709fb
15
LTC3709
W U U
U
APPLICATIO S I FOR ATIO
2.0
1.5
1.0
0.5
0
self-consistency between the assumed junction tempera-
ture and the resulting value of ILIMIT, which heats the
junction.
DROPOUT
REGION
Cautionshouldbeusedwhensettingthecurrentlimitbased
upon the RDS(ON) of the MOSFETs. The maximum current
limitisdeterminedbytheminimumMOSFETon-resistance.
Datasheetstypicallyspecifynominalandmaximumvalues
for RDS(ON), but not a minimum. A reasonable assumption
is that the minimum RDS(ON) lies the same amount below
the typical value as the maximum lies above it. Consult the
MOSFET manufacturer for further guidelines.
0
0.25
0.50
0.75
1.0
DUTY CYCLE (V /V
)
OUT IN
3709 F03
For a more accurate current limiting, a sense resistor can
be used. Sense resistors in the 1W power range are easily
available with 5%, 2% or 1% tolerance. The temperature
coefficient of these resistors are very low, ranging from
±250ppm/°C to ±75ppm/°C. In this case, the denomina-
tor in the above equation can simply be replaced by the
Figure 3. Maximum Switching Frequency vs Duty Cycle
Pulling the RUN/SS pin below 1.4V puts the LTC3709 into
a low quiescent current shutdown (IQ < 30µA). Releasing
the pin allows an internal 1.2µA internal current source to
charge the external capacitor CSS. If RUN/SS has been
pulledallthewaytoground, thereisadelaybeforestarting
of about:
RSENSE value.
Minimum Off-Time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3709 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON +tOFF(MIN)).Ifthemaximumdutycycleisreached,
due to a dropping input voltage for example, then the
output will drop out of regulation in order to maintain the
duty cycle at its limit. The minimum input voltage to avoid
dropout is:
1.4V
1.2µA
tDELAY
=
•CSS = 1.2s/µF C
(
)
SS
When the RUN/SS voltage reaches the ON threshold
(typically 1.4V), the LTC3709 begins operating with a
clamponEA’sreferencevoltage.TheclamplevelisoneON
thresholdvoltagebelowRUN/SS.AsthevoltageonRUN/SS
continues to rise, EA’s reference is raised at the same rate,
achieving monotonic output voltage soft-start (Figure 4).
1
V
= VOUT
IN(MIN)
RUN/SS
1– tOFF(MIN) •f
∆V = 0.6V
ON THRESHOLD
A plot of maximum duty cycle vs frequency is shown in
Figure 3.
TIME
V
OUT1
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3709 as well as a timer for soft-start and overcurrent
latchoff.
TIME
3709 F04
Figure 4. Monotonic Soft-Start Waveforms
3709fb
16
LTC3709
W U U
APPLICATIO S I FOR ATIO
U
V
CC
reachedthe3Vthreshold.Ingeneral,thiswilldependupon
the size of the output capacitance, output voltage and load
currentcharacteristic.Aminimumsoft-startcapacitorcan
be estimated from:
R
*
SS
V
IN
RUN/SS
3.3V OR 5V
RUN/SS
*
D2*
R
SS
D1
2N7002
C
SS > COUT VOUT RSENSE (10–4 [F/VS])
C
SS
C
SS
Overcurrent latchoff operation is not always needed or
desired and can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
of >5µA to the RUN/SS pin. The additional current pre-
vents the discharge of CSS during a fault and also shortens
the soft-start period. Using a resistor to VIN as shown in
Figure 5 is simple, but slightly increases shutdown cur-
rent. Any pull-up network must be able to pull RUN/SS
above the 3V threshold that arms the latchoff circuit and
overcome the 2µA maximum discharge current.
3709 F05
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(5a)
(5b)
Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated
When RUN/SS rises 0.6V above the ON threshold, the
reference clamp is invalidated and the internal precision
reference takes over.
After the controller has been started and given adequate
timetochargetheoutputcapacitor, CSS isusedasashort-
circuit timer. After the RUN/SS pin charges above 3V, and
if the output voltage falls below 67% of its regulated value,
then a short-circuit fault is assumed. A 2µA current then
beginsdischargingCSS. Ifthefaultconditionpersistsuntil
the RUN/SS pin drops to 2.5V, then the controller turns off
both power MOSFETs, shutting down the converter per-
manently. The RUN/SS pin must be actively pulled down
to ground in order to restart operation.
Output Voltage Tracking
The feedback voltage, VFB, will follow the TRACK pin
voltage when the TRACK pin voltage is less than the
reference voltage, VREF (0.6V). When the TRACK pin
voltage is greater than VREF, the feedback voltage will
servo to VREF. When selecting components for the TRACK
pin, ensurethefinalsteady-statevoltageontheTRACKpin
is greater than VREF at the end of the tracking interval.
The LTC3709 allows the user to set up start-up sequenc-
ing among different supplies in either coincident tracking
orratiometrictrackingasshowninFigure6. Toimplement
the coincident tracking, connect an extra resistor divider
The overcurrent protection timer requires that the soft-
start timing capacitor CSS be made large enough to guar-
antee that the output is in regulation by the time CSS has
V
V
V
V
OUT1
OUT2
OUT1
OUT2
3709 F06
TIME
TIME
(6a) Coincident Tracking
(6b) Ratiometric Tracking
Figure 6. Two Different Forms of Output Voltage Sequencing
3709fb
17
LTC3709
APPLICATIO S I FOR ATIO
W U U
U
to the output of supply 1. This resistor divider is selected resistanceofoneMOSFETcansimplybesummedwiththe
tobethesameasthedivideracrosssupply2’soutput. The resistances of L and the board traces to obtain the DC I2R
TRACK pin of supply 2 is connected to this extra resistor loss.Forexample,ifRDS(ON) =0.01ΩandRL =0.005Ω,the
divider. For the ratiometric tracking, simply connect the loss will range from 0.1% up to 10% as the output current
TRACK pin of supply 2 to the VFB pin of supply 1. Figure varies from 1A to 10A for a 1.5V output.
7 shows this implementation. Note that in the coincident
2. Transition loss. This loss arises from the brief amount
tracking, output voltage of supply 1 has to be set higher
of time the top MOSFET spends in the saturated region
than output voltage of supply 2.
during switch node transitions. It depends upon the input
Note that since the shutdown trip point varies from part to voltage, load current, driver strength and MOSFET capaci-
part, the “slave” part’s RUN/SS pin will need to be con- tance, among other factors. The loss is significant at input
nected to VCC. This eliminates the possibility that different voltages above 20V and can be estimated from:
LTC3709s may shut down at different times.
TransitionLoss ≈ (0.5)• V 2 •IOUT •CRSS • f •
If output sequencing is not needed, connect the TRACK
IN
pins to VCC. Do Not Float these pins.
⎛
⎞
1
1
RDS(ON)_DRV
+
⎜
⎟
SUPPLY 1
SUPPLY 2
LTC3709
DRV − V
VGS(TH)
⎝
⎠
CC
GS(TH)
V
OUT1
V
OUT2
R5
R6
3. Gate driver supply current. The driver current supplies
thegatechargeQG requiredtoswitchthepowerMOSFETs.
This current is typically much larger than the control
circuit current. In continuous mode operation:
R1
R2
R3
V
FB
TRACK
V
FB
R4
3709 F07
R3 R5
=
IGATECHG = f (Qg(TOP) + Qg(BOT)
)
V
OUT2
COINCIDENTLY TRACKS V
OUT1
R4 R6
R3 R1 RATIOMETRIC POWER UP
=
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky conduc-
tionlossduringdeadtimeandinductorcorelossgenerally
account for less than 2% additional loss.
R4 R2 BETWEEN V
AND V
OUT1
OUT2
Figure 7. Setup for Coincident and Ratiometric Tracking
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement.
When making any adjustments to improve efficiency, the
final arbiter is the total input current for the regulator at
your operating point. If you make a change and the input
current decreases, then you improved the efficiency. If
thereisnochangeininputcurrent, thenthereisnochange
in efficiency.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3709 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
3709fb
18
LTC3709
W U U
APPLICATIO S I FOR ATIO
U
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lems. The ITH pin external components shown in Figure 9
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
⎛
⎞
146mV
1
2
ILIMIT ≥ ⎜
+
5.1A ⎟ • 2 = 24A
(
)
⎜
⎝
⎟
⎠
1.5 0.010Ω
(
)(
)
and double check the assumed TJ in the MOSFET:
2
⎛
⎞
28 V –2.5V 24A
PBOT
=
1.5 0.010Ω = 1.97W
(
)(
)
⎜
⎟
28 V
2
⎝
⎠
TJ = 70°C + (1.97W)(40°C/W) = 149°C
Design Example
Because the top MOSFET is on for such a short time, an
As a design example, take a supply with the following
specifications: VIN = 7V to 28V (15V nominal), VOUT
2.5V, IOUT(MAX) = 20A, f = 250kHz. First, calculate the
timing resistor:
Si4884 RDS(ON)(MAX) = 0.0165Ω, CRSS = 100pF, θJA
=
=
40°C/W will be sufficient. Checking its power dissipation
at current limit with ρ100°C = 1.4:
2
⎛
⎞
2.5V
2.5V 24A
RON
=
= 476k
PTOP
=
1.4 0.0165Ω +
(
)(
)
⎜
⎟
0.7V 250kHz 30pF
28V
2
⎝
⎠
(
)(
)(
)
2
1.7 28V 12A 100pF 250kHz
and choose the inductor for about 40% ripple current at
the maximum VIN. Maximum output current for each
channel is 10A:
(
)(
) (
)(
)(
)
= 0.30W + 0.40W = 0.7W
TJ = 70°C + (0.7W)(40°C/W) = 98°C
⎛
⎞
2.5V
2.5V
28V
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
L =
1−
= 2.3µH
⎜
⎟
⎝
⎠
250kHz 0.4 10A
(
)( )(
)
Selecting a standard value of 1.8µH results in a maximum
CIN is chosen for an RMS current rating of about 10A
at 85°C. The output capacitors are chosen for a low ESR
of 0.013Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
ripple current of:
⎛
⎞
2.5V
2.5V
28V
∆IL =
1–
= 5.1A
⎜
⎟
⎝
⎠
250kHz 1.8µH
(
)(
)
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (5.1A) (0.013Ω) = 66mV
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
qJA = 40°C/W) yields a nominal sense voltage of:
However, a 0A to 10A load step will cause an output
change of up to:
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
∆VOUT(STEP) =∆ILOAD (ESR)=(10A)(0.013Ω)=130mV
TyingVRNG to1.1V willsetthecurrentsensevoltagerange
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ150°C = 1.5:
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 9.
3709fb
19
LTC3709
W U U
U
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point, which is then tied to a “clean” point in the
power ground such as the “–” node of CIN.
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
• Minimize impedance between input ground and output
ground.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Connect PGND1 to the source of M2 or RS1 (QFN)
directly. This also applies to channel 2.
• Place M2 as close to the controller as possible, keeping
the PGND1, BG1 and SW1 traces short. The same for
the other channel. SW2 trace should connect to the
drain of M2 directly.
• Place CIN, COUT, MOSFETs, D1, D2 and inductors all in
one compact area. It may help to have some compo-
nents on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3709.
Use several larger vias for power components.
• Connect the input capacitor(s) CIN close to the power
MOSFETs: (+) node to drain of M1, (–) node to source
of M2. This capacitor carries the MOSFET AC current.
• Use a compact plane for switch node (SW) to keep EMI
down.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Connect the DRVCC decoupling capacitor CVCC closely
to the DRVCC and PGND pins.
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
powercomponent.Youcanconnectthecopperareasto
any DC net (VIN, VOUT, GND or to any other DC rail in
your system).
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Connect the VIN pin decoupling capacitor CF closely to
the VCC and PGND pins.
• Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor be-
tweenSENSE– andSENSE+ (CSENSE)shouldbeasclose
as possible to the IC. Ensure accurate current sensing
with Kelvin connections at the sense resistor as shown
in Figure 8.
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 9.
D
D
D
D
G
S
S
S
R
SENSE
MOSFET
+
–
+
–
SENSE SENSE
SENSE SENSE
3709 F08
(8a) Sensing the Bottom MOSFET
(8b) Sensing a Resistor
Figure 8. Kelvin Sensing
3709fb
20
LTC3709
W U U
APPLICATIO S I FOR ATIO
U
MMSD4148
(OPTIONAL)
10nF
C
0.1µF
SS
10k
1
32
31
30
29
28
27
26
25
24
RUN/SS
V
RNG
FCB
R 20k
C
C
470pF
2
3
4
5
6
7
8
9
C
35.7k
f
I
IN
TH
100pF
R
476k
ON
V
IN
7V TO 28V
V
I
ON
FB
R
100k
PGOOD
DRV
5V
CC
TRACK
SGND
PGOOD
BOOST1
TG1
D1
B340A
PGOOD
TRACK
100pF
D
CMDSH-3
B1
C
0.22µF
B1
SGND
–
M1
M2
L1
1.8µH
V
SW1
+
OS
R
10k
R
31.6k
F1
F2
DIFFOUT SENSE1
+
100pF
–
V
SENSE1
OS
100nF
475Ω
C
OUT
LTC3709EUH
180µF
4V ×4
C
10µF
1nF
IN
35V ×3
10
11
12
13
14
15
16
23
22
21
20
19
18
17
V
2.5V
20A
EXTLPF
INTLPF
NC
PGND1
BG1
OUT
100nF
1µF
1µF
3.32k
470pF
DRV
CC
BOOST2
TG2
BG2
C
B2
0.22µF
PGND2
–
SW2
SENSE2
L2
1.8µH
10Ω
1µF
+
SENSE2
V
CC
M3
M4
D
100pF
B2
CMDSH-3
D2
B340A
3709 F09
L1, L2: PANASONIC ETQP6FIR8BFA
: PANASONIC EEFUEOG181R
C
OUT
M1, M3: SILICONIX Si4884DY
M2, M4: SILICONIX Si4874DY
Figure 9. 2-Phase 2.5V/20A Supply at 250kHz with Tracking and External Synch
3709fb
21
LTC3709
U
PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
NOTE:
MIN
1. CONTROLLING DIMENSION: MILLIMETERS
G36 SSOP 0204
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3709fb
22
LTC3709
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ± 0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 ± 0.05
5.00 ± 0.10
(4 SIDES)
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
3.50 REF
(4-SIDES)
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3709fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC3709
U
TYPICAL APPLICATIO
Low Output Ripple, 2-Phase 12V/25A Supply
C
0.1µF
SS
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
10k
26.1k
RUN/SS
V
RNG
10nF
2.86M
R
C
20k
5V
C
1nF
C
I
TH
FCB
R
ON
3
V
IN
V
FB
I
ON
220pF
20V–28V
R
100k
D
PGOOD
4
D1
B340A
DRV
5V
CC
TRACK
SGND
SGND
PGOOD
BOOST1
TG1
CMDSH-3
5
B1
C
B1
0.22µF
6
L1
3.5µH
M2
M1
LTC3709
7
–
V
OS
SW1
+
8
DIFFOUT SENSE1
+
C
OUT
R
10k
R
F1
191k
100pF
F2
9
–
180µF
V
OS
SENSE1
16V ×2
10
11
12
13
14
15
16
EXTLPF
INTLPF
NC
PGND1
BG1
100nF
V
OUT
3.32k
1µF
C
10µF
IN
35V ×3
470pF
DRV
CC
BOOST2
TG2
BG2
C
B2
1µF
0.22µF
PGND2
L2
3.5µH
–
SW2
SENSE2
10Ω
1µF
+
SENSE2
100pF
V
CC
D
B2
CMDSH-3
M3
M4
D2
B340A
M1-M4: RENESAS HAT2167
C
: SANYO 16SVP180MX
OUT
L1, L2: SUMIDA CDEP147-3R5MC-H
3709 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
Fast 2-Phase Dual Output Step-Down Controller
Wide Operating Range, No R Step-Down Controller
COMMENTS
LTC1708
PLL, V up to 36V, Tracking
IN
LTC1778
Single Channel, GN16 Package
SENSE
LTC3413
DDR, QDR Memory Termination Regulator
Fast, Dual No R , 2-Phase Synchronous Step-Down Controller
±3A Output Current, 90% Efficiency
LTC3708
Very Fast Transient Response; Very Low Duty Factor
Tracking; Minimum C , C
SENSE
IN OUT
LTC3728
LTC3729
Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator
Fixed Frequency, Dual Output
550kHz, PolyPhase, High Efficiency, Synchronous Step-Down
Switching Regulator
Fixed Frequency, Single Output, Up to 12-Phase
Operation
LTC3730/LTC3731 3-Phase to 12-Phase Synchronous Step-Down Controllers
LTC3732
40A to 240A, 4.5V ≤ V ≤ 32V, 0.6V ≤ V
≤ 5V
IN
OUT
LTC3778
Wide Operating Range, No R
Step-Down Controller
Single Channel, Separate V Programming
ON
SENSE
3709fb
LT/LWI 1006 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
相关型号：
LTC3709EUH#TRPBF
LTC3709 - Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
Linear
LTC3711EGN#PBF
LTC3711 - 5-Bit Adjustable, Wide Operating Range, No RSENSE Step-Down Controller; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C
Linear
LTC3711EGN#TR
LTC3711 - 5-Bit Adjustable, Wide Operating Range, No RSENSE Step-Down Controller; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明