LTC3642EDD#PBF [Linear]
LTC3642 - High Efficiency, High Voltage 50mA Synchronous Step-Down Converter; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC3642EDD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3642 - High Efficiency, High Voltage 50mA Synchronous Step-Down Converter; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总22页 (文件大小：1681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3642
High Efficiency, High Voltage
50mA Synchronous
Step-Down Converter
FEATURES
DESCRIPTION
The LTC®3642 is a high efficiency, high voltage step-down
DC/DC converter with internal high side and synchronous
power switches that draws only 12μA typical DC sup-
ply current at no load while maintaining output voltage
regulation.
n
Wide Input Voltage Range: 4.5V to 45V
n
Tolerant of 60V Input Transients
n
Internal High Side and Low Side Power Switches
n
No Compensation Required
50mA Output Current
n
n
Low Dropout Operation: 100% Duty Cycle
The LTC3642 can supply up to 50mA load current and
features a programmable peak current limit that provides
a simple method for optimizing efficiency in lower current
applications. The LTC3642’s combination of Burst Mode®
operation, integrated power switches, low quiescent cur-
rent, and programmable peak current limit provides high
efficiency over a broad range of load currents.
n
Low Quiescent Current: 12µA
n
0.8V Feedback Voltage Reference
n
Adjustable Peak Current Limit
n
Internal and External Soft-Start
n
Precise RUN Pin Threshold with Adjustable
Hysteresis
n
3.3V, 5V and Adjustable Output Versions
n
With its wide 4.5V to 45V input range and internal
overvoltagemonitorcapableofprotectingthepartthrough
60V surges, the LTC3642 is a robust converter suited for
regulating a wide variety of power sources. Additionally,
theLTC3642includesapreciserunthresholdandsoft-start
feature to guarantee that the power system start-up is
well-controlled in any environment.
Only Three External Components Required for Fixed
Output Versions
n
Low Profile (0.75mm) 3mm × 3mm DFN and
Thermally-Enhanced MS8E Packages
APPLICATIONS
n
4mA to 20mA Current Loops
The LTC3642 is available in the thermally enhanced
3mm × 3mm DFN and MS8E packages.
L, LT, LTC, LTM, Burst Mode, Linear Technology, and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
n
ꢀIndustrial Control Supplies
n
ꢀDistributed Power Systems
n
ꢀPortable Instruments
n
ꢀBattery-Operated Devices
n
ꢀAutomotive Power Systems
Efficiency and Power Loss vs Load Current
TYPICAL APPLICATION
100
V
= 10V
IN
95
90
85
80
75
70
65
100
10
1
5V, 50mA Step-Down Converter
EFFICIENCY
150µH
V
OUT
V
IN
V
SW
5V
IN
5V TO 45V
1µF
50mA
LTC3642-5
10µF
POWER LOSS
RUN
HYST
V
OUT
SS
I
SET
GND
3642 TA01a
0.1
100
0.1
1
10
LOAD CURRENT (mA)
3642 TA01b
3642fc
1
LTC3642
(Note 1)
ABSOLUTE MAXIMUM RATINGS
V Supply Voltage.....................................–0.3V to 60V
Operating Junction Temperature Range
IN
SW Voltage (DC)........................... –0.3V to (V + 0.3V)
(Note 2)..................................................–40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
IN
RUN Voltage ..............................................–0.3V to 60V
HYST, I , SS Voltages ...............................–0.3V to 6V
SET
V ...............................................................–0.3V to 6V
MS8E................................................................ 300°C
FB
V
OUT
(Fixed Output Versions).......................–0.3V to 6V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
SW
1
2
3
4
8
7
6
5
GND
SW 1
8 GND
7 HYST
V
HYST
IN
9
GND
V
SET
SS 4
2
3
9
GND
IN
6 V /V
I
I
V
/V
OUT FB
SET
OUT FB
5 RUN
SS
RUN
MS8E PACKAGE
8-LEAD PLASTIC MSOP
= 125°C, θ = 40°C/W, θ = 5°-10°C/W
JA JC
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
JMAX
T
= 125°C, θ = 43°C/W, θ = 3°C/W
JA JC
JMAX
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTDTH
LTDYN
LTDYQ
LTDTH
LTDYN
LTDYQ
LDTJ
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3642EMS8E#PBF
LTC3642EMS8E-3.3#PBF
LTC3642EMS8E-5#PBF
LTC3642IMS8E#PBF
LTC3642IMS8E-3.3#PBF
LTC3642IMS8E-5#PBF
LTC3642EDD#PBF
LTC3642EMS8E#TRPBF
LTC3642EMS8E-3.3#TRPBF
LTC3642EMS8E-5#TRPBF
LTC3642IMS8E#TRPBF
LTC3642IMS8E-3.3#TRPBF
LTC3642IMS8E-5#TRPBF
LTC3642EDD#TRPBF
8-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
LTC3642EDD-3.3#PBF
LTC3642EDD-5#PBF
LTC3642IDD#PBF
LTC3642EDD-3.3#TRPBF
LTC3642EDD-5#TRPBF
LTC3642IDD#TRPBF
LDYM
LDYP
LDTJ
LTC3642IDD-3.3#PBF
LTC3642IDD-5#PBF
LTC3642IDD-3.3#TRPBF
LTC3642IDD-5#TRPBF
LDYM
LDYP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3642fc
2
LTC3642
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). VIN = 10V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply (V )
IN
V
IN
Input Voltage Operating Range
4.5
45
V
l
l
UVLO
V
IN
Undervoltage Lockout
V
V
Rising
Falling
3.80
3.75
4.15
4.00
150
4.50
4.35
V
V
mV
IN
IN
Hysteresis
OVLO
V
Overvoltage Lockout
V
V
Rising
Falling
47
45
50
48
2
52
50
V
V
V
IN
IN
IN
Hysteresis
I
Q
DC Supply Current (Note 3)
Active Mode
125
12
3
220
22
6
µA
µA
µA
Sleep Mode
Shutdown Mode
V
= 0V
RUN
Output Supply (V /V
)
OUT FB
l
l
V
OUT
Output Voltage Trip Thresholds
LTC3642-3.3V, V
LTC3642-3.3V, V
Rising
Falling
3.260
3.240
3.310
3.290
3.360
3.340
V
V
OUT
OUT
l
l
LTC3642-5V, V
LTC3642-5V, V
Rising
Falling
4.940
4.910
5.015
4.985
5.090
5.060
V
V
OUT
OUT
l
l
V
V
Feedback Comparator Trip Voltage
Feedback Comparator Hysteresis Voltage
Feedback Pin Current
V
Rising
FB
0.792
3
0.800
5
0.808
7
V
mV
nA
FB
HYST
I
Adjustable Output Version, V = 1V
–10
0
10
FB
FB
∆V
LINEREG
Feedback Voltage Line Regulation
V
= 4.5V to 45V
IN
0.001
%/V
LTC3642-5, V = 6V to 45V
IN
Operation
V
RUN
Run Pin Threshold Voltage
RUN Rising
RUN Falling
Hysteresis
1.17
1.06
1.21
1.10
110
1.25
1.14
V
V
mV
I
Run Pin Leakage Current
RUN = 1.3V
–10
0
10
0.1
10
nA
V
RUN
V
Hysteresis Pin Voltage Low
Hysteresis Pin Leakage Current
Soft-Start Pin Pull-Up Current
Internal Soft-Start Time
RUN < 1V, I
= 1mA
HYST
0.07
0
HYSTL
HYST
SS
I
I
t
I
V
V
= 1.3V
–10
4.5
nA
µA
ms
HYST
< 1.5V
5.5
0.75
6.5
SS
SS Pin Floating
INTSS
PEAK
l
Peak Current Trip Threshold
I
Floating
100
20
115
55
25
130
32
mA
mA
mA
SET
500k Resistor from I to GND
SET
I
Shorted to GND
SET
R
Power Switch On-Resistance
Top Switch
Bottom Switch
ON
I
SW
I
SW
= –25mA
= 25mA
3.0
1.5
Ω
Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors. The junction temperature (T , in °C) is calculated from the ambient
J
temperature (T , in °C) and power dissipation (P , in Watts) according to
A
D
Note 2: The LTC3642 is tested under pulsed load conditions such that T ≈ T .
J
A
the formula:
LTC3642E is guaranteed to meet specifications from 0°C to 85°C junction
temperature. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3642I is guaranteed over the
full –40°C to 125°C operating junction temperature range. Note that the
T = T + (P • θ ), where θ (in °C/W) is the package thermal
J
A
D
JA
JA
impedance.
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
3642fc
3
LTC3642
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Efficiency vs Load Current
Line Regulation
Load Regulation
5.05
100
95
90
85
80
75
70
65
60
0.30
0.20
0.10
0
FIGURE 11 CIRCUIT
I
= 25mA
V
= 10V
IN
LOAD
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
4.96
4.95
I
OPEN
= 5V
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
OPEN
SET
OUT
V
= 10V
IN
V
I
SET
V
IN
= 15V
V
= 45V
IN
V
IN
= 24V
–0.10
–0.20
–0.30
V
= 36V
IN
0
10
20
30
40
50
0.1
1
10
100
30 35
10 15 20 25
INPUT VOLTAGE (V)
5
40 45
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3642 G01
3642 G03
3642 G02
Feedback Comparator Voltage
vs Temperature
Feedback Comparator Hysteresis
Voltage vs Temperature
Peak Current Trip Threshold
vs Temperature and ISET
0.801
0.800
0.799
0.798
130
120
110
100
90
80
70
60
50
40
30
20
10
5.6
5.4
5.2
5.0
4.8
4.6
4.4
V
= 10V
V
= 10V
IN
IN
V
= 10V
IN
I
OPEN
SET
R
I
= 500k
= GND
ISET
SET
0
–40
–10
20
50
80
110
–40
–10
20
50
80
110
–40
20
50
80
110
–10
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3642 G04
3642 G06
3642 G05
Quiescent Supply Current
vs Temperature
Peak Current Trip Threshold
vs RISET
Quiescent Supply Current
vs Input Voltage
120
110
100
90
14
12
10
8
14
12
10
8
V
= 10V
V
= 10V
IN
IN
SLEEP
SLEEP
80
70
60
6
6
50
SHUTDOWN
4
4
40
SHUTDOWN
30
2
2
20
0
–40
10
0
–10
20
50
80
0
200
400
600
(kΩ)
800 1000 1200
110
15
25
35
5
45
R
TEMPERATURE (°C)
SET
INPUT VOLTAGE (V)
3642 G07
3642 G09
3642 G08
3642fc
4
LTC3642
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Switch On-Resistance
vs Input Voltage
Switch On-Resistance
vs Temperature
Switch Leakage Current
vs Temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4
3
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 45V
V
= 10V
IN
IN
TOP
TOP
SW = 0V
BOTTOM
2
1
0
BOTTOM
SW = 45V
–40
–10
20
50
80
110
–40
–10
20
50
80
110
0
40
50
10
20
30
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3642 G12
3642 G11
3642 G10
Run Comparator Threshold
Voltage vs Temperature
Internal Soft-Start Time
vs Temperature
Efficiency vs Input Voltage
1.30
1.25
1.20
1.15
1.10
1.05
1.00
95
90
1.20
1.15
1.10
1.05
1.00
0.95
0.90
FIGURE 11 CIRCUIT
I
OPEN
SET
RISING
I
= 50mA
LOAD
85
80
I
= 10mA
LOAD
I
= 1mA
LOAD
FALLING
75
70
65
–40
20
50
80
110
–10
10
15
20
25
30
35
40
45
–40
20
50
80
110
–10
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3642 G14
3642 G13
3642 G15
Soft-Start Waveforms
Operating Waveforms
Load Step Transient Response
OUTPUT
VOLTAGE
50mV/DIV
OUTPUT
VOLTAGE
25mV/DIV
SWITCH
VOLTAGE
5V/DIV
OUTPUT
VOLTAGE
1V/DIV
LOAD
CURRENT
25mA/DIV
INDUCTOR
CURRENT
50mA/DIV
3642 G16
3642 G17
3642 G18
C
= 0.047µF
5ms/DIV
SS
V
= 10V
10µs/DIV
V
SET
= 10V
OPEN
1ms/DIV
IN
IN
I
I
OPEN
I
SET
LOAD
FIGURE 11 CIRCUIT
= 25mA
FIGURE 11 CIRCUIT
3642fc
5
LTC3642
PIN FUNCTIONS
SW (Pin 1): Switch Node Connection to Inductor. This
pin connects to the drains of the internal power MOSFET
switches.
V
/V (Pin 6): Output Voltage Feedback. For the fixed
OUT FB
output versions, connect this pin to the output supply. For
the adjustable version, an external resistive divider should
be used to divide the output voltage down for comparison
to the 0.8V reference.
V (Pin 2): Main Supply Pin. A ceramic bypass capacitor
IN
should be tied between this pin and GND (Pin 8).
HYST (Pin 7): Run Hysteresis Open-Drain Logic Output.
This pin is pulled to ground when RUN (Pin 5) is below
1.2V.ThispincanbeusedtoadjusttheRUNpinhysteresis.
See Applications Information.
I
(Pin 3): Peak Current Set Input. A resistor from this
SET
pin to ground sets the peak current trip threshold. Leave
floating for the maximum peak current (115mA). Short
this pin to ground for the minimum peak current (25mA).
A 1µA current is sourced out of this pin.
GND (Pin 8, Exposed Pad Pin 9): Ground. The exposed
pad must be soldered to the printed circuit board ground
plane for optimal electrical and thermal performance.
SS (Pin 4): Soft-Start Control Input. A capacitor to ground
at this pin sets the ramp time to full current output dur-
ing start-up. A 5µA current is sourced out of this pin. If
left floating, the ramp time defaults to an internal 0.75ms
soft-start.
RUN (Pin 5): Run Control Input. A voltage on this pin
above 1.2V enables normal operation. Forcing this pin
below 0.7V shuts down the LTC3642, reducing quiescent
current to approximately 3µA.
3642fc
6
LTC3642
BLOCK DIAGRAM
V
IN
1µA
2
I
SET
C2
3
–
+
PEAK CURRENT
COMPARATOR
RUN
5
LOGIC
AND
+
–
SW
1
L1
SHOOT-
V
OUT
THROUGH
PREVENTION
C1
1.2V
HYST
7
+
–
REVERSE CURRENT
COMPARATOR
VOLTAGE
REFERENCE
FEEDBACK
COMPARATOR
0.800V
+
+
–
5µA
SS
4
V
/V
OUT FB
GND
8
GND
9
R1
6
3642 BD
R2
IMPLEMENT DIVIDER
EXTERNALLY FOR
ADJUSTABLE VERSION
PART
NUMBER
R1
R2
LTC3642
LTC3642-3.3
LTC3642-5
0
∞
2.5M 800k
4.2M 800k
3642fc
7
LTC3642
(Refer to Block Diagram)
OPERATION
TheLTC3642isastep-downDC/DCconverterwithinternal
power switches that uses Burst Mode control, combining
low quiescent current with high switching frequency,
which results in high efficiency across a wide range of
load currents. Burst Mode operation functions by using
short “burst” cycles to ramp the inductor current through
the internal power switches, followed by a sleep cycle
where the power switches are off and the load current is
supplied by the output capacitor. During the sleep cycle,
the LTC3642 draws only 12µA of supply current. At light
loads, the burst cycles are a small percentage of the total
cycle time which minimizes the average supply current,
greatly improving efficiency.
The hysteretic nature of this control architecture results
in a switching frequency that is a function of the input
voltage, output voltage and inductor value. This behavior
provides inherent short-circuit protection. If the output
is shorted to ground, the inductor current will decay very
slowly during a single switching cycle. Since the high side
switch turns on only when the inductor current is near
zero,theLTC3642inherentlyswitchesatalowerfrequency
during start-up or short-circuit conditions.
Start-Up and Shutdown
IfthevoltageontheRUNpinislessthan0.7V, theLTC3642
enters a shutdown mode in which all internal circuitry is
disabled,reducingtheDCsupplycurrentto3µA.Whenthe
voltageontheRUNpinexceeds1.21V,normaloperationof
the main control loop is enabled. The RUN pin comparator
has 110mV of internal hysteresis, and therefore must fall
below 1.1V to disable the main control loop.
Main Control Loop
The feedback comparator monitors the voltage on the V
FB
pin and compares it to an internal 800mV reference. If
this voltage is greater than the reference, the comparator
activates a sleep mode in which the power switches and
The HYST pin provides an added degree of flexibility for
the RUN pin operation. This open-drain output is pulled
to ground whenever the RUN comparator is not tripped,
signaling that the LTC3642 is not in normal operation. In
current comparators are disabled, reducing the V pin
IN
supplycurrenttoonly12µA.Astheloadcurrentdischarges
the output capacitor, the voltage on the V pin decreases.
FB
When this voltage falls 5mV below the 800mV reference,
applications where the RUN pin is used to monitor the V
IN
the feedback comparator trips and enables burst cycles.
voltage through an external resistive divider, the HYST pin
can be used to increase the effective RUN comparator
hysteresis.
At the beginning of the burst cycle, the internal high side
power switch (P-channel MOSFET) is turned on and the
inductor current begins to ramp up. The inductor current
increases until either the current exceeds the peak cur-
An internal 1ms soft-start function limits the ramp rate of
the output voltage on start-up to prevent excessive input
supply droop. If a longer ramp time and consequently less
supplydroopisdesired,acapacitorcanbeplacedfromthe
SS pin to ground. The 5µA current that is sourced out of
thispinwillcreateasmoothvoltageramponthecapacitor.
If this ramp rate is slower than the internal 1ms soft-start,
then the output voltage will be limited by the ramp rate
on the SS pin instead. The internal and external soft-start
functions are reset on start-up and after an undervoltage
or overvoltage event on the input supply.
rent comparator threshold or the voltage on the V pin
FB
exceeds 800mV, at which time the high side power switch
is turned off and the low side power switch (N-channel
MOSFET)turnson. Theinductorcurrentrampsdownuntil
the reverse current comparator trips, signaling that the
current is close to zero. If the voltage on the V pin is
FB
still less than the 800mV reference, the high side power
switch is turned on again and another cycle commences.
The average current during a burst cycle will normally be
greaterthantheaverageloadcurrent.Forthisarchitecture,
the maximum average output current is equal to half of
the peak current.
In order to ensure a smooth start-up transition in any
application, the internal soft-start also ramps the peak
3642fc
8
LTC3642
(Refer to Block Diagram)
OPERATION
inductor current from 25mA during its 1ms ramp time to
the set peak current threshold. The external ramp on the
SS pin does not limit the peak inductor current during
Input Undervoltage and Overvoltage Lockout
The LTC3642 implements a protection feature which dis-
ables switching when the input voltage is not within the
start-up; however, placing a capacitor from the I
to ground does provide this capability.
pin
SET
4.5V to 45V operating range. If V falls below 4V typical
IN
(4.35V maximum), an undervoltage detector disables
switching. Similarly, if V rises above 50V typical (47V
IN
Peak Inductor Current Programming
minimum), an overvoltage detector disables switching.
Whenswitchingisdisabled,theLTC3642cansafelysustain
input voltages up to the absolute maximum rating of 60V.
Switching is enabled when the input voltage returns to the
4.5V to 45V operating range.
The offset of the peak current comparator nominally
provides a peak inductor current of 115mA. This peak
inductor current can be adjusted by placing a resistor
from the I pin to ground. The 1µA current sourced out
SET
of this pin through the resistor generates a voltage that is
translated into an offset in the peak current comparator,
which limits the peak inductor current.
3642fc
9
LTC3642
APPLICATIONS INFORMATION
ThebasicLTC3642applicationcircuitisshownonthefront
page of this data sheet. External component selection is
determinedbythemaximumloadcurrentrequirementand
beginswiththeselectionofthepeakcurrentprogramming
maximum average output current for this architecture
is limited to half of the peak current. Therefore, be sure
to select a value that sets the peak current with enough
margintoprovideadequateloadcurrentunderallforesee-
able operating conditions.
resistor,R .TheinductorvalueLcanthenbedetermined,
ISET
followed by capacitors C and C
.
IN
OUT
Inductor Selection
Peak Current Resistor Selection
Theinductor,inputvoltage,outputvoltageandpeakcurrent
determine the switching frequency of the LTC3642. For
a given input voltage, output voltage and peak current,
the inductor value sets the switching frequency when the
output is in regulation. A good first choice for the inductor
value can be determined by the following equation:
The peak current comparator has a maximum current
limit of 115mA nominally, which results in a maximum
average current of 55mA. For applications that demand
less current, the peak current threshold can be reduced
to as little as 25mA. This lower peak current allows the
use of lower value, smaller components (input capacitor,
output capacitor and inductor), resulting in lower input
supply ripple and a smaller overall DC/DC converter.
VOUT
V
V
IN
OUT
L =
• 1–
f •I
PEAK
The threshold can be easily programmed with an ap-
The variation in switching frequency with input voltage
and inductance is shown in the following two figures for
propriately chosen resistor (R ) between the I
pin
ISET
SET
and ground. The value of resistor for a particular peak
current can be computed by using Figure 1 or the follow-
ing equation:
typical values of V . For lower values of I
, multiply
OUT
PEAK
the frequency in Figure 2 and Figure 3 by 115mA/I
.
PEAK
An additional constraint on the inductor value is the
LTC3642’s100nsminimumon-timeofthehighsideswitch.
Therefore, in order to keep the current in the inductor well
controlled, the inductor value must be chosen so that it is
6
R
ISET
= I
• 9.09 • 10
PEAK
where 25mA < I
< 115mA.
PEAK
The peak current is internally limited to be within the
larger than L , which can be computed as follows:
MIN
range of 25mA to 115mA. Shorting the I pin to ground
SET
V
IN(MAX) • tON(MIN)
programs the current limit to 25mA, and leaving it floating
sets the current limit to the maximum value of 115mA.
When selecting this resistor value, be aware that the
LMIN
=
IPEAK(MAX)
where V
is the maximum input supply voltage for
IN(MAX)
the application, t
1100
1000
900
800
700
600
500
400
300
200
100
0
is 100ns, and I
is the
ON(MIN)
PEAK(MAX)
maximum allowed peak inductor current. Although the
above equation provides the minimum inductor value,
higherefficiencyisgenerallyachievedwithalargerinductor
value, which produces a lower switching frequency. For a
given inductor type, however, as inductance is increased
DCresistance(DCR)alsoincreases.HigherDCRtranslates
into higher copper losses and lower current rating, both
of which place an upper limit on the inductance. The
recommended range of inductor values for small surface
mount inductors as a function of peak current is shown in
Figure 4. The values in this range are a good compromise
between the tradeoffs discussed above. For applications
3642fc
10
20 25 30 35 40 45 50
MAXIMUM LOAD CURRENT (mA)
15
3642 F01
Figure 1. RISET Selection
10
LTC3642
APPLICATIONS INFORMATION
where board area is not a limiting factor, inductors with
largercorescanbeused,whichextendstherecommended
range of Figure 4 to larger values.
700
V
I
= 5V
OUT
SET
OPEN
L = 47µH
600
500
L = 68µH
Inductor Core Selection
400
300
200
100
L = 100µH
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of the more expensive ferrite cores. Actual
core loss is independent of core size for a fixed inductor
value but is very dependent of the inductance selected.
As the inductance increases, core losses decrease. Un-
fortunately, increased inductance requires more turns of
wire and therefore copper losses will increase.
L = 150µH
L = 220µH
L = 470µH
0
10 15 20 25
INPUT VOLTAGE (V)
40 45
5
30 35
3642 F02
Figure 2. Switching Frequency for VOUT = 5V
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequently output voltage ripple. Do
not allow the core to saturate!
500
V
SET
= 3.3V
OUT
450
400
350
300
250
200
150
100
50
L = 47µH
I
OPEN
L = 68µH
L = 100µH
L = 150µH
L = 220µH
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials
are small and do not radiate energy but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko, Sumida and Vishay.
L = 470µH
0
5
25
INPUT VOLTAGE (V)
35 40
10 15 20
30
45
3642 F03
Figure 3. Switching Frequency for VOUT = 3.3V
10000
C and C
Selection
IN
OUT
1000
100
The input capacitor, C , is needed to filter the trapezoidal
IN
current at the source of the top high side MOSFET. To
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used.
Approximate RMS current is given by:
10
100
PEAK INDUCTOR CURRENT (mA)
VOUT
V
IN
V
IN
VOUT
3642 F04
IRMS = IOUT(MAX)
•
•
− 1
Figure 4. Recommended Inductor Values for Maximum Efficiency
3642fc
11
LTC3642
APPLICATIONS INFORMATION
Dry tantalum, special polymer, aluminum electrolytic,
and ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important only to use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and long-
termreliability.CeramiccapacitorshaveexcellentlowESR
characteristics but can have high voltage coefficient and
audible piezoelectric effects. The high quality factor (Q)
of ceramic capacitors in series with trace inductance can
also lead to significant ringing.
This formula has a maximum at V = 2V , where
IN
OUT
I
= I /2. This simple worst-case condition is
RMS
OUT
commonly used for design because even significant
deviationsdonotoffermuchrelief.Notethatripplecurrent
ratings from capacitor manufacturers are often based
only on 2000 hours of life which makes it advisable to
further derate the capacitor, or choose a capacitor rated
at a higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements
in the design.
The output capacitor, C , filters the inductor’s ripple
OUT
current and stores energy to satisfy the load current when
the LTC3642 is in sleep. The output ripple has a lower limit
of V /160 due to the 5mV typical hysteresis of the feed-
OUT
back comparator. The time delay of the comparator adds
an additional ripple voltage that is a function of the load
current. During this delay time, the LTC3642 continues to
switch and supply current to the output. The output ripple
can be approximated by:
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now be-
coming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
thepowerissuppliedbyawalladapterthroughlongwires,
a load step at the output can induce ringing at the input,
–6
LOAD
VOUT
160
IPEAK
2
4 •10
COUT
ΔVOUT
≈
–I
+
Theoutputrippleisamaximumatnoloadandapproaches
lower limit of V /160 at full load. Choose the output
OUT
capacitor C
to limit the output voltage ripple at mini-
mum load current.
V . At best, this ringing can couple to the output and be
OUT
IN
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
The value of the output capacitor must be large enough
to accept the energy stored in the inductor without a large
changeinoutputvoltage. Settingthisvoltagestepequalto
1% of the output voltage, the output capacitor must be:
voltage spike at V large enough to damage the LTC3642.
IN
For applications with inductive source impedance, such
as a long wire, a series RC network may be required in
parallel with C to dampen the ringing of the input supply.
IN
2
I
V
Figure 5 shows this circuit and the typical values required
PEAK
OUT
COUT > 50 •L •
to dampen the ringing.
Typically, a capacitor that satisfies the voltage ripple
requirement is adequate to filter the inductor ripple. To
avoid overheating, theoutputcapacitor mustalsobe sized
to handle the ripple current generated by the inductor. The
worst-case ripple current in the output capacitor is given
LTC3642
L
IN
V
IN
L
C
IN
R =
4 • C
IN
3642 F05
C
IN
IN
by I
= I
/2. Multiple capacitors placed in parallel
RMS
PEAK
maybeneededtomeettheESRandRMScurrenthandling
requirements.
Figure 5. Series RC to Reduce VIN Ringing
3642fc
12
LTC3642
APPLICATIONS INFORMATION
Output Voltage Programming
controller is enabled. Figure 7 shows examples of con-
figurations for driving the RUN pin from logic.
For the adjustable version, the output voltage is set by
an external resistive divider according to the following
equation:
V
V
IN
SUPPLY
4.7M
LTC3642
RUN
LTC3642
RUN
R1
R2
VOUT = 0.8V • 1+
3642 F07
The resistive divider allows the V pin to sense a fraction
FB
of the output voltage as shown in Figure 6. Output voltage
Figure 7. RUN Pin Interface to Logic
adjustment range is from 0.8V to V .
IN
V
OUT
The RUN pin can alternatively be configured as a precise
R1
undervoltage lockout (UVLO) on the V supply with a
IN
V
FB
resistive divider from V to ground. The RUN pin com-
IN
R2
LTC3642
GND
parator nominally provides 10% hysteresis when used in
this method; however, additional hysteresis may be added
with the use of the HYST pin. The HYST pin is an open-
drain output that is pulled to ground whenever the RUN
comparator is not tripped. A simple resistive divider can
Figure 6. Setting the Output Voltage
be used as shown in Figure 8 to meet specific V voltage
IN
To minimize the no-load supply current, resistor values in
themegohmrangeshouldbeused;however,largeresistor
values should be used with caution. The feedback divider
is the only load current when in shutdown. If PCB leak-
age current to the output node or switch node exceeds
the load current, the output voltage will be pulled up. In
normal operation, this is generally a minor concern since
the load current is much greater than the leakage. The
increase in supply current due to the feedback resistors
can be calculated from:
requirements.
V
IN
R1
RUN
LTC3642
HYST
R2
R3
3642 F08
Figure 8. Adjustable Undervoltage Lockout
VOUT
R1+R2
V
V
OUT
IN
∆IVIN
=
•
SpecificvaluesfortheseUVLOthresholdscanbecomputed
from the following equations:
Run Pin with Programmable Hysteresis
R1
R2
Rising V UVLO Threshold= 1.21V • 1+
The LTC3642 has a low power shutdown mode controlled
by the RUN pin. Pulling the RUN pin below 0.7V puts the
LTC3642 into a low quiescent current shutdown mode
(IQ ~ 3µA). When the RUN pin is greater than 1.2V, the
IN
R1
Falling V UVLO Threshold= 1.10V • 1+
IN
R2+R3
3642fc
13
LTC3642
APPLICATIONS INFORMATION
I
pin. With only a capacitor connected between I
SET
The minimum value of these thresholds is limited to the
SET
and ground, the peak current ramps linearly from 25mA
to 115mA, and the peak current soft-start time can be
expressed as:
internal V UVLO thresholds that are shown in the Electri-
IN
cal Characteristics table. The current that flows through
this divider will directly add to the shutdown, sleep and
active current of the LTC3642, and care should be taken to
minimizetheimpactofthiscurrentontheoverallefficiency
of the application circuit. Resistor values in the megohm
range may be required to keep the impact on quiescent
shutdown and sleep currents low. Be aware that the HYST
pin cannot be allowed to exceed its absolute maximum
rating of 6V. To keep the voltage on the HYST pin from
exceeding 6V, the following relation should be satisfied:
0.8V
1µA
tSS(ISET) = CISET
•
A linear ramp of peak current appears as a quadratic
waveform on the output voltage. For the case where the
peak current is reduced by placing a resistor from I
to ground, the peak current offset ramps as a decaying
exponential with a time constant of R • C . For this
case, the peak current soft-start time is approximately
3 • R • C
SET
ISET
ISET
R3
V
•
< 6V
IN(MAX)
.
ISET
ISET
R1+R2+R3
Unlike the SS pin, the I
pin does not get pulled to
SET
The RUN pin may also be directly tied to the V supply
IN
ground during an abnormal event; however, if the I
SET
for applications that do not require the programmable
pin is floating (programmed to 115mA peak current),
undervoltagelockoutfeature.Inthisconfiguration,switch-
the SS and I pins may be tied together and connected
SET
ingisenabledwhenV surpassestheinternalundervoltage
IN
to a capacitor to ground. For this special case, both the
peak current and the reference voltage will soft-start on
power-up and after fault conditions. The ramp time for
lockout threshold.
Soft-Start
this combination is C
• (0.8V/6µA).
SS(ISET)
The internal 0.75ms soft-start is implemented by ramping
boththeeffectivereferencevoltagefrom0Vto0.8Vandthe
Efficiency Considerations
peak current limit set by the I pin (25mA to 115mA).
SET
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Toincreasethedurationofthereferencevoltagesoft-start,
place a capacitor from the SS pin to ground. An internal
5µA pull-up current will charge this capacitor, resulting
in a soft-start ramp time given by:
0.8V
5µA
Efficiency = 100% – (L1 + L2 + L3 + ...)
tSS = CSS
•
where L1, L2, etc. are the individual losses as a percent-
age of input power.
When the LTC3642 detects a fault condition (input supply
undervoltage or overvoltage) or when the RUN pin falls
below 1.1V, the SS pin is quickly pulled to ground and the
internal soft-start timer is reset. This ensures an orderly
restart when using an external soft-start capacitor.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
2
the losses: V operating current and I R losses. The V
IN
IN
operating current dominates the efficiency loss at very
2
low load currents whereas the I R loss dominates the
The duration of the 1ms internal peak current soft-start
efficiency loss at medium to high load currents.
may be increased by placing a capacitor from the I pin
SET
1. The V operating current comprises two components:
toground.Thepeakcurrentsoft-startwillrampfrom25mA
IN
The DC supply current as given in the electrical charac-
to the final peak current value determined by a resistor
teristics and the internal MOSFET gate charge currents.
from I
to ground. A 1µA current is sourced out of the
SET
3642fc
14
LTC3642
APPLICATIONS INFORMATION
The gate charge current results from switching the gate
capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to
First, calculate the inductor value that gives the required
switching frequency:
3.3V
250kHz • 115mA
3.3V
24V
Ê
ˆ Ê
ˆ
L =
• 1–
@ 100µH
high again, a packet of charge, dQ, moves from V to
Á
Ë
˜ Á
¯ Ë
˜
¯
IN
ground. The resulting dQ/dt is the current out of V
IN
that is typically larger than the DC bias current.
Next, verify that this value meets the L
requirement.
MIN
2
2. I R losses are calculated from the resistances of the
For this input voltage and peak current, the minimum
inductor value is:
internal switches, R , and external inductor R . When
SW
L
switching, the average output current flowing through
the inductor is “chopped” between the high side PMOS
switch and the low side NMOS switch. Thus, the series
resistance looking back into the switch pin is a function
24V • 100ns
LMIN
=
≅ 22µH
115mA
Therefore, theminimuminductorrequirementissatisfied,
and the 100μH inductor value may be used.
of the top and bottom switch R
values and the
DS(ON)
duty cycle (DC = V /V ) as follows:
OUT IN
Next,C andC areselected.Forthisdesign,C should
IN
OUT
IN
R
= (R
)DC + (R
)(1 – DC)
SW
DS(ON)TOP
DS(ON)BOT
be size for a current rating of at least:
The R
for both the top and bottom MOSFETs can
DS(ON)
3.3V
24V
24V
3.3V
be obtained from the Typical Performance Characteris-
IRMS = 50mA •
•
– 1 ≅ 18mARMS
2
tics curves. Thus, to obtain the I R losses, simply add
R
to R and multiply the result by the square of the
SW
L
Due to the low peak current of the LTC3642, decoupling
average output current:
the V supply with a 1µF capacitor is adequate for most
IN
2
2
I R Loss = I (R + R )
O
SW
L
applications.
Other losses, including C and C
losses and inductor core losses, generally account for
less than 2% of the total power loss.
ESR dissipative
OUT
IN
C
will be selected based on the output voltage ripple
OUT
requirement. For a 1.5% (50mV) output voltage ripple at
no load, C
can be calculated from:
OUT
–6
115
mA • 4 •10
Thermal Considerations
COUT
=
3.3V
160
The LTC3642 does not dissipate much heat due to its high
efficiency and low peak current level. Even in worst-case
conditions (high ambient temperature, maximum peak
current and high duty cycle), the junction temperature will
exceed ambient temperature by only a few degrees.
2 50mV –
A 7.8µF capacitor gives this typical output voltage ripple at
no load. Choose a 10µF capacitor as a standard value.
The output voltage can now be programmed by choosing
the values of R1 and R2. Choose R2 = 240k and calculate
R1 as:
Design Example
As a design example, consider using the LTC3642 in an
application with the following specifications: V = 24V,
IN
VOUT
0.8V
V
= 3.3V, I
= 50mA, f = 250kHz. Furthermore, as-
R1=
– 1 •R2 = 750k
OUT
OUT
sume for this example that switching should start when
IN
V is greater than 12V and should stop when V is less
than 8V.
IN
3642fc
15
LTC3642
APPLICATIONS INFORMATION
3. Keep the switching node, SW, away from all sensitive
smallsignalnodes.Therapidtransitionsontheswitching
node can couple to high impedance nodes, in particular
The undervoltage lockout requirement on V can be
IN
satisfied with a resistive divider from V to the RUN and
IN
HYST pins. Choose R1 = 2M and calculate R2 and R3 as
V , and create increased output ripple.
follows:
FB
4. Flood allunused area on alllayers with copper. Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
1.21V
IN(RISING) – 1.21V
R2 =
R3 =
•R1= 224k
V
DC net (V , V , GND or any other DC rail in your
IN OUT
1.1V
IN(FALLING) – 1.1V
system).
•R1–R2 = 90.8k
V
L1
2
1
6
3
Choose standard values for R2 = 226k and R3 = 91k. The
pin should be left open in this example to select maxi-
mum peak current (115mA). Figure 9 shows a complete
schematic for this design example.
V
IN
V
SW
V
OUT
IN
I
LTC3642
R1
R2
SET
5
7
4
C
OUT
RUN
HYST
SS
V
FB
C
IN
I
SET
GND
8, 9
C
R
SET
SS
100µH
V
OUT
V
IN
V
SW
LTC3642
3.3V
IN
3642 F10a
24V
50mA
10µF
2M
1µF
RUN
I
SET
226k
91k
SS
750k
240k
V
FB
HYST
L1
GND
3642 F09
V
IN
V
OUT
C
IN
C
OUT
Figure 9. 24V to 3.3V, 50mA Regulator at 250kHz
R1
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3642. Check the following in your layout:
R2
R
C
SS
SET
GND
3642 F10b
1. Large switched currents flow in the power switches
and input capacitor. The loop formed by these compo-
nents should be as small as possible. A ground plane
is recommended to minimize ground impedance.
VIAS TO GROUND PLANE
VIAS TO INPUT SUPPLY (V
)
IN
OUTLINE OF LOCAL GROUND PLANE
Figure 10. Layout Example
2. Connect the (+) terminal of the input capacitor, C , as
IN
close as possible to the V pin. This capacitor provides
IN
the AC current into the internal power MOSFETs.
3642fc
16
LTC3642
TYPICAL APPLICATIONS
Efficiency vs Load Current
L1
94
93
92
91
90
89
88
220µH
V
= 10V
IN
V
V
IN
OUT
V
SW
LTC3642
IN
5V TO 45V
5V
R
SET
= 750k
C
R1
C
IN
OUT
4.7µF
4.2M
100µF
R
SET
= 500k
RUN
HYST
V
FB
R2
800k
I
OPEN
SET
I
SS
SET
C
GND
SS
R
SET
47nF
3642 F11a
C
C
: TDK C5750X7R2A475MT
: AVX 1812D107MAT
IN
OUT
L1: TDK SLF7045T-221MR33-PF
Figure 11. High Efficiency 5V Regulator
1
10
LOAD CURRENT (mA)
100
3642 F11b
3.3V, 50mA Regulator with Peak Current Soft-Start, Small Size
Soft-Start Waveforms
L1
47µH
V
OUT
V
IN
V
SW
LTC3642
RUN
3.3V
IN
4.5V TO 24V
C
R1
50mA
C
OUTPUT VOLTAGE
1V/DIV
IN
1µF
OUT
294k
10µF
V
FB
R2
93.1k
I
SET
SS
HYST
GND
3642 TA02a
C
INDUCTOR CURRENT
20mA/DIV
SS
0.1µF
C
C
: TDK C3216X7R1E105KT
: AVX 08056D106KAT2A
IN
OUT
3642 TA03b
2ms/DIV
L1: TAIYO YUDEN CBC2518T470K
Positive-to-Negative Converter
Maximum Load Current vs Input Voltage
L1
100µH
50
V
= –3V
V
OUT
V
IN
45
40
35
30
25
20
15
10
V
SW
LTC3642
RUN
IN
4.5V TO 33V
C
IN
R1
= –5V
1µF
OUT
1M
C
OUT
I
V
FB
SET
10µF
V
OUT
= –12V
HYST
GND
SS
R2
71.5k
V
OUT
–12V
C
C
: TDK C3225X7R1H105KT
: MURATA GRM32DR71C106KA01
IN
OUT
3642 TA04a
L1: TYCO/COEV DQ6530-101M
25 30
10 15 20
INPUT VOLTAGE (V)
5
35 40 45
3642 TA04b
3642fc
17
LTC3642
TYPICAL APPLICATIONS
Small Size, Limited Peak Current, 10mA Regulator
L1
470µH
V
OUT
V
IN
V
SW
LTC3642
5V
IN
7V TO 45V
C
R3
R1
10mA
C
IN
OUT
1µF 470k
470k
10µF
RUN
V
FB
R4
100k
R2
88.7k
HYST
SS
3642 TA05a
R5
33k
I
GND
SET
C
C
: TDK C3225X7R1H105KT
IN
: AVX 08056D106KAT2A
OUT
L1: MURATA LQH32CN471K23
High Efficiency 15V, 10mA Regulator
Efficiency vs Load Current
100
95
90
85
80
75
70
65
L1
4700µH
V
OUT
V
IN
15V
V
V
= 24V
= 36V
V
SW
LTC3642
IN
IN
IN
15V TO 45V
10mA
C
R1
C
IN
OUT
1µF
3M
4.7µF
RUN
V
FB
R2
169k
I
SET
SS
HYST
GND
V
= 45V
IN
3642 TA07a
C
C
: AVX 18125C105KAT2A
IN
OUT
: TDK C3216X7R1E475KT
L1: COILCRAFT DS1608C-475
60
0.1
1
10
LOAD CURRENT (mA)
3642 TA07b
3642fc
18
LTC3642
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
2.10 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.125
0.40 ± 0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3642fc
19
LTC3642
PACKAGE DESCRIPTION
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev I)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1.68
1
0.29
REF
1.88 ± 0.102
(.074 ± .004)
0.889 ± 0.127
(.035 ± .005)
(.066)
0.05 REF
DETAIL “B”
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ± 0.102
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
(.066 ± .004)
DETAIL “B”
8
NO MEASUREMENT PURPOSE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.65
(.0256)
BSC
0.52
(.0205)
REF
0.42 ± 0.038
(.0165 ± .0015)
8
7 6 5
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.65
(.0256)
BSC
MSOP (MS8E) 0910 REV I
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
3642fc
20
LTC3642
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
6/10
Text updates in Description
1
2
Updates to Absolute Maximum Ratings
LTC3642IMS8E-3.3E#PBF changed to LTC3642IMS8E-3.3#PBF in Order Information
Updates to Electrical Characteristics
2
3
Updates to graphs G05, G06, G14, G16, G17
Updated description for Pins 8 and 9 in Pin Functions
Text updates in Operation section
4, 5
6
8,9
13
16
17
22
22
12
15
Text updates in Applications Information section
Figure 10 graphic added
Updated Y-axis text on TA04b graphic
Asterisk and related text added to Typical Application
Related Parts updated
C
10/10 Updated text in C and C
Selection section
IN
OUT
Updated text in Design Example section
3642fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC3642
TYPICAL APPLICATION
5V, 50mA Regulator for Automotive Applications
L1
220µH
V
*
OUT
5V
50mA
V
BATT
12V
V
SW
LTC3642
RUN
IN
C
IN
1µF
R1
C
OUT
10µF
470k
V
FB
R2
88.7k
I
SET
SS
HYST
GND
3642 TA06a
C
C
: TDK C3225X7R2A105M
*V
= V
BATT
FOR V < 5V
BATT
IN
OUT
: KEMET C1210C106K4RAC
OUT
L1: COILTRONICS DRA73-221-R
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 4.5V to 45V (60V
LTC3631/LTC3631-3.3/ 45V, 100mA Synchronous Micropower Step-Down DC/DC
), V
= 0.8V, I = 12µA,
Q
IN
MAX
OUT(MIN)
LTC3631-5
LTC3632
Converter
I
= 3µA, 3mm × 3mm DFN8, MS8E
SD
50V, 20mA Synchronous Micropower Step-Down DC/DC
Converter
V : 4.5V to 50V (60V
SD
), V
= 0.8V, I = 12µA,
Q
IN
MAX
OUT(MIN)
I
= 3µA, 3mm × 3mm DFN8, MS8E
LTC1474
18V, 250mA (I ), High Efficiency Step-Down DC/DC Converter V : 3V to 18V, V
= 1.2V, I = 10µA, I = 6µA, MSOP8
OUT(MIN) Q SD
OUT
IN
LT1934/LT1934-1
36V, 250mA (I ), Micropower Step-Down DC/DC Converter V : 3.2V to 34V, V
= 1.25V, I = 12µA, I < 1µA,
Q SD
OUT
IN
OUT(MIN)
™ Package
with Burst Mode Operation
ThinSOT
LT1939
LT3437
LT3470
LT3685
25V, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO
Controller
V : 3.6V to 25V, V
= 0.8V, I = 2.5mA, I < 10µA,
Q SD
IN
OUT(MIN)
3mm × 3mm DFN10
60V, 400mA (I ), Micropower Step-Down DC/DC Converter V : 3.3V to 60V, V
= 1.25V, I = 100µA, I < 1µA,
Q SD
OUT
IN
OUT(MIN)
with Burst Mode Operation
3mm × 3mm DFN10, TSSOP16E
V : 4V to 40V, V = 1.2V, I = 26µA, I < 1µA,
40V, 250mA (I ), High Efficiency Step-Down DC/DC
OUT
IN
OUT(MIN)
Q
SD
Converter with Burst Mode Operation
2mm × 3mm DFN8, ThinSOT
= 0.78V, I = 70µA, I < 1µA,
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High V : 3.6V to 38V, V
OUT
IN
OUT(MIN)
Q
SD
Efficiency Step-Down DC/DC Converter
3mm × 3mm DFN10, MSOP10E
3642fc
LT 1010 REV C • PRINTED IN USA
22 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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