LTC3447EDD#PBF [Linear]
LTC3447 - I<sup>2</sup>C Controllable Buck Regulator in 3mm x 3mm DFN; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C;型号: | LTC3447EDD#PBF |
厂家: | Linear |
描述: | LTC3447 - I<sup>2</sup>C Controllable Buck Regulator in 3mm x 3mm DFN; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C 稳压器 |
文件: | 总16页 (文件大小:561K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3447
I C Controllable Buck
Regulator in 3mm × 3mm DFN
2
U
FEATURES
DESCRIPTIO
2
I C Programmable Output with 21.6mV Resolution
TheLTC®3447isahighefficiencymonolithicsynchronous
■
2
■
Overtemperature Protected
current mode buck regulator. Using an I C interface, the
■
High Efficiency: Up to 93%
output voltage can be set between 0.69V and 2.05V using
an internal 6-bit DAC.
■
Very Low Quiescent Current: Only 33µA
■
600mA Output Current at V = 3V
IN
The buck regulator has optional external feedback resis-
tors that can be used for setting the initial start up voltage.
The feedback voltage reference for this start-up option
■
■
■
■
■
■
■
■
■
■
■
■
■
■
2.5V to 5.5V Input Voltage Range
1MHz Constant Frequency Operation
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
Stable with Ceramic Capacitors
Shutdown Mode Draws <1µA Supply Current
2% Output Voltage Accuracy
Standard (100kHz) or Fast Mode (400kHz) I C
6-Bit Voltage DAC (0.69V to 2.05V)
Disable Burst Mode Operation
Enable Power Good Blanking
Optional External Start-Up Resistors
Soft-Start
10 Lead, 3mm ×U3mm DFN Package
2
is 0.6V. Once the voltage DAC is updated via the I C, the
buckregulatorswitchesfromexternaltointernalfeedback
resistors. When there are no external resistors, the default
start-up voltage is 1.38V.
2
The switching frequency is internally set at 1MHz, al-
lowing the use of small surface mount inductors and
capacitors.
In Burst Mode® operation, supply current is only 33µA,
dropping to <1µA in shutdown. The 2.5V to 5.5V input
voltage range makes the LTC3447 ideally suited for single
cell Li-Ion battery-powered applications. 100% duty cycle
capability provides low dropout operation, extending
battery life in portable systems. Automatic Burst Mode
operation increases efficiency at light loads, further ex-
tending battery life.
APPLICATIO S
■
Distributed Power Supplies
Notebook Computers
PDAs and Other Handheld Devices
■
■
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815,
6498466, 6611131.
U
Efficiency and Power Loss vs
Load Current (VIN = 3.6V)
TYPICAL APPLICATIO
V
IN
1000
100
10
100
90
80
70
60
50
40
30
20
10
0
2.5V TO 5.5V
C2
4.7µF
V
IN
CERAMIC
RPU1
20k
V
IN
2
PWREN
RUN
PGOOD
I C
V
CCD
V
OUT
LTC3447
0.69V
V
SW
CCD
TO 2.05V
AT 600mA*
L1
3.3µH
C3
4.7µF
C1
10µF
10k
SDA
SCL
10k
R1
SDA
SCL
GND
V
OUT
100k
FB
PULSE SKIP EFFICIENCY
Burst Mode EFFICIENCY
LOSS
R2
49.9k
* 600mA AT V = 3V
IN
1
EXPOSED PADDLE
TO GROUND
1
10
100
1000
3447 TA01
3447 TA01b
LOAD CURRENT (mA)
3447f
1
LTC3447
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
TOP VIEW
V , V
Voltages .......................................–0.3V to 6V
OUT
IN CCD
RUN, V , FB Voltages ..............................–0.3V to V
IN
V
1
2
3
4
5
10 SDA
OUT
SW Voltage ................................... –0.3V to (V + 0.3V)
SCL, SDA Voltages...................................– 0.3V to V
LTC3447EDD
GND
FB
9
8
7
6
V
CCD
IN
11
SCL
RUN
SW
CCD
PGOOD
P-Channel Switch Source Current (DC) ...............800mA
N-Channel Switch Sink Current (DC) ...................800mA
Peak SW Sink and Source Current...........................1.3A
Operating Temperature Range (Note 2) ...–40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range...................–65°C to 125°C
V
IN
DD PART
MARKING
DD PACKAGE
10-LEAD (3mm x 3mm)PLASTIC DFN
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
LBKB
T
= 125°C, θ = 43°C/W, θ = 2.96°C/W
JA JC
JMAX
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified.
SYMBOL
RUN
PARAMETER
CONDITIONS
MIN
0.3
3
TYP
MAX
UNITS
V
Run Threshold
1
1.5
PGOOD
Reports Undervoltage
Feedback Resistance
Regulated Output Voltage
Regulated Output Voltage
Output Voltage Step Size (6-bits)
PGOOD = 0.4V
mA
kΩ
V
R
VOUT
460
0.69
2.05
21.6
V
V
V
●
●
●
0.669
1.989
20.3
0.711
2.112
22.9
OUT(MIN)
OUT(MAX)
OUT
V
mV
ΔVOUT
Output Voltage Line Regulation
VIN = 2.5V to 5.5V (Note 6)
●
0.2
0.2
1.2
1
%/V
%/V
I
Peak Inductor Current
Duty Cycle < 35%, Wafer Level
0.75
2.5
1
1.25
A
%
V
PK
V
V
Output Voltage Load Regulation
Input Voltage Range
0.5
LOADREG
IN
●
5.5
I
S
Input DC Bias Current
Burst Mode Operation
Active Mode
(Note 4)
I
= 0A
= 90%, I
34
280
0.1
60
400
1
µA
µA
µA
LOAD
V
= 0A
OUT
RUN
LOAD
IN
Shutdown
V
= 0V, V = 5.5V
f
Nominal Oscillator Frequency
V
OUT
V
OUT
= 100%
= 0V
●
0.7
1
160
1.3
MHz
kHz
OSC
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 100mA, Wafer Level
= –100mA, Wafer Level
0.32
0.22
0.1
Ω
Ω
PFET
NFET
LSW
DS(ON)
SW
SW
DS(ON)
I
SW Leakage
V
= 0V, V = 0V or 5V, V = 5V
1
µA
V
nA
V
RUN
SW
IN
FB
Optional Start-Up Feedback Voltage
Feedback Input Current
Regulated Feedback Voltage
0.6
2.5
I
10
FB
2
SCL
I C Clock Logic Threshold
(Note 5)
(Note 5)
(Note 5)
(Note 5)
V
CCD/2
THR
2
SCL
I C Clock Logic Hysteresis
300
mV
V
HYST
2
SDA
SDA
I C Data Logic Threshold
V
CCD/2
THR
2
I C Data Logic Hysteresis
300
mV
HYST
3447f
2
LTC3447
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified.
SYMBOL PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
2
I C Interface Timing
2
f
t
t
t
t
t
t
t
t
Maximum I C Operating Frequency
(Note 5)
400
kHz
µs
µs
µs
µs
ns
ns
ns
ns
I2C, MAX
BUF
Bus Free Time Between Stop and Start Condition (Note 5)
1.3
0.6
0.6
20
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time, Input
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
HD,RSTA
SU,RSTA
SU,STOP
HD,DIN
HD,DOUT
SU,DAT
SP
0
Data Hold Time, Output
280
50
410
670
150
Data Setup Time
Pulse Width of Spikes
Suppressed by Input Filter
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3447E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature are assured by design, characterization and correlation with
statistical process controls.
This IC includes overtemperature protection that is intended to protect
the device during momentary overload conditions. Junction temperature
will exceed 125°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 3: T is calculated from the ambient temperature, T , and the power
J
A
dissipation, P , according to the following formula:
Note 5: Determined by design, not production tested.
D
T = T + P • 43°C/W
Note 6: The LTC3447 is tested in a proprietary test mode that connects
J
A
D
V
OUT to FB.
W U
W
TI I G DIAGRA
SDA
t
t
BUF
SU, STA
t
SU, DAT
t
t
t
SU, STO
HD, DAT
HD, STA
t
LOW
SCL
t
HD, STA
t
HIGH
t
r
t
f
START
COMMAND
REPEATED
START
COMMAND
STOP
COMMAND
START
COMMAND
3447 F01
Figure 1. Timing Diagram
3447f
3
LTC3447
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency and Power Loss vs
Load Current (VIN = 5.5V)
EffIciency and Power Loss vs
Load Current (VIN = 3.6V)
DAC Nonlinearity
0.5
0.4
1000
100
10
1000
100
10
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
OUTMAX
V
OUTMAX
0.3
V
OUTMIN
0.2
INL
V
OUTMIN
0.1
0
LOSS
MAX
DNL
–0.1
–0.2
–0.3
–0.4
–0.5
LOSS
10
MAX
LOSS
MIN
LOSS
MIN
1
1000
1
1000
0
20
30
40
50
60
10
1
100
1
10
100
DAC
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3447 GO1
3447 G02
3447 G04
EffIciency and Power Loss vs
Load Current (VIN = 2.5V)
Output Voltage vs Load Current
Bias Current vs Supply Voltage
1000
100
10
0.80
0.75
0.70
0.65
0.60
100
90
80
70
60
50
40
30
20
10
0
2.10
2.05
2.00
1.95
1.90
350
300
250
200
150
100
50
V
OUTMAX
PULSE SKIP
DAC = MAX
DAC = MIN
V
V
V
= 3.6V
= 2.5V
OUTMIN
IN
IN
V
V
= 3.6V
= 2.5V
IN
IN
LOSS
MAX
LOSS
MIN
BURST
1
1000
0
1
10
100
0
200
400
600
800
1000
2.5
4.5
3.5
SUPPLY VOLTAGE (V)
5.5
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3447 G03
3447 G05
3447 G06
Bias Current and Shutdown
Current vs Temperature
Frequency vs Supply Voltage
Frequency vs Temperature
1.12
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
1.30
1.24
1.18
1.12
1.06
1.00
0.94
0.88
0.82
0.76
0.70
3.0
2.5
2.0
1.5
1.0
0.5
0
BIAS CURRENT
360
310
260
210
160
V
= 5.5V
IN
V
= 3.6V
IN
V
= 2.5V
IN
SHUTDOWN CURRENT
V
= 5.5V
IN
V
= 3.6V
IN
V
= 2.5V
IN
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
2.5
3.5
SUPPLY VOLTAGE (V)
5.5
–40 –20
0
20 40 60 80 100 120
4.5
TEMPERATURE (°C)
3447 G07
3447 G08
3447 G09
3447f
4
LTC3447
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RDS(ON) vs Supply Voltage
RDS(ON) vs Temperature
Output Voltage vs Supply Voltage
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
2.060
2.055
2.050
2.045
2.040
2.035
2.030
2.025
2.020
0.720
0.715
0.710
0.705
0.700
0.695
0.690
0.685
0.680
V
= 3.6V
IN
DAC = MAX
PFET
NFET
PFET
NFET
DAC = MIN
2.5
3.5
SUPPLY VOLTAGE (V)
5.5
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
4.5
2.5
3.5
SUPPLY VOLTAGE (V)
5.5
4.5
3447 G10
3447 G11
3447 G12
Feedback Reference vs Supply
Voltage
Feedback Voltage vs
Temperature
Load Step (200mA to 400mA)
610
605
600
595
590
618
612
606
600
594
588
582
V
OUT
50mV/DIV
LOAD CURRENT
200mA/DIV
–40 –20
0
20 40 60 80 100 120
2.5
3.5
SUPPLY VOLTAGE (V)
5.5
4.5
40µs/DIV
TEMPERATURE (°C)
3447 G13
3447 G15
3447 G15
Soft-Start with No Load
VOUT(MIN) to VOUT(MAX) Transition
VOUT(MAX) to VOUT(MIN) Transition
PULSE SKIP MODE
BURST MODE OPERATION
500mV/DIV
5V/DIV
500mV/DIV
V
OUT
V
OUT
500mV/DIV
500mV/DIV
V
OUT
PGOOD
INDUCTOR CURRENT
100mA/DIV
5V/DIV
200mA/DIV
5V/DIV
200mA/DIV
INDUCTOR CURRENT
PGOOD
PGOOD
INDUCTOR CURRENT
3447 G16
3447 G17
3447 G18
200µs/DIV
100µs/DIV
100µs/DIV
3447f
5
LTC3447
U
U
U
PI FU CTIO S
V
(Pin 1): Output Voltage Sensing Pin. An internal
SW (Pin 6): Switch Node Connector to Inductor. This pin
connects the drains of the internal main and synchronous
power MOSFET switches.
OUT
resistor divider provides the divided down feedback refer-
ence for comparison.
GND (Pin 2): Ground for all Circuits Excluding the Internal
RUN (Pin 7): Run Control Input. Forcing pin above 1.5V
enables the part. Forcing the pin below 0.3V shuts down
the device. In shutdown, all functions are disabled draw-
ing <1µA of supply current. Do not leave the RUN pin
floating.
Synchronous Power NFET.
FB (Pin 3): Feedback Sensing Pin for the Optional External
Feedback Resistors. Must be tied to V if there are no
IN
external feedback resistors.
2
SCL (Pin 8): I C Clock Input.
PGOOD (Pin 4): Fault Report. Open drain driver sinks cur-
2
rent when V
is 10% out of tolerance. Blanking during
V
CCD
(Pin 9): I C Power Rail.
OUT
2
DAC changes can be enabled via the I C.
2
SDA (Pin 10): I C Data Input.
V (Pin 5): Main Supply Pin. Must be closely decoupled
IN
Exposed Pad (Pin 11): Ground. Must be connected to
PCB ground for electrical contact and optimized thermal
performance.
to GND with a 2.2µF or greater capacitor.
W
BLOCK DIAGRA
V
IN
C
IN
RUN
V
OUT
6-BIT DAC
SW
V
SW
CCD
SLEW
SOFT-START
V
DAC
+
–
BUCK
C
OUT
REGULATOR
V
REF
SDA
2
DAC
I C
1.3R
MUX
BURST
BLANK
V
FB
SCL
BURST
LOAD
R
REF
UV REF
OV REF
R1
POWER
GOOD
PGOOD
MUX
FB
R2
S
DAC
LTC3447
3447 BD
Figure 2. LTC3447 High Level Block Diagram
3447f
6
LTC3447
U
OPERATIO
50mA.Whenbelowthislevel,thepowerMOSFETsandany
unneeded circuitry are turned off, reducing the quiescent
current to 33µA, and the peak current level reference level
is held at 150mA. The LTC3447 remains in this sleep state
until the output voltage falls below the output voltage set-
ting. Once this occurs, the regulator wakes up and allows
the inductor to develop 150mA current pulses. For light
loads,thiswillcausetheoutputvoltagetoincreaseandthe
internalpeakcurrentreferencetodecrease.Whenthepeak
current reference falls to below 50mA, the part re-enters
sleepmodeandthecycleisrepeated.Thisprocessrepeats
at a rate that is dependent on the load demand.
BUCK OPERATION
V
IN
V
FB
PEAK CURRENT LEVEL REF
EA
V
REF
I
RS
RS
COMP
LATCH
S
Q
OSC
PFET
NFET
R
QB
SW
LOGIC
BURST
Pulse Skipping Mode Operation
I
RCMP
At light loads, the inductor current may reach zero or
reverse on each pulse. The bottom MOSFET is turned off
BUCK REGULATOR
3447 AI01
Figure 3. LTC3447 Buck Regulator Diagram
by the current reversal comparator, I
, and the switch
RCMP
voltage will ring. This is discontinuous mode operation,
and is normal behavior for a switching regulator. At very
light loads, the LTC3447 will automatically skip pulses
in pulse skipping mode operation to maintain output
regulation. This feature is enabled when the Burst Mode
operation is disabled.
Main Control Loop
The LTC3447 uses current mode step-down architecture
withboththemain(P-channelMOSFET)andsynchronous
(N-channel MOSFET) switches internal. During normal
operation, the internal top power MOSFET is turned on
each cycle when the oscillator sets the RS latch, and
turned off when the current comparator, I
the RS latch. The peak inductor current at which I
resets the RS latch, is controlled by the output of error
amplifier EA. When the load current increases, it causes
a slight decrease in the feedback voltage, FB, relative to
an internal reference voltage, which in turn, causes the
EA amplifier’s output voltage to increase until the average
inductor current matches the new load current. While the
top MOSFET is off, the bottom MOSFET is turned on until
either the inductor current starts to reverse, as indicated
Short-Circuit Protection
, resets
COMP
When the output is shorted to ground, the frequency of
the oscillator is reduced to about 160kHz. This frequency
foldback ensures that the inductor current has more
time to decay, thereby preventing thermal runaway. The
oscillator’s frequency will progressively increase to 1MHz
COMP
when V
rises above 0V.
OUT
Dropout Operation
When using the optional external feedback resistors, it is
bythecurrentreversalcomparatorI
of the next clock cycle.
,orthebeginning
RCMP
possible for V to approach the output voltage level. As
IN
the input supply voltage decreases to a value approaching
the output voltage, the duty cycle increases toward the
maximumon-time.Furtherreductionofthesupplyvoltage
forcesthemainswitchtoremainonformorethanonecycle
until it reaches 100% duty cycle. The output voltage will
then be determined by the input voltage minus the voltage
drop across the P-channel MOSFET and the inductor.
Burst Mode Operation
The LTC3447 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
onloaddemand. BurstModeoperationcanbedisabledvia
2
the I C interface. When Burst Mode operation is disabled,
the regulator is in pulse skipping mode operation.
Animportantdetailtorememberisthatatlowinputsupply
During Burst Mode operation, the LTC3447’s internal
circuits sense when the inductor peak current falls below
voltages, the R
of the P-channel switch increases
DS(ON)
(see Typical Performance Characteristics). Therefore,
3447f
7
LTC3447
U
OPERATIO
for duty cycles >40%; however, the LTC3447 uses a
patent-pendingschemethatcounteractsthiscompensat-
ingramp,whichallowsthemaximuminductorpeakcurrent
to remain unaffected throughout all duty cycles.
the user should calculate the power dissipation when
the LTC3447 is used at 100% duty cycle with low input
voltage (See Thermal Considerations in the Applications
Information section).
DAC
Low Supply Operation
2
The I C interface is used to control the internal voltage
The LTC3447 will operate with input supply voltages as
low as 2.5V, but the maximum allowable output current
is reduced at this low voltage. Figure 4 shows the reduc-
tion in the maximum output current as a function of input
voltage for various output voltages.
DAC for the buck regulator. The output voltage range is
0.69V to 2.05V in 21.6mV steps. The default DAC setting
is100000whichequatestoa1.38Voutputvoltage.Output
voltage transitions begin once the I C interface receives
the STOP command.
2
Slope Compensation and Inductor Peak Current
Slew Rate
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscil-
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
The LTC3447 has a slew rate of approximately 11mV/µs.
The slew rate is controlled by the RC time constant of a
low pass filter at the voltage DAC output. Figure 5 shows
a typical transition from min to max DAC settings.
1200
T
= 25°C
A
BURST MODE OPERATION
IN
V
= 3.6V
DAC = MIN
DAC = MAX
V
1100
1000
900
OUT
500mV/DIV
INDUCTOR CURRENT
200mA/DIV
5V/DIV
800
PGOOD
700
2.5
3.5
4.0
4.5
5.0
5.5
3.0
100µs/DIV
SUPPLY VOLTAGE (V)
3447 F04
Figure 4. Maximum Load Current vs Supply Voltage
Figure 5.Transition from DAC = MIN to DAC = MAX
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
START
COMMAND
ST0P
COMMAND
3447 TD02
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
Figure 6. Typical I2C Write Protocol
3447f
8
LTC3447
U
OPERATIO
External Start-Up Option
out an address on the bus and wait to see if another device
responds to it. After a response is detected, meaningful
data can be exchanged between the parts.
TheLTC3447allowsfortheuseofoptionalexternalresistors
to determine the start-up voltage. Using this option, the
start-up voltage can be set to levels inside or outside the
DAC output’s operating range. The output voltage will be
regulatedatthisvalueuntiltheinternalDACisupdatedand
aSTOPcommandisreceived. OncetheSTOPcommandis
received, the internal DAC will retain control of the output
voltage until the part is disabled then enabled again.
Typically,onedevicewillcontroltheclocklineatleastmost
of the time and will normally be sending data to the other
parts and polling them to send data back to it, and this
device is called the master. There can certainly be more
than one master, since there is an effective protocol to
resolve bus contentions, and nonmaster (slave) devices
can also control the clock to delay rising edges and give
themselves more time to complete calculations or com-
munications (clock stretching). Slave devices need to be
able to control the data line to acknowledge communica-
tions from the master, and some devices will need to able
to send data back to the master; they will be in control of
the data line while they are doing so. Many slave devices
will have no need to stretch the clock signal and will have
no ability to pull the clock line low, which is the case with
the LTC3447.
If this feature is not used, the feedback pin must be tied
to V .
IN
2
I C OPERATION
2
Typical 2-wire serial I C
Serial interface
Simple 2-wire interface
Multiple devices on same bus
Idle bus must have SDA and SCL lines high
LTC3447 is write only
Master controls bus
Devices listen for unique address that precedes data
Data is exchanged in the form of bytes, which are 8-bit
packets. Every byte needs to be acknowledged by the
slave (data line pulled low) or not acknowledged by the
master (data line left high), so communications are bro-
ken up into 9-bit segments, one byte followed by one bit
for acknowledging. For example, sending out an address
consists of 7-bits of device address, 1-bit that signals
whether a read or write operation will be performed, and
then 1 more bit to allow the slave to acknowledge. There
is no theoretical limit to how many total bytes can be
exchanged in a given transmission.
2
General I C Bus/SMBus Description
2
I C Bus and SMBus are reasonably similar examples of
two wire, bidirectional, serial communications busses.
Calling them two wire is not strictly accurate, as there
is an implied third wire, which is the ground line. Large
ground drops or spikes between the grounds of different
parts on the bus can interrupt or disrupt communica-
tions, as the signals on the two wires are both inherently
referenced to a ground which is expected to be common
to all parts on the bus. Both bus types have one data line
and one clock line which are externally pulled to a high
voltage when they are not being controlled by a device on
the bus. The devices on the bus can only pull the data and
clock lines low, which makes it simple to detect if more
than one device is trying to control the bus; eventually, a
device will release a line and it will not pull high because
another device is still holding it low. Pull-ups for the data
and clock lines are usually provided by external discrete
resistors, but external current sources can also be used.
Since there are no dedicated lines to use to tell a given
device if another device is trying to communicate with it,
each device must have a unique address to which it will
respond. The first part of any communication is to send
2
I CandSMBusareverysimilarspecifications,SMBushav-
2
ing been derived from I C. In general, SMBus is targeted
toward low power devices (particularly battery powered
2
ones) and emphasizes low power consumption, while I C
is targeted toward higher speed systems where the power
2
consumption of the bus is not so critical. I C has three dif-
ferent specifications for three different maximum speeds,
these being standard mode (100kHz max), fast mode
(400kHzmax), andHSmode(3.4MHzmax). Standardand
fast mode are not radically different, but HS mode is very
different from a hardware and software perspective and
requires an initiating command at standard or fast speed
before data can start transferring at HS speed. SMBus
simply specifies a 100kHz maximum speed.
3447f
9
LTC3447
U
OPERATIO
be left HIGH by the slave. The master can then generate
a STOP command to abort the transfer.
The START and STOP Commands
When the bus is not in use, both SCL and SDA must be
high.Abusmastersignalsthebeginningofatransmission
with a START command by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP command
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Ifaslavereceiverdoesacknowledgetheslaveaddressbut,
some time later in the transfer cannot receive any more
data bytes, the master must again abort the transfer. This
is indicated by the slave generating the not acknowledge
on the first byte to follow. The slave leaves the data line
HIGH and the master generates the STOP command. The
data line is also left high by the slave and master after a
slave has transmitted a byte of data to the master in a read
operation, but this is a not acknowledge that indicates that
the data transfer is successful.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge signal (LOW
active) is generated by the slave lets the master know that
the latest byte of information was received. The acknowl-
edge-related clock pulse is generated by the master. The
transmitter master releases the SDA line (HIGH) during
the acknowledge clock pulse. The slave receiver must pull
down the SDA line during the acknowledge clock pulse
so that it remains stable LOW during the HIGH period of
this clock pulse.
Commands Supported
The LTC3447 supports only write byte commands to a
single register. During ACK bit periods, the LTC3447 will
pull the data line low to acknowledge the master device.
See Figure 7.
Data Transfer Timing for Write Commands
In order to help assure that bad data is not written into
the part, data from a write command is only stored after
a valid STOP command has been performed.
When a slave receiver doesn’t acknowledge the slave
address (for example, it’s unable to receive because it’s
performing some real-time function), the data line must
WRITE BYTE PROTOCOL
1
7
1
1
8
1
1
1100110
0
ACK
XXXXXXXX
DATA
ACK
STOP
START
SLAVE
ADDRESS
WRITE
2
I C REGISTER DEFINITION
MSB
7
6
5
4
3
2
1
0
LSB
DISABLE
BURST
ENABLE
PGOOD
BUCK
DAC5
BUCK
DAC4
BUCK
DAC3
BUCK
DAC2
BUCK
DAC1
BUCK
DAC0
(DEFAULT = 0) BLANKING (DEFAULT = 1) (DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0)(DEFAULT = 0) (DEFAULT = 0)
(DEFAULT = 0)
3447 F07
Figure 7. LTC3447’s Write I2C Protocol
3447f
10
LTC3447
U
OPERATIO
Table 1. I2C Fast-Mode Timing Specifications (for Reference)
2
f
t
t
t
t
t
t
t
t
t
t
t
I C Operating Frequency
0
400
0.9
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
I2C
Bus free time between Stop and Start Condition
Hold Time after (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
1.3
BUF
0.6
HD,RSTA
SU,RSTA
SU,STOP
HD,DAT
SU,DAT
LOW
0.6
0.6
0
Data Setup Time
100
1.3
Clock Low Period
Clock High Period
0.6
HIGH
SP
Pulse Width of Spikes Suppressed by Input Filter
Clock, Data Fall Time
0
50
20 + 0.1 • C
20 + 0.1 • C
300
300
f
B
B
Clock, Data Rise Time
r
C
= Capacitance of one bus line.
B
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APPLICATIO S I FOR ATIO
The basic LTC3447 application circuit is shown on the
front page of the data sheet. External component selec-
tion is driven by the load requirement and begins with the
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
selection of L1 followed by C and C
.
OUT
IN
Inductor Selection
Inductor Core Selection
For most applications, the value of the inductor will fall
in the range of 1µH to 4.7µH. Its value is chosen based
on the desired ripple current. Large value inductors
lower ripple current and small value inductors result in
Differentcorematerialsandshapeswillchangethesize/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or perm alloy materials are
small and don’t radiate much energy, but generally cost
more than powdered-iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price versus size
requirements and any radiated field/EMI requirements
than on what the LTC3447 requires to operate. Table 2
shows some typical surface mount inductors that work
well in LTC3447 applications.
higher ripple currents. Higher V or V
also increases
IN
OUT
the ripple current as shown in Equation 1. A reasonable
starting point for setting ripple current is ΔI = 240mA
L
(40% of 600mA).
⎛
⎞
1
(f)(L)
VOUT
V
IN(MAX)
∆IL =
VOUT 1–
⎜
⎟
⎝
⎠
(1)
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 920mA rated
inductor should be enough for most applications (800mA
+ 120mA). For better efficiency, choose a low DC resis-
tance inductor.
Table 2.
Manufacturer
Part Number
Value
DCR
Max DC
Size
3
(µH) (mΩ max) Current (A) W x L x H (mm )
Sumida
CDRH3D16/HP3R3
3.3
4.7
2.2
2.2
85
109
29
1.4
1.15
3.2
4.0 x 4.0 x 1.8
4.0 x 4.5 x 3.5
5.0 x 5.0 x 4.7
5.0 x 5.0 x 2.0
Sumida
CR434R7
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
Murata
LQH55DN2R2MO3
Toko
59
1.63
D52LC-A914BYW-2R2M
50mA. Lower inductor values (higher ΔI ) will cause this
L
3447f
11
LTC3447
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APPLICATIO S I FOR ATIO
C and C
Selection
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them
ideal for switching regulator applications. Because the
LTC3447’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
IN
OUT
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle V /V . To prevent large
voltage transients, a low ESR input capacitor sized for
the maximum RMS current must be used. The maximum
RMS capacitor current is given by:
OUT IN
1/2
V
OUT (V – VOUT )
[
]
IN
CIN required IRMS ≅ IOMAX
However, care must be taken when ceramic capacitors
are used at the input and the output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
V
IN
(2)
This formula has a maximum at V = 2V , where
IN
OUT
I
= I /2. This simple worst-case condition is com-
RMS
OUT
output can induce ringing at the input, V . At best, this
IN
monly used for design because even significant devia-
tions do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based
on 2000 hours of life. This makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question.
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at V ,
IN
large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically, once the ESR require-
ment for C
has been met, the RMS current rating
OUT
Output Voltage Programming
generally far exceeds the I
requirement. The
RIPPLE(P-P)
output ripple ΔV
is determined by:
The LTC3447 has an internal resistor divider network tied
to the OUT pin. The output voltage is controlled by a DAC
OUT
⎛
⎝
1
⎞
2
∆VOUT ≅ ∆I ESR +
(6-bit register) whose setting is programmed via the I C
⎜
⎟
⎠
L
8fCOUT
(3)
interface. The DAC controls the V
range of 0.69V to
OUT
2.05Vin21.6mVsteps. ThedefaultvalueforV
is1.38V
OUT
and is reset to this value whenever V comes up.
IN
where f = operating frequency, C
= output capacitance
OUT
and ΔI = ripple current in the inductor. For a fixed output
L
Efficiency Considerations
voltage, the output ripple is highest at maximum input
voltage since ΔI increases with input voltage.
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
L
Aluminumelectrolyticanddrytantalumcapacitorsareboth
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
foruseinswitchingpowersupplies. Anexcellentchoiceis
the AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague593Dand595Dseries. Consultthemanufacturer
for other specific recommendations.
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3447 circuits: V quiescent current and
IN
2
Using Ceramic Input and Output Capacitors
I R losses. The V quiescent current loss dominates the
IN
2
efficiency loss at very low load currents whereas the I R
Higher values, lower cost ceramic capacitors are now
3447f
12
LTC3447
U
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APPLICATIO S I FOR ATIO
loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
R and multiply the result by the square of the average
L
output current.
OtherlossesincludingC andC ESRdissipativelosses
and inductor core losses generally account for less than
2% total additional loss.
IN
OUT
in Figure 8.
1
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
0.1
a load step occurs, V
immediately shifts by an amount
OUT
0.01
equal to (ΔI
• ESR), where ESR is the effective series
OUT
LOAD
resistance of C . ΔI
also begins to charge or dis-
LOAD
DAC = MAX
DAC = MIN
charge C , which generates a feedback error signal.
OUT
0.001
0.1
1
10
100
1000
The regulator loop then acts to return V
to its steady
OUT
can be moni-
OUT
LOAD CURRENT (mA)
state value. During this recovery time V
3447 F08
toredforovershootorringingthatwouldindicateastability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
Figure 8. Power Loss vs Load Current
The V quiescent current is due to two components: the
IN
DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately (25
from V to ground. The resulting dQ/dt is the current out
IN
of V that is typically larger than the DC bias current. In
IN
continuous mode, I
= f(QT + QB) where QT and
GATECHG
• C ). Thus, a 10µF capacitor charging to 3.3V would
LOAD
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
require a 250µs rise time, limiting the charging current
to about 130mA.
proportional to V and thus their effects will be more
IN
pronounced at higher supply voltages.
Thermal Considerations
2
I Rlossesarecalculatedfromtheresistancesoftheinternal
InmostapplicationstheLTC3447doesnotdissipatemuch
heatduetoitshighefficiency.But,inapplicationswherethe
LTC3447 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperatureofthepart.Ifthejunctiontemperaturereaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
switches, R , and external inductor R . In continuous
SW
L
mode,theaverageoutputcurrentflowingthroughinductor
L is “chopped” between the main switch and the synchro-
nous switch. Thus, the series resistance looking into the
SW pin is a function of both top and bottom MOSFET
R
DS(ON)
and the duty cycle (DC) as follows:
R
= (R )(DC) + (R
DS(ON)TOP
)(1 – DC)
DS(ON)BOT
SW
To avoid the LTC3447 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
The R
for both the top and bottom MOSFETs can
DS(ON)
be obtained from the Typical Performance Characteristics
2
curves. Thus, to obtain I R losses, simply add R to
SW
whether the power dissipated exceeds the maximum
3447f
13
LTC3447
U
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APPLICATIO S I FOR ATIO
junction temperature of the part. The temperature rise
is given by:
possible? This capacitor provides the AC current to the
internal power MOSFETs.
T = θ • P
D
5. Keep the switching node, SW, away from the sensitive
OUT
R
JA
V
and FB nodes.
where P is the power dissipated by the regulator and
D
θ
is the thermal resistance from the junction of the die
6. Keep the (–) plates of C and C
as close as pos-
JA
IN
OUT
to the temperature.
sible.
The junction temperature, T , is given by:
J
T = T + T
R
J
A
R2
GND PLANE
where T is the ambient temperature.
A
Asanexample,considertheLTC3447whenusinganinput
voltage of 3.6V, an ambient temperature of 70°C, and a
buckloadcurrentof500mA.Fromthetypicalperformance
R1
C2
graph of switch resistance, the R
of the P-channel
DS(ON)
V
SDA
OUT
switch at 70°C is approximately 0.45Ω. Therefore, power
dissipated by the part is:
V
CCD
GND
FB
2
P = I
D
• R
= 112.5mW
LOAD
DS(ON)
SCL
For the DFN-10 package, the θ is 43°C/W. Thus, the
JA
junction temperature of the regulator is:
PGOOD
RUN
SW
T = 70°C + (0.1125)(43) = 74.8°C
J
V
IN
which is well below the maximum junction temperature of
150°C. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
V
IN
C
L1
IN
(R
).
DS(ON)
C
OUT
GND PLANE
VIA
TO
PC Board Layout Checklist
V
OUT
3447 F09
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3447. These items are also illustrated graphically
in Figures 9 and 10. Check the following in your layout:
Figure 9. LTC3447 Suggested Layout
V
SDA
OUT
1. The power traces, consisting of the GND trace, the
R1
R2
SW trace, and the V trace should be kept short, direct
IN
V
GND
FB
CCD
SCL
C2
and wide.
2. Does the V
pin connect directly to the output voltage
OUT
reference? Ensure that there is no load current running
from the output voltage and the V sense pin.
PGOOD
RUN
OUT
3. DoestheFBpinconnectdirectlytothefeedbackvoltage
reference? Ensure that there is no load current running
from the feedback reference voltage and the FB pin.
V
SW
OUT
IN
L1
C
C
IN
V
V
IN
OUT
3447 F11
4. Does the (+) plate of C connect to V as closely as
IN
IN
Figure 10. LTC3447 Layout Diagram
3447f
14
LTC3447
U
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APPLICATIO S I FOR ATIO
Design Example
⎛
⎝
⎞
⎟
1
∆VOUT = 0.280A 0.25Ω +
=
⎜
As a design example, assume the LTC3447 is used in a
singlelithium-ionbattery-poweredcellularphoneapplica-
8(1MHz)(4.7µF)⎠
70mV + 7.4mV = 77.4mV
tion. The V will be operating from a maximum of 4.2V
IN
Note that the majority of the ripple voltage is generated
by the capacitor’s ESR. Most ceramic capacitors will have
a typical ESR of 10mΩ or less. Selecting capacitors with
low ESRs will significantly reduce the ripple voltage.
down to about 2.7V. The normal load current requirement
isamaximumof500mAat1.4V, butmostofthetimeitwill
beinstandbymode,requiringonly200µAat1V.Efficiency
at both low and high load currents is important.
Efficiency can be improved by taking advantage of the
LT3447’sBurstModeoperation.Whenenteringthestandby
mode, ensure that the burst disable bit is set to 0 when
the output voltage DAC is updated. Likewise, when enter-
ing a heavy current load mode, ensure the burst disable
bit is set to 1 when the output voltage DAC is updated.
Figure 11 shows the advantage of utilizing the Burst Mode
To ensure that the ripple currents and voltages do not
exceed desired expectations over the DAC output range,
calculationswithmaximumV andminimumV should
IN
OUT
be used. Note that either increasing the output voltage or
decreasing V will result in a decrease of ripple current
IN
and voltage. Choosing a maximum ripple current, ΔI , of
L
280mA, Equation 1 can be used to determine the size of
the inductor that should be used.
function.
100
DAC(MAX)
STBY
DAC(MAX)
1
1.4V
4.2V
⎛
⎝
⎞
⎟
⎠
90
80
70
60
50
40
30
20
10
0
L =
•1.4V 1–
= 3.3µH
⎜
(1MHz)(280mA)
NORMAL
DAC(MIN)
A 3.3µH inductor works well for this application. For best
efficiency choose a 640mA or greater inductor with less
than 0.2Ω series resistance.
BURST
PSK
C will require an RMS current of at least 0.25A, approxi-
IN
DAC(MIN)
1
matelyI
/2,overtemperature(seeEquation2).For
0.1
10
100
1000
LOAD(MAX)
LOAD CURRENT (mA)
C
, selecting a 4.7µF capacitor with an ESR of 0.25Ω
OUT
3447 F11
yields the following ripple voltage using Equation 3.
Figure 11. Efficiency vs Load Current ( VIN = 4.2V)
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
6
0.38 0.10
10
0.675 0.05
3.50 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD10) DFN 1103
5
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
0.25 0.05
0.50
BSC
2.38 0.10
(2 SIDES)
2.38 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD
FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 5. EXPOSED PAD SHALL BE SOLDER PLATED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3447f
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3447
U
TYPICAL APPLICATIO
Li-Ion Battery to 1.4V/1V Regulator
Li Ion
BATTERY
L1
3.3
V
IN
FB
H
C
1.4V AT 500mA IN NORMAL OPERATION
1V AT 200 A IN STBY MODE
IN
V
OUT
=
SW
OUT
4.7
F
20k
LTC3447
C
PGOOD
RUN
V
OUT
4.7
F
2
PWREN
I C BUS
V
CCD
V
CCD
4.7
F
10k 10k
C
, C : TDK C1608X5R0J475MT
IN OUT
L1: SUMIDA CDRH3D16-3R3
SDA
SCL
SDA
SCL
GND
EXPOSED PADDLE
TO GROUND
3447 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 1.8V to 20V, V
LT1761
100mA, Low Noise Micropower, LDO
= 1.22V, Dropout Voltage = 0.30V,
I = 20µA, I < 1µA, V = Adj, 1.5V, 1.8V, 2V, 2.5V, 2.8V, 3V,
OUT
IN
OUT(MIN)
Q
SD
3.3V, 5V, ThinSOTTM Package. Low Noise < 20µV
with 1µF Ceramic Capacitors
, Stable
RMS(P-P)
LT1762
LT1763
LTC1844
150mA, Low Noise Micropower, LDO
500mA, Low Noise Micropower, LDO
150mA, Very Low Dropout LDO
V : 1.8V to 20V, V
= 1.22V, Dropout Voltage = 0.30V,
I = 25µA, I < 1µA, V = Adj, 2.5V, 3V, 3.3V, 5V, MS8
OUT
IN
OUT(MIN)
Q
SD
Package. Low Noise < 20µV
RMS(P-P)
V : 1.8V to 20V, V
= 1.22V, Dropout Voltage = 0.30V,
I = 30µA, I < 1µA, V = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, S8
OUT
IN
OUT(MIN)
Q
SD
Package. Low Noise < 20µV
RMS(P-P)
V : 6.5V to 1.6V, V
= 1.25V, Dropout Voltage = 0.08V,
I = 40µA, I < 1µA, V = Adj, 1.5V, 1.8V, 2.5V, 2.8V, 3.3V,
OUT
IN
OUT(MIN)
Q
SD
ThinSOT Package. Low Noise < 30µV
Ceramic Capacitors
, Stable with 1µF
RMS(P-P)
LT1962
300mA, Low Noise Micropower, LDO
V : 1.8V to 20V, V
= 1.22V, Dropout Voltage = 0.27V,
I = 30µA, I < 1µA, V = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, MS8
OUT
IN
OUT(MIN)
Q
SD
Package. Low Noise < 20µV
RMS(P-P)
LT3020
Low V (0.9V) Low V
(0.2V) VLDOTM
V : 0.9V to 10V, V
= 0.20V, Dropout Voltage = 0.15V,
OUT(MIN)
IN
OUT
IN
I = 120µA, I < 1µA, V
= Adj, DFN Package
Q
SD
OUT
LTC3405/LTC3405A
LTC3406/LTC3406B
LTC3407
300mA (I ), 1.5MHz Synchronous Step-Down
V : 2.5V to 5.5V, V
= 0.8V, I = 20µA, I < 1µA, ThinSOT
OUT
IN
OUT(MIN) Q SD
DC/DC Converter
Package
600mA (I ), 1.5MHz Synchronous Step-Down
V : 2.5V to 5.5V, V
= 0.6V, I = 20µA, I < 1µA, ThinSOT
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
DC/DC Converter
Package
Dual 600mA, 1.5MHz Synchronous Step-Down
DC/DC Converter
V : 2.5V to 5.5V, V
= 0.6V, I = 40µA, I < 1µA, MS10E,
Q SD
IN
QFN Packages
LTC3411
1.25A (I ), 4MHz Synchronous Step-Down
V : 2.5V to 5.5V, V
= 0.8V, I = 60µA, I < 1µA, MS10
Q SD
OUT
IN
DC/DC Converter
Package
LTC3412
2.5A (I ), 4MHz Synchronous Step-Down
V : 2.5V to 5.5V, V
IN
= 0.8V, I = 60µA, I < 1µA,
Q SD
OUT
DC/DC Converter,
TSSOP16E Package
LTC3445
600mA, 1.5MHz Synchronous Step-Down DC/DC Converter V : 2.5V to 5.5V, V
= 0.85V to 1.55V, I = 27µA, I < 1µA,
IN
OUT Q SD
with Two LDOs and PowerPathTM Manager
Two LDOs I C Interface, Back-Up Battery Management, QFN24
2
LTC3455
Dual DC/DC Converter with USB Power Manager and
Li-Ion Battery Charger
V : 3V to 5.5V, Seamless Transition Between Input Sources and
IN
Li-Ion Battery, USB, 5V Wall Adapter, QFN24 Package
LTC4055
USB Power Manager and Li-Ion Battery Charger
Standalone Charger, Automatic Switchover when Input Supply
is Removed
LTC4411/LTC4412
PowerPath Controllers in ThinSOT
More Efficient than Diode ORing
ThinSOT, VLDO and PowerPath are trademarks of Linear Technology Corporation.
3447f
LT/TP 0505 500 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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