LTC3300-2_技术文档

LTC3300-2

Addressable High Efficiency

Bidirectional Multicell

Battery Balancer

FEATURES

DESCRIPTION

The LTC^®3300-2 is a fault-protected controller IC for

transformer-based bidirectional active balancing of multi-

cell battery stacks. All associated gate drive circuitry,

precision current sensing, fault detection circuitry and a

robust serial interface with built-in watchdog timer are

integrated.

n

Bidirectional Synchronous Flyback Balancing

of Up to 6 Li-Ion or LiFePO Cells in Series

4

n

Up to 10A Balancing Current (Set by Externals)

n

Integrates Seamlessly with the LTC680x Family of

Multicell Battery Stack Monitors

n

Bidirectional Architecture Minimizes Balancing

Time and Power Dissipation

Up to 92% Charge Transfer Efficiency

Each LTC3300-2 can balance up to 6 series-connected

battery cells with an input common mode voltage up to

36V. Charge from any selected cell can be transferred at

high efficiency to or from 12 or more adjacent cells. Each

LTC3300-2hasanindividuallyaddressableserialinterface,

allowing up to 32 LTC3300-2 devices to interface to one

control processor.

n

Stackable Architecture Enables >800V Systems

n

Uses Simple 2-Winding Transformers

n

1MHz Serial Interface with 4-Bit

CRC Packet Error Checking

n

Individually Addressable with 5-Bit Address

n

Numerous Fault Protection Features

n

Fault protection features include readback capability, cy-

clic redundancy check (CRC) error detection, maximum

on-time volt-second clamps, and overvoltage shutoffs.

48-Lead Exposed Pad QFN and LQFP Packages

APPLICATIONS

n

Electric Vehicles/Plug-in HEVs

The related LTC3300-1 offers a serial interface that allows

theserialportsofmultipleLTC3300-1devicestobedaisy-

chained without opto-couplers or isolators.

n

High Power UPS/Grid Energy Storage Systems

n

General Purpose Multicell Battery Stacks

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and isoSPI

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

TYPICAL APPLICATION

High Efficiency Bidirectional Balancing

NEXT CELL ABOVE

CHARGE

Balancer Efficiency

+

SUPPLY

CHARGE

RETURN

DISCHARGE

CELL 12

LTC3300-2

100

(I

1-6)

CHARGE

4

5

DC2064A DEMO BOARD

(I

1-6)

ISOLATOR

I

V

= I

= 2.5A

CHARGE DISCHARGE

= 3.6V

CELL

+

ADDRESS n + 1

CELL 7

CELL 6

95

90

85

80

•

CHARGE

DISCHARGE

CHARGE

RETURN

I

DISCHARGE

4

•

4

SERIAL I/O

LTC3300-2

•

6

8

10

12

+

CHARGE

SUPPLY

I

4

CHARGE

CELL 1

NUMBER OF CELLS (SECONDARY SIDE)

33001 TA01b

•

4

5

ISOLATOR

ADDRESS n

33002 TA01a

NEXT CELL BELOW

33002f

1

For more information www.linear.com/LTC3300-2

LTC3300-2

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

–

Total Supply Voltage (C6 to V ).................................36V

Voltage Between Pins

–

Input Voltage (Relative to V )

Cn to Cn-1* .............................................. –0.3V to 6V

InP to Cn-1* .......................................... –0.3V to 0.3V

C1 ........................................................... –0.3V to 6V

I1P ....................................................... –0.3V to 0.3V

I1S, I2S, I3S, I4S, I5S, I6S.................... –0.3V to 0.3V

CSBI, SCKI, SDI ....................................... –0.3V to 6V

+

BOOST to C6 .......................................... –0.3V to 6V

SDO Current...........................................................10mA

–

G1P, GnP, G1S, GnS, BOOST Current............... ± 200mA

V

, SDO ............................................... –0.3V to 6V

Operating Junction Temperature Range (Notes 2, 7)

LTC3300I-2........................................ –40°C to 125°C

LTC3300H-2 ...................................... –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

*n = 2 to 6

REG

RTONP, RTONS...........–0.3V to Min[V

CTRL, BOOST, WDT....–0.3V to Min[V

A4, A3, A2, A1, A0.......–0.3V to Min[V

+ 0.3V, 6V]

REG

PIN CONFIGURATION

TOP VIEW

G6S

I6S

G5S

I5S

G4S

I4S

G3S

I3S

1

2

3

4

5

6

7

8

9

36 C5

G6S

I6S

G5S

I5S

G4S

I4S

G3S

I3S

G2S

I2S 10

G1S 11

I1S 12

1

2

3

4

5

6

7

8

9

36 C5

35 G5P

34 I5P

33 C4

32 G4P

31 I4P

30 C3

29 G3P

28 I3P

27 C2

26 G2P

25 I2P

35 G5P

34 I5P

33 C4

32 G4P

31 I4P

30 C3

29 G3P

28 I3P

27 C2

49

–

V

G2S

I2S 10

G1S 11

I1S 12

26 G2P

25 I2P

UK PACKAGE

LXE PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

48-LEAD (7mm × 7mm) PLASTIC LQFP

T

= 150°C, θ = 34°C/W, θ = 3°C/W

JA JC

JMAX

–

T

= 150°C, θ = 20.46°C/W, θ = 3.68°C/W

JMAX JA JC

EXPOSED PAD (PIN 49) IS V , MUST BE SOLDERED TO PCB

–

EXPOSED PAD (PIN 49) IS V , MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3300IUK-2#PBF

LTC3300HUK-2#PBF

LEAD FREE FINISH

LTC3300ILXE-2#PBF

LTC3300HLXE-2#PBF

TAPE AND REEL

PART MARKING*

LTC3300UK-2

PACKAGE DESCRIPTION

48-Lead (7mm × 7mm) Plastic QFN

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3300IUK-2#TRPBF

LTC3300HUK-2#TRPBF

TRAY

LTC3300UK-2

–40°C to 150°C

PART MARKING*

LTC3300LXE-2

TEMPERATURE RANGE

–40°C to 125°C

LTC3300ILXE-2#PBF

LTC3300HLXE-2#PBF

48-Lead (7mm × 7mm) Plastic eLQFP

–40°C to 150°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

33002f

2

For more information www.linear.com/LTC3300-2

LTC3300-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) BOOST⁺= 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,

C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V^–= 0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC Specifications

I

Supply Current When Not

Balancing (Post Suspend or Pre

First Execute)

Measured at C1, C2, C3, C4, C5

Measured at C6

0

14

0

1

µA

Q_SD

6

22

10

+

Measured at BOOST

–

I

Supply Current When Balancing

(Note 3)

Balancing C1 Only (Note 4 for V , C2, C6)

Measured at C1

Q_ACTIVE

250

70

560

0

375

105

840

10

µA

Measured at C2, C3, C4, C5

Measured at C6

+

Measured at BOOST

Balancing C2 Only (Note 4 for C1, C3, C6)

Measured at C1

–105

–70

250

70

560

0

µA

Measured at C2

375

105

840

10

Measured at C3, C4, C5

Measured at C6

+

Measured at BOOST

Balancing C3 Only (Note 4 for C2, C4, C6)

Measured at C1, C4, C5

Measured at C2

70

–70

250

560

0

105

µA

–105

Measured at C3

375

840

10

Measured at C6

Measured at BOOST

+

Balancing C4 Only (Note 4 for C3, C5, C6)

Measured at C1, C2, C5

Measured at C3

70

–70

250

560

0

105

µA

Measured at C4

375

840

10

Measured at C6

Measured at BOOST

+

Balancing C5 Only (Note 4 for C4, C6)

Measured at C1, C2, C3

Measured at C4

70

–70

250

560

0

105

µA

Measured at C5

375

840

10

Measured at C6

Measured at BOOST

+

Balancing C6 Only (Note 4 for C5, C6, BOOST )

Measured at C1, C2, C3, C4

Measured at C5

70

–70

740

60

105

µA

Measured at C6

1110

90

10

+

–

Measured at BOOST (BOOST = V )

Measured at BOOST (BOOST = V

)

0

REG

l

V

Minimum Cell Voltage (Rising)

Required for Primary Gate Drive

Cn to Cn – 1 Voltage to Balance Cn, n = 2 to 6

C1 Voltage to Balance C1

1.8

2

2.2

V

CELL|MIN

Cn + 1 to Cn Voltage to Balance Cn, n = 1 to 5

+

–

BOOST to C6 Voltage to Balance C6, BOOST = V

V

Comparator Hysteresis

CELL|MIN

70

5

mV

V

CELL|MIN(HYST)

l

Maximum Cell Voltage (Rising)

Before Disabling Balancing

C1, Cn to Cn – 1 Voltage to Balance Any Cell,

n = 2 to 6

4.7

5.3

CELL|MAX

V

Comparator Hysteresis

CELL|MAX

0.5

V

CELL|MAX(HYST)

l

Maximum Cell Voltage (Falling) to

Re-Enable Balancing

4.25

4.4

CELL|RECONNECT

V

Regulator Pin Voltage

9V ≤ C6 ≤ 36V, 0mA ≤ I

≤ 20mA

4.8

4.0

5.2

V

REG

LOAD

V

Voltage (Rising) for

REG

REG|POR

Power-On Reset

Minimum V Voltage (Falling)

l

V

V Voltage to Balance Cn, n = 1 to 6

REG

3.8

V

REG|MIN

REG

for Secondary Gate Drive

33002f

3

For more information www.linear.com/LTC3300-2

LTC3300-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) BOOST⁺= 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,

C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V^–= 0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

= 0V

MIN

TYP

MAX

UNITS

I

Regulator Pin Short Circuit Current

Limit

V

55

mA

REG_SC

REG

l

V

RTONP Servo Voltage

R

= 20kΩ

1.158

72

1.2

1.242

88

V

RTONP

RTONS Servo Voltage

= 15kΩ

RTONS

I

WDT Pin Current, Balancing

WDT Pin Current as a Percentage

= 15kΩ, WDT = 0.5V

= 15kΩ, WDT = 2V

80

µA

%

WDT_RISING

WDT_FALLING

TONS

85

87.5

90

of I

, Secondary OV

WDT_RISING

l

V

Primary Winding Peak Current

Sense Voltage

I1P

45

50

55

mV

PEAK_P

PEAK_S

ZERO_P

InP to Cn – 1, n = 2 to 6

l

V

Matching (All 6)

± [(Max – Min)/(Max + Min)] ꢀ 100%

± 1.7

± 5

%

PEAK_P

l

Secondary Winding Peak Current

Sense Voltage

I1S

45

50

55

mV

InS to Cn – 1, n = 2 to 6, CTRL = 0 Only

l

V

Matching (All 6)

± [(Max – Min)/(Max + Min)] ꢀ 100%

± 0.5

± 3

%

PEAK_S

l

Primary Winding Zero Current

Sense Voltage (Note 5)

I1P

–7

–2

3

mV

InP to Cn – 1, n = 2 to 6

l

V

Matching (All 6)

± ±[(Max – Min)/2]/(V

)} ꢀ 100%

PEAK_P|MIDRANGE

± 1.7

± 5

%

ZERO_P

Normalized to Mid-Range V

(Note 6)

PEAK_P

l

V

Secondary Winding Zero Current

Sense Voltage (Note 5)

I1S

–12

–7

–2

mV

ZERO_S

InS to Cn – 1, n = 2 to 6, CTRL = 0 Only

l

V

Matching (All 6)

± ±[(Max – Min)/2]/(V

)} ꢀ 100%

PEAK_S|MIDRANGE

± 0.5

± 3

%

ZERO_S

Normalized to Mid-Range V

(Note 6)

PEAK_S

–

R

BOOST Pin Pull-Down R

Measured at 100mA Into Pin, BOOST = V

REG

2.5

4

Ω

BOOST_L

BOOST_H

SD

ON

–

BOOST Pin Pull-Up R

Measured at 100mA Out of Pin, BOOST = V

Rising Temperature

ON

REG

T

Thermal Shutdown Threshold

(Note 7)

155

°C

Thermal Shutdown Hysteresis

10

°C

HYS

Timing Specifications

t

Primary Winding Gate Drive Rise

Time (10% to 90%)

G1P Through G6P, C

= 2500pF

35

20

70

40

ns

r_P

GATE

Primary Winding Gate Drive Fall

Time (90% to 10%)

f_P

GATE

Secondary Winding Gate Drive

Rise Time (10% to 90%)

G1S, C

= 2500pF

30

60

ns

r_S

GATE

G2S Through G6S, CTRL = 0 Only, C

= 2500pF

GATE

Secondary Winding Gate Drive Fall G1S, C

Time (90% to 10%)

= 2500pF

20

40

ns

f_S

GATE

G2S Through G6S, CTRL = 0 Only, C

l

Primary Winding Switch Maximum

On-Time

R

RTONP

= 20kΩ (Measured at G1P-G6P)

6

1

7.2

8.4

µs

ONP|MAX

l

t

Matching (All 6)

± [(Max – Min)/(Max + Min)] ꢀ 100%

= 15kΩ (Measured at G1S-G6S)

± 1

± 4

%

ONP|MAX

t

Secondary Winding Switch

Maximum On-Time

R

RTONS

1.2

1.4

µs

ONS|MAX

l

t

Matching (All 6)

± [(Max – Min)/(Max + Min)] ꢀ 100%

± 1

2

± 4

%

ONS|MAX

Delayed Start Time After New/

Different Balance Command or

Recovery from Voltage/Temp Fault

ms

DLY_START

SPI Port Timing Specifications

l

t

1

t

2

t

3

t

4

SDI Valid to SCKI Rising Setup

SDI Valid from SCKI Rising Hold

SCKI Low

Write Operation

10

ns

250

400

SCKI High

ns

33002f

4

For more information www.linear.com/LTC3300-2

LTC3300-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) BOOST⁺= 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,

C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V^–= 0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

400

100

TYP

MAX

UNITS

ns

l

t

f

t

CSBI Pulse Width

5

SCKI Rising to CSBI Rising

CSBI Falling to SCKI Rising

SCKI Falling to SDO Valid

Clock Frequency

ns

6

ns

7

Read Operation

250

1

ns

8

MHz

second

CLK

WD1

Watchdog Timer Timeout Period

WDT Assertion Measured from Last Valid

Command Byte

0.75

1.5

2.25

l

t

Watchdog Timer Reset Time

WDT Negation Measured from Last Valid

Command Byte

5

µs

WD2

Digital I/O Specifications

l

V

Digital Input Voltage High

Digital Input Voltage Low

Digital Input Current High

Digital Input Current Low

Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT

V

– 0.5

V

IH

REG

– 0.5

2

l

V

IL

Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT

0.5

0.8

V

I

Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT, Timed Out

–1

0

1

µA

IH

Pins CSBI, SCKI, SDI

Pins CTRL, BOOST

Pins A4, A3, A2, A1, A0

Pin WDT, Not Balancing

–1

0

1

µA

IL

l

V

Digital Output Voltage Low

Digital Output Current High

Pin SDO, Sinking 500µA; Read

Pin SDO at 6V

0.3

V

OL

I

OH

100

nA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

that are on. Second, for each additional balancer that is on, subtract 70µA

from the resultant sums for C1, C2, C3, C4, and C5, and 450µA from the

resultant sum for C6. For example, if all six balancers are on, the resultant

current for C1 is [250 – 70 + 70 + 70 + 70 + 70 – 5(70)]µA = 110µA and

for C6 is [560 + 560 + 560 + 560 + 560 + 740 – 5(450)]µA = 1290µA.

Note 2: The LTC3300-2 is tested under pulsed load conditions such

that T ≈ T . The LTC3300I-2 is guaranteed over the –40°C to 125°C

Note 4: Dynamic supply current is higher due to gate charge being

delivered at the switching frequency during active balancing. See Gate

Drivers/Gate Drive Comparators and Voltage Regulator in the Operation

section for more information on estimating these currents.

Note 5: The zero current sense voltages given in the table are DC

thresholds. The actual zero current sense voltage seen in application will

be closer to zero due to the slew rate of the winding current and the finite

delay of the current sense comparator.

Note 6: The mid-range value is the average of the minimum and maximum

readings within the group of six.

Note 7: This IC includes overtemperature protection intended to protect

the device during momentary overload conditions. The maximum junction

temperature may be exceeded when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may result in device degradation or failure.

J

A

operating junction temperature range and the LTC3300H-2 is guaranteed

over the –40°C to 150°C operating junction temperature. High junction

temperatures degrade operating lifetimes; operating lifetime is derated

for junction temperatures greater than 125°C. Note that the maximum

ambient temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal impedance and other environmental factors. The junction

temperature (T , in °C) is calculated from the ambient temperature

J

(T , in °C) and power dissipation (P , in Watts) according to the formula:

A

D

T = T + (P ꢀ θ )

JA

J

A

D

where θ (in °C/W) is the package thermal impedance.

JA

Note 3: When balancing more than one cell at a time, the individual cell

supply currents can be calculated from the values given in the table as

follows: First add the appropriate table entries cell by cell for the balancers

33002f

5

For more information www.linear.com/LTC3300-2

LTC3300-2

T_A= 25°C unless otherwise specified.

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Cell Voltage Required

for Primary Gate Drive vs

Temperature

C6 Supply Current When Not

Balancing vs Temperature

Supply Current When Balancing

vs Temperature Normalized to 25°C

20

18

16

14

12

10

2.10

2.05

2.00

1.95

1.90

1.85

1.80

1.06

1.04

1.02

1.00

0.98

0.96

0.94

C6 = 21.6V

3.6V PER CELL

MATCH CURVE WITH TABLE ENTRY

CELL VOLTAGE RISING

CELL VOLTAGE FALLING

TYP = 740µA

TYP = 560µA

TYP = 250µA

TYP = 70µA

TYP = 60µA

TYP = –70µA

75 100

50

TEMPERATURE (°C)

–50 –25

0

25 50

125 150

–50 –25

0

25

75 100 125 150

75 100

–50 –25

0

25 50

125 150

TEMPERATURE (°C)

33002 G01

33002 G03

33002 G02

Maximum Cell Voltage to Allow

Balancing vs Temperature

V_REGLoad Regulation

V_REGVoltage vs Temperature

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.70

4.69

4.68

4.67

4.66

4.65

4.64

4.63

4.62

4.61

4.60

5.0

4.9

4.8

I

= 10mA

T

A

= 25°C

VREG

CELL VOLTAGE RISING

C6 = 36V

C6 = 9V

4.7

4.6

4.5

CELL VOLTAGE FALLING

C6 = 36V

C6 = 9V

–50

50

100 125

0

5

10 15

30 35 40 45 50

–50

50

100 125

150

–25

0

25

75

150

20 25

–25

0

25

75

TEMPERATURE (°C)

I

(mA)

VREG

LT33002 G04

33002 G05

33002 G06

V_REGPOR Voltage and Minimum

Secondary Gate Drive vs

Temperature

V

_REGShort-Circuit Current Limit

vs Temperature

V_RTONP, V_RTONSvs Temperature

60

59

58

57

56

55

54

53

52

51

50

4.100

4.075

4.050

4.025

4.000

3.975

3.950

3.925

3.900

1.236

1.224

1.212

1.200

1.188

1.176

1.164

C6 = 21.6V

V

RISING (POR)

REG

V

RTONP

V

RTONS

V

FALLING

REG

(MIN SEC. GATE DRIVE)

75 100

50 75

TEMPERATURE (°C)

–50

125

150

–50 –25

0

25 50

125 150

–50 –25

0

25

100 125 150

–25

0

25 50 75 100

TEMPERATURE (°C)

33002 G07

33002 G08

33002 G09

33002f

6

For more information www.linear.com/LTC3300-2

LTC3300-2

T_A= 25°C unless otherwise specified.

TYPICAL PERFORMANCE CHARACTERISTICS

V_RTONP, V_RTONS

vs External Resistance

WDT Pin Current vs Temperature

WDT Pin Current vs R_TONS

1.236

1.224

1.212

1.200

1.188

1.176

1.164

85

80

75

70

240

200

160

120

80

T

= 25°C

R

= 15k

T

= 25°C

A

TONS

A

BALANCING

WDT = 0.5V

BALANCING

WDT = 0.5V

SECONDARY OV

WDT = 2V

V

RTONP

RTONS

40

SECONDARY OV

WDT = 2V

65

0

30 35

(kΩ)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

5

10 15 20 25

40 45

1

10

100

R

TONS

R

, R

RESISTANCE (kΩ)

TONP TONS

33002 G10

33002 G11

33002 G12

Peak Current Sense Threshold

vs Temperature

Zero Current Sense Threshold

vs Temperature

Primary Winding Switch Maximum

On-Time vs Temperature

5.0

2.5

8.4

8.0

7.6

7.2

6.8

6.4

6.0

55

53

51

V

= 3.6V

R

= 20k

= 3.6V

CELL

TONP

CELL

V

= 3.6V

CELL

RANDOM CELL SELECTED

V

RANDOM CELL SELECTED

PRIMARY

0

–2.5

–5.0

–7.5

–10.0

SECONDARY

49

47

45

75 100

125 150

–50 –25

0

25 50

125 150

–50 –25

0

25 50

50

–50 –25

0

25

75 100 125 150

TEMPERATURE (°C)

33002 G14

33002 G15

33002 G13

Secondary Winding Switch

Maximum On-Time vs Temperature

Maximum On-Time

vs R_TONP, R_TONS

Watchdog Timer Timeout Period

vs Temperature

20

18

16

14

12

10

8

1.4

1.3

1.2

1.1

1.65

1.60

1.55

1.50

1.45

1.40

1.35

T

= 25°C

R

TONS

= 15k

A

PRIMARY

6

4

SECONDARY

2

1.0

0

75 100

TEMPERATURE (°C)

5

40

–50 –25

0

25 50

125 150

33002 G18

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

10 15 20 25 30 35

, R (kΩ)

45

R

TONP TONS

33002 G16

33002 G17

33002f

7

For more information www.linear.com/LTC3300-2

LTC3300-2

T_A= 25°C unless otherwise specified.

TYPICAL PERFORMANCE CHARACTERISTICS

Balancer Efficiency

vs Cell Voltage

Balance Current vs Cell Voltage

2.7

2.6

2.5

2.4

93

92

91

90

DC2064A DEMO BOARD

= I = 2.5A

CHARGE, 12-CELL STACK

I

CHARGE DISCHARGE

FOR 12-CELL STACK ONLY

DISCHARGE, 12-CELL STACK

DISCHARGE, 6-CELL STACK

DC2064A DEMO BOARD

2.3

2.2

2.1

I

= I

= 2.5A

CHARGE DISCHARGE

DISCHARGE, 12-CELL STACK

FOR 12-CELL STACK ONLY

DISCHARGE, 6-CELL STACK

CHARGE, 6-CELL STACK

CHARGE, 12-CELL STACK

CHARGE, 6-CELL STACK

89

2.8 3.0

3.2 3.4 3.6 3.8 4.0 4.2

VOLTAGE PER CELL (V)

3.6

VOLTAGE PER CELL (V)

4.0

4.2

2.8 3.0

3.2 3.4

3.8

33002 G19

33002 G20

Typical Charge Waveforms

Typical Discharge Waveforms

I1S

50mV/DIV

I1P

50mV/DIV

I1P

50mV/DIV

I1S

50mV/DIV

PRIMARY

DRAIN

SECONDARY

DRAIN

50V/DIV

SECONDARY

PRIMARY

DRAIN

50V/DIV

DRAIN

50V/DIV

33002 G21

33002 G22

2µs/DIV

DC2064A DEMO BOARD

I

= 2.5A

I

= 2.5A

CHARGE

DISCHARGE

T = 2

S = 12

Protection for Broken Connection

to Secondary Stack While

Discharging

Protection for Broken Connection

to Cell While Charging

Changing Balancer Direction

“On the Fly”

SCKI

2ms

~5.2V

~66V

5V/DIV

C1 PIN

CHARGING

SECONDARY

STACK VOLTAGE

10V/DIV

1V/DIV 3.6V

I1P

50mV/DIV

DISCHARGING

CONNECTION TO

STACK BROKEN

CONNECTION TO

C1 BROKEN

43.2V

BALANCING

SHUTS OFF

G1P

2V/DIV

G1P

2V/DIV

G1P

2V/DIV

BALANCING

SHUTS OFF

33002 G24

33002 G25

33002 G23

500µs/DIV

20µs/DIV

50µs/DIV

33002f

8

For more information www.linear.com/LTC3300-2

LTC3300-2

PIN FUNCTIONS

Note: The convention adopted in this data sheet is to refer

tothetransformerwindingparallelinganindividualbattery

cellastheprimaryandthetransformerwindingparalleling

multiple series-stacked cells as the secondary, regardless

of the direction of energy transfer.

CSBI (Pin 16): Chip Select (Active Low) Input. The CSBI

pin interfaces to a rail-to-rail output logic gate. See Serial

Port in the Operation section.

SCKI (Pin 17): Serial Clock Input. The SCKI pin interfaces

to a rail-to-rail output logic gate. See Serial Port in the

Operation section.

G6S, G5S, G4S, G3S, G2S, G1S (Pins 1, 3, 5, 7, 9,

11): G1S through G6S are gate driver outputs for driving

external NMOS transistors connected in series with the

secondary windings of transformers whose primaries are

connected in parallel with battery cells 1 through 6. For

the minimum part count balancing application employing

SDI (Pin 18): Serial Data Input. When writing data to the

LTC3300-2, the SDI pin interfaces to a rail-to-rail output

logic gate. See Serial Port in the Operation section.

SDO (Pin 19): Serial Data Output. When reading data

from the LTC3300-2, the SDO pin is an NMOS open-drain

output. See Serial Port in the Operation section.

a single transformer (CTRL = V ), G2S through G6S

are no connects.

REG

WDT (Pin 20): Watchdog Timer Output (Active High). At

initialpower-upandwhennotattemptingtoexecuteavalid

balancecommand,theWDTpinishighimpedanceandwill

be pulled high (internally clamped to ~5.6V) if an external

pull-up resistor is present. While balancing (or attempt-

ing to balance but not able to due to voltage/temperature

faults)andduringnormalcommunicationactivity,theWDT

pin is pulled low by a precision current source slaved to

I6S, I5S, I4S, I3S, I2S, I1S (Pins 2, 4, 6, 8, 10, 12): I1S

through I6S are current sense inputs for measuring sec-

ondary winding current in transformers whose primaries

are connected in parallel with battery cells 1 through 6.

Fortheminimumpartcountbalancingapplicationemploy-

ing a single transformer (CTRL = V ), I2S through I6S

REG

–

should be tied to V .

RTONS (Pin 13): Secondary Winding Max t Setting

ON

the R

resistor. However, if no valid command byte is

TONS

Resistor. The RTONS pin servos to 1.2V. A resistor to

written for 1.5 seconds (typical), the WDT output will go

back high. When WDT is high, all balancers are off. The

watchdog timer function can be disabled by connecting

–

V programs the maximum on-time for all external NMOS

transistors connected in series with secondary windings.

This protects against a short-circuited current sense re-

sistor in any secondary winding. To defeat this function,

–

WDT to V . The secondary winding OVP function can also

be implemented using this pin (See Operation section).

connect RTONS to V . The secondary winding OVP

REG

–

V (Pin 21, Exposed Pad Pin 49): Connect V to the most

negative potential in the series of cells. The exposed pad

shouldbeconnectedtoacontinuous(ground)planebiased

threshold (see WDT pin) is also slaved to the value of the

R

TONS

resistor.

RTONP (Pin 14): Primary Winding Max t_ONSetting

Resistor. The RTONP pin servos to 1.2V. A resistor to

V^–programs the maximum on-time for all external NMOS

transistorsconnectedinserieswithprimarywindings.This

protects against a short-circuited current sense resistor

in any primary winding. To defeat this function, connect

–

at V on the second layer of the printed circuit board by

several vias directly under the LTC3300-2.

I1P, I2P, I3P, I4P, I5P, I6P (Pins 22, 25, 28, 31, 34, 37):

I1P through I6P are current sense inputs for measuring

primary winding current in transformers connected in

parallel with battery cells 1 through 6.

RTONP to V_REG

.

G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35,

38): G1P through G6P are gate driver outputs for driving

external NMOS transistors connected in series with the

primary windings of transformers connected in parallel

with battery cells 1 through 6.

CTRL: (Pin 15): Control Input. The CTRL pin configures

the LTC3300-2 for the minimum part count application

employing a single transformer if CTRL is tied to V

or

REG

for the multiple transformer application if CTRL is tied to

–

V . This pin must be tied to either V

or V .

REG

33002f

9

For more information www.linear.com/LTC3300-2

LTC3300-2

PIN FUNCTIONS

C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39):

C1 through C6 connect to the positive terminals of bat-

tery cells 1 through 6. Connect the negative terminal of

BOOST(Pin42):EnableBoostPin.ConnectBOOSTtoV

REG

to enable the boosted gate drive needed for balancing the

+

top cellin a given LTC3300-2 sub-stack. If the BOOST pin

–

battery cell 1 to V .

can be connected to the next cell up in the stack (i.e., C1

of the next LTC3300-2 in the stack), then BOOST should

+

BOOST (Pin 40): Boost Pin. Connects to the anode of

the external flying capacitor used for generating sufficient

gatedrivenecessaryforbalancingthetopmostbatterycell

in a given LTC3300-2 sub-stack. A Schottky diode from

–

be tied to V and BOOST no connected. This pin must

–

be tied to either V

or V .

REG

A0, A1, A2, A3, A4 (Pins 43, 44, 45, 46, 47): Address

+

–

C6 to BOOST is needed as well. Alternately, the BOOST

Inputs. The state of the address pins (V

= 1, V = 0)

REG

pin can connect to one cell up in the above sub-stack (if

present).ThispiniseffectivelyC7.(Note:“Sub-stack”refers

to the 3-6 battery cells connected locally to an individual

LTC3300-2 as part of a larger stack.)

determines the LTC3300-2 address. These pins must be

–

tied to either V

section.

or V . See Serial Port in the Operation

REG

V

(Pin 48): Linear Voltage Regulator Output. This 4.8V

REG

–

BOOST (Pin 41): Boost Pin. Connects to the cathode of

the external flying capacitor used for generating sufficient

gate drive necessary for balancing the topmost battery

cell in a given LTC3300-2 sub-stack. Alternately, if the

output should be bypassed with a 1µF or larger capacitor

–

to V . The V

to internal and external loads. The V

current.

pin is capable of supplying up to 40mA

REG

pin does not sink

REG

+

BOOST pin connects to the next higher cell in the above

sub-stack (if present), this pin is a no connect.

33002f

10

For more information www.linear.com/LTC3300-2

LTC3300-2

BLOCK DIAGRAM

48

41

BOOST

40

BOOST

–

+

V

REG

C6

40mA

MAX

V

REG

BOOST

GATE DRIVE

GENERATOR

BOOST

C6

VOLTAGE

REGULATOR

THERMAL

SHUTDOWN

SD

42

39

4.8V

POR

–

V

+

BOOST

G6P

I6P

38

37

C5

47

46

45

44

43

A4

A3

A2

A1

A0

C5

+

–

+

2

50mV/0

0/50mV

5

ADDRESS

I6S

2

1

V

REG

LEVEL-SHIFTING

SERIAL

INTERFACE

G6S

–

V

PINS 3 TO 10,

25 TO 36

DATA

12

6-CELL

SYNCHRONOUS

FLYBACK

CONTROLLER

BALANCER

16

STATUS

12

C1

G1P

I1P

24

23

22

SDO

C2

19

18

SDI

–

V

+

–

+

ACTIVE

2

SCKI

WATCHDOG

TIMER

50mV/0

0/50mV

17

16

20

CSBI

WDT

I1S

12

11

V

REG

RESET

G1S

5.6V

–

V

–

V

MAX ON-TIME

VOLT-SEC

CLAMPS

1.2V

TONS

R

EXPOSED

PAD

–

V

CTRL

RTONS

RTONP

14

V

21

49

15

13

33002 BD

33002f

11

For more information www.linear.com/LTC3300-2

LTC3300-2

TIMING DIAGRAM

Timing Diagram of the Serial Interface

t

4

1

t

6

t

3

t

7

2

SCKI

SDI

t

5

CSBI

SDO

t

8

33002 TD

33002f

12

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

Battery Management System (BMS)

In the process of bringing the cells into balance, the over-

all stack is slightly discharged. The charger component

provides a means for net charging of the entire stack from

an alternate power source.

The LTC3300-2 multicell battery cell balancer is a key

component in a high performance battery management

system (BMS) for series-connected Li-Ion cells. It is de-

signedtooperateinconjunctionwithamonitor, acharger,

and a microprocessor or microcontroller (see Figure 1).

The last component in the BMS is a microprocessor/

microcontroller which communicates directly with the

balancer, monitor, and charger to receive voltage, cur-

rent, and temperature information and to implement a

balancing algorithm.

Thefunctionofthebalanceristoefficientlytransfercharge

to/from a given out-of-balance cell in the stack from/to

a larger group of neighboring cells (which includes that

individual cell) in order to bring that cell into voltage or

capacity balance with its neighboring cells. Ideally, this

charge would always be transferred directly from/to the

entire stack, but this is impractical for voltage reasons

when the number of cells in the overall stack is large. The

LTC3300-2 is designed to interface to a group of up to 6

series cells, so the number of LTC3300-2 ICs required to

balance a series stack of N cells is N/6 rounded up to the

nearest integer. Since the LTC3300-2 address is 5 bits,

the maximum N can be is 192 cells. For connecting an

individual LTC3300-2 in the stack to fewer than 6 cells,

refer to the Applications Information section.

There is no single balancing algorithm optimal for all

situations. For example, during net charging of the overall

stack, it may be desirable to discharge the highest voltage

cells first to avoid reaching terminal charge on any cell

before the entire stack is fully charged. Similarly, during

net discharging of the overall stack, it may be desirable

to charge the lowest voltage cells first to keep them from

reaching a critically low level. Other algorithms may

prioritize fastest time to overall balance. The LTC3300-2

implementsnoalgorithmforbalancingthestack.Insteadit

providesmaximumflexibilitybyimposingnolimitationon

the algorithm implemented as all individual cell balancers

can operate simultaneously and bidirectionally.

Because the balancing function entails switching large

(multiampere) currents between cells, precision voltage

monitoring in the BMS is better served by a dedicated

monitor component such as the LTC6803-2 or one of its

familyofparts.TheLTC6803-2providesforhighprecision

A/D monitoring of up to 12 series cells. The only voltage

monitoring provided by the LTC3300-2 is a coarse “out-

of-range” overvoltage and undervoltage cell balancing

disqualification, which provides a safety shutoff in the

event Kelvin sensing to the monitor component is lost.

Unidirectional Versus Bidirectional Balancing

Most balancers in use today employ a unidirectional (dis-

charge only) approach. The simplest of these operate by

switching in a resistor across the highest voltage cell(s)

in the stack (passive balancing). No charge is recovered

in this approach -instead it is dissipated as heat in the

resistive element. This can be improved by employing an

energystorageelement(inductiveorcapacitive)totransfer

33002f

13

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

TOP OF STACK

+

CELL N

I

CHARGE

I

LOAD

C6

C12

C5

C4

C3

C2

C1

C11

C10

C9

+

CELL N – 1

CELL N – 2

CELL N – 3

CELL N – 4

CELL N – 5

LTC3300-2

BALANCER

C8

DIGITAL

ISOLATOR

–

C7

V

LTC6803-2

MONITOR

C6

C5

C4

C3

C2

C1

CELL N – 6

CELL N – 7

CELL N – 8

C6

C5

C4

C3

C2

C1

LTC3300-2

BALANCER

CELL N – 9

CELL N – 10

CELL N – 11

DIGITAL

ISOLATOR

DIGITAL

ISOLATOR

–

V

CN

•

CHARGER

+

CELL 12

CELL 11

CELL 10

CELL 9

–

V

C6

C12

C5

C4

C3

C2

C1

C11

C10

C9

LTC3300-2

BALANCER

C8

DIGITAL

ISOLATOR

CELL 8

–

C7

V

LTC6803-2

MONITOR

CELL 7

CELL 6

C6

C5

C4

C3

C6

C5

C4

C3

CELL 5

CELL 4

CELL 3

CELL 2

CELL 1

LTC3300-2

BALANCER

C2

C1

C2

C1

–

V

CC

µP/µC

33002 F01

SERIAL COMMUNICATION BUS

V

EE

Figure 1. LTC3300-2/LTC6803-2 Typical Battery Management System (BMS)

33002f

14

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

chargefromthehighestvoltagecell(s)inthestacktoother

lower voltage cells in the stack (active balancing). This

can be very efficient (in terms of charge recovery) for the

case where only a few cells in the overall stack are high,

but will be very inefficient (and time consuming) for the

case where only a few cells in the overall stack are low. A

bidirectionalactivebalancingapproach,suchasemployed

by the LTC3300-2, is needed to achieve minimum balanc-

ing time and maximum charge recovery for all common

cell capacity errors.

Synchronous Flyback Balancer

ThebalancingarchitectureimplementedbytheLTC3300-2

is bidirectional synchronous flyback. Each LTC3300-2

containssixindependentsynchronousflybackcontrollers

that are capable of directly charging or discharging an

individual cell. Balance current is scalable with external

components. Each balancer operates independently of

the others and provides a means for bidirectional charge

transfer between an individual cell and a larger group of

adjacent cells. Refer to Figure 2.

Single-Cell Discharge Cycle for Cell 1

Single-Cell Charge Cycle for Cell 1

I

= 2A

I

= 2A

PEAK_SEC

PEAK_PRI

(I1P = 50mV)

(I1S = 50mV)

V

CC

I

PRIMARY

SECONDARY

I

CHARGE

V

TOP_OF_STACK

t

5µs

+

~417ns

I

CELL N

LOAD

2A

+

–I

PRIMARY

I

SECONDARY

CELL 13

(48V)

SECONDARY

t

5µs

t

CELL 12

~417ns

50mV

52.05V

52V

48V

+

CELL 2

(4V)

I

PRIMARY

V

SECONDARY

PRIMARY

T:1

•

L

CELL 1

PRI

50mV

4V

50mV

10µH

t

•

V

PRIMARY

SECONDARY

G1S

52V

50mV

51.95V

G1P

48V

I1P

I1S

R

SNS_PRI

25mΩ

V

SNS_SEC

25mΩ

V

PRIMARY

SECONDARY

4V

50mV

t

50mV

33002 F02

Figure 2. Synchronous Flyback Balancing Example with T = 1, S = 12

33002f

15

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

Cell Discharging (Synchronous)

at the InS pin), the secondary switch is turned off and

current then flows in the primary side thus charging the

selected cell from the entire stack of secondary cells. As

with the discharging case, the primary-side synchronous

switch is turned on to minimize power loss during the cell

charging phase. Once the primary current drops to zero,

the primary switch is turned off and the secondary-side

switch is turned back on thus repeating the cycle.

When discharging is enabled for a given cell, the primary

side switch is turned on and current ramps in the primary

winding of the transformer until the programmed peak

current (I ) is detected at the InP pin. The primary

PEAK_PRI

side switch is then turned off, and the stored energy in

the transformer is transferred to the secondary-side cells

causing current to flow in the secondary winding of the

transformer. The secondary-side synchronous switch

is turned on to minimize power loss during the transfer

period until the secondary current drops to zero (detected

at InS). Once the secondary current reaches zero, the

secondary switch turns off and the primary-side switch is

turned back on thus repeating the cycle. In this manner,

charge is transferred from the cell being discharged to

all of the cells connected between the top and bottom of

the secondary side—thereby charging the adjacent cells.

In the example of Figure 2, the secondary-side connects

across 12 cells including the cell being discharged.

I

is programmed using the following equation:

PEAK_SEC

50mV

R_{SNS_SEC}

I_{PEAK_SEC}

=

Cell charge current and corresponding secondary-side

discharge current are determined to first order by the

following equations:

I_{PEAK_SEC}

ST

S+T

⎛

⎜

⎝

⎞

⎟

⎠

I_CHARGE

=

η_CHARGE

2

I_{PEAK_SEC}

T

S+T

⎛

⎞

⎟

I

is programmed using the following equation:

I_SECONDARY

=

PEAK_PRI

⎜

⎝

⎠

2

50mV

R_{SNS_PRI}

I_{PEAK_PRI}

=

where S is the number of secondary cells in the stack, 1:T

is the transformer turns ratio from primary to secondary,

andη

isthetransferefficiencyfromsecondary-side

Cell discharge current (primary side) and secondary-side

charge recovery current are determined to first order by

the following equations:

CHARGE

stack discharge to the primary-side cell.

Each balancer’s charge transfer “frequency” and duty

factor depend on a number of factors including I ,

I_{PEAK_PRI}

S

S+T

⎛

⎜

⎝

⎞

⎟

⎠

PEAK_PRI

I_DISCHARGE

=

I

, transformer winding inductances, turns ratio,

cell voltage and the number of secondary-side cells.

PEAK_SEC

2

I_{PEAK_PRI}

1

S+T

⎛

⎞

⎠

The frequency of switching seen at the gate driver outputs

is given by:

I_SECONDARY

=

η_DISCHARGE

⎟

⎜

⎝

2

S

V_CELL

where S is the number of secondary-side cells, 1:T is the

transformer turns ratio from primary to secondary, and

DISCHARGE

f_DISCHARGE

=

•

S+T L_PRI•I_{PEAK_PRI}

η

is the transfer efficiency from primary cell

S

V_CELL

discharge to the secondary side stack.

f_CHARGE

=

•

S+T L_PRI•I_{PEAK_SEC}•T

Cell Charging

where L is the primary winding inductance.

PRI

When charging is enabled for a given cell, the secondary-

sideswitchfortheenabledcellisturnedonandcurrentflows

from the secondary-side cells through the transformer.

OnceI_{PEAK_SEC}isreachedinthesecondaryside(detected

Figure 3 shows a fully populated LTC3300-2 application

employing all six balancers.

33002f

16

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

6.8Ω

0.1µF

UP TO

CELL 12

•

–

+

BOOST BOOST

C6

1:1

•

10µF

10µH

•

G6P

I6P

+

CELL 6

25mΩ

G6S

I6S

25mΩ

1:1

C5

•

10µF

10µH

•

G5P

I5P

+

CELL 5

25mΩ

G5S

I5S

25mΩ

C4

C3

•

LTC3300-2

C2

1:1

•

10µF

10µH

•

G2P

I2P

A4

A3

A2

A1

A0

+

CELL 2

25mΩ

SERIAL

COMMUNICATION

I2S

CSBI

SCKI

SDI

PINS

25mΩ

1:1

SDO

C1

WDT

•

10µF

10µH

•

G1P

I1P

+

CELL 1

25mΩ

V

G1S

I1S

REG

BOOST

25mΩ

–

V

CTRL

RTONP RTONS

22.6k

•

10µF

6.98k

33002 F03

Figure 3. LTC3300-2 6-Cell Active Balancer Module Showing Power Connections for the Multi-Transformer Application (CTRL = V^–)

33002f

17

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

Balancing High Voltage Battery Stacks

TOP

LTC3300-2

Balancing series connected batteries which contain >>12

cellsinseriesrequiresinterleavingofthetransformersec-

ondaryconnectionsinordertoachievefullstackbalancing

while limiting the breakdown voltage requirements of the

primary- and secondary-side power FETs. Figure 4 shows

typical interleaved transformer connections for a multicell

battery stack in the generic sense, and Figure 5 for the

specific case of an 18-cell stack. In these examples, the

secondary side of each transformer is connected to the

top of the cell that is 12 positions higher in the stack than

the bottom of the lowest voltage cell in each LTC3300-2

sub-stack. For the top most LTC3300-2 in the stack, it is

not possible to connect the secondary side of the trans-

former across 12 cells. Instead, it is connected to the top

of the stack, or effectively across only 6 cells. Interleaving

in this fashion allows charge to transfer between 6-cell

sub-stacks throughout the entire battery stack.

PRI

SEC

POWER STAGES

•

+

CELL N

•

FROM CELL N-12

SECONDARY

CELL N-6

TO CELL 24

•

LTC3300-2

SEC POWER STAGES PRI

•

+

CELL 18

•

+

CELL 13

PRI

•

LTC3300-2

POWER STAGES

SEC

•

+

CELL 12

Max On-Time Volt-Sec Clamps

•

The LTC3300-2 contains programmable fault protection

clamps which limit the amount of time that current is

allowed to ramp in either the primary or secondary wind-

ings in the event of a shorted sense resistor. Maximum

on time for all primary connections (active during cell

discharging)andallsecondaryconnections(activeduring

•

+

CELL 7

PRI

LTC3300-2

SEC

POWER STAGES

•

+

CELL 6

cellcharging)isindividuallyprogrammablebyconnecting

•

–

resistors from the R

and R

pins to V according

TONP

TONS

CELL 5

CELL 4

CELL 3

CELL 2

CELL 1

to the following equations:

R_TONP

20kΩ

t

_{ON(MAX)|PRIMARY}= 7.2µs

R_TONS

15kΩ

_{ON(MAX)|SECONDARY}=1.2µs

For more information on selecting the appropriate

maximum on-times, refer to the Applications Information

section.

33002 F04

To defeat this function, short the appropriate R

pin(s)

TON

to V

.

REG

Figure 4. Diagram of Power Transfer Interleaving Through the

Stack, Transformer Connections for High Voltage Stacks

33002f

18

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

0.1µF

6.8Ω

–

+

BOOST BOOST

C6

C1

+

TO TRANSFORMER

SECONDARIES OF

CELL 18

BALANCERS 14 TO 18

1:1

•

10µH

10µF

•

LTC3300-2

G1P

I1P

CELL 13

25mΩ

G1S

I1S

V

25mΩ

REG

–

V

BOOST

+

BOOST

C6

C1

+

TO TRANSFORMER

SECONDARIES OF

BALANCERS 8 TO 12

CELL 12

1:1

•

10µH

•

LTC3300-2

G1P

I1P

CELL 7

25mΩ

G1S

I1S

25mΩ

–

V

BOOST

+

BOOST

C6

C1

+

TO TRANSFORMER

SECONDARIES OF

BALANCERS 2 TO 6

CELL 6

1:1

•

10µH

•

LTC3300-2

G1P

I1P

CELL 1

25mΩ

G1S

I1S

25mΩ

–

V

BOOST

33002 F05

Figure 5. 18-Cell Active Balancer Showing Power Connections, Interleaved

Transformer Secondaries and BOOST⁺Rail Generation Up the Stack

33002f

19

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

Gate Drivers/Gate Drive Comparators

balancer(s) and only the affected balancer(s) will shut off.

The balance command remains stored in memory, and

active balancing will resume where it left off if sufficient

gate drive is subsequently restored. This can happen if,

for example, the stack is being charged.

All secondary-side gate drivers (G1S through G6S) are

powered from the V

output, pulling up to 4.8V when

REG

–

on and pulling down to V when off. All primary-side

gate drivers (G1P through G6P) are powered from their

respective cell voltage and the next cell voltage higher in

the stack (see Table 1). An individual cell balancer will only

be enabled if its corresponding cell voltage is greater than

2V and the cell voltage of the next higher cell in the stack

is also greater than 2V. For the G6P gate driver output,

the next higher cell in the stack is C1 of the next higher

LTC3300-2 in the stack (if present) and is only used if the

boosted gate drive is disabled (by connecting BOOST =

Cell Overvoltage Comparators

In addition to sufficient gate drive being required to en-

able balancing, there are additional comparators which

disable all active balancing if any of the six individual cell

voltages is greater than 5V. These comparators have a

DC hysteresis of 500mV. For improved noise immunity,

the inputs are internally low pass filtered and the outputs

are filtered so as to not transition unless the internal

comparator state is unchanged for 3µs to 6µs (typical).

If any cell voltage goes overvoltage while active balanc-

ing is in progress, all active balancers will shut off. The

balance command remains stored in memory, and active

balancing will resume where if left off if the cell voltage

subsequently comes back in range. These comparators

will protect the LTC3300-2 if a connection to a battery is

lost while balancing and the cell voltage is still increasing

as a result of that balancing.

–

V ). If the boosted gate drive is enabled (by connecting

BOOST = V ), only the C6 cell voltage is looked at to

REG

enable balancing of Cell 6. In the case of the topmost

LTC3300-2 in the stack, the boosted gate drive must be

enabled. Theboostedgatedriverequiresanexternaldiode

+

from C6 to BOOST and a boost capacitor from BOOST to

–

BOOST . For information on selecting these components,

refer to the Applications Information section. Also note

that the dynamic supply current referred to in Note 4 of

the Electrical Characteristics table adds to the terminal

currents of the pins indicated in the Voltage When Off and

Voltage When On columns of Table 1.

Voltage Regulator

A linear voltage regulator powered from C6 creates a

ThegatedrivecomparatorshaveaDChysteresisof70mV.

For improved noise immunity, the inputs are internally

low pass filtered and the outputs are filtered so as to

not transition unless the internal comparator state is

unchangedfor3µsto6µs(typical).Ifinsufficientgatedrive

is detected while active balancing is in progress (perhaps,

for example, if the stack is under heavy load), the affected

4.8V rail at the V

pin which is used for powering

REG

certain internal circuitry of the LTC3300-2 including all 6

secondary gate drivers. The V output can also be used

REG

for powering external loads, provided that the total DC

loading of the regulator does not exceed 40mA at which

point current limit is imposed to limit on-chip power dis-

Table 1

DRIVER OUTPUT

VOLTAGE WHEN OFF

VOLTAGE WHEN ON

GATE DRIVE REQUIRED TO ENABLE BALANCING

–

G1P

G2P

G3P

G4P

G5P

G6P

V-

C1

C2

C3

C4

C5

C2

C3

C4

C5

C6

(C2 – C1) ≥ 2V and (C1 – V ) ≥2V

(C3 – C2) ≥ 2V and (C2 – C1) ≥2V

(C4 – C3) ≥ 2V and (C3 – C2) ≥2V

(C5 – C4) ≥ 2V and (C4 – C3) ≥2V

(C6 – C5) ≥ 2V and (C5 – C4) ≥2V

(C6 – C5) ≥ 2V

If BOOST = V : BOOST+ (Generated)

REG

–

+

If BOOST = V : BOOST = C7*

(C7* – C6) ≥ 2V and (C6 – C5) ≥ 2V

*C7 is equal to C1 of the next higher LTC3300-2 in the stack if this connection is used.

33002f

20

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

sipation. The internal component of the DC load current

is dominated by the average gate driver current(s) (G1S

through G6S), each approximated by C ꢀ V ꢀ f, where C

is the gate capacitance of the external NMOS transistor,

Watchdog Timer Circuit

The watchdog timer circuit provides a means of shutting

down all active balancing in the event that communication

to the LTC3300-2 is lost. The watchdog timer initiates

when a balance command begins executing and is reset

to zero every time a valid 8-bit command byte (see Serial

Port Operation) is written. The valid command byte can

be an execute, a write, or a read (command or status).

“Partial” reads and writes are considered valid, i.e., it is

only necessary that the first 8 bits have to be written and

contain the correct address.

V = V

= 4.8V, and f is the frequency that the gate

REG

driver output is running at. FET manufacturers usually

specify the C ꢀ V product as Q (gate charge) measured

g

in coulombs at a given gate drive voltage. The frequency,

f, is dependent on many terms, primarily the voltage of

each individual cell, the number of cells in the secondary

stack, the programmed peak balancing current, and the

transformer primary and secondary winding inductances.

In a typical application, the C ꢀ V ꢀ f current loading the

Referring to Figure 6a, at initial power-up and when not

balancing, the WDT pin is high impedance and will be

pulled high (internally clamped to ~5.6V) if an external

pull-up resistor is present. While balancing and during

normal communication activity, the WDT pin is pulled

V

outputisexpectedtobelowsingle-digitmilliamperes

REG

per driver. Note that the V

loading current is ultimately

REG

delivered from the C6 pin. For applications involving very

large balance currents and/or employing external NMOS

low by a precision current source equal to 1.2V/R

.

transistors with very large gate capacitance, the V

TONS

REG

(Note: if the secondary volt-second clamp is defeated

by connecting R to V , the watchdog function is

output may need to source more than 40mA average. For

information on how to design for these situations, refer

to the Applications Information section.

TONS

REG

also defeated.) If no valid command byte is written for

1.5 seconds (typical), the WDT output will go back high.

When WDT is high, all balancers will be shut down but

the previously executing balance command still remains

in memory. From this timed-out state, a subsequent valid

command byte will reset the timer, but the balancers will

only restart if an execute command is written. To defeat

One additional function slaved to the V

the power-on reset (POR). During initial power-up and

subsequently if the V pin voltage ever falls below ap-

proximately 4V (e.g., due to overloading), the serial port

is cleared to the default power-up state with no balancers

active.Thisfeaturethusguaranteesthattheminimumgate

drive provided to the external secondary side FETs is also

4V.Fora10µFcapacitorloadingtheoutputatinitialpower-

up, the output reaches regulation in approximately 1ms.

output is

REG

–

the watchdog function, simply connect the WDT pin to V .

Pause/Resume Balancing (via WDT Pin)

The WDT output pin doubles as a logic input (TTL levels)

which can be driven by an external logic gate as shown in

Figure 6b (no watchdog), or by a PMOS/three-state logic

gate as shown in Figure 6c (with watchdog) to pause and

resume balancing in progress. The external pull-up must

havesufficientdrivecapabilitytooverridethecurrentsource

Thermal Shutdown

The LTC3300-2 has an overtemperature protection circuit

whichshutsdownallactivebalancingiftheinternalsilicon

die temperature rises to approximately 155°C. When in

thermalshutdown,allserialcommunicationremainsactive

and the cell balancer status (which contains temperature

information) can be read back. The balance command

whichhadbeenbeingexecutedremainsstoredinmemory.

This function has 10°C of hysteresis so that when the die

temperature subsequently falls to approximately 145°C,

active balancing will resume with the previously execut-

ing command.

to ground at the WDT pin (= 1.2V/R

). Provided that

TONS

the internal watchdog timer has not independently timed

out, externally pulling the WDT pin high will immediately

pause balancing, and it will resume where it left off when

the pin is released.

33002f

21

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

Secondary Winding OVP Function (via WDT pin)

balance command remains stored in memory, and active

balancing will resume where it left off if the stack voltage

subsequently falls to a safer level.

The precision current source pull-down on the WDT pin

during balancing can be used to construct an accurate

secondary winding OVP protection circuit as shown in

Single Transformer Application (CTRL = V

)

REG

Figure 6c. A second external resistor, scaled to R

TONS

Figure 7 shows a fully populated LTC3300-2 application

employing all six balancers with a single shared custom

transformer. In this application, the transformer has six

primary windings coupled to a single secondary winding.

Only one balancer can be active at a given time as all six

sharethesecondarygatedriverG1Sandsecondarycurrent

sense input I1S. The unused gate driver outputs G2S-G6S

must be left floating and the unused current sense inputs

and connected to the transformer secondary winding, is

used to set the comparator threshold. An NMOS cascode

device (with gate tied to V ) is also needed to protect

REG

the WDT pin from high voltage. The secondary winding

OVP thresholds are given by:

V

= 1.4V + 1.2V ꢀ (R

/R

)

SEC|OVP(RISING)

SEC_OVP TONS

= 1.4V + 1.05V ꢀ (R

/R

)

SEC|OVP(FALLING)

SEC_OVP TONS

–

I2S-I6SshouldbeconnectedtoV .Anybalancecommand

This comparator will protect the LTC3300-2 application

circuit if the secondary winding connection to the battery

stack is lost while balancing and the secondary winding

voltage is still increasing as a result of that balancing. The

whichattemptstooperatemorethanonebalanceratatime

will be ignored. This application represents the minimum

component count active balancer achievable.

V

REG

V

REG

V

= 1.4V

LTC3300-2

WDT

TH

LTC3300-2

R

WDT

PAUSE/

RESUME

WDT

5.6V

1.2V

ACTIVE

5.6V

1.2V

ACTIVE

RTONS

R

TONS

R

TONS

R

TONS

R

TONS

–

V

33002 F06b

33002 F06a

(6a) Watchdog Timer Only (WDT = V^–to Defeat)

(6b) Pause/Resume Balancing Only

TO TRANSFORMER

SECONDARY WINDINGS

V

REG

R

SEC_OVP

LTC3300-2

PAUSE/

RESUME

V

REG

WDT

EITHER/OR

5.6V

1.2V

V

REG

ACTIVE

REG

RTONS

PAUSE/

RESUME

R

TONS

R

TONS

33002 F06c

(6c) Watchdog Timer with Pause/Resume Balancing and Secondary Winding OVP Protection

Figure 6. WDT Pin Connection Options

33002f

22

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

0.1µF

6.8Ω

C6

•

–

+

BOOST BOOST

UP TO CELL 12

EACH

1:1

•

10µH

10µF

•

G6P

I6P

25mΩ

CELL 6

+

C5

10µH

10µF

G5P

I5P

25mΩ

CELL 5

+

C4

10µH

10µF

G4P

I4P

25mΩ

CELL 4

+

C3

LTC3300-2

10µH

10µF

G3P

I3P

25mΩ

CELL 3

+

C2

10µF

G2P

I2P

A4

A3

A2

A1

A0

25mΩ

CELL 2

+

SERIAL

COMMUNICATION

CSBI

SCKI

SDI

PINS

10µF

SDO

G1P

I1P

WDT

25mΩ

G1S

V

REG

I1S

G2S-G6S

I2S-I6S

BOOST

+

NC

25mΩ

CELL 1

–

CTRL

V

33002 F07

RTONP RTONS

22.6k

10µF

6.98k

Figure 7. LTC3300-2 6-Cell Active Balancer Module Showing Power Connections for the Single Transformer Application (CTRL = V_REG

)

33002f

23

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

SERIAL PORT OPERATION

Data Link Layer

Clock Phase and Polarity: The LTC3300-2 SPI-compatible

interface is configured to operate in a system using

CPHA = 1 and CPOL = 1. Consequently, data on SDI must

be stable during the rising edge of SCKI.

Overview

The LTC3300-2 has an SPI bus compatible serial port.

Devicescanbeconnectedinparallel,usingdigitalisolators.

Multiple devices are uniquely identified by a part address

determined by the A0 to A4 pins.

Data Transfers: Every byte consists of 8 bits. Bytes are

transferred with the most significant bit (MSB) first. On a

write, the data value on SDI is latched into the device on

the rising edge of SCKI (Figure 8a). Similarly, on a read,

the data value on SDO is valid during the rising edge of

SCKIandtransitionsonthefallingedgeofSCKI(Figure8b).

Physical Layer

On theLTC3300-2, fourpinscomprise theserialinterface:

CSBI, SCKI, SDI and SDO. The SDO and SDI pins may

be tied together, if desired, to form a single bidirectional

port. Five address pins (A0 to A4) set the part address.

All serial communication related pins are voltage mode

withvoltagelevelsreferencedtotheV

CSBI must remain low for the entire duration of a com-

mand sequence, including between a command byte and

subsequent data. On a write command, data is latched in

on the rising edge of CSBI.

–

andV supplies.

REG

CSBI

SCKI

LSB (DATA)

MSB (CMD)

LSB (CMD)

MSB (DATA)

SDI

(8a) Transmission Format (Write)

CSBI

SCKI

SDI

MSB (CMD)

LSB (CMD)

LSB (DATA)

SDO

MSB (DATA)

33002 F08

(8b) Transmission Format (Read)

Figure 8.

33002f

24

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

Command Byte

Write Balance Command

AllcommunicationtotheLTC3300-2takesplacewithCSBI

logic low. The first 8 clocked in data bits after a high-to-

low transition on CSBI represent the command byte. The

8-bit command byte is written MSB first per Table 2. The

first 5 bits must match the fixed pin-strapped address

[A4 A3 A2 A1 A0] for the individual device, or all sub-

sequent data will be ignored until CSBI transitions high

and then low again. The 6th and 7th bits program one of

four commands as shown in Table 3. The 8th bit in the

command byte must be set such that the entire 8-bit com-

mand byte has even parity. If the parity is incorrect, the

current balance command being executed (from the last

previouslysuccessfulwrite)isterminatedimmediatelyand

all subsequent (write) data is ignored until CSBI transi-

tions high and then low again. Incorrect parity takes this

action whether or not the address matches. This thereby

providesafastmeanstoimmediatelyterminatebalancing-

in-progress by intentionally writing a command byte with

incorrect parity.

If the command bits program Write Balance Command,

all subsequent write data must be exactly 16 bits (before

CSBI transitions high) or it will be ignored. The internal

command holding register will be cleared which can be

verifiedonreadback. Thecurrentbalancecommandbeing

executed (from the last previously successful write) will

continue, but all active balancing will be turned off if an

Execute Balance Command is subsequently written. Only

the individual LTC3300-2 in the stack with the matching

addresswillloadinthewritedata. The16-bitwritebalance

command is written MSB first per Table 4.

The first 12 bits of the 16-bit balance command are used

to indicate which balancer (or balancers) is active and in

which direction (charge or discharge). Each of the 6 cell

balancers is controlled by 2 bits of this data per Table 5.

The balancing algorithm for a given cell is:

Charge Cell n: Ramp up to I

in secondary winding,

PEAK

ramp down to I

in primary winding. Repeat.

ZERO

Discharge Cell n (Synchronous): Ramp up to Ipeak in

Table 2. Command Byte Bit Mapping

(Defaults to 0x00 in Reset State)

primary winding, ramp down to I

winding. Repeat.

in secondary

ZERO

A4

A3

A2

A1

A0

CMDA CMDB Parity Bit

(LSB)

(MSB)

Table 5. Cell Balancer Control Bits

Table 3. Command Bits

DnA

DnB

BALANCING ACTION (n = 1 to 6)

None

CMDA

CMDB

COMMUNICATION ACTION

0

1

0

1

0

1

0

1

0

1

0

1

Write Balance Command (without Executing)

Readback Balance Command

Read Balance Status

Discharge Cell n (Nonsynchronous)

Discharge Cell n (Synchronous)

Charge Cell n

Execute Balance Command

Table 4. Write Balance Command Data Bit Mapping (Defaults to 0x000F in Reset State)

D1A

(MSB)

D1B

D2A

D2B

D3A

D3B

D4A

D4B

D5A

D5B

D6A

D6B

CRC[3] CRC[2] CRC[1] CRC[0]

(LSB)

33002f

25

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

For nonsynchronous discharging of cell n, both the sec-

ondary winding gate drive and (zero) current sense amp

are disabled. The secondary current will conduct either

through the body diode of the secondary switch (if pres-

ent) or through a substitute Schottky diode. The primary

will only turn on again after the secondary winding Volt-

sec clamp times out. In a bidirectional application with a

secondary switch, it may be possible to achieve slightly

higherdischargeefficiencybyoptingfornonsynchronous

discharge mode (if the gate charge savings exceed the

added diode drop losses) but the balancing current will be

less predictable because the secondary winding Volt-sec

clamp must be set longer than the expected time for the

current to hit zero in order to guarantee no current rever-

sal. In the case where a Schottky diode replaces the sec-

ondary switch, it is possible to build a undirectional

discharge-only balancing application charging an isolated

auxiliary cell as shown in Figure 16 in the Typical Applica-

tions section.

Commandareinverted.Thiswasdonesothatan“allzeros”

command is invalid. The LTC3300-2 will ignore the write

data if the remainder is not zero and the internal command

holding register will be cleared which can be verified on

readback. The current balance command being executed

(from the last previously successful write) will continue,

but all active balancing will be turned off if an Execute Bal-

ance Command is subsequently written. For information

on how to calculate the CRC including an example, refer

to the Applications Information section.

Readback Balance Command

ThebitmappingforReadbackBalanceCommandisidenti-

cal to that for Write Balance Command. If the command

bits program Readback Balance Command, the 16 bits of

previously written data (latched in 12-bit message plus

newly calculated 4-bit CRC) are shifted out in the same

order bitwise (MSB first) per Table 4. Only the individ-

ual LTC3300-2 in the stack with the matching address

will send out the read data. This command allows for

microprocessor verification of written commands before

executing. Note that the CRC bits in the Readback Balance

Command are also inverted. This was done so that an “all

zeros” readback is invalid.

In the CTRL = 1 application of Figure 7 employing a single

transformer which can only balance one cell at a time,

anycommandrequestingsimultaneousbalancingofmore

than one cell will be ignored. All active balancing will be

turned off if an Execute Balance Command is subse-

quently written.

Read Balance Status

The last 4 bits of the 16-bit balance command are used

for packet error checking (PEC). The 16 bits of write data

(12-bit message plus 4-bit CRC) are input to a cyclic re-

dundancy check (CRC) block employing the International

Telecommunication Union CRC-4 standard characteristic

polynomial:

IfthecommandbitsprogramReadBalanceStatus, 16bits

of status data (12 bits of data plus associated 4-bit CRC)

areshiftedoutMSBfirstperTable6. SimilartoaReadback

Balance Command, the last 4 bits in each 16-bit balance

status are used for error detection. The first 12 bits of

the status are input to a cyclic redundancy check (CRC)

block employing the same characteristic polynomial used

for write commands. The LTC3300-2 will calculate and

append the appropriate 4-bit CRC to the outgoing 12-bit

message which can then be used for microprocessor er-

4

x + x + 1

In the write data, the 4-bit CRC appended to the message

must be selected such that the remainder of the CRC divi-

sion is zero. Note that the CRC bits in the Write Balance

Table 6. Read Balance Status Data Bit Mapping (defaults to 0x000F in Reset State)

Gate

Cells

Sec

Temp

OK

0

CRC[3] CRC[2] CRC[1] CRC[0]

(LSB)

Drive 1 Drive 2 Drive 3 Drive 4 Drive 5 Drive 6 Not OV Not OV

OK

(MSB)

OK

33002f

26

For more information www.linear.com/LTC3300-2

LTC3300-2

OPERATION

Execute Balance Command

ror checking. Only the individual LTC3300-2 in the stack

with the matching address will send out the status data.

Note that the CRC bits in the Read Balance Status are

inverted. This was done so that an “all zeros” readback

is invalid.

If the command bits program Execute Balance Command,

the last successfully written and latched in balance com-

mandwillbeexecutedimmediately.Allsubsequent(write)

data will be ignored until CSBI transitions high and then

low again.

The first 6 bits of the read balance status indicate if there

is sufficient gate drive for each of the 6 balancers. These

bits correspond to the right-most column in Table 1, but

can only be logic high for a given balancer following an

execute command involving that same balancer. If a bal-

ancer is not active, its Gate Drive OK bit will be logic low.

The7th,8th,and9thbitsinthereadbalancestatusindicate

that all 6 cells are not overvoltage, that the transformer

secondary is not overvoltage, and that the LTC3300-2 die

isnotovertemperature, respectively. These3bitscanonly

be logic high following an execute command involving at

least one balancer. The 10th, 11th, and 12th bits in the

read balance status are currently not used and will always

be logic zero. As an example, if balancers 1 and 4 are both

active with no voltage or temperature faults, the 12-bit

read balance status should be 100100111000.

Pause/Resume Balancing (via SPI Port)

The LTC3300-2 provides a simple means to interrupt bal-

ancing in progress (stack wide) and then restart without

having to rewrite the previous balance command to all

LTC3300-2 ICs in the stack. To pause balancing, simply

write an 8-bit Execute Balance Command with incorrect

parity. To resume balancing, simply write an Execute Bal-

ance Command with the correct parity to each different

address. This feature is useful if precision cell voltage

measurements want to be performed during balancing

with the stack “quiet.” Immediate pausing of balancing

in progress will occur for any 8-bit Command Byte with

incorrect parity.

The restart time is typically 2ms which is the same as the

delayedstarttimeafteranewordifferentbalancecommand

(t

). It is measured from the 8th rising SCKI edge

DLY_START

until the balancer turns on and is illustrated in G25 in the

Typical Performance Characteristics section.

33002f

27

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

External Sense Resistor Selection

LTC3300-2 compared to the true sense resistor voltage.

ThiserrorcanbecompensatedforbyselectingtheRvalue

to add back this same drop using the typical current value

of 20µA out of the LTC3300-2 current sense pins at the

comparator trip point.

The external current sense resistors for both primary

and secondary windings set the peak balancing current

according to the following formulas:

50mV

I_{PEAK_PRI}

R_{SENSE|PRIMARY}

=

Setting Appropriate Max On-Times

The primary and secondary winding volt-second clamps

are intended to be used as a current runaway protection

feature and not as a substitute means of current control

replacing the sense resistors. In order to not interfere with

50mV

=

R_{SENSE|SECONDARY}

I_{PEAK_SEC}

Balancer Synchronization

normalI

/I

operation,themaximumontimesmust

PEAK ZERO

be set longer than the time required to ramp to I

(or

PEAK

Duetothestackedconfigurationoftheindividualsynchro-

nous flyback power circuits and the interleaved nature of

the gate drivers, it is possible at higher balance currents

for adjacent and/or penadjacent balancers within a group

of six to sync up. The synchronization will typically be to

thehighestfrequencyofanyactiveindividualbalancerand

can result in a slightly lower balance current in the other

affected balancer(s). This error will typically be very small

provided that the individual cells are not significantly out

I

)fortheminimumcellvoltageseenintheapplication:

ZERO

t

> L ꢀ I

/V

ON(MAX)|PRIMARY

PRI PEAK_PRI CELL(MIN)

t

>L ꢀI

ꢀT/(SꢀV

)

ON(MAX)|SECONDARY PRI PEAK_SEC

CELL(MIN)

These can be further increased by 20% to account for

manufacturing tolerance in the transformer winding

inductance and by 10% to account for I

variation.

PEAK

External FET Selection

of balance voltage-wise and due to the matched I

/

PEAK

I

’s and matched power circuits. Balancer synchro-

In addition to being rated to handle the peak balancing

current, external NMOS transistors for both primary and

secondary windings must be rated with a drain-to-source

breakdown such that for the primary MOSFET:

ZERO

nization can be reduced by lowpass filtering the primary

and/or secondary current sense signals with a simple RC

network as shown in Figure 9. A good starting point for

the RC time constant is one-tenth of the on-time of the

associated switch (primary or secondary). In the case

V

_STACK+ V_DIODE

V_{DS(BREAKDOWN)|MIN}> V_CELL

+

T

of I

sensing, phase lag associated with the lowpass

PEAK

S

T

V_DIODE

⎛

⎝

⎞

⎟

⎠

filter will result in a slightly lower voltage seen by the

= V_CELL1+

+

⎜

T

and for the secondary MOSFET:

_{DS(BREAKDOWN)|MIN}> V_STACK+T V_CELL+ V_DIODE

LTC3300-2

G1P/GnP/G1S/GnS

V

(

)

20µA

R

I1P/InP/I1S/InS

= V_CELLS+T +TV

(

)

C

DIODE

R

SNS

–

V /Cn – 1/V /V

n = 2 TO 6

where S is the number of cells in the secondary winding

stack and 1:T is the transformer turns ratio from primary

to secondary. For example, if there are 12 Li-Ion cells in

the secondary stack and using a turns ratio of 1:2, the

primary FETs would have to be rated for greater than 4.2V

(1 + 6) + 0.5 = 29.9V and the secondary FETs would have

to be rated for greater than 4.2V (12 + 2) + 2V = 60.8V.

33002 F09

Figure 9. Using an RC Network to Filter

Current Sense Inputs to the LTC3300-2

33002f

28

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

Gooddesignpracticerecommendsincreasingthisvoltage

ratingbyatleast20%toaccountforhighervoltagespresent

due to leakage inductance ringing. See Table 7 for a list of

FETs that are recommended for use with the LTC3300-2.

Snubber Design

Careful attention must be paid to any transient ringing

seen at the drain voltages of the primary and secondary

windingFETsinapplication.Thepeakoftheringingshould

not approach and must not exceed the breakdown voltage

rating of the FETs chosen. Minimizing leakage inductance

present in the application and utilizing good board layout

techniques can help mitigate the amount of ringing. In

some applications, it may be necessary to place a series

resistor + capacitor snubber network in parallel with each

winding of the transformer. This network will typically

lower efficiency by a few percent, but will keep the FETs

in a safer operating region. Determining values for R and

C usually requires some trial-and-error optimization in the

application. For the transformers shown in Table 8, good

starting point values for the snubber network are 330Ω

in series with 100pF.

Table 7

PART NUMBER

SiR882DP

MANUFACTURER

Vishay

I

V

DS(MAX)

60A

100V

SiS892DN

Vishay

25A

70A

35A

60A

92A

100V

IPD70N10S3-12

IPB35N10S3L-26

RJK1051DPB

RJK1054DPB

Infineon

Renesas

Transformer Selection

The LTC3300-2 is optimized to work with simple 2-wind-

ing transformers with a primary winding inductance of

between 1 and 20 microhenries, a 1:2 turns ratio (primary

to secondary), and the secondary winding paralleling up

to 12 cells. If a larger number of cells in the secondary

stackisdesiredformoreefficientbalancing,atransformer

with a higher turns ratio can be selected. For example, a

1:10 transformer would be optimized for up to 60 cells in

the secondary stack. In this case the external FETs would

need to be rated for a higher voltage (see above). In all

cases the saturation current of the transformer must be

selected to be higher than the peak currents seen in the

application.

Boosted Gate Drive Component Selection

(BOOST = V

)

REG

+

The external boost capacitor connected from BOOST to

–

BOOST suppliesthegatedrivevoltagerequiredforturning

on the external NMOS connected to G6P. This capacitor

is charged through the external Schottky diode from C6

+

–

to BOOST when the NMOS is off (G6P = BOOST = C5).

When the NMOS is to be turned on, the BOOST driver

switches the lower plate of the capacitor from C5 to C6,

+

and the BOOST voltage common modes up to one cell

SeeTable8foralistoftransformersthatarerecommended

for use with the LTC3300-2.

voltage higher than C6. When the NMOS turns off again,

–

the BOOST driver switches the lower plate of the capaci-

tor back to C5 so that the boost capacitor is refreshed.

Table 8

TURNS

PRIMARY

A good rule of thumb is to make the value of the boost

capacitor 100 times that of the input capacitance of the

NMOSatG6P.Formostapplications,a0.1µF/10Vcapacitor

will suffice. The reverse breakdown of the Schottky diode

must only be greater than 6V. To prevent an excessive and

potentially damaging surge current from flowing in the

boostedgatedrivecomponentsduringinitialconnectionof

the battery voltages to the LTC3300-2, it is recommended

to place a 6.8Ω resistor in series with the Schottky diode

as shown in Figure 3. The surge current must be limited

to 1A to avoid potential damage.

PART NUMBER

MANUFACTURER RATIO* INDUCTANCE

I

SAT

750312504 (SMT) Würth Electronics

750312677 (THT) Würth Electronics

1:1

3.5µH

3.4µH

3µH

10A

MA5421-AL

CTX02-18892-R

XF0036-EP13S

LOO-3218

Coilcraft

Coiltronics

XFMRS Inc

BH Electronics

TOKO

3.4µH

DHCP-X79-1001

C128057LF

GCI

T10857-1

Inter Tech

*All transformers listed in the table are 8-pin components and can be

configured with turns ratios of 1:1, 1:2, 2:1, or 2:2.

33002f

29

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

Sizing the Cell Bypass Caps for Broken Connection

Protection

Protection from a broken connection to a cluster of sec-

ondary windings is provided local to each LTC3300-2 in

the stack by the secondary winding OVP function (via

WDT pin) described in the Operation section. However,

because of the interleaving of the transformer windings

up the stack, it is possible for a remote LTC3300-2 to still

act on the cell voltage seen locally by another LTC3300-2

at the point of the break which has shut itself off. For this

reason, each cluster of secondary windings must have

a dedicated connection to the stack separate from the

individual cell connection that it connects to.

If a single connection to the battery stack is lost while bal-

ancing,thedifferentialcellvoltagesseenbytheLTC3300-2

power circuit on each side of the break can increase or

decrease depending on whether charging or discharging

and where the actual break occurred. The worst-case

scenario is when the balancers on each side of the break

are both active and balancing in opposite directions. In

this scenario, the differential cell voltage will increase

rapidly on one side of the break and decrease rapidly

on the other. The cell overvoltage comparators working

in conjunction with appropriately-sized differential cell

bypass capacitors protect the LTC3300-2 and its asso-

ciated power components by shutting off all balancing

before any local differential cell voltage reaches its abso-

lute maximum rating. The comparator threshold (rising)

is 5V, and it takes 3µs to 6μs for the balancing to stop,

during which the bypass capacitor must prevent the dif-

ferential cell voltage from increasing past 6V. Therefore,

the minimum differential bypass capacitor value for full

broken connection protection is:

Using the LTC3300-2 with Fewer Than 6 Cells

To balance a series stack of N cells, the required number

ofLTC3300-2ICsisN/6roundeduptothenearestinteger.

SincetheLTC3300-2addressis5bits,themaximumNcan

be is 192 cells. Additionally, each LTC3300-2 in the stack

must interface to a minimum of 3 cells (must include C4,

C5, and C6). Thus, any stack of between 3 and 192 cells

can be balanced using an appropriate stack of LTC3300-2

ICs. Unused cell inputs (C1, C1 + C2, or C1 + C2 + C3) in a

–

given LTC3300-2 sub-stack should be shorted to V (see

Figure 10). However, in all configurations, the write data

remains at 16 bits. The LTC3300-2 will not act on the cell

balancing bits for the unused cell(s) but these bits are still

included in the CRC calculation.

I

_CHARGE+I_DISCHARGE•6µs

(

)

C_BYPASS(MIN)

=

6V –5V

are set nominally equal, then

DISCHARGE

If I

and I

CHARGE

approximately12µFofrealcapacitanceperampofbalance

current is required.

•

+

CELL n + 3

CELL n + 2

CELL n + 1

CELL n

CELL n + 2

CELL n + 1

CELL n

C6

CELL n + 4

CELL n + 3

CELL n + 2

CELL n + 1

CELL n

C6

C5

C4

C5

C4

C5

C4

+

LTC3300-2

C3

LTC3300-2

C3

LTC3300-2

C3

C2

C1

C2

C1

C2

C1

–

V

•

33002 F10

(10a) Sub-Stack Using Only 5 Cells (10b) Sub-Stack Using Only 4 Cells (10c) Sub-Stack Using Only 3 Cells

Figure 10. Battery Stack Connections for 5, 4 or 3 Cells

33002f

30

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

Supplementary Voltage Regulator Drive (>40mA)

The4.8VlinearvoltageregulatorinternaltotheLTC3300-2

powered from C6 as shown in Figure 11. The internal

regulator of the LTC3300-2 has very limited sink current

capability and will not fight the higher forced voltage.

is capable of providing 40mA at the V

pin. If additional

REG

current capability is required, the V

pin can be back-

REG

Fault Protection

driven by an external low cost 5V buck DC/DC regulator

Care should always be taken when using high energy

sources such as batteries. There are numerous ways

that systems can be misconfigured when considering

the assembly and service procedures that might affect a

battery system during its useful lifespan. Table 9 shows

the various situations that should be considered when

planning protection circuitry. The first four scenarios

are to be anticipated during production and appropriate

protection is included within the LTC3300-2 device itself.

C6

LTC3300-2

I

> 40mA

OUT

4.8V

LINEAR

VOLTAGE

REGULATOR

L

5V

V

IN

REG

SW

BUCK

DC/DC

R

FB2

C

IN

C

–

OUT

FB

V

GND

33002 F11

R

FB1

Figure 11. Adding External Buck DC/DC for >40mA V_REGDrive

Table 9. LTC3300-2 Failure Mechanism Effect Analysis

SCENARIO

EFFECT

DESIGN MITIGATION

–

Top cell (C6) input connection loss to LTC3300-2.

Power will come from highest connected cell

input or via data port fault current.

Clamp diodes at each pin to C6 and V (within IC)

provide alternate power path. Diode conduction at

data ports will impair communication with higher

potential units.

–

Bottom cell (V ) input connection loss to

LTC3300-2.

Power will come from lowest connected cell

input or via data port fault current.

Clamp diodes at each pin to C6 and V (within IC)

provide alternate power path. Diode conduction at

data ports will impair communication with higher

potential units.

–

Random cell (C1-C5) input connection loss to

LTC3300-2.

Power-up sequence at IC inputs/differential

input voltage overstress.

Clamp diodes at each pin to C6 and V (within IC)

provide alternate power path. Zener diodes across

each cell voltage input pair (within IC) limit stress.

–

Disconnection of a harness between a sub-stack

of battery cells and the LTC3300-2 (in a system of

stacked groups).

Loss of all supply connections to the IC.

Clamp diodes at each pin to C6 and V (within

IC) provide alternate power path if there are other

devices (which can supply power) connected to

the LTC3300-2.

Secondary winding connection loss to battery

stack.

Secondary winding power FET could be

subjected to a higher voltage as bypass

capacitor charges up.

WDT pin implements a secondary winding OVP

circuit which will detect overvoltage and terminate

balancing.

Shorted primary winding sense resistor.

Shorted secondary winding sense resistor.

Primary winding peak current cannot be

detected to shut off primary switch.

Maximum ON-time set by R

resistor will shut

TONP

off primary switch if peak current detect doesn’t

occur.

Secondary winding peak current cannot be

detected to shut off secondary switch.

Maximum ON-time set by R

shut off secondary switch if peak current detect

doesn’t occur.

resistor will

TONS

Data error (noise margin induced or otherwise)

occurs during a write command.

Incoming checksum will not agree with the

incoming message when read in by any

individual LTC3300-2 in the stack.

Since the CRC remainder will not be zero, the

LTC3300-2 will not execute the write command,

even if an execute command is given. All

balancers with nonzero remainders will be off.

Data error (noise margin induced or otherwise)

occurs during a read command.

Outgoing checksum (calculated by the

LTC3300-2) will not agree with the

outgoing message when read in by the host

microprocessor.

Since the CRC remainder (calculated by the

host) will not be zero, the data cannot be trusted.

All balancers will remain in the state of the last

previously successful write.

33002f

31

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

Internal Protection Diodes

–

14μA shows up at the V pin of the LTC3300-2. To the

extentthatthe14μAcurrentsmatchperfectlychip-to-chip

in a long series stack, the resultant stack terminal currents

in shutdown are as follows: 14μA out of the top of stack

node and 14μA into the bottom of stack node. All other

intermediate node currents are zero.

Each pin of the LTC3300-2 has protection diodes to help

prevent damage to the internal device structures caused

by external application of voltages beyond the supply rails

asshowninFigure12. Thediodesshownareconventional

silicon diodes with a forward breakdown voltage of 0.5V.

The unlabeled Zener diode structures have a reverse-

breakdown characteristic which initially breaks down at

9V then snaps back to a 7V clamping potential. The Zener

Differences Between LTC3300-2 and LTC3300-1

TheLTC3300-1employsanSPI-compatibleserialinterface

inwhicheachICinthestackcommunicatesbidirectionally

to the ICs of the same type above and below it via currents.

There is no limit to the stack height. Large common mode

voltage differences are handled by each LTC3300-1. The

microprocessor in the BMS system communicates ONLY

with the bottom IC in the stack and subsequently all of

the ICs use the same fixed internal address.

diodes labeled Z

are higher voltage devices with an

CLAMP

initial reverse breakdown of 25V snapping back to 22V.

The forward voltage drop of all Zeners is 0.5V.

The internal protection diodes shown in Figure 12 are

power devices which are intended to protect against

limited-power transient voltage excursions. Given that

these voltages exceed the absolute maximum ratings of

the LTC3300-2, any sustained operation at these voltage

levels will damage the IC.

TheLTC3300-2employsanSPI-compatibleserialinterface

in which each IC has a unique 5-bit pin-strapped address.

The microprocessor in the BMS system communicates

directly with every IC in the stack with common mode

voltage differences handled by digital isolators or opto-

couplers. Because of the 5-bit address, the stack height is

limited to 32 LTC3300-2 ICs or 192 cells (~800V).

Initial Battery Connection to LTC3300-2

In addition to the above-mentioned internal protection

diodes, there are additional lower voltage/lower current

diodes across each of the six differential cell inputs (not

shown in Figure 12) which protect the LTC3300-2 during

initial installation of the battery voltages in the application.

Thesediodeshaveabreakdownvoltageof5.3Vwith20kΩ

of series resistance and keep the differential cell voltages

below their absolute maximum rating during power-up

when the cell terminal currents are zero to tens of mi-

croamps. This allows the six batteries to be connected in

any random sequence without fear of an unconnected cell

input pin overvoltaging due to leakage currents acting on

its high impedance input. Differential cell-to-cell bypass

capacitors used in the application must be of the same

nominal value for full random sequence protection.

There are 5 pins which have a different assignment, all of

them serial interface related.

See Table 10 for a summary of differences between

LTC3300-1 and LTC3300-2

Table 10. LTC3300-1 vs LTC3300-2 Differences

LTC3300-1

LTC3300-2

High Side Current Mode SPI Pins

CSBO, SCKO,

SDOI

None

“Where Am I in The Stack?” Pins

SPI Address

V

, TOS

None*

MODE

10101 (Fixed)

A A A A A

4 3 2 1 0

(Pin Strapped)

32 × 6 = 192 Cells

14µA

Maximum Height of Battery Stack

Unlimited

23.5µA

–

GND (V ) Pin Current in

Analysis of Stack Terminal Currents in Shutdown

Shutdown/Suspend

AsgivenintheElectricalCharacteristicstable,thequiescent

current of the LTC3300-2 when not balancing is 14μA at

the C6 pin and zero at the C1 through C5 pins. All of this

*LTC3300-2 has V

= TOS = 1 fixed internally. Each IC in the stack

MODE

thinks it is both top-of-stack and bottom-of-stack. Consequently, opto-

couplers or digital isolators are needed to communicate between the µP

and each IC.

33002f

32

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

V

REG

48

LTC3300-2

WDT

SDO

20

19

18

17

16

42

A4

47

A3

46

SDI

A2

45

SCKI

CSBI

BOOST

A1

44

A0

43

+

BOOST

CTRL

RTONP

RTONS

40

15

14

13

–

BOOST

41

C6

39

G6P

38

G6S

I6S

1

2

I6P

37

C5

36

G5P

35

G5S

I5S

3

4

I5P

34

C4

33

Z

CLAMP

G4P

32

G4S

I4S

5

6

I4P

31

C3

30

G3P

29

G3S

I3S

7

8

I3P

28

C2

27

Z

CLAMP

G2P

26

G2S

I2S

9

I2P

25

10

C1

24

G1S

I1S

G1P

23

11

12

I1P

22

4Ω

–

EXPOSED PAD

49

V

33002 F12

21

Figure 12. Internal Protection Diodes

33002f

33

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

How to Calculate the CRC

desiredbalancecommandcallsforsimultaneouscharging

ofCell1andsynchronousdischargingofCell4. The12-bit

message (MSB first) will be 110000010000. Appending

4 zeros results in 1100000100000000 for the dividend.

The long division is shown in Figure 13a with a resultant

CRC of 1101. Note that the CRC bits in the write balance

command are inverted. Thus the correct 16-bit balance

command is 1100000100000010. Figure 13b shows the

same long division procedure being used to check the

CRC of data (command or status) read back from the

LTC3300-2. In this scenario, the remainder after the long

division must be zero (0000) for the data to be valid. Note

thatthereadbackCRCbitsmustbeinvertedinthedividend

before performing the division.

Onesimplemethodofcomputingann-bitCRCistoperform

arithmetic modulo-2 division of the n+1 bit characteristic

polynomial into the m bit message appended with n ze-

ros (m+n bits). Arithmetic modulo-2 division resembles

normal long division absent borrows and carries. At each

intermediate step of the long division, if the leading bit

of the dividend is a 1, a 1 is entered in the quotient and

the dividend is exclusive-ORed bitwise with the divisor.

If the leading bit of the dividend is a 0, a 0 is entered in

the quotient and the dividend is exclusive-ORed bitwise

with n zeros. This process is repeated m times. At the end

of the long division, the quotient is disregarded and the

n-bit remainder is the CRC. This will be more clear in the

example to follow.

An alternate method to calculate the CRC is shown in

Figure 14 in which the balance command bits are input to

a combinational logic circuit comprised solely of 2-input

exclusive-OR gates. This “brute force” implementation is

easily replicated in a few lines of C code.

For the CRC implementation in the LTC3300-2, n = 4 and

4

m = 12. The characteristic polynomial employed is x + x

4

3

2

1

0

+ 1, which is shorthand for 1x + 0x + 0x + 1x + 1x ,

resulting in 10011 for the divisor. The message is the first

12 bits of the balance command. Suppose for example the

READBACK = 1100000100000010

DIVIDEND = 1100000100001101

1 1 0 1 0 1 1 0 1 0 1 1

1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1

1 0 0 1 1

(a)

(b)

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 0

0 0 0 0 0

1 1 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 0

1 0 0 1 1

0 1 1 1 0

0 0 0 0 0

1 1 1 0 0

1 0 0 1 1

1 1 1 1 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 0

0 0 0 0 0

1 1 0 0 0

1 0 0 1 1

1 0 1 1 0

1 0 0 1 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

1 0 0 1 1

0 1 1 0 1

0 0 0 0 0

1 1 0 1 0

1 0 0 1 1

REMAINDER = 1 1 0 1 = 4-BIT CRC

REMAINDER = 0

33002 F13

0 0 1 0 = 4-BIT CRC INVERTED

Figure 13. (a) Long Division Example to Calculate CRC for Writes.

(b) Long Division Example to Check CRC for Reads

33002f

34

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

“Ø”

D6B

D5B

CRC [3]

D3B

D1B

D2A

D5A

CRC [2]

D3A

D1A

D4B

D2B

CRC [1]

D4A

D6A

“Ø”

CRC [0]

33002 F14

Figure 14. Combinational Logic Circuit Implementation of the CRC Calculator

Serial Communication Using the LTC6803 and LTC6804

The Typical Application shown on the back page of this

data sheet shows the serial communication connections

for a joint LTC3300-2/LTC6804-2 BMS. Each stacked

12-cell module contains two LTC3300-2 ICs and a single

LTC6804-2 monitor IC. . The LTC6804-2 in the module

is configured to provide an effective SPI port output at its

GPIO3, GPIO4, and GPIO5 pins which connect directly to

the low side communication pins (CSBI, SDI=SDO, SCKI)

of the lower LTC3300-2. The upper LTC3300-2 in each

module receives its serial communication via a digital

isolator from the lower LTC3300-2. Communication to

the lowermost LTC6804-2 and between monitor chips is

done via the LTC6820 and the isoSPI™ interface. In this

application, unused battery cells can be shorted from

the bottom of any module (i.e., outside the module, not

on the module board) as shown without any decrease in

monitor accuracy.

The LTC3300-2 is compatible with and convenient to

use with all LTC monitor chips, such as the LTC6803 and

LTC6804. Figure 17 in the Typical Applications section

shows the serial communications connections for a joint

LTC3300-2/LTC6803-2 BMS using a common micropro-

cessor SPI port. The SCKI, SDI, and SDO lines of the low-

ermost LTC3300-2 and LTC6803-2 are tied together. The

CSBI lines, however, must be separated to prevent talking

to both ICs at the same time. This is easily accomplished

by using one of the GPIO outputs from the LTC6803-2

to gate and invert the CSBI line to the LTC3300-2. In this

setup, communicating to the LTC6803-2 is no different

than without the LTC3300-2, as the GPIO1 output bit is

normallyhigh.To talktotheLTC3300-2,writtencommands

must be “bookended” with a GPIO1 negation write to the

LTC6803-2 prior to talking to the LTC3300-2 and with

a GPIO1 assertion write after talking to the LTC3300-2.

Communicationtoallnon-groundreferredLTC3300-2and

LTC6803-2 ICs is done through digital isolators.

33002f

35

For more information www.linear.com/LTC3300-2

LTC3300-2

APPLICATIONS INFORMATION

PCB Layout Considerations

2. The differential cell inputs (C6 to C5, C5 to C4, …, C1 to

exposed pad) should be bypassed with a 1µF or larger

capacitor as close to the LTC3300-2 as possible. This

is in addition to bulk capacitance present in the power

stages.

The LTC3300-2 is capable of operation with as much as

+

–

40V between BOOST and V . Care should be taken on

the PCB layout to maintain physical separation of traces

at different potentials. The pinout of the LTC3300-2 was

chosen to facilitate this physical separation. There is no

more than 8.4V between any two adjacent pins with the

–

3. Pin 21 (V ) is the ground sense for current sense resis-

tors connected to I1S-I6S and I1P (seven resistors).

Pin 21 should be Kelvined as well as possible with low

impedance traces to the ground side of these resistors

before connecting to the LTC3300-2 exposed pad.

–

exception of one instance (BOOST to BOOST ). In this

instance, the BOOST pin is pin-strapped in the applica-

–

tion to V or V

and does not need to route far from

REG

the LTC3300-2. The package body is used to separate

the highest voltage (e.g., 25.2V) from the lowest voltage

(0V). As an example, Figure 15 shows the DC voltage on

4. Cell inputs C1 to C5 are the ground sense for current

sense resistors connected to I2P-I6P (five resistors).

These pins should be Kelvined as well as possible

with low impedance traces to the ground side of these

resistors.

–

each pin with respect to V when six 4.2V battery cells

are connected to the LTC3300-2.

Additional “good practice” layout considerations are as

follows:

5. Thegroundsideofthemaximumon-timesettingresis-

tors connected to the RTONS and RTONP pins should

–

1. The V

pin should be bypassed to the exposed pad

be Kelvined to Pin 21 (V ) before connecting to the

REG

–

and to V , each with 1µF or larger capacitors as close

to the LTC3300-2 as possible.

LTC3300-2 exposed pad.

6. Trace lengths from the LTC3300-2 gate drive outputs

(G1S-G6S and G1P-G6P) and current sense inputs

(I1S-I6S and I1P-I6P) should be as short as possible.

7. The boosted gate drive components (diode and ca-

pacitor), if used, should form a tight loop close to the

+

–

LTC3300-2 C6, BOOST , and BOOST pins.

0V TO 4.8V G6S—PIN 1

0V I6S

0V TO 4.8V G5S

0V I5S

0V TO 4.8V G4S

0V I4S

0V TO 4.8V G3S

0V I3S

0V TO 4.8V G2S

0V I2S

0V TO 4.8V G1S

0V I1S

C5 21V

G5P 16.8V TO 25.2V

I5P 16.8V

C4 16.8V

G4P 12.6V TO 21V

I4P 12.6V

C3 12.6V

G3P 8.4V TO 16.8V

I3P 8.4V

C2 8.4V

G2P 4.2V TO 12.6V

I2P 4.2V

8. For the external power components (transformer, FETs

and current sense resistors), it is important to keep the

area encircled by the two high speed current switching

loops (primary and secondary) as tight as possible.

This is greatly aided by having two additional bypass

capacitors local to the power circuit: one differential

cell to cell and one from the transformer secondary to

LTC3300-2

(EXPOSED PAD = 0V)

–

local V .

A representative layout incorporating all of these recom-

mendations is implemented on the DC2064A demo board

for the LTC3300-1 companion product (with further ex-

planation in its accompanying demo board manual). To

accommodate the LTC3300-2, only minor modifications

to Pins 43 to 47 connections need to be made. PCB layout

files (.GRB) are also available from the factory.

33002 F15

Figure 15. Typical Pin Voltages for Six 4.2V Cells

33002f

36

For more information www.linear.com/LTC3300-2

LTC3300-2

TYPICAL APPLICATIONS

6.8Ω

0.1µF

•

–

+

BOOST BOOST

1:1

C6

•

+

CELL 6

10µH

10µF

•

G6P

I6P

25mΩ

•

1:1

C5

+

CELL 5

10µH

10µF

•

G5P

I5P

25mΩ

C4

C3

C2

•

1:1

LTC3300-2

•

+

CELL 2

10µH

A4

A3

A2

A1

10µF

•

G2P

I2P

A0

SERIAL

COMMUNICATION

SCKI

SDI

PINS

25mΩ

•

1:1

C1

SDO

+

CELL 1

10µH

WDT

ISOLATED

+

12V LEAD ACID

AUXILIARY

CELL

10µF

•

G1P

I1P

25mΩ

G1S-G6S

I1S-I6S

NC

V

REG

–

BOOST

V

ISOLATION

BOUNDARY

CTRL

RTONP RTONS

33002 F16

10µF

28k

41.2k

Figure 16. LTC3300-2 Unidirectional Discharge-Only Balancing Application to Charge an Isolated Auxiliary Cell

33002f

37

For more information www.linear.com/LTC3300-2

LTC3300-2

TYPICAL APPLICATIONS

TOP OF BATTERY STACK

+

C6

C5

C4

C3

C2

C1

CELL 24

C12

C11

C10

C9

C8

C7

+

CELL 23

LTC3300-2

DIGITAL

ISOLATOR

ADDRESS =

+

CELL 22

00011

CSBI

SCKI

SDI

+

V

REG

CELL 21

C

–

VREG4

SDO

V

+

CELL 20

LTC6803-2

ADDRESS = 0001

+

CELL 19

C6

+

CELL 18

C6

C5

C4

C3

C2

C1

GPIO2

GPIO1

C5

C4

C3

C2

C1

NC

+

CELL 17

DIGITAL

ISOLATOR

LTC3300-2

ADDRESS =

00010

DIGITAL

ISOLATOR

+

CELL 16

CSBI

SCKI

SDI

CSBI

SCKI

SDI

V

REG

+

V

REG

CELL 15

C

SDO

VREG6

C

VREG3

–

+

SDO

V

CELL 14

+

CELL 13

+

CELL 12

C6

C5

C4

C3

C2

C1

C12

C11

C10

C9

C8

C7

+

CELL 11

LTC3300-2

ADDRESS =

00001

DIGITAL

ISOLATOR

+

CELL 10

CSBI

SCKI

SDI

+

V

REG

CELL 9

C

–

VREG2

SDO

V

+

CELL 8

LTC6803-2

ADDRESS = 0000

+

CELL 7

C6

+

CELL 6

C6

C5

C4

C3

C2

C1

GPIO2

GPIO1

NC

C5

C4

C3

C2

C1

V

+

DIGITAL

ISOLATOR

CELL 5

3V

LTC3300-2

ADDRESS =

00000

V

REG1

V

REG5

OR

+

V1

V2

+

CELL 4

CSBI

SCKI

SDI

CS

MPU

CLK

CSBI

SCKI

SDI

V

REG5

REG1

REG

+

CELL 3

C

VREG5

SDO

VREG1

–

+

SDO

V

CELL 2

MOSI

+

MOSO

CELL 1

–

V1

–

V2

33002 F17

Figure 17. LTC3300-2/LTC6803-2 Battery and Serial Communication Connections for a 24-Cell Stack

33002f

38

For more information www.linear.com/LTC3300-2

LTC3300-2

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ704 Rev C)

0.70 0.05

5.ꢀ5 0.05

5.50 REF

6.ꢀ0 0.05 7.50 0.05

(4 SIDES)

5.ꢀ5 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.ꢀꢀ5

TYP

7.00 0.ꢀ0

(4 SIDES)

R = 0.ꢀ0

TYP

47 48

0.40 0.ꢀ0

PIN ꢀ TOP MARK

(SEE NOTE 6)

ꢀ

2

PIN ꢀ

CHAMFER

C = 0.35

5.ꢀ5 0.ꢀ0

5.50 REF

(4-SIDES)

5.ꢀ5 0.ꢀ0

(UK48) QFN 0406 REV C

0.200 REF

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE

33002f

39

For more information www.linear.com/LTC3300-2

LTC3300-2

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LXE Package

48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)

(Reference LTC DWG #05-08-1832 Rev C)

7.15 – 7.25

5.50 REF

48

37

36

1

0.50 BSC

C0.30

5.50 REF

7.15 – 7.25

0.20 – 0.30

3.60 0.05

e 3

12

13

25

PACKAGE OUTLINE

24

COMPONENT

PIN “A1”

1.30 MIN

TRAY PIN 1

BEVEL

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PACKAGE IN TRAY LOADING ORIENTATION

9.00 BSC

7.00 BSC

3.60 0.10

48

37

48

SEE NOTE: 3

1

36

1

C0.30

9.00 BSC

7.00 BSC

3.60 0.10

A

25

12

25

C0.30 – 0.50

24

13

24

BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)

1.60

11° – 13°

1.35 – 1.45 MAX

R0.08 – 0.20

GAUGE PLANE

0.25

0° – 7°

LXE48 LQFP 0113 REV C

11° – 13°

1.00 REF

0.50

BSC

0.09 – 0.20

0.17 – 0.27

SIDE VIEW

0.05 – 0.15

0.45 – 0.75

SECTION A – A

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

4. DRAWING IS NOT TO SCALE

2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

33002f

40

For more information www.linear.com/LTC3300-2

LTC3300-2

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

12/13 Add new bullet Integrates Seamlessly with the LTC680x Family of Multicell Battery Stack Monitors

Change part number XF0036-EP135 to XF0036-EP13S

1

29

33002f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

41

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC3300-2

LTC3300-2

TYPICAL APPLICATION

LTC3300-2/LTC6804-2 Serial Communication Connections

DATA

12-CELL

MODULE 2

LTC3300-2

ADDRESS =

00011

4

DIGITAL

ISOLATOR

LTC6804-2

9 CELLS

LTC3300-2

ADDRESS =

0001

ADDRESS =

00010

SCKI

GPIO5

SDI

GPIO4

ISO IN

SDO

CSBI

GPIO3

12-CELL

MODULE 1

LTC3300-2

ADDRESS =

00001

4

DIGITAL

ISOLATOR

LTC6804-2

12 CELLS

LTC3300-2

ADDRESS =

00000

SCKI

ADDRESS =

0000

LTC6820

isoSPI

GPIO5

GPIO4

4

SDI

ISO SPI

ISO IN

SDO

CSBI

GPIO3

33002 TA02

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3300-1

High Efficiency Bidirectional Mulitcell Battery Balancer Allows Serial Ports of Multiple Devices to Be Daisy-Chained without

Opto-Couplers or Isolators

LTC6801

Independent Multicell Battery Stack Monitor

Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or

Overvoltage, Companion to LTC6802, LTC6803 and LTC6804

LTC6802-1/LTC6802-2 Multicell Battery Stack Monitors

Measures Up to 12 Series-Connected Battery Cells, 1st Generation:

Superseded by the LTC6803 and LTC6804 for New Designs

LTC6803-1/LTC6803-3 Multicell Battery Stack Monitors

LTC6803-2/LTC6803-4

Measures Up to 12 Series-Connected Battery Cells, 2nd Generation:

Functionally Enhanced and Pin Compatible to the LTC6802

LTC6804-1/LTC6804-2 Multicell Battery Monitors

Measures Up to 12 Series-Connected Battery Cells, 3rd Generation:

Higher Precision Than LTC6803 and Built-In isoSPI Interface

LTC6820

isoSPI Isolated Communications Interface

Provides an Isolated Interface for SPI Communication Up to 100m

Using a Twisted Pair, Companion to the LTC6804

33002f

LT 0813 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

42

For more information www.linear.com/LTC3300-2

●

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3300-2

LINEAR TECHNOLOGY CORPORATION 2013


型号：	LTC3300-2
厂家：	Linear
描述：	Addressable High Efficiency Bidirectional Multicell Battery Balancer 电池
文件：	总42页 (文件大小：473K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3300-2 [Linear]

相关型号：

LTC3300-2_15

LTC3307A

LTC3307B

LTC3308A

LTC3308B

LTC3309A

LTC3309B

LTC3310

LTC3310S

LTC3310S-1

LTC3311

LTC3311HV