LTC2377CMS-16#TRPBF [Linear]
LTC2377-16 - 16-Bit, 500ksps, Low Power SAR ADC with 97dB SNR; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC2377CMS-16#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC2377-16 - 16-Bit, 500ksps, Low Power SAR ADC with 97dB SNR; Package: MSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总26页 (文件大小：735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2377-16
16-Bit, 500ksps, Low Power
SAR ADC with 97dB SNR
FEATURES
DESCRIPTION
The LTC®2377-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2377-16 has a
n
500ksps Throughput Rate
n
0ꢀ5ꢁSꢂ INꢁ ꢃ(aꢄx
n
Guaranteed 16-ꢂit No (issing Codes
n
ꢁow Power: 6ꢀ8mW at 500ksps, 6ꢀ8µW at 500sps
97dꢂ SNR ꢃTypx at f = 2kHz
–123dꢂ THD ꢃTypx at f = 2kHz
±V fully differential input range with V ranging from
REF REF
n
2.5V to 5.1V. The LTC2377-16 consumes only 6.8mW and
achieves ±±.5LSꢀ ꢁIL maximum, no missing codes at 16
bits with 97dꢀ SIR.
IN
n
n
n
n
n
n
n
n
n
n
n
IN
Digital Gain Compression ꢃDGCx
Guaranteed Operation to 125°C
2.5V Supply
The LTC2377-16 has a high speed SPꢁ-compatible se-
rial interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 5±±ksps
throughput with no cycle latency makes the LTC2377-16
ideally suited for a wide variety of high speed applications.
Aninternaloscillatorsetstheconversiontime,easingexter-
nal timing considerations. The LTC2377-16 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
Fully Differential ꢁnput Range ±V
REF
V
ꢁnput Range from 2.5V to 5.1V
REF
Io Pipeline Delay, Io Cycle Latency
1.8V to 5V ꢁ/O Voltages
SPꢁ-Compatible Serial ꢁ/O with Daisy-Chain Mode
ꢁnternal Conversion Clock
16-Lead MSOP and 4mm × 3mm DFI Packages
The LTC2377-16 features a unique digital gain compres-
sion(DGC)function,whicheliminatesthedriveramplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
APPLICATIONS
n
Medical ꢁmaging
n
High Speed Data Acquisition
n
Portable or Compact ꢁnstrumentation
function that maps zero-scale code from ±V to ±.1 • V
REF
n
ꢁndustrial Process Control
and full-scale code from V
to ±.9 • V . For a typical
REF
REF
n
Low Power ꢀattery-Operated ꢁnstrumentation
reference voltage of 5V, the full-scale input range is now
±.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
n
ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
32k Point FFT fS = 500ksps, fIN = 2kHz
2.5V 1.8V TO 5V
0
SNR = 97.2dB
–20
–40
THD = –123dB
SINAD = 97.2dB
SFDR = 126dB
10µF
0.1µF
V
OV
DD
CHAIN
RDL/SDI
SDO
DD
6800pF
3300pF
6800pF
V
V
REF
20Ω
20Ω
–60
+
–
IN
+
–
–80
0V
LTC2377-16
SCK
REF
BUSY
CNV
REF/DGC
–100
–120
–140
–160
–180
IN
SAMPLE CLOCK
0V
V
REF
GND
REF
237716 TA01
2.5V TO 5.1V
47µF
(X5R, 0805 SIZE)
0
50
100
150
200
250
FREQUENCY (kHz)
237716 TA02
237716fa
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For more information www.linear.com/LTC2377-16
LTC2377-16
ABSOLUTE MAXIMUM RATINGS
ꢃNotes 1, 2x
Supply Voltage (V )...............................................2.8V
Digital Output Voltage
DD
Supply Voltage (OV )................................................6V
(Iote 3)........................... (GID –±.3V) to (OV + ±.3V)
DD
DD
Reference ꢁnput (REF).................................................6V
Power Dissipation.............................................. 5±±mW
Operating Temperature Range
LTC2377C ................................................ ±°C to 7±°C
LTC2377ꢁ .............................................–4±°C to 85°C
LTC2377H.......................................... –4±°C to 125°C
Storage Temperature Range .................. –65°C to 15±°C
Analog ꢁnput Voltage (Iote 3)
+
–
ꢁI , ꢁI ......................... (GID –±.3V) to (REF + ±.3V)
REF/DGC ꢁnput (Iote 3).... (GID –±.3V) to (REF + ±.3V)
Digital ꢁnput Voltage
(Iote 3)........................... (GID –±.3V) to (OV + ±.3V)
DD
PIN CONFIGURATION
TOP VIEW
CHAIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OV
TOP VIEW
V
DD
DD
CHAIN 1
16 GND
GND
SDO
V
2
15 OV
DD
DD
+
GND 3
14 SDO
13 SCK
17
GND
IN
SCK
+
–
IN
IN
4
5
–
IN
RDL/SDI
BUSY
GND
12 RDL/SDI
11 BUSY
10 GND
GND
REF
GND 6
REF 7
REF/DGC 8
9
CNV
REF/DGC
CNV
MS PACKAGE
16-LEAD PLASTIC MSOP
DE PACKAGE
T
= 15±°C, θ = 11±°C/W
16-LEAD (4mm × 3mm) PLASTIC DFN
JMAX
JA
T
= 15±°C, θ = 4±°C/W
JA
JMAX
EXPOSED PAD (PꢁI 17) ꢁS GID, MUST ꢀE SOLDERED TO PCꢀ
http://wwwꢀlinearꢀcom/product/ꢁTC2377-16#orderinfo
ORDER INFORMATION
ꢁEAD FREE FINISH
LTC2377CMS-16#PꢀF
LTC2377ꢁMS-16#PꢀF
LTC2377HMS-16#PꢀF
LTC2377CDE-16#PꢀF
LTC2377ꢁDE-16#PꢀF
TAPE AND REEꢁ
PART (ARKING*
PACKAGE DESCRIPTION
16-Lead Plastic MSOP
16-Lead Plastic MSOP
16-Lead Plastic MSOP
TE(PERATURE RANGE
±°C to 7±°C
LTC2377CMS-16#TRPꢀF 237716
LTC2377ꢁMS-16#TRPꢀF 237716
LTC2377HMS-16#TRPꢀF 237716
LTC2377CDE-16#TRPꢀF 23776
–4±°C to 85°C
–4±°C to 125°C
±°C to 7±°C
16-Lead (4mm × 3mm) Plastic DFI
16-Lead (4mm × 3mm) Plastic DFI
LTC2377ꢁDE-16#TRPꢀF
23776
–4±°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 5±± unit reels through
designated sales channels with #TRMPꢀF suffix.
237716fa
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For more information www.linear.com/LTC2377-16
LTC2377-16
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ ꢃNote 4x
SY(ꢂOꢁ
V +
PARA(ETER
CONDITIONS
(Iote 5)
(IN
–±.±5
–±.±5
TYP
(AX
UNITS
+
l
l
l
l
Absolute ꢁnput Range (ꢁI )
V
V
+ ±.±5
V
V
V
V
ꢁI
REF
REF
–
V
–
Absolute ꢁnput Range (ꢁI )
(Iote 5)
+ ±.±5
ꢁI
V + – V – ꢁnput Differential Voltage Range
V
ꢁI
= V + – V –
–V
+V
REF
ꢁI
ꢁI
ꢁI
ꢁI
REF
V
CM
Common-Mode ꢁnput Range
V
/2–
V /2
REF
V
/2+
REF
REF
±.1
±.1
±1
l
ꢁ
Analog ꢁnput Leakage Current
Analog ꢁnput Capacitance
µA
ꢁI
C
Sample Mode
Hold Mode
45
5
pF
pF
ꢁI
CMRR
ꢁnput Common Mode Rejection Ratio
f
ꢁI
= 25±kHz
86
dꢀ
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ ꢃNote 4x
SY(ꢂOꢁ PARA(ETER
CONDITIONS
(IN
16
TYP
(AX
UNITS
ꢀits
l
l
Resolution
Io Missing Codes
16
ꢀits
Transition Ioise
±.15
±±.2
±±.1
±
LSꢀ
RMS
l
l
l
ꢁIL
ꢁntegral Linearity Error
Differential Linearity Error
ꢀipolar Zero-Scale Error
ꢀipolar Zero-Scale Error Drift
ꢀipolar Full-Scale Error
ꢀipolar Full-Scale Error Drift
(Iote 6)
(Iote 7)
(Iote 7)
–±.5
–±.5
–4
±.5
±.5
4
LSꢀ
DIL
ꢀZE
LSꢀ
LSꢀ
1
mLSꢀ/°C
LSꢀ
l
FSE
–13
±2
13
±±.±5
ppm/°C
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dꢂFSꢀ ꢃNotes 4, 8x
SY(ꢂOꢁ PARA(ETER
CONDITIONS
(IN
94.6
94.5
TYP
97
(AX
UNITS
dꢀ
l
l
SꢁIAD
SIR
Signal-to-(Ioise + Distortion) Ratio
f
ꢁI
f
ꢁI
= 2kHz, V = 5V
REF
= 2kHz, V = 5V, (H-Grade)
97
dꢀ
REF
l
l
l
Signal-to-Ioise Ratio
f
ꢁI
f
ꢁI
f
ꢁI
= 2kHz, V = 5V
95.3
94.5
92.1
97
96.4
95
dꢀ
dꢀ
dꢀ
REF
= 2kHz, V = 5V, REF/DGC = GID
REF
= 2kHz, V = 2.5V
REF
l
l
l
f
ꢁI
f
ꢁI
f
ꢁI
= 2kHz, V = 5V, (H-Grade)
95.2
94.3
91.8
97
96.4
95
dꢀ
dꢀ
dꢀ
REF
= 2kHz, V = 5V, REF/DGC = GID, (H-Grade)
REF
= 2kHz, V = 2.5V, (H-Grade)
REF
l
l
l
THD
Total Harmonic Distortion
f
ꢁI
f
ꢁI
f
ꢁI
= 2kHz, V = 5V
–123
–125
–122
–1±3
–1±1
–1±3
dꢀ
dꢀ
dꢀ
REF
= 2kHz, V = 5V, REF/DGC = GID
REF
= 2kHz, V = 2.5V
REF
l
SFDR
Spurious Free Dynamic Range
–3dꢀ ꢁnput ꢀandwidth
Aperture Delay
f
= 2kHz, V = 5V
1±4
124
34
dꢀ
MHz
ps
ꢁI
REF
5±±
4
Aperture Jitter
ps
Transient Response
Full-Scale Step
1.46
µs
237716fa
3
For more information www.linear.com/LTC2377-16
LTC2377-16
REFERENCE INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°Cꢀ ꢃNote 4x
SY(ꢂOꢁ
PARA(ETER
CONDITIONS
(Iote 5)
(IN
TYP
(AX
5.1
UNITS
l
l
l
l
V
Reference Voltage
2.5
V
mA
V
REF
REF
ꢁ
Reference ꢁnput Current
High Level ꢁnput Voltage REF/DGC Pin
Low Level ꢁnput Voltage REF/DGC Pin
(Iote 9)
±.32
±.4
V
ꢁHDGC
V
ꢁLDGC
±.8V
REF
±.2V
V
REF
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°Cꢀ ꢃNote 4x
SY(ꢂOꢁ PARA(ETER
CONDITIONS
(IN
TYP
(AX
UNITS
V
l
l
l
V
V
High Level ꢁnput Voltage
Low Level ꢁnput Voltage
Digital ꢁnput Current
±.8 • OV
ꢁH
ꢁL
DD
±.2 • OV
1±
V
DD
ꢁ
V
= ±V to OV
DD
–1±
µA
pF
ꢁI
ꢁI
C
V
V
Digital ꢁnput Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
ꢁI
l
l
l
ꢁ = –5±±µA
O
OV – ±.2
DD
V
OH
OL
ꢁ = 5±±µA
O
±.2
1±
V
ꢁ
ꢁ
ꢁ
V
V
V
= ±V to OV
DD
–1±
µA
mA
mA
OZ
OUT
OUT
OUT
= ±V
= OV
–1±
1±
SOURCE
SꢁIK
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°Cꢀ ꢃNote 4x
SY(ꢂOꢁ
PARA(ETER
Supply Voltage
Supply Voltage
CONDITIONS
(IN
2.375
1.71
TYP
(AX
2.625
5.25
3.2
UNITS
l
l
l
V
DD
2.5
V
V
OV
DD
ꢁ
ꢁ
ꢁ
ꢁ
Supply Current
Supply Current
Power Down Mode
Power Down Mode
5±±ksps Sample Rate
2.7
±.1
±.9
±.9
mA
mA
µA
VDD
OVDD
PD
5±±ksps Sample Rate (C = 2±pF)
L
+ ꢁ
+ ꢁ
l
l
Conversion Done (ꢁ
Conversion Done (ꢁ
+ ꢁ )
REF
9±
14±
VDD
VDD
OVDD
OVDD
REF
+ ꢁ , H-Grade)
µA
PD
P
Power Dissipation
Power Down Mode
Power Down Mode
5±±ksps Sample Rate
6.75
2.25
2.25
8
225
315
mW
µW
µW
D
Conversion Done (ꢁ
Conversion Done (ꢁ
+ ꢁ
+ ꢁ
+ ꢁ )
REF
REF
VDD
VDD
OVDD
OVDD
+ ꢁ , H-Grade)
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ ꢃNote 4x
SY(ꢂOꢁ
PARA(ETER
CONDITIONS
(IN
TYP
(AX
5±±
1.5
UNITS
ksps
µs
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
SMPL
COIV
ACQ
1
Acquisition Time
t
= t
– t (Iote 1±)
HOLD
1.46
µs
ACQ
CYC
Maximum Time ꢀetween Acquisitions
Time ꢀetween Conversions
CIV High Time
54±
13
ns
HOLD
CYC
2
µs
2±
ns
CIVH
ꢀUSYLH
CIVL
QUꢁET
C = 2±pF
L
ns
CIV↑ to ꢀUSY Delay
Minimum Low Time for CIV
SCK Quiet Time from CIV↑
(Iote 11)
(Iote 1±)
2±
2±
ns
ns
237716fa
4
For more information www.linear.com/LTC2377-16
LTC2377-16
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ ꢃNote 4x
SY(ꢂOꢁ
PARA(ETER
CONDITIONS
(IN
1±
4
TYP
(AX
UNITS
ns
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
SCK Period
(Iotes 11, 12)
SCK
SCK High Time
ns
SCKH
SCK Low Time
4
ns
SCKL
(Iote 11)
(Iote 11)
4
ns
SDꢁ Setup Time From SCK↑
SDꢁ Hold Time From SCK↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK↑
SDO Data Remains Valid Delay from SCK↑
SDO Data Valid Delay from ꢀUSY↓
ꢀus Enable Time After RDL↓
ꢀus Relinquish Time After RDL↑
SSDꢁSCK
HSDꢁSCK
SCKCH
DSDO
HSDO
DSDOꢀUSYL
EI
1
ns
t
= t
+ t (Iote 11)
DSDO
13.5
ns
SCKCH
SSDꢁSCK
C = 2±pF (Iote 11)
L
9.5
ns
C = 2±pF (Iote 1±)
L
1
ns
C = 2±pF (Iote 1±)
L
5
ns
(Iote 11)
(Iote 11)
16
13
ns
ns
DꢁS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 7: ꢀipolar zero-scale error is the offset voltage measured from
–±.5LSꢀ when the output code flickers between ±±±± ±±±± ±±±± ±±±± and
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 2: All voltage values are with respect to ground.
Note 8: All specifications in dꢀ are referred to a full-scale ±5V input with a
5V reference voltage.
Note 3: When these pin voltages are taken below ground or above REFor
OV , they will be clamped by internal diodes. This product can handle
DD
input currents up to 1±±mA below ground or above REFor OV without
latch-up.
Note 9: f
= 5±±kHz, ꢁ varies proportionately with sample rate.
SMPL REF
DD
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V
Note 4: V = 2.5V, OV = 2.5V, REF = 5V, V = 2.5V, f
= 5±±kHz,
DD
DD
CM
SMPL
DD
DD
REF/DGC = V
.
REF
and OV = 5.25V.
DD
Note 5: Recommended operating conditions.
Note 12: t
of 1±ns maximum allows a shift clock frequency up to
SCK
Note 6: ꢁntegral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
1±±MHz for rising capture.
0.8*OV
DD
t
WIDTH
0.2*OV
DD
50%
50%
t
t
DELAY
DELAY
237716 F01
0.8*OV
0.8*OV
0.2*OV
DD
DD
DD
0.2*OV
DD
Figure 1ꢀ Voltage ꢁevels for Timing Specifications
237716fa
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For more information www.linear.com/LTC2377-16
LTC2377-16
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 2ꢀ5V, OVDD = 2ꢀ5V, VC( = 2ꢀ5V,
REF = 5V, fS(Pꢁ = 500ksps, unless otherwise notedꢀ
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
1.0
0.8
0.5
0.4
140000
120000
100000
80000
60000
40000
20000
0
σ = 0.15
0.6
0.3
0.4
0.2
0.2
0.1
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
–32768
–16384
0
16384
32768
–32768
–16384
0
16384
32768
–2
–1
0
1
2
OUTPUT CODE
OUTPUT CODE
CODE
237716 G01
237716 G02
237716 G03
THD, Harmonics
32k Point FFT fS = 500ksps,
fIN = 2kHz
vs Input Frequency
SNR, SINAD vs Input Frequency
0
–20
98.0
97.5
97.0
96.5
96.0
95.5
95.0
94.5
94.0
93.5
93.0
–80
–90
SNR = 97.2dB
THD = –123dB
SINAD = 97.2dB
SFDR = 126dB
THD
2ND
3RD
SNR
–40
–60
–100
–110
–120
–130
–140
SINAD
–80
–100
–120
–140
–160
–180
0
50
100
150
200
250
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
237716 G05
237716 G06
237716 G04
SNR, SINAD vs Input level,
fIN = 2kHz
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
98.0
98.0
97.5
97.0
96.5
96.0
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
97.5
97.0
SNR
96.5
96.0
SNR
THD
3RD
SINAD
SINAD
95.5
95.0
2ND
94.5
94.0
2.5
3.0
3.5
4.0
4.5
5.0
–40
–30
–20
–10
0
2.5
3.0
3.5
4.0
4.5
5.0
REFERENCE VOLTAGE (V)
INPUT LEVEL (dB)
REFERENCE VOLTAGE (V)
237716 G08
237716 G07
237716 G09
237716fa
6
For more information www.linear.com/LTC2377-16
LTC2377-16
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 2ꢀ5V, OVDD = 2ꢀ5V, VC( = 2ꢀ5V,
REF = 5V, fS(Pꢁ = 500ksps, unless otherwise notedꢀ
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
INꢁ/DNꢁ vs Temperature
98.0
97.5
97.0
96.5
96.0
–110
–115
–120
–125
–130
–135
–140
0.5
0.3
SNR
MAX INL
MAX DNL
THD
SINAD
0.1
3RD
MIN DNL
–0.1
–0.3
–0.5
MIN INL
2ND
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–50 –25 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
237716 G10
237716 G11
237716 G12
Supply Current vs Temperature
Full-Scale Error vs Temperature
Offset Error vs Temperature
1.0
0.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.0
1.5
I
VDD
–FS
1.0
0.5
0.0
0.0
–0.5
–1.0
–1.5
–2.0
–0.5
I
REF
+FS
I
OVDD
–1.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
237716 G14
237716 G15
237716 G13
Reference Current
vs Reference Voltage
Shutdown Current vs Temperature
C(RR vs Input Frequency
45
40
35
30
25
20
15
10
5
100
95
90
85
80
75
70
0.4
0.35
0.3
I
+ I
+ I
VDD OVDD REF
0.25
0.2
0.15
0.1
0.05
0
0
2.5
3.0
3.5
4.0
4.5
5.0
0
50
100
150
250
–55 –35 –15
5
25 45 65 85 105 125
REFERENCE VOLTAGE (V)
FREQUENCY (kHz)
TEMPERATURE (°C)
237716 G16
237716 G17
237716 G18
237716fa
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For more information www.linear.com/LTC2377-16
LTC2377-16
PIN FUNCTIONS
CHAIN ꢃPin 1x: Chain Mode Selector Pin. When low, the
LTC2377-16 operates in normal mode and the RDL/SDꢁ
input pin functions to enable or disable SDO. When high,
the LTC2377-16 operates in chain mode and the RDL/SDꢁ
pin functions as SDꢁ, the daisy-chain serial data input.
ꢂUSY ꢃPin 11x: ꢀUSY ꢁndicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by ±V .
DD
RDꢁ/SDI ꢃPin 12x: When CHAꢁI is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAꢁI is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy-chain is input. Logic levels are
Logic levels are determined by ±V .
DD
V
ꢃPin 2x: 2.5V Power Supply. The range of V is
DD
DD
2.375Vto2.625V. ꢀypassV toGIDwitha1±µFceramic
DD
capacitor.
determined by ±V .
DD
GND ꢃPins 3, 6, 10 and 16x: Ground.
SCKꢃPin13x:SerialDataClockꢁnput.WhenSDOisenabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSꢀ
+
–
IN , IN ꢃPins 4, 5x: Positive and Iegative Differential
Analog ꢁnputs.
first. Logic levels are determined by ±V .
DD
REF ꢃPin 7x: Reference ꢁnput. The range of REF is 2.5V
to 5.1V. This pin is referred to the GID pin and should be
decoupledcloselytothepinwitha47µFceramiccapacitor
(X5R, ±8±5 size).
SDOꢃPin14x:SerialDataOutput. Theconversionresultor
daisy-chain data is output on this pin on each rising edge
of SCK MSꢀ first. The output data is in 2’s complement
format. Logic levels are determined by ±V .
DD
REF/DGCꢃPin8x:WhentiedtoREF,digitalgaincompression
OV ꢃPin 15x: ꢁ/O ꢁnterface Digital Power. The range of
DD
isdisabledandtheLTC2377-16definesfull-scaleaccording
OV is 1.71V to 5.25V. This supply is nominally set to
DD
to the ±V analog input range. When tied to GID, digital
REF
the same supply as the host interface (1.8V, 2.5V, 3.3V,
gain compression is enabled and the LTC2377-16 defines
or 5V). ꢀypass OV to GID with a ±.1µF capacitor.
DD
full-scale with inputs that swing between 1±% and 9±%
of the ±V analog input range.
GND ꢃEꢄposed Pad Pin 17 – DFN Package Onlyx: Ground.
Exposedpadmustbesoldereddirectlytothegroundplane.
REF
CNV ꢃPin 9x: Convert ꢁnput. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by ±V .
DD
FUNCTIONAL BLOCK DIAGRAM
V
= 2.5V
DD
OV = 1.8V to 5V
DD
REF = 5V
LTC2377-16
CHAIN
SDO
RDL/SDI
SCK
+
+
IN
SPI
PORT
16-BIT SAMPLING ADC
–
–
IN
CNV
BUSY
REF/DGC
CONTROL LOGIC
GND
237716 BD01
237716fa
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For more information www.linear.com/LTC2377-16
LTC2377-16
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0
CNV
CONVERT
POWER-DOWN
BUSY
SCK
HOLD
ACQUIRE
D15 D14 D13 D2 D1 D0
SDO
237716 TD01
237716fa
9
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
OVERVIEW
TRANSFER FUNCTION
The LTC2377-16 is a low noise, low power, high speed
16-ꢀit successive approximation register (SAR) ADC.
Operating from a single 2.5V supply, the LTC2377-16
The LTC2377-16 digitizes the full-scale voltage of 2 × REF
16
into 2 levels, resulting in an LSꢀ size of 152µV with
REF = 5V. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
supports a large and flexible ±V fully differential input
REF
range with V ranging from 2.5V to 5.1V, making it ideal
REF
for high performance applications which require a wide
dynamic range. The LTC2377-16 achieves ±±.5LSꢀ ꢁIL
max, no missing codes at 16 bits and 97dꢀ SIR.
011...111
BIPOLAR
011...110
ZERO
000...001
000...000
111...111
111...110
Fast 5±±ksps throughput with no cycle latency makes
the LTC2377-16 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the con-
version time, easing external timing considerations. The
LTC2377-16 dissipates only 6.8mW at 5±±ksps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
100...001
FSR = +FS – –FS
1LSB = FSR/65536
100...000
–1 0V
LSB
INPUT VOLTAGE (V)
1
LSB
–FSR/2
FSR/2 – 1LSB
237716 F02
The LTC2377-16 features a unique digital gain compres-
sion(DGC)function,whicheliminatesthedriveramplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
Figure 2ꢀ ꢁTC2377-16 Transfer Function
ANAꢁOG INPUT
function that maps zero-scale code from ±V to ±.1 • V
The analog inputs of the LTC2377-16 are fully differential
in order to maximize the signal swing that can be digitized.
Theanaloginputscanbemodeledbytheequivalentcircuit
shown in Figure 3. The diodes at the input provide ESD
protection. ꢁn the acquisition phase, each input sees ap-
REF
and full-scale code from V
to ±.9 • V . For a typical
REF
REF
reference voltage of 5V, the full-scale input range is now
±.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
proximately 45pF (C ) from the sampling CDAC in series
ꢁI
with 4±Ω (R ) from the on-resistance of the sampling
OI
CONVERTER OPERATION
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
The LTC2377-16 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
+
–
the C capacitors during acquisition. During conversion,
the analog inputs draw only a small leakage current.
converter (CDAC) is connected to the ꢁI and ꢁI pins
to sample the differential analog input voltage. A rising
edge on the CIV pin initiates a conversion. During the
conversionphase,the16-bitCDACissequencedthrougha
successiveapproximationalgorithm,effectivelycomparing
the sampled input with binary-weighted fractions of the
ꢁI
REF
C
45pF
IN
R
40Ω
ON
+
IN
IN
referencevoltage(e.g.V /2,V /4…V /65536)using
REF
REF
REF
BIAS
the differential comparator. At the end of conversion, the
CDAC output approximates the sampled analog input. The
ADC control logic then prepares the 16-bit digital output
code for serial transfer.
VOLTAGE
REF
C
45pF
IN
R
40Ω
ON
–
237716 F03
Figure 3ꢀ The Equivalent Circuit for the
Differential Analog Input of the ꢁTC2377-16
237716fa
10
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
Highqualitycapacitorsandresistorsshouldbeusedinthe
RCfilterssincethesecomponentscanadddistortion.IPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
A low impedance source can directly drive the high im-
pedance inputs of the LTC2377-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
Single-Ended-to-Differential Conversion
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2377-16. The ampli-
fier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
ꢁt also provides isolation between the signal source and
the current spike the ADC inputs draw.
Forsingle-endedinputsignals,asingle-endedtodifferential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2377-16. The LT635± ADC
driver is recommended for performing single-ended-to-
differential conversions. The LT635± is flexible and may
be configured to convert single-ended signals of various
amplitudes to the ±5V differential input range of the
LTC2377-16. The LT635± is also available in H-grade to
complement the extended temperature operation of the
LTC2377-16 up to 125°C.
Input Filtering
The noise and distortion of the buffer amplifier and signal
sourcemustbeconsideredsincetheyaddtotheADCnoise
and distortion. Ioisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)
shown in Figure 4 is sufficient for many applications.
Figure 5a shows the LT635± being used to convert a ±V
to 5V single-ended input signal. ꢁn this case, the first
amplifierisconfiguredasaunitygainbufferandthesingle-
ended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5b,
the LT635± drives the LTC2377-16 to near full data sheet
performance.
LPF2
6800pF
SINGLE-ENDED-
20Ω
LPF1
INPUT SIGNAL
+
–
IN
500Ω
3300pF
The LT635± can also be used to buffer and convert large
true bipolar signals which swing below ground to the
±5V differential input range of the LTC2377-16 in order
to maximize the signal swing that can be digitized. Fig-
ure 6a shows the LT635± being used to convert a ±1±V
true bipolar signal for use by the LTC2377-16. ꢁn this
case, the first amplifier in the LT635± is configured as
an inverting amplifier stage, which acts to attenuate and
level shift the input signal to the ±V to 5V input range of
the LTC2377-16. ꢁn the inverting amplifier configuration,
the single-ended input signal source no longer directly
drives a high impedance input of the first amplifier. The
LTC2377-16
6600pF
IN
20Ω
237716 F04
SINGLE-ENDED- 6800pF
TO-DIFFERENTIAL
DRIVER
BW = 48kHz
BW = 600kHz
Figure 4ꢀ Input Signal Chain
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noisecontributionofthebufferandtohelpminimizedistur-
bances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SIR.
input impedance is instead set by resistor R . R must
ꢁI ꢁI
be chosen carefully based on the source impedance of the
signal source. Higher values of R tend to degrade both
ꢁI
the noise and distortion of the LT635± and LTC2377-16
as a system.
237716fa
11
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
V
CM
LT6350
5V
0V
OUT1
4
5V
0V
R2 = 499Ω
R
R
INT
INT
200pF
8
1
+
–
LT6350
5V
0V
OUT1
OUT2
4
5
5V
0V
–
+
R
INT
R
INT
8
+
–
OUT2
5
10µF
R4 = 402Ω
R3 = 2k
2
5V
0V
–
+
+
–
V
= V /2
REF
CM
1
2
237716 F05a
10V
0V
–10V
R
= 2k
R1 = 499Ω
IN
+
–
V
= V /2
REF
CM
Figure 5aꢀ ꢁT6350 Converting a 0V-5V Single-Ended
Signal to a 5V Differential Input Signal
220pF
237716 F06a
Figure 6aꢀ ꢁT6350 Converting a 10V Single-Ended Signal to
a 5V Differential Input Signal
0
–20
–40
0
–20
–40
–60
–80
–60
–100
–120
–140
–160
–180
–80
–100
–120
–140
–160
–180
0
50
100
150
200
250
FREQUENCY (kHz)
237716 F05b
0
50
100
150
200
250
Figure 5bꢀ 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
FREQUENCY (kHz)
237716 F06b
Figure 6bꢀ 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 6a
R1, R2, R3 and R4 must be selected in relation to R to
ꢁI
achievethedesiredattenuationandtomaintainabalanced
input impedance in the first amplifier. Table 1 shows the
5V
LT6203
5V
0V
3
2
+
–
resulting SIR and THD for several values of R , R1, R2,
ꢁI
1
7
0V
R3 and R4 in this configuration. Figure 6b shows the re-
sulting FFT when using the LT635± as shown in Figure 6a.
5V
0V
5V
0V
5
6
+
–
Table 1ꢀ SNR, THD vs RIN for 10V Single-Ended Input Signalꢀ
R
R1
ꢃΩx
R2
ꢃΩx
R3
ꢃΩx
R4
ꢃΩx
SNR
ꢃdꢂx
THD
ꢃdꢂx
IN
ꢃΩx
237716 F07
2k
499
499
2k
4±2
2k
96.4
96.3
96.3
–1±1
–92
Figure 7ꢀ ꢁT6203 ꢂuffering a Fully Differential Signal Source
1±k
1±±k
2.49k
24.9k
2.49k
24.9k
1±k
1±±k
2±k
–98
Digital Gain Compression
The LTC2377-16 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be be-
Fully Differential Inputs
tween 1±% and 9±% of the ±V analog input range. To
REF
To achieve the full distortion performance of the
LTC2377-16,alowdistortionfullydifferentialsignalsource
driven through the LT62±3 configured as two unity gain
buffers as shown in Figure 7 can be used to get the full
data sheet THD specification of –123dꢀ.
enable digital gain compression, bring the REF/DGC pin
low. This feature allows the LT635± to be powered off of
a single +5.5V supply since each input swings between
±.5V and 4.5V as shown in Figure 8. Ieeding only one
237716fa
12
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
5V
many applications. With its small size, low power and
highaccuracy, theLTC6655-5isparticularlywellsuitedfor
use with the LTC2377-16. The LTC6655-5 offers ±.±25%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications. The LTC6655-5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2377-16 up to 125°C. We recommend bypassing the
LTC6655-5witha47µFceramiccapacitor(X5R,±8±5size)
close to the REF pin.
4.5V
0.5V
0V
237716 F08
Figure 8ꢀ Input Swing of the ꢁTC2377 with Gain
Compression Enabled
positive supply to power the LT635± results in additional
power savings for the entire system.
TheREFpinoftheLTC2377-16drawscharge(Q
)from
COIV
Figure 9a shows how to configure the LT635± to accept a
±1±V true bipolar input signal and attenuate and level shift
the signal to the reduced input range of the LTC2377-16
whendigitalgaincompressionisenabled.Figure9bshows
anFFTplotwiththeLTC2377-16beingdrivenbytheLT635±
with digital gain compression enabled.
the 47µF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
ꢁ
ꢁ
= Q
/t . The DC current draw of the REF pin,
REF
REF
COIV CYC
, depends on the sampling rate and output code. ꢁf
the LTC2377-16 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than ±.5LSꢀs.
ADC REFERENCE
The LTC2377-16 requires an external reference to define
its input range. A low noise, low temperature drift refer-
enceiscriticaltoachievingthefulldatasheetperformance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
When idling, the REF pin on the LTC2377-16 draws only
a small leakage current (< 1µA). ꢁn applications where a
burst of samples is taken after idling for long periods as
shown in Figure 1±, ꢁ quickly goes from approximately
REF
5.5V
V
V
V
LTC6655-5
IN
0
–20
OUT_F
OUT_S
5V
1k
–40
47µF
V
CM
–60
4.5V
0.5V
2.5V
1k
10µF
3
+
–80
V
6800pF
LT6350
OUT1
OUT2
6.04k
4.32k
REF
V
4
DD
LTC2377-16
REF/DGC
–100
–120
–140
–160
–180
+
–
20Ω
IN
IN
R
R
INT
8
+
–
INT
10µF
R
3300pF
20Ω
–
+
5
6
1
4.5V
2
–
237716 F09a
V
6800pF
10V
0V
–10V
= 15k
3.01k
IN
0
50
100
150
200
250
0.5V
V
CM
FREQUENCY (kHz)
237716 F09b
Figure 9aꢀ ꢁT6350 Configured to Accept a 10V Input Signal While Running Off of a
Single 5ꢀ5V Supply When Digital Gain Compression Is Enabled in the ꢁTC2377-16
Figure 9bꢀ 32k Point FFT Plot
with fIN = 2kHz for Circuit Shown
in Figure 9a
CNV
IDLE
PERIOD
IDLE
PERIOD
237716 F10
Figure 10ꢀ CNV Waveform Showing ꢂurst Sampling
237716fa
13
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
±µA to a maximum of ±.4mA at 5±±ksps. This step in DC
currentdrawtriggersatransientresponseinthereference
that must be considered since any deviation in the refer-
ence output voltage will affect the accuracy of the output
code. ꢁn applications where the transient response of the
reference is important, the fast settling LTC6655-5 refer-
ence is also recommended.
Signal-to-Noise Ratio ꢃSNRx
The signal-to-noise ratio (SIR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 11 shows
that the LTC2377-16 achieves a typical SIR of 97dꢀ at a
5±±kHz sampling rate with a 2kHz input.
DYNA(IC PERFOR(ANCE
Total Harmonic Distortion ꢃTHDx
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. ꢀy applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2377-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
TotalHarmonicDistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
THD is expressed as:
/2).
SMPL
V22 + V32 + V42 +…+ VI2
THD=2±log
V1
Signal-to-Noise and Distortion Ratio ꢃSINADx
where V1 is the RMS amplitude of the fundamental fre-
quencyandV2throughV aretheamplitudesofthesecond
I
The signal-to-noise and distortion ratio (SꢁIAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 11 shows that the LTC2377-16 achieves
a typical SꢁIAD of 97dꢀ at a 5±±kHz sampling rate with
a 2kHz input.
through Ith harmonics.
POWER CONSIDERATIONS
The LTC2377-16 provides two power supply pins: the
2.5V power supply (V ), and the digital input/output
DD
interface power supply (OV ). The flexible OV supply
DD
DD
allows the LTC2377-16 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
0
SNR = 97.2dB
–20
–40
THD = –123dB
SINAD = 97.2dB
SFDR = 126dB
Power Supply Sequencing
–60
The LTC2377-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2377-16
has a power-on-reset (POR) circuit that will reset the
LTC2377-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. Io conversions should be initiated
until 2±µs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
–80
–100
–120
–140
–160
–180
0
50
100
150
200
250
FREQUENCY (kHz)
237716 F11
Figure 11ꢀ 32k Point FFT with fIN = 2kHz of the ꢁTC2377-16
time will produce invalid results.
237716fa
14
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
TI(ING AND CONTROꢁ
DIGITAꢁ INTERFACE
The LTC2377-16 has a serial digital interface. The flexible
CNV Timing
OV supply allows the LTC2377-16 to communicate with
DD
The LTC2377-16 conversion is controlled by CIV. A ris-
ing edge on CIV will start a conversion and power up the
LTC2377-16.Onceaconversionhasbeeninitiated,itcannot
berestarteduntiltheconversioniscomplete.Foroptimum
performance, CIV should be driven by a clean low jitter
signal. Converter status is indicated by the ꢀUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CIV should occur within 4±ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2377-16 powers down and begins acquiring the
input signal.
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
anexternalclockisappliedtotheSCKpinifSDOisenabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
4±MHz, a 5±±ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2377-16 is simple and
straightforwardtouse.Thefollowingsectionsdescribethe
operation of the LTC2377-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPꢁ bus or are daisy-chained.
Acquisition
AproprietarysamplingarchitectureallowstheLTC2377-16
to begin acquiring the input signal for the next conver-
sion 527ns after the start of the current conversion. This
extends the acquisition time to 1.46µs, easing settling
requirementsandallowingtheuseofextremelylowpower
ADC drivers. (Refer to the Timing Diagram.)
3.0
2.5
I
VDD
2.0
1.5
1.0
0.5
0
Internal Conversion Clock
The LTC2377-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 1.5µs.
I
REF
Auto Power-Down
I
OVDD
0
100
200
300
400
500
The LTC2377-16 automatically powers down after a con-
version has been completed and powers up once a new
conversion is initiated on the rising edge of CIV. During
power down, data from the last conversion can be clocked
out. To minimize power dissipation during power down,
disableSDOandturnoffSCK.Theautopower-downfeature
will reduce the power dissipation of the LTC2377-16 as
the sampling frequency is reduced. Since power is con-
sumedonlyduringaconversion, theLTC2377-16remains
powered-downforalargerfractionoftheconversioncycle
SAMPLING RATE (kHz)
237716 F12
Figure 12ꢀ Power Supply Current of the ꢁTC2377-16
Versus Sampling Rate
(t ) at lower sample rates, thereby reducing the average
CYC
power dissipation which scales with the sampling rate as
shown in Figure 12.
237716fa
15
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
Normal (ode, Single Device
Figure 13 shows a single LTC2377-16 operated in normal
mode with CHAꢁI and RDL/SDꢁ tied to ground. With RDL/
SDꢁ grounded, SDO is enabled and the MSꢀ(D15) of the
new conversion data is available at the falling edge of
ꢀUSY. ThisisthesimplestwaytooperatetheLTC2377-16.
When CHAꢁI = ±, the LTC2377-16 operates in normal
mode. ꢁn normal mode, RDL/SDꢁ enables or disables the
serial data output pin SDO. ꢁf RDL/SDꢁ is high, SDO is in
high impedance. ꢁf RDL/SDꢁ is low, SDO is driven.
CONVERT
DIGITAL HOST
IRQ
CNV
CHAIN
BUSY
LTC2377-16
SCK
RDL/SDI
SDO
DATA IN
CLK
237716 F13a
POWER-DOWN
ACQUIRE
CONVERT
POWER-DOWN
ACQUIRE
CONVERT
CHAIN = 0
RDL/SDI = 0
t
CYC
t
CNVH
t
CNVL
CNV
t
t
HOLD
ACQ
t
= t
– t
ACQ CYC HOLD
t
CONV
BUSY
t
SCK
t
BUSYLH
t
t
QUIET
SCKH
1
2
3
14
15
16
SCK
SDO
t
t
SCKL
HSDO
t
t
DSDO
DSDOBUSYL
D15
D14
D13
D1
D0
237716 F13
Figure 13ꢀ Using a Single ꢁTC2377-16 in Normal (ode
237716fa
16
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
Normal (ode, (ultiple Devices
Since SDO is shared, the RDL/SDꢁ input of each ADC must
be used to allow only one LTC2377-16 to drive SDO at a
timeinordertoavoidbusconflicts. AsshowninFigure14,
the RDL/SDꢁ inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDꢁ is brought low, the MSꢀ of the selected
device is output onto SDO.
Figure 14 shows multiple LTC2377-16 devices operating
in normal mode (CHAꢁI = ±) sharing CIV, SCK and SDO.
ꢀy sharing CIV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
RDL
RDL
B
A
CONVERT
CNV
CNV
CHAIN
BUSY
SDO
IRQ
CHAIN
LTC2377-16
B
LTC2377-16
A
DIGITAL HOST
SDO
RDL/SDI
RDL/SDI
SCK
SCK
DATA IN
CLK
237716 F14a
POWER-DOWN
ACQUIRE
CONVERT
POWER-DOWN
ACQUIRE
CONVERT
CHAIN = 0
t
CNVL
CNV
t
HOLD
BUSY
t
CONV
t
BUSYLH
RDL/SDI
A
B
RDL/SDI
t
SCK
t
t
QUIET
SCKH
SCK
SDO
1
2
3
14
15
16
17
18
19
30
31
32
t
t
SCKL
HSDO
t
t
DIS
DSDO
t
EN
Hi-Z
Hi-Z
Hi-Z
D15
D14
D13
D1
A
D0
A
D15
D14
D13
D1
B
D0
B
A
A
A
B
B
B
237716 F14
Figure 14ꢀ Normal (ode With (ultiple Devices Sharing CNV, SCK and SDO
237716fa
17
For more information www.linear.com/LTC2377-16
LTC2377-16
APPLICATIONS INFORMATION
Chain (ode, (ultiple Devices
This is useful for applications where hardware constraints
may limit the numberoflines needed to interface toa large
number of converters. Figure 15 shows an example with
two daisy-chained devices. The MSꢀ of converter A will
appear at SDO of converter ꢀ after 16 SCK cycles. The
MSꢀ of converter A is clocked in at the SDꢁ/RDL pin of
converter ꢀ on the rising edge of the first SCK.
When CHAꢁI = OV , the LTC2377-16 operates in chain
DD
mode.ꢁnchainmode,SDOisalwaysenabledandRDL/SDꢁ
serves as the serial data input pin (SDꢁ) where daisy-chain
data output from another ADC can be input.
CONVERT
OV
OV
DD
DD
CNV
CNV
CHAIN
CHAIN
DIGITAL HOST
LTC2377-16
LTC2377-16
RDL/SDI
SDO
RDL/SDI
BUSY
SDO
IRQ
A
B
DATA IN
SCK
SCK
CLK
237716 F16a
POWER-DOWN
ACQUIRE
CONVERT
POWER-DOWN
ACQUIRE
CONVERT
CHAIN = OV
DD
RDL/SDI = 0
A
t
CYC
t
CNVL
CNV
t
HOLD
BUSY
t
CONV
t
BUSYLH
SCK
t
SCKCH
t
t
QUIET
SCKH
1
2
3
14
15
16
17
18
30
31
32
t
SCKL
t
t
HSDO
SSDISCK
t
t
DSDO
HSDISCK
SDO = RDL/SDI
A
B
D15
D14
D13
D1
D0
D0
A
A
A
A
A
t
DSDOBUSYL
D15
D14
D13
D1
B
D15
D14
D1
A
D0
A
SDO
B
B
B
B
A
A
B
237716 F15
Figure 15ꢀ Chain (ode Timing Diagram
237716fa
18
For more information www.linear.com/LTC2377-16
LTC2377-16
BOARD LAYOUT
To obtain the best performance from the LTC2377-16
a printed circuit board is recommended. Layout for the
printed circuit board (PCꢀ) should ensure the digital and
analog signal lines are separated as much as possible. ꢁn
particular,careshouldbetakennottorunanydigitalclocks
orsignalsalongsideanalogsignalsorunderneaththeADC.
Recommended ꢁayout
ThefollowingisanexampleofarecommendedPCꢀlayout.
A single solid ground plane is used. ꢀypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1783A, the
evaluation kit for the LTC2377-16.
Partial Top Silkscreen
237716fa
19
For more information www.linear.com/LTC2377-16
LTC2377-16
BOARD LAYOUT
Partial ꢁayer 1 Component Side
Partial ꢁayer 2 Ground Plane
237716fa
20
For more information www.linear.com/LTC2377-16
LTC2377-16
BOARD LAYOUT
Partial ꢁayer 3 PWR Plane
Partial ꢁayer 4 ꢂottom ꢁayer
237716fa
21
For more information www.linear.com/LTC2377-16
LTC2377-16
BOARD LAYOUT
Partial Schematic of Demo ꢂoard
D G C R E F /
R E F
8
7
1 5
2
1
G N D
D D
D D
V
G N D 1 6
O V
G N D
1 0
G N D
6
3
3
2
1
3
2
1
237716fa
22
For more information www.linear.com/LTC2377-16
LTC2377-16
PACKAGE DESCRIPTION
Please refer to http://wwwꢀlinearꢀcom/product/ꢁTC2377-16#packaging for the most recent package drawingsꢀ
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-ꢀ732 Rev Ø)
0.70 0.05
3.30 0.05
ꢀ.70 0.05
3.60 0.05
2.20 0.05
PACKAGE
OUTLINE
0.25 0.05
0.45 BSC
3.ꢀ5 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.ꢀꢀ5
TYP
0.40 0.ꢀ0
4.00 0.ꢀ0
(2 SIDES)
9
ꢀ6
R = 0.05
TYP
3.30 0.ꢀ0
3.00 0.ꢀ0
(2 SIDES)
ꢀ.70 0.ꢀ0
PIN ꢀ NOTCH
R = 0.20 OR
0.35 × 45°
PIN ꢀ
TOP MARK
(SEE NOTE 6)
CHAMFER
(DEꢀ6) DFN 0806 REV Ø
8
ꢀ
0.23 0.05
0.45 BSC
0.75 0.05
0.200 REF
3.ꢀ5 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
237716fa
23
For more information www.linear.com/LTC2377-16
LTC2377-16
PACKAGE DESCRIPTION
Please refer to http://wwwꢀlinearꢀcom/product/ꢁTC2377-16#packaging for the most recent package drawingsꢀ
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)
0.889 ±0.127
(.035 ±.005)
5.10
3.20 – 3.45
(.201)
(.126 – .136)
MIN
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.50
(.0197)
BSC
0.305 ±0.038
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
REF
16151413121110
9
RECOMMENDED SOLDER PAD LAYOUT
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
DETAIL “A”
0.254
4.90 ±0.152
(.193 ±.006)
(.010)
0° – 6° TYP
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS16) 0213 REV A
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
237716fa
24
For more information www.linear.com/LTC2377-16
LTC2377-16
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NU(ꢂER
A
±9/16 Updated graphs G±1, G±2 and G±3.
6
237716fa
ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LTC2377-16
TYPICAL APPLICATION
ꢁT6350 Configured to Accept a 10V Input Signal While Running Off of a Single 5ꢀ5V Supply When
Digital Gain Compression Is Enabled in the ꢁTC2377-16
5.5V
V
V
V
LTC6655-5
IN
OUT_F
OUT_S
5V
1k
1k
47µF
V
CM
4.5V
0.5V
2.5V
10µF
3
+
V
6800pF
6800pF
LT6350
OUT1
OUT2
6.04k
4.32k
REF
V
4
DD
LTC2377-16
REF/DGC
+
–
20Ω
IN
IN
R
R
INT
8
+
–
INT
10µF
R
3300pF
20Ω
–
+
5
6
1
4.5V
2
–
237716 TA03
V
10V
0V
= 15k
3.01k
IN
0.5V
V
CM
–10V
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Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 Packages
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SC7± 6-Pin Package, ꢁnternal Reference, ±1LSꢀ ꢁIL (12 ꢀits)
OUT
REFERENCES
LTC6655
Precision Low Drift Low Ioise ꢀuffered Reference
Precision Low Drift Low Ioise ꢀuffered Reference
5V/2.5V, 5ppm/°C, ±.25ppm Peak-to-Peak Ioise, MSOP-8 Package
5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Ioise, MSOP-8 Package
LTC6652
A(PꢁIFIERS
LT635±
Low Ioise Single-Ended-to-Differential ADC Driver
Rail-to-Rail ꢁnput and Outputs, 24±ns, ±.±1% Settling Time
LT62±±/LT62±±-5/
LT62±±-1±
165MHz/8±±MHz/1.6GHz Op Amp with
Unity Gain/AV = 5/AV = 1±
Low Ioise Voltage: ±.95nV/√Hz (1±±kHz), Low Distortion: –8±dꢀ at
1MHz, TSOT23-6 Package
LT62±2/LT62±3
Single/Dual 1±±MHz Rail-to-Rail ꢁnput/Output Ioise Low 1.9nV√Hz, 3mA Maximum, 1±±MHz Gain ꢀandwidth
Power Amplifiers
LTC1992
Low Power, Fully Differential ꢁnput/Output Amplifier/
Driver Family
1mA Supply Current
237716fa
LT 0916 REV A • PRINTED IN USA
LinearTechnology Corporation
163± McCarthy ꢀlvd., Milpitas, CA 95±35-7417
26
(4±8)432-19±± FAX: (4±8) 434-±5±7 www.linear.com/LTC2377-16
●
●
LINEAR TECHNOLOGY CORPORATION 2011
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