LTC2274CUJ-TRPBF_技术文档

LTC2274

16-Bit, 105Msps Serial

Output ADC

FEATURES

DESCRIPTION

The LTC^®2274 is a 105Msps, 16-bit A/D converter with

a high speed serial interface. It is designed for digitizing

high frequency, wide dynamic range signals with an input

bandwidth of 700MHz. The input range of the ADC can

be optimized using the PGA front end. The output data is

serialized according to the JEDEC Serial Interface for Data

Converters speciﬁcation (JESD204).

n

High Speed Serial Interface (JESD204)

n

Sample Rate: 105Msps

n

77.7dBFS Noise Floor

100dB SFDR

SFDR >82dB at 250MHz (1.5V Input Range)

PGA Front End (2.25V or 1.5V Input Range)

n

P-P

n

P-P

n

700MHz Full Power Bandwidth S/H

Optional Internal Dither

Single 3.3V Supply

The LTC2274 is perfect for demanding applications where

it is desirable to isolate the sensitive analog circuits from

the noisy digital logic. The AC performance includes a

77.7dBNoiseFloorand100dBspuriousfreedynamicrange

(SFDR). Ultra low internal jitter of 80fs RMS allows under-

sampling of high input frequencies with excellent noise

performance. Maximum DC specs include 4.5LSB INL

and 1LSB DNL (no missing codes) over temperature.

Power Dissipation: 1300mW

Clock Duty Cycle Stabilizer

Pin Compatible Family

105Msps: LTC2274

80Msps: LTC2273

65Msps: LTC2272

n

40-Pin 6mm × 6mm QFN Package

+

–

The encode clock inputs, ENC and ENC , may be driven

differentially or single-ended with a sine wave, PECL,

LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer

allows high performance at full speed with a wide range

of clock duty cycles.

APPLICATIONS

n

Telecommunications

n

Receivers

n

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

Cellular Base Stations

n

Spectrum Analysis

n

Imaging Systems

n

ATE

TYPICAL APPLICATION

3.3V

FAM

SENSE

+

SYNC

128k Point FFT, f_IN= 4.93MHz,

SYNC^–

1.25V

COMMON MODE

BIAS VOLTAGE

INTERNAL ADC

REFERENCE

GENERATOR

–1dBFS, PGA = 0

V

ASIC OR FPGA

50Ω

CM

8B/10B

ENCODER

1.2V TO 3.3V

0

–10

–20

–30

–40

–50

–60

–70

–80

OV

DD

2.2μF

16

20

0.1μF

+

50Ω

CMLOUT

+

A

IN

SERIAL

RECEIVER

+

SERIALIZER

16-BIT

PIPELINED

ADC CORE

ANALOG

INPUT

S/H

AMP

CORRECTION

LOGIC

–

CMLOUT

–

–90

A

IN

CLOCK

–100

–110

–120

–130

3.3V

V

DD

SCRAMBLER/

PATTERN

GENERATOR

20X

PLL

CLOCK/DUTY

CYCLE

0

10

20

30

40

50

CONTROL

0.1μF 0.1μF

GND

FREQUENCY (MHz)

2274 TA01b

2274 TA01

–

+

ENC

ENC PGA DITH MSBINV SHDN

PAT1 PAT0 SCRAM SRR1 SRR0

2274f

1

LTC2274

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

OV_DD= V_DD(Notes 1, 2)

TOP VIEW

Supply Voltage (V ) ................................... –0.3V to 4V

DD

40 39 38 37 36 35 34 33 32 31

Analog Input Voltage (Note 3).......–0.3V to (V + 0.3V)

DD

V

1

2

3

4

5

6

7

8

9

30

29

28

GND

DD

Digital Input Voltage......................–0.3V to (V + 0.3V)

DD

–

+

SYNC

DD

Digital Output Voltage ................ –0.3V to (OV + 0.3V)

GND

+

DD

A

27 GND

26 GND

IN

Power Dissipation.............................................2000mW

–

A

IN

41

Operating Temperature Range

GND

25

OV

DD

+

–

24 CMLOUT

LTC2274C ................................................ 0°C to 70°C

LTC2274I.............................................. –40°C to 85°C

Storage Temperature Range................... –65°C to 150°C

23

22

21

CMLOUT

OV

+

ENC

DD

GND

–

ENC 10

11 12 13 14 15 16 17 18 19 20

Digital Output Supply Voltage (OV ).......... –0.3V to 4V

DD

UJ PACKAGE

40-LEAD (6mm s 6mm) PLASTIC QFN

T

= 150°C, θ = 22°C/W

JA

JMAX

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC2274CUJ#PBF

LTC2274IUJ#PBF

LEAD BASED FINISH

LTC2274CUJ

TAPE AND REEL

LTC2274CUJ#TRPBF

LTC2274IUJ#TRPBF

TAPE AND REEL

LTC2274CUJ#TR

LTC2274IUJ#TR

PART MARKING*

LTC2274UJ

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

40-Lead (6mm × 6mm) Plastic QFN

PACKAGE DESCRIPTION

LTC2274UJ

–40°C to 85°C

TEMPERATURE RANGE

0°C to 70°C

PART MARKING*

LTC2274UJ

40-Lead (6mm × 6mm) Plastic QFN

LTC2274IUJ

LTC2274UJ

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

CONVERTER CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL

CONDITIONS

MIN

TYP

1.2

1.5

0.3

1

MAX

4

UNITS

LSB

Integral Linearity Error

Differential Linearity Error

Offset Error

Differential Analog Input (Note 5) T = 25°C

A

l

Differential Analog Input (Note 5)

Differential Analog Input

(Note 6)

4.5

1

LSB

8.5

mV

Offset Drift

10

μV/°C

%FS

l

Gain Error

External Reference

0.2

1.5

Full-Scale Drift

Internal Reference

External Reference

30

15

ppm/°C

Transition Noise

3

LSB

RMS

2274f

2

LTC2274

ANALOG INPUT ^Thel denotes denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

1.5 or 2.25

1.25

MAX

UNITS

+

–

l

V

3.135V ≤ V ≤ 3.465V

V

Analog Input Range (A

–

A

IN

)

IN

DD

P-P

IN

V

I

Analog Input Common Mode

Differential Input (Note 7)

1

1.5

1

V

μA

IN, CM

+

–

Analog Input Leakage Current

SENSE Input Leakage Current

Analog Input Capacitance

–1

–3

0V ≤ A

,

A

≤ V (Note 10)

IN

IN DD

I

0V ≤ SENSE ≤ V (Note 11)

3

SENSE

DD

+

–

C

IN

Sample Mode ENC < ENC

Hold Mode ENC > ENC

6.7

1.8

pF

+

–

t

Sample-and-Hold

1

ns

AP

Acquisition Delay Time

Sample-and-Hold

Acquisition Delay Time Jitter

80

fs

RMS

JITTER

+

–

CMRR

Analog Input

Common Mode Rejection Ratio

1V < (A = A ) <1.5V

80

dB

IN

BW-3dB

Full Power Bandwidth

700

MHz

R ≤ 25Ω

S

DYNAMIC ACCURACY ^Thel denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. A_IN= –1dBFS. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SNR

Signal-to-Noise Ratio

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

77.6

75.4

dBFS

15MHz Input (2.25V Range, PGA = 0), T = 25°C

76.5

76.2

77.5

77.2

75.3

dBFS

A

l

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

77.2

75.1

dBFS

140MHz Input (2.25V Range, PGA = 0)

76.3

74.5

74.2

dBFS

140MHz Input (1.5V Range, PGA = 1), T = 25°C

73.8

73.4

A

l

140MHz Input (1.5V Range, PGA = 1)

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

75.9

74.3

dBFS

SFDR

Spurious Free Dynamic Range

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

100

dBc

nd

rd

2

or 3 Harmonic

15MHz Input (2.25V Range, PGA = 0), T = 25°C

85

84

95

100

dBc

A

l

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

86

94

dBc

140MHz Input (2.25V Range, PGA = 0)

85

90

89

dBc

140MHz Input (1.5V Range, PGA = 1), T = 25°C

81

80

A

l

140MHz Input (1.5V Range, PGA = 1)

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

80

85

dBc

2274f

3

LTC2274

DYNAMIC ACCURACY

The l denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. A_IN= –1dBFS unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

th

SFDR

Spurious Free Dynamic Range 4

Harmonic or Higher

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

100

dBc

l

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

90

100

dBc

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

100

dBc

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

95

100

dBc

l

85

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

90

95

dBc

S/(N+D)

Signal-to-Noise

Plus Distortion Ratio

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

77.5

75.3

dBFS

15MHz Input (2.25V Range, PGA = 0), T = 25°C

76.3

75.9

77.4

77

75.2

dBFS

A

l

15MHz Input (2.25V Range, PGA = 0

15MHz Input (1.5V Range, PGA = 1)

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

76.7

74.2

dBFS

140MHz Input (2.25V Range, PGA = 0), T = 25°C

75.3

74.3

74

dBFS

A

140MHz Input (1.5V Range, PGA = 1)

73.6

73.2

l

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

73.4

dBFS

SFDR

Spurious Free Dynamic Range

at –25dBFS Dither “OFF”

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

105

dBFS

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

105

dBFS

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

105

dBFS

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

100

dBFS

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

100

dBFS

SFDR

Spurious Free Dynamic Range

at –25dBFS Dither “ON”

5MHz Input (2.25V Range, PGA = 0)

5MHz Input (1.5V Range, PGA = 1)

115

dBFS

l

15MHz Input (2.25V Range, PGA = 0)

15MHz Input (1.5V Range, PGA = 1)

97

115

dBFS

70MHz Input (2.25V Range, PGA = 0)

70MHz Input (1.5V Range, PGA = 1)

115

dBFS

140MHz Input (2.25V Range, PGA = 0)

140MHz Input (1.5V Range, PGA = 1)

110

dBFS

170MHz Input (2.25V Range, PGA = 0)

170MHz Input (1.5V Range, PGA = 1)

105

dBFS

2274f

4

LTC2274

COMMON MODE BIAS CHARACTERISTICS The l denotes the speciﬁcations which apply over

the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

PARAMETER

CONDITIONS

MIN

TYP

1.25

40

1

MAX

UNITS

V

CM

V

CM

V

CM

V

CM

Output Voltage

Output Tempco

Line Regulation

Output Resistance

I

= 0

1.15

1.35

OUT

ppm/°C

l

3.135V ≤ V ≤ 3.465V

mV/V

Ω

DD

–1mA ≤ | I

| ≤ 1mA

2

OUT

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

Encode Inputs (ENC , ENC )

l

V

Differential Input Voltage

(Note 7)

0.2

1.4

V

ID

V

Common Mode Input Voltage Internally Set

Externally Set (Note 7)

1.6

ICM

3.0

R

Input Resistance

(See Figure 2)

6

3

k

Ω

IN

C

Input Capacitance

pF

IN

+

–

SYNC Inputs (SYNC , SYNC )

l

V

SYNC Differential Input

(Note 7)

0.2

1.1

V

SID

Voltage

V

SYNC Common Mode Input

Voltage

Internally Set

Externally Set (Note 7)

1.6

SICM

2.2

R

SYNC Input Resistance

SYNC Input Capacitance

16.5

3

k

Ω

SIN

C

pF

SIN

Logic Inputs (DITH, PGA, MSBINV, SCRAM, FAM, SHDN, SRR1, SRR0, ISMODE, PAT1, PAT0)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

DD

V

DD

V

IN

= 3.3V

2

V

IH

IL

V

0.8

10

I

= 0V to V

μA

pF

IN

DD

C

IN

Input Capacitance

1.5

+

–

High-Speed Serial Outputs (CMLOUT , CMLOUT )

V

Output High Level

Directly-Coupled 50Ω to OV

OV

DD

OV – 0.2

DD

V

OH

DD

Directly-Coupled 100Ω Differential

AC-Coupled

OV – 0.2

Output Low Level

Directly-Coupled 50Ω to OV

OV – 0.4

V

OL

DD

Directly-Coupled 100Ω Differential

AC-Coupled

OV – 0.6

DD

OV – 0.6

DD

Output Common Mode

Voltage

Directly-Coupled 50Ω to OV

OV – 0.2

V

OCM

DD

Directly-Coupled 100Ω Differential

AC-Coupled

OV – 0.4

DD

OV – 0.4

DD

l

R

OUT

Output Resistance

Single-Ended Differential

35

50

100

65

Ω

2274f

5

LTC2274

POWER REQUIREMENTS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. A_IN= –1dBFS. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

3.3

5

MAX

UNITS

V

l

V

P

Analog Supply Voltage

Shutdown Power

3.135

3.465

DD

SHDN Pins = V

mW

SHDN

DD

l

OV

Output Supply Range

CMLOUT Directly-Coupled 50Ω to OV (Note 7)

1.2

1.4

V

DD

CMLOUT Directly-Coupled 100Ω Differential (Note 7)

CMLOUT AC-Coupled (Note 7)

l

I

Analog Supply Current

Output Supply Current

DC Input

394

450

mA

VDD

CMLOUT Directly-Coupled, 50Ω to 0V

CMLOUT Directly-Coupled 100Ω Differential

CMLOUT AC-Coupled

8

16

mA

OVDD

DD

l

P

DIS

Power Dissipation

DC Input

1300

1485

mW

TIMING CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

MHz

s

l

f

t

Sampling Frequency

(Note 9)

20

105

S

Conversion Period

1/f

S

CONV

L

l

ENC Clock Low Time

(Note 7)

3.1

4.762

0.7

25

ns

ENC Clock High Time

ns

H

Sample-and-Hold Aperture Delay

Period of a Serial Bit

ns

AP

, UI

t

/20

CONV

s

BIT

l

Total Jitter of CMLOUT (P-P)

Differential Rise and Fall Time of CMLOUT (20% to 80%)

BER = 1E–12 (Note 7)

0.35

UI

JIT

t , t

R

TERM

= 50Ω, C = 2pF

50

110

ps

F

L

(Note 7)

l

t

SU

t

HD

t

CS

SYNC to ENC Clock Setup Time

ENC Clock to SYNC Hold Time

ENC Clock to SYNC Delay

2

ns

2.5

t

– t

SU

ns

HD

CONV

LAT

Pipeline Latency

9

3

2

Cycles

P

Latency from SYNC Active to COMMA Out

Latency from SYNC Release to DATA Out

SC

SD

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: Offset error is the offset voltage measured from –1/2LSB when the

output code ﬂickers between 0000 0000 0000 0000 and 1111 1111 1111

1111 in 2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.

Note 2: All voltage values are with respect to GND (unless otherwise

noted).

Note 8: V = 3.3V, f

differential drive.

= 105MHz input range = 2.25V with

P-P

DD

SAMPLE

Note 3: When these pin voltages are taken below GND or above V , they

will be clamped by internal diodes. This product can handle input currents

DD

Note 9: Recommended operating conditions.

Note 10: The dynamic current of the switched capacitors analog inputs

can be large compared to the leakage current and will vary with the sample

rate.

Note 11: Leakage current will have higher transient current at power up.

Keep drive resistance at or below 1k.

of greater than 100mA below GND or above V without latchup.

DD

+

–

Note 4: V = 3.3V, f

= 105MHz differential ENC /ENC = 2V sine

P-P

DD

SAMPLE

wave with 1.6V common mode, input range = 2.25V with differential

P-P

drive (PGA = 0), unless otherwise speciﬁed.

Note 5: Integral nonlinearity is deﬁned as the deviation of a code from

a “best ﬁt straight line” to the transfer curve. The deviation is measured

from the center of the quantization band.

2274f

6

LTC2274

TIMING DIAGRAMS

t

N + 9

AP

N + 2

N + 10

ANALOG INPUT

N + 8

N + 1

N

t

CONV

+

ENC

t

H

t

L

INTERNAL

PARALLEL DATA

N – 6

N – 5

N – 8

N – 4

N – 7

N + 3

N

N + 4

N + 1

INTERNAL

8B/10B DATA

N – 9

LAT

P

t

BIT

+

–

CMLOUT /CMLOUT

N – 10

N – 9

N – 8

N – 1

N

2274 TD01

Analog Input to Serial Data Out Timing

t

CONV

N + 3

N

N – 1

N + 2

N + 4

N + 5

ANALOG INPUT

N + 1

t

HD

SU

+

ENC

CS(MIN)

+

SYNC

LAT

SC

t

CS(MAX)

+

–

CMLOUT /CMLOUT

N – 10

N – 9

N – 8

N – 7

K28.5 (x2)

2274 TD02

SYNC⁺Falling Edge to Comma (K28.5) Timing

t

CONV

N + 3

N

N – 1

N + 2

N + 4

ANALOG INPUT

N + 1

t

SU

HD

+

ENC

t

CS(MIN)

+

SYNC

LAT

t

SD

CS(MAX)

+

–

CMLOUT /CMLOUT

K28.5 (x2)

N – 7

N – 6

2274 TD03

SYNC⁺Rising Edge to Data Timing

2274f

7

LTC2274

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3.3V, OV_DD= 1.5V, T_A= 25°C, F_S= 105Msps,

unless otherwise noted.

Integral Non-Linearity (INL)

vs Output Code

Differential Non-Linearity (DNL)

vs Output Code

AC Grounded Input Histogram

2.0

1.5

1.0

0.8

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

0.6

1.0

0.4

0.5

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

0

16384

32768

49152

65536

0

16384

32768

49152

65536

32777

32787

32797

32807

OUTPUT CODE

2274 G01

2274 G02

2274 G03

128k Point FFT, f_IN= 4.93MHz,

–1dBFS, PGA = 0

64k Point FFT, f_IN= 14.8MHz,

–1dBFS, PGA = 0

64k Point FFT, f_IN= 14.8MHz,

–10dBFS, PGA = 0

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–100

–110

–120

–130

0

10

20

30

40

50

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2274 G04

2274 G05

2274 G06

64k Point 2-Tone FFT,

f_IN= 14.2MHz and 15.8MHz,

–7dBFS, PGA = 0

SFDR vs Input Level, f_IN

=

SFDR vs Input Level, f_IN

=

15MHz, PGA = 0, Dither “Off”

15MHz, PGA = 0, Dither “On”

140

130

120

110

100

90

140

130

120

110

100

90

0

–10

–20

–30

–40

–50

–60

–70

80

–80

–90

–100

–110

–120

–130

70

60

50

40

30

0

10

20

30

40

50

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

FREQUENCY (MHz)

2274 G09

2274 G07

2274 G08

2274f

8

LTC2274

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3.3V, OV_DD= 1.5V, T_A= 25°C, F_S= 105Msps,

unless otherwise noted.

64k Point 2-Tone FFT,

f_IN= 14.2MHz and 15.8MHz,

–15dBFS, PGA = 0

64k FFT, f_IN= 70.1MHz, –1dBFS,

PGA = 0

64k FFT, f_IN= 70.1MHz, –1dBFS,

PGA = 1

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–100

–110

–120

–130

0

10

20

30

40

50

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2274 G10

2274 G11

2274 G12

128k Point FFT, f_IN= 70.1MHz,

–20dBFS, PGA = 0, Dither “Off”

128k Point FFT, f_IN= 70.1MHz,

–20dBFS, PGA = 0, Dither “On”

64k Point FFT, f_IN= 140.2MHz,

–1dBFS, PGA = 1

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

–100

–110

–120

–130

0

10

20

30

40

50

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

2274 G13

2274 G14

2274 G15

SFDR vs Input Level,

f_IN= 140MHz, PGA = 1,

Dither “Off”

SFDR vs Input Level,

f_IN= 140MHz, PGA = 1,

Dither “On”

64k Point FFT, f_IN= 170.2MHz,

–1dBFS, PGA = 1

140

130

120

110

100

90

140

130

120

110

100

90

0

–10

–20

–30

–40

–50

–60

–70

80

–80

–90

–100

–110

–120

–130

70

60

50

40

30

0

10

20

30

40

50

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

FREQUENCY (MHz)

2274 G18

2274 G16

2274 G17

2274f

9

LTC2274

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3.3V, OV_DD= 1.5V, T_A= 25°C, F_S= 105Msps,

unless otherwise noted.

64k Point FFT, f_IN= 250.2MHz,

–1dBFS, PGA = 1

SFDR (HD2 and HD3) vs

Input Frequency

SNR vs Input Frequency

0

–10

–20

–30

–40

105

100

95

78

76

PGA = 0

74

90

–50

–60

–70

–80

72

PGA = 1

85

70

68

66

64

80

PGA = 0

–90

75

–100

–110

–120

–130

70

65

0

10

20

30

40

50

0

100

200

300

400

500

0

100

200

300

400

500

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

2274 G19

2274 G21

2274 G20

SNR and SFDR vs Sample Rate,

_IN= 5.1MHz

SNR and SFDR vs Supply Voltage

(V_DD), f_IN= 5.2MHz

f

110

105

100

95

110

105

100

95

SFDR

LIMIT

LOWER LIMIT

UPPER LIMIT

90

85

SNR

80

SNR

75

70

20

40

60

80

100

120

2.8

3.0

3.2

3.4

SAMPLE RATE (Msps)

SUPPLY VOLTAGE (V)

2274 G22

2274 G23

SFDR vs Analog Input

Common Mode Voltage, 5MHz

and 70MHz, –1dBFS

IV_DDvs Sample Rate, 5MHz Sine,

–1dBFS

110

105

100

95

420

410

400

390

380

370

360

350

340

330

320

310

300

290

5MHz

90

85

70MHz

80

75

70

65

60

0.50 0.75 1.00 1.25 1.50 1.75 2.00

0

40

80

120

ANALOG INPUT COMMON MODE VOLTAGE (V)

SAMPLE RATE (Msps)

2274 G25

2274 G02

2274f

10

LTC2274

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3.3V, OV_DD= 1.5V, T_A= 25°C, F_S= 105Msps,

unless otherwise noted.

CMLOUT Dual-Dirac BER

Bathtub Curve, 400Mbps

CMLOUT Dual-Dirac BER

Bathtub Curve, 1.2Gbps

1.0E+00

1.0E–02

1.0E–04

1.0E–06

1.0E–08

1.0E+00

1.0E–02

1.0E–04

1.0E–06

1.0E–08

1.0E

–10

1.0E–10

1.0E–12

1.0E–14

1.0E–12

1.0E–14

0

0.2

0.4

0.6

0.8

1.0

0

0.2

0.4

0.6

0.8

1.0

UNIT INTERVAL (UI)

2274 G26

2274 G27

CMLOUT Dual-Dirac BER

Bathtub Curve, 2.1Gbps

CMLOUT Eye Diagram 400Mbps

1.0E+00

1.0E–02

1.0E–04

1.0E–06

1.0E–08

100mV/DIV

1.0E–10

2274 G29

416.7ps/DIV

1.0E–12

1.0E–14

0

0.2

0.4

0.6

0.8

1.0

UNIT INTERVAL (UI)

2274 G28

CMLOUT Eye Diagram 1.2Gbps

CMLOUT Eye Diagram 2.1Gbps

100mV/DIV

2274 G30

2274 G31

138.9ps/DIV

79.4ps/DIV

2274f

11

LTC2274

PIN FUNCTIONS

V

(Pins 1, 2, 12, 13 ): Analog 3.3V Supply. Bypass to

OV (Pins22,25):PositiveSupplyfortheOutputDrivers.

DD

GND with 0.1μF ceramic chip capacitors.

This supply range is 1.2V to V for directly coupled CML

DD

outputs, or 1.4V to OV for AC-coupled or differentially

DD

GND (Pins 3, 6, 7, 8, 11, 14, 21, 26, 27, 30, 37, 40):

ADC Power Ground.

terminated CML outputs. Bypass to ground with 0.1μF

ceramic chip capacitor.

+

A

(Pin 4): Positive Differential Analog Input.

(Pin 5): Negative Differential Analog Input.

IN

–

CMLOUT (Pin 23): Negative High-Speed CML Output.

–

+

CMLOUT (Pin 24): Positive High-Speed CML Output.

+

ENC (Pin 9): Positive Differential Encode Input. The

+

SYNC (Pin 28): Sync Request Positive Input (Active

+

sampled analog input is held on the rising edge of ENC .

Low for Compatibility with JESD204). A low level on this

pin for at least two sample clock cycles will initiate frame

synchronization.

Thispinisinternallybiasedto1.6Vthrougha6.2kΩresistor.

+

Output data can be latched on the falling edge of ENC .

–

ENC (Pin 10): Negative Differential Encode Input. The

–

SYNC (Pin 29): Sync Request Negative Input. A high

sampled analog input is held on the falling edge of ENC-.

This pin is internally biased to 1.6V through a 6.2kΩ

resistor. Bypass to ground with a 0.1uF capacitor for a

single-ended Encode signal.

level on this pin for at least two sample clock cycles will

initiateframesynchronization.Forsingle-endedoperation,

+

bypass to ground with a 0.1μF capacitor and use SYNC

as the SYNC point.

DITH (Pin 15): Internal Dither Enable Pin. DITH = low

disablesinternaldither.DITH=highenablesinternaldither.

RefertoInternalDithersectionofthisdatasheetfordetails

on dither operation.

FAM (Pin 31): Frame Alignment Monitor Enable. A high

level enables the substitution of predetermined data at the

end of the frame with a K28.7 symbol for frame alignment

monitoring.

ISMODE (Pin 16): Idle Synchronization mode. When IS-

MODE is not asserted, synchronization is performed with

a series of COMMAS (K28.5). When ISMODE is asserted,

a special Idle SYNC mode is enabled where synchroniza-

tion is performed by sending a COMMA (K28.5) followed

by the appropriate data code-group (D5.6 or D16.2) for

establishing a negative running disparity for the ﬁrst data

code-group after synchronization.

PAT0 (Pin 32): Pattern Select Bit0. Use with PAT1 to select

a test pattern for the serial interface.

PAT1 (Pin 33): Pattern Select Bit1. Use with PAT0 to select

a test pattern for the serial interface.

SCRAM (Pin 34): Enable Data Scrambling. A high level on

14

15

this pin will apply the polynomial 1 + x + x in scram-

bling each ADC data sample. The scrambling takes place

before the 8B/10B encoding.

SRR0 (Pin 17): Sample Rate Range Select Bit0. Used with

the SRR1 pin to select the sample rate operating range.

PGA (Pin 35): Programmable Gain Ampliﬁer Control

SRR1 (Pin 18): Sample Rate Range Select Bit1. Used with

the SRR0 pin to select the sample rate operating range.

Pin. Low selects a front-end gain of 1, input range of

2.25V . High selects a front-end gain of 1.5, input range

P-P

of 1.5V

.

P-P

SHDN (Pins 19, 20): Shutdown Pins. A high level on both

pins will shut down the chip.

MSBINV (Pin 36): Invert the MSB. A high level will invert

the MSB to enable the 2’s complement format.

2274f

12

LTC2274

PIN FUNCTIONS

SENSE (Pin 38): Reference Mode Select and External

V

(Pin 39): 1.25V Output. Optimum voltage for input

CM

Reference Input. Tie SENSE to V to select the internal

common mode. Must be bypassed to ground with a

minimum of 2.2μF. Ceramic chip capacitors are recom-

mended.

DD

2.5V bandgap reference. An external reference of 2.5V or

1.25V may be used; both reference values will set a full

scale ADC range of 2.25V (PGA = 0).

GND (Exposed Pad) (Pin 41): ADC Power Ground. The

Exposed Pad on the bottom of the package needs to be

soldered to ground.

BLOCK DIAGRAM

FAM

PIPELINED ADC STAGES

+

SYNC

+

A

IN

S/H

8B/10B

ENCODER

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

FOURTH

STAGE

FIFTH

STAGE

–

AND PGA

SYNC

–

16

DITHER SIGNAL

GENERATOR

20

CORRECTION

LOGIC

OV

DD

+

CMLOUT

REFERENCE

CONTROL

SERIALIZER

–

CMLOUT

ADC

REFERENCE

SENSE

0.5x

20X CLK

1x OR 2x

V

CM

CLOCK DRIVER

WITH DUTY CYCLE

CONTROL

SCRAMBLER/

PATTERN

GENERATOR

V

DD

2.5V

REFERENCE

PLL

CONTROL LOGIC

–

+

ENC

PGA

DITH

MSBINV

SHDN

PAT1

PAT0

SCRAM

SRR1

SRR0 GND

22743 BD

Figure 1. Functional Block Diagram

2274f

13

LTC2274

DEFINITIONS

DYNAMIC PERFORMANCE TERMS

Spurious Free Dynamic Range (SFDR)

The ratio of the RMS input signal amplitude to the RMS

value of the peak spurious spectral component expressed

in dBc. SFDR may also be calculated relative to full scale

and expressed in dBFS.

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N+D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band lim-

ited to frequencies above DC to below half the sampling

frequency.

Full Power Bandwidth

The full power bandwidth is that input frequency at which

theamplitudeofthereconstructedfundamentalisreduced

by 3dB for a full scale input signal.

Signal-to-Noise Ratio

The signal-to-noise (SNR) is the ratio between the RMS

amplitudeofthefundamentalinputfrequencyandtheRMS

amplitude of all other frequency components, except the

ﬁrst ﬁve harmonics.

Aperture Delay Time

+

–

ThetimefromwhenarisingENC equalstheENC voltage

to the instant that the input signal is held by the sample-

and-hold circuit.

Total Harmonic Distortion

Aperture Delay Jitter

Total harmonic distortion is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

The variation in the aperture delay time from conversion

to conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNR

= –20log (2π • f • t

)

JITTER

IN JITTER

2

THD = –20Log (

√

(V + V + V + ... V )/V )

2 3 4 N 1

where V is the RMS amplitude of the fundamental fre-

quencyandV throughV aretheamplitudesofthesecond

1

SERIAL INTERFACE TERMS

8B/10B Encoding

2

N

through nth harmonics.

A data encoding method designed to make an 8-bit data

word (octet) more suitable for serial transmission. The

resulting 10-bit word (code-group) has two fundamental

strengths: 1) The receiver does not require a high-speed

clock to capture the data. This is because the output

code-groups are run-length limited, ensuring that there

are enough transitions in the bit stream for the receiver

to lock onto the data and recover the high-speed clock.

2) AC coupling is permitted because the code-groups are

generated in a way that ensures the data stream is DC

balanced (see Running Disparity).

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

If two pure sine waves of frequencies fa and fb are applied

totheADCinput,nonlinearitiesintheADCtransferfunction

can create distortion products at the sum and difference

frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 3rd order IMD terms include (2fa + fb),

(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is

deﬁned as the ratio of the RMS value of either input tone

to the RMS value of the largest 3rd order IMD product.

A table of the 256 possible input octets with the resulting

10-bitcode-groupsisdocumentedinIEEEStd802.3-2002

part3 Table 36-1. The name associated with each of the

256 data code-groups is formatted Dx.y, with x ranging

from 0 to 31 and y ranging from 0 to 7. Table 36-2 of

2274f

14

LTC2274

DEFINITIONS

the standard deﬁnes an additional set of 12 special code-

groups for non-data characters such as commas. Special

code-group names begin with K instead of D. A complete

8B/10B description is found in Clause 36.2 of IEEE Std

802.3-2002 part3.

whentheaveragenumberof1’sand0’sareequal,eliminat-

ing the undesirable effects of DC wander on the receive

side of the coupling capacitor. When 8B/10B coding is

used, DC balance is achieved by following disparity rules

(see Running Disparity).

Current Mode Logic (CML)

De-Scrambler

Atechniqueusedtoimplementdifferentialhigh-speedlogic.

CML employs differential pairs (usually n-type) to steer

currentintoresistiveloads. Itispossibletoimplementany

logic function using CML. The output swing and offset is

dependant on the bias current, the load resistance, and

termination resistance.

A logic block that restores scrambled data to its pre-

scrambled state. A self aligning de-scrambler is based on

the same pseudo random bit sequence as the scrambler,

so it requires no alignment signals. In this product family

the scrambler is based on the 1 + x + x polynomial,

and the self aligning process results in an initial loss of

one ADC sample.

14

15

This product family uses CML drivers to transmit high-

speed serial data to the outside world. The output driver

bias current is typically 16mA, generating a signal swing

Frame

A group of octets or code-groups that make up one

complete word. For this product family, a frame consists

of two complete octets or code-groups, and constitutes

one ADC sample.

potential of 400mV (800mV diff.) across the com-

P-P

bined internal and external termination resistance of 25Ω

on each output.

Code-Group

Frame Alignment Monitoring (FAM)

The 10-bit output from an 8B/10B encoder or the 10-bit

input to the 8B/10B decoder.

After initial frame synchronization has been established,

frame alignment monitoring enables the receiver to verify

that code-group alignment is maintained without the loss

ofdata.ThisisdonebysubstitutingaK28.7commaforthe

last code-group of the frame when certain conditions are

met. The receiver uses this comma as a position marker

within the frame for alignment veriﬁcation. After decoding

the data, the receiver replaces the K28.7 comma with the

original data.

Comma

A special 8B/10B code-group containing the binary se-

quence “0011111” or “1100000”. Commas are used for

frame alignment and synchronization because a comma

sequence cannot be generated by any combination of

normal code-groups (unless a bit error occurs). There are

three special code-groups that contain a comma, K28.1,

K28.5, and K28.7.

Idle Frame Synchronization Mode (ISMODE)

For brevity, each of these three special code-groups are

often called a comma, but in the strictest sense it is the

ﬁrst 7 bits of these code-groups that are designated a

comma.

A special synchronization mode where idle ordered sets

are used to establish initial frame synchronization instead

of K28.5 commas.

An Idle Ordered Set is deﬁned in the IEEE Std 802.3-2002

part3, Clause 36.2.4.12. In general, it is a K28.5 comma

followed by either a D5.6 or a D16.2. If the running dispar-

ity after the transmission of the K28.5 comma is positive,

DC Balanced Signal

AspeciallyconditionedsignalthatmaybeACcoupledwith

minimal degradation to the signal. DC balance is achieved

2274f

15

LTC2274

DEFINITIONS

a D16.2 will be transmitted after the comma, otherwise

a D5.6 will be transmitted. The result is that the ending

disparity of an idle ordered set will always be negative.

running disparity is calculated to determine which of the

two code-groups should be transmitted to maintain DC

balance.

The disparity of a code-group is analyzed in two segments

called sub-blocks. Sub-block1 consists of the ﬁrst six bits

of a code-group and sub-block2 consists of the last four

bits of a code-group. When a sub-block is more heavily

weightedwith1’stherunningdisparityispositive,andwhen

it is more heavily weighted with 0’s the running disparity

is negative. When the number of 1’s and 0’s are equal in a

sub-block, the running disparity remains unchanged.

Initial Frame Synchronization

The process of communicating frame synchronization

informationtothereceiverupontherequestofthereceiver.

For JESD204 compliance, K28.5 commas are transmitted

as the preamble. Once the preamble has been detected

the receiver terminates the synchronization request, and

the preamble transmission continues until the end of the

frame. The receiver designates the ﬁrst normal data word

after the preamble to be the start of the data frame.

The polarity of the current running disparity determines

which code-group should be transmitted to maintain DC

balance.Foracompletedescriptionofdisparityrules,refer

to IEEE Std 802.3-2002 part3, Clause 36.2.4.4.

Octet

The 8-bit input to an 8B/10B encoder, or the 8-bit output

from an 8B/10B decoder.

Pseudo Random Bit Sequence (PRBS)

A data sequence having a random nature over a ﬁnite

interval. The most commonly used PRBS test patterns

Run-Length Limited (RLL)

m

The act of limiting the number of consecutive 1’s or 0’s

in a data stream by encoding the data prior to serial

transmission.

may be described by a polynomial in the form of 1 + x +

n

x and have a random nature for the length of up to 2 – 1

bits, where n indicates the order of the PRBS polynomial

and m plays a role in maximizing the length of the random

sequence.

This process guarantees that there will be an adequate

number of transitions in the serial data for the receiver

to lock onto with a phase-locked loop and recover the

high-speed clock.

Scrambler

A logic block that applies a pseudo random bit sequence

to the input octets to minimize the tonal content of the

high-speed serial bit stream.

Running Disparity

In order to maintain DC balance there are two possible

8B/10B output code-groups for each input octet. The

2274f

16

LTC2274

APPLICATIONS INFORMATION

CONVERTER OPERATION

The pipelined ADC of the LTC2274 has two phases of

operation determined by the state of the differential

The core of the LTC2274 is a CMOS pipelined multi-step

converter with a front-end PGA. As shown in Figure 1, the

converterhasﬁvepipelinedADCstages.Asampledanalog

+

–

ENC /ENC input pins. For brevity, the text will refer to

+

–

+

ENC greater than ENC as ENC high and ENC less than

ENC as ENC low.

input will result in a digitized value nine clock cycles later

+

(see the Timing Diagram section). The analog input (A

,

WhenENCislow, theanaloginputissampleddifferentially

ontotheinputsample-and-holdcapacitors,insidethe“S/H

& PGA” block of Figure 1. On the rising edge of ENC, the

voltage on the sample capacitors is held. While ENC is

high, theheldinputvoltageisbufferedbytheS/Hampliﬁer

which drives the ﬁrst pipelined ADC stage. The ﬁrst stage

acquires the output of the S/H ampliﬁer during the high

phase of ENC. On the falling edge of ENC, the ﬁrst stage

producesitsresiduewhichisacquiredbythesecondstage.

The process continues to the end of the pipeline.

IN

–

A

IN

) is differential for improved common mode noise im-

munity and to maximize the input range. Additionally, the

differential input drive will reduce even order harmonics

of the sample and hold circuit. The encode clock input

+

–

(ENC , ENC ) is also differential for improved common

mode noise immunity.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC, and an error residue ampliﬁer. The

functionofeachstageistoproduceadigitalrepresentation

of its input voltage along with the resulting analog error

residue. The ADC of each stage provides the quantization,

andtheresidueisproducedbytakingthedifferencebetween

theinputvoltageandtheoutputofthereconstructionDAC.

Theresidueisampliﬁedbytheresidueampliﬁerandpassed

on to the next stage. The successive stages of the pipeline

operate on alternating phases of the clock so that when

odd stages are outputting their residue, the even stages

are acquiring that residue and vice versa.

Each ADC stage following the ﬁrst has additional error

correctionrangetoaccommodateﬂashandampliﬁeroffset

errors. Results from all of the ADC stages are digitally

delayed such that the results can be properly combined

in the correction logic before being encoded, serialized,

and sent to the output buffer.

2274f

17

LTC2274

APPLICATIONS INFORMATION

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Input Drive Impedance

As with all high performance, high speed ADCs the dy-

namic performance of the LTC2274 can be inﬂuenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and input reactance

can inﬂuence SFDR. At the falling edge of ENC the

sample-and-hold circuit will connect the 4.9pF sampling

capacitor to the input pin and start the sampling period.

The sampling period ends when ENC rises, holding the

sampled input on the sampling capacitor. Ideally, the

input circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

Sample/Hold Operation

Figure2showsanequivalentcircuitfortheLTC2274CMOS

differentialsampleandhold. Thedifferentialanaloginputs

are sampled directly onto sampling capacitors (C

throughNMOStransistors.Thecapacitorsshownattached

)

SAMPLE

to each input (C

) are the summation of all other

PARASITIC

capacitance associated with each input.

During the sample phase when ENC is low, the NMOS

transistors connect the analog inputs to the sampling

capacitors and they charge to, and track, the differential

input voltage. On the rising edge of ENC, the sampled

input voltage is held on the sampling capacitors. During

the hold phase when ENC is high, the sampling capacitors

are disconnected from the input and the held voltage is

passed to the ADC core for processing. As ENC transitions

for high to low, the inputs are reconnected to the sampling

capacitors to acquire a new sample. Since the sampling

capacitorsstillholdtheprevioussample, achargingglitch

proportionaltothechangeinvoltagebetweensampleswill

be seen at this time. If the change between the last sample

and the new sample is small, the charging glitch seen at

the input will be small. If the input change is large, such

as the change seen with input frequencies near Nyquist,

then a larger charging glitch will be seen.

1/(2F

); however, this is not always possible and the

ENCODE

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

LTC2274

V

DD

C

SAMPLE

4.9pF

R

ON

PARASITIC

3Ω

20Ω

+

A

IN

C

PARASITIC

1.8pF

V

Common Mode Bias

DD

C

SAMPLE

4.9pF

R

PARASITIC

3Ω

ON

TheADCsample-and-holdcircuitrequiresdifferentialdrive

toachievespeciﬁedperformance.Eachinputshouldswing

0.5625V for the 2.25V range (PGA = 0) or 0.375V for

the 1.5V range (PGA = 1), around a common mode volt-

20Ω

–

A

IN

C

PARASITIC

1.8pF

V

DD

age of 1.25V. The V output pin (Pin 39) is designed to

CM

provide the common mode bias level. V can be tied

CM

1.6V

6k

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

+

–

ENC

driver circuit. The V pin must be bypassed to ground

CM

close to the ADC with 2.2μF or greater.

6k

1.6V

2274 F02

Figure 2. Equivalent Input Circuit

2274f

18

LTC2274

APPLICATIONS INFORMATION

INPUT DRIVE CIRCUITS

the input bandwidth and increase high frequency distor-

tion. A disadvantage of using a transformer is the loss of

lowfrequencyresponse.MostsmallRFtransformershave

poor performance at frequencies below 1MHz.

Input Filtering

A ﬁrst order RC lowpass ﬁlter at the input of the ADC can

servetwofunctions:limitthenoisefrominputcircuitryand

provide isolation from ADC S/H switching. The LTC2274

has a very broadband S/H circuit, DC to 700MHz; it can

be used in a wide range of applications; therefore, it is not

possible to provide a single recommended RC ﬁlter.

Center-tapped transformers provide a convenient means

of DC biasing the secondary; however, they often show

poor balance at high input frequencies, resulting in large

2nd order harmonics.

Figure 4a shows transformer coupling using a transmis-

sion line balun transformer. This type of transformer has

much better high frequency response and balance than

ﬂux coupled center tap transformers. Coupling capacitors

are added at the ground and input primary terminals to

allowthesecondaryterminalstobebiasedat1.25V. Figure

4b shows the same circuit with components suitable for

higher input frequencies.

Figures 3, 4a and 4b show three examples of input RC

ﬁltering at three ranges of input frequencies. In general

it is desirable to make the capacitors as large as can be

tolerated—this will help suppress random noise as well

as noise coupled from the digital circuitry. The LTC2274

does not require any input ﬁlter to achieve data sheet

speciﬁcations;however,noﬁlteringwillputmorestringent

noise requirements on the input drive circuitry.

V

CM

Transformer Coupled Circuits

2.2μF

5Ω

0.1μF

+

10Ω

Figure 3 shows the LTC2274 being driven by an RF trans-

former with a center-tapped secondary. The secondary

center tap is DC biased with V , setting the ADC input

signal at its optimum DC level. Figure 3 shows a 1:1 turns

ratio transformer. Other turns ratios can be used; however,

astheturnsratioincreasessodoestheimpedanceseenby

the ADC. Source impedance greater than 50Ω can reduce

A

IN

ANALOG

INPUT

LTC2274

0.1μF

25Ω

4.7pF

T1

1:1

CM

4.7pF

–

10Ω

5Ω

4.7pF

T1 = MA/COM ETC1-1-13

2274 F04a

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

V

CM

Figure 4a. Using a Transmission Line Balun Transformer.

Recommended for Input Frequencies from 100MHz to 250MHz

2.2μF

50Ω

+

10Ω

5Ω

A

IN

T1

V

CM

8.2pF

LTC2274

35Ω

2.2μF

5Ω

8.2pF

0.1μF

10Ω

+

A

IN

ANALOG

INPUT

–

5Ω

8.2pF

A

LTC2274

25Ω 0.1μF

25Ω

2.2pF

T1

1:1

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

2274 F03

–

5Ω

2.2pF

T1 = MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

2274 F04b

Figure 3. Single-Ended to Differential Conversion

Using a Transformer. Recommended for Input

Frequencies from 5MHz to 150MHz

Figure 4b. Using a Transmission Line Balun Transformer.

Recommended for Input Frequencies from 250MHz to 500MHz

2274f

19

LTC2274

APPLICATIONS INFORMATION

Direct Coupled Circuits

reference; it will not be stable without this capacitor. The

minimum value required for stability is 2.2μF.

Figure 5 demonstrates the use of a differential ampliﬁer to

convert a single ended input signal into a differential input

signal. The advantage of this method is that it provides

low frequency input response; however, the limited gain

bandwidth of any op amp or closed-loop ampliﬁer will de-

gradetheADCSFDRathighinputfrequencies.Additionally,

wideband op amps or differential ampliﬁers tend to have

high noise. As a result, the SNR will be degraded unless

the noise bandwidth is limited prior to the ADC input.

The internal programmable gain ampliﬁer provides the

internal reference voltage for the ADC. This ampliﬁer has

very stringent settling requirements and is not accessible

for external use.

TheSENSEpincanbedriven 5%aroundthenominal2.5V

or 1.25V external reference inputs. This adjustment range

can be used to trim the ADC gain error or other system

gain errors. When selecting the internal reference, the

SENSE pin should be tied to V as close to the converter

DD

Reference Operation

as possible. If the sense pin is driven externally it should

be bypassed to ground as close to the device as possible

with 1μF (or larger) ceramic capacitor.

Figure6showstheLTC2274referencecircuitryconsisting

of a 2.5V bandgap reference, a programmable gain ampli-

ﬁer and control circuit. The LTC2274 has three modes of

reference operation: Internal Reference, 1.25V external

reference or 2.5V external reference. To use the internal

PGA Pin

The PGA pin selects between two gain settings for

the ADC front-end. PGA = 0 selects an input range of

reference, tie the SENSE pin to V . To use an external

DD

reference, simply apply either a 1.25V or 2.5V reference

2.25V ; PGA = 1 selects an input range of 1.5V . The

P-P

voltagetotheSENSEinputpin.Both1.25Vand2.5Vapplied

2.25V input range has the best SNR; however, the distor-

tion will be higher for input frequencies above 100MHz.

For applications with high input frequencies, the low

input range will have improved distortion; however, the

SNR will be 2.4dB worse. See the Typical Performance

Characteristics section of this datasheet.

to SENSE will result in a full scale range of 2.25V (PGA

P-P

= 0). A 1.25V output V is provided for a common mode

CM

biasforinputdrivecircuitry.Anexternalbypasscapacitoris

requiredfortheV output.Thisprovidesahighfrequency

CM

low impedance path to ground for internal and external

circuitry. This is also the compensation capacitor for the

LTC2274

RANGE

SELECT

V

CM

AND GAIN

2.2μF

12pF

TIE TO V TO USE

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

DD

INTERNAL

ADC

CONTROL

INTERNAL 2.5V

+

–

25Ω

A

REFERENCE

OR INPUT FOR

EXTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 1.25V

REFERENCE

IN

REFERENCE

SENSE

LTC2274

ANALOG

INPUT

+

1x OR 2x

CM

–

2.5V

BANDGAP

REFERENCE

12pF

AMPLIFIER = LTC6600-20,

LTC1993, ETC.

2274 F05

V

CM

1.25V

BUFFER

Figure 5. DC Coupled Input with Differential Ampliﬁer

2.2μF

2274 F06

Figure 6. Reference Circuit

2274f

20

LTC2274

APPLICATIONS INFORMATION

LTC2274

V

DD

TO INTERNAL

ADC CLOCK

DRIVERS

1.6V

6k

V

DD

V

CM

1.25V

+

ENC

2.2μF

LTC2274

1.6V

6k

SENSE

2.2μF

V

DD

6

2, 3

3.3V

1μF

LTC6652-2.5

4, 5, 7, 8

–

ENC

2274 F07

2274 F08a

Figure 7. A 2.25V Range ADC with

an External 2.5V Reference

Figure 8a. Equivalent Encode Input Circuit

0.1μF

+

T1

ENC

50Ω

100Ω

+

ENC

LTC2274

8.2pF

V

= 1.6V

THRESHOLD

0.1μF

–

LTC2274

1.6V

ENC

–

0.1μF

ENC

0.1μF

2274 F09

2274 F08b

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

Figure 8b. Transformer Driven Encode

Figure 9. Single-Ended ENC Drive,

Not Recommended for Low Jitter

3.3V

MC100LVELT22

130Ω

Q0

130Ω

+

ENC

D0

–

LTC2274

ENC

Q0

83Ω

2274 F10

Figure 10. ENC Drive Using a CMOS to PECL Translator

2274f

21

LTC2274

APPLICATIONS INFORMATION

Driving the Encode Inputs

For the ADC to operate properly, the internal CLK signal

should have a 50% duty cycle. A duty cycle stabilizer cir-

cuit has been implemented on chip to facilitate non-50%

ENC duty cycles.

The noise performance of the LTC2274 can depend on

the encode signal quality as much as for the analog input.

The encode inputs are intended to be driven differentially,

primarily for noise immunity from common mode noise

sources. Each input is biased through a 6k resistor to a

1.6V bias. The bias resistors set the DC operating point

fortransformercoupleddrivecircuitsandcansetthelogic

threshold for single-ended drive circuits.

Data Format

The MSBINV pin selects the ADC data format. A low level

selectsoffsetbinaryformat(code0correspondsto–FS,and

code 65535 corresponds to +FS). A high level on MSBINV

selects2’scomplementformat(code–32768corresponds

to –FS and code 32767 corresponds to +FS.

Any noise present on the encode signal will result in ad-

ditional aperture jitter that will be RMS summed with the

inherent ADC aperture jitter.

Shutdown

In applications where jitter is critical (high input frequen-

cies), take the following into consideration:

A high level on both SHDN pins will shutdown the ADC

and the serial interface and place the chip in a low cur-

rent state.

1. Differential drive should be used.

2. Use as large an amplitude possible. If using trans-

former coupling, use a higher turns ratio to increase the

amplitude.

Internal Dither

The LTC2274 is a 16-bit ADC with a very linear transfer

function;however,atlowinputlevelsevenslightimperfec-

tions in the transfer function will result in unwanted tones.

Small errors in the transfer function are usually a result

of ADC element mismatches. An optional internal dither

mode can be enabled to randomize the input location on

the ADC transfer curve, resulting in improved SFDR for

low signal levels.

3. If the ADC is clocked with a ﬁxed frequency sinusoidal

signal, ﬁlter the encode signal to reduce wideband

noise.

4. Balance the capacitance and series resistance at both

encode inputs such that any coupled noise will appear

at both inputs as common mode noise.

As shown in Figure 11, the output of the sample-and-hold

ampliﬁer is summed with the output of a dither DAC. The

dither DAC is driven by a long sequence pseudo-random

number generator; the random number fed to the dither

DAC is also subtracted digitally from the ADC result. If the

dither DAC is precisely calibrated to the ADC, very little

of the dither signal will be seen at the output. The dither

signal that does leak through will appear as white noise.

The dither DAC is calibrated to result in less than 0.5dB

elevation in the noise ﬂoor of the ADC, as compared to

the noise ﬂoor with dither off.

The encode inputs have a common mode range of 1.2V

to V . Each input may be driven from ground to V for

DD

single-ended drive.

Maximum and Minimum Conversion Rates

The maximum conversion rate is 105Msps for the

LTC2274.

The lower limit of the LTC2274 sample rate is determined

by the PLL minimum operating frequency of 20Msps.

2274f

22

LTC2274

APPLICATIONS INFORMATION

LTC2274

+

AIN

CMLOUT

16-BIT

PIPELINED

ADC CORE

DIGITAL

SUMMATION

8b10b

ENCODER

ANALOG

INPUT

S/H

AMP

SERIALIZER

–

AIN

CMLOUT

CLOCK/DUTY

CYCLE

CONTROL

MULTIBIT DEEP

PSEUDO-RANDOM

NUMBER

PRECISION

DAC

GENERATOR

2274 F11

+

–

ENC

DITH

DITHER ENABLE

HIGH = DITHER ON

LOW = DITHER OFF

Figure 11. Functional Equivalent Block Diagram of Internal Dither Circuit

SERIALIZED DATA FRAME

Figure12illustratesthegenerationofonecomplete8B/10B

frame. The 8 most signiﬁcant bits of the ADC are assigned

to the ﬁrst half of the frame, and the remaining 8 bits

to the second half of the frame. Next, the two resulting

octets are optionally scrambled and encoded into their

corresponding 8B/10B code. Finally, the two 10-bit code

groups are serialized and transmitted beginning with Bit

0 of code group 1.

Prior to serialization, the ADC data is encoded into the

8B/10B format, which is DC balanced, and run-length

limited. The receiver is required to lock onto the data

and recover the clock with the use of a PLL. The 8B/10B

format requires that the ADC data be broken up into 8-bit

blocks (octets), which is encoded into 10-bit code groups

applying the 8B/10B rules (refer to IEEE Std 802.3-2002

Part 3, for a complete 8B/10B description).

MSB

ADC OUTPUT WORD

LSB

BIT

15

BIT

14

BIT

13

BIT

12

BIT

11

BIT

10

BIT

9

BIT

8

BIT

7

BIT

6

BIT

5

BIT

4

BIT

3

BIT

2

BIT

1

BIT

0

OCTET

ASSIGNMENT

H

G

F

E

D

C

B

A

H

G

F

E

D

C

B

A

BIT

7

BIT

6

BIT

5

BIT

4

BIT

3

BIT

2

BIT

1

BIT

0

BIT

7

BIT

6

BIT

5

BIT

4

BIT

3

BIT

2

BIT

1

BIT

0

FIRST OCTET

SECOND OCTET

OPTIONAL

SCRAMBLER

H

G

F

E

D

C

B

A

H

G

F

E

D

C

B

A

BIT

7

BIT

6

BIT

5

BIT

4

BIT

3

BIT

2

BIT

1

BIT

0

BIT

7

BIT

6

BIT

5

BIT

4

BIT

3

BIT

2

BIT

1

BIT

0

FIRST SCRAMBLED OCTET

SECOND SCRAMBLED OCTET

8B/10B

ENCODER

a

b

c

d

e

i

f

g

h

j

a

b

c

d

e

i

f

g

h

j

BIT

0

BIT

1

BIT

2

BIT

3

BIT

4

BIT

5

BIT

6

BIT

7

BIT

8

BIT

9

BIT

0

BIT

1

BIT

2

BIT

3

BIT

4

BIT

5

BIT

6

BIT

7

BIT

8

BIT

9

8B/10B CODE GROUP 1

8B/10B CODE GROUP 2

ONE FRAME

SERIAL OUT

BIT 0 OF CODE GROUP 1 IS TRANSMITTED FIRST

2274 F12

Figure 12. Evolution of One Transmitted Frame (Compare to IEEE Std 802.3-2002 Part 3, Figure 36-3)

2274f

23

LTC2274

APPLICATIONS INFORMATION

t

N + 9

AP

N + 2

N + 10

ANALOG INPUT

N

N + 8

N + 1

t

CONV

+

ENC

t

H

t

L

INTERNAL

PARALLEL DATA

N – 6

N – 9

N – 5

N – 8

N – 4

N – 7

N + 3

N

N + 4

N + 1

INTERNAL

8B/10B DATA

LAT

P

t

BIT

SERIAL DATA OUT

N – 10

N – 9

N – 8

N – 1

N

2274 F13

Figure 13. Timing Relationship of Analog Sample to Serial Data Out

Initial Frame Synchronization

• The receiver searches for the expected preamble and

waits for the correct reception of an adequate number

of preamble characters.

In the absence of a frame clock, it is necessary to deter-

mine the start of each frame through a synchronization

process. To establish frame synchronization, Figures 14

and 15 illustrate the following sequence:

• The receiver deactivates the synchronization request.

• Upon detecting the deactivation of the synchroniza-

tion request, the LTC2274 continues to transmit the

synchronization preamble until the end of the frame.

• The receiver issues a synchronization request via the

synchronization interface.

• If the synchronization request is active for more than

one ENC clock cycle, the LTC2274 will transmit a

synchronization preamble. When the ISMODE pin is

low the transmitted preamble will consist of consecu-

tive K28.5 comma symbols in conformance with the

JESD204 speciﬁcation. When the ISMODE pin is high,

a series of idle ordered sets will be transmitted. The

idle ordered sets consist of a K28.5 comma followed by

either D5.6 or D16.2 as deﬁned in IEEE Std 802.3-2002

part3, Clause 36.2.4.12.

• At the start of the next frame, the LTC2274 will begin

transmitting data characters.

• Thereceiverdesignatestheﬁrstdatacharacterreceived

after the preamble transmission to be the start of the

frame. The ﬁrst octet of the frame contains the most

signiﬁcant byte of the ADC’s output word.

2274f

24

LTC2274

APPLICATIONS INFORMATION

t

CONV

N + 3

N

N – 1

N + 2

N + 4

N + 5

ANALOG INPUT

N + 1

t

SU

HD

+

ENC

CS(MIN)

+

SYNC

LAT

t

SC

CS(MAX)

SERIAL DATA OUT

N – 10

N – 9

N – 8

N – 7

K28.5 (x2)

2274 F14a

Figure 14a. SYNC⁺Low Transition to Comma Output Timing (ISMODE is Low)

t

CONV

N + 3

N

N – 1

N + 2

N + 4

ANALOG INPUT

N + 1

t

SU

HD

+

ENC

t

CS(MIN)

+

SYNC

LAT

t

SD

CS(MAX)

SERIAL DATA OUT

K28.5 (x2)

N – 7

N – 6

2274 F14b

Figure 14b. SYNC⁺High Transition to Data Output Timing (ISMODE is Low)

2274f

25

LTC2274

APPLICATIONS INFORMATION

START

WAIT FOR NEXT

FRAME CLOCK

SYNC

REQUEST?

NO

YES

NO

YES

IS ISMODE

ENABLED?

DATA TRANSMISSION

FLOW (SEE FIGURE 18)

NO

YES

NEGATIVE

DISPARITY?

TRANSMIT K28.5

AS CODE GROUP 1

TRANSMIT K28.5

AS CODE GROUP 2

(DISPARITY NOT OK)

(DISPARITY IS OK)

TRANSMIT K28.5

AS CODE GROUP 1

TRANSMIT K28.5

AS CODE GROUP 1

(NEGATIVE DISPARITY)

(POSITIVE DISPARITY)

TRANSMIT D5.6

AS CODE GROUP 2

TRANSMIT D16.2

AS CODE GROUP 2

(NEGATIVE DISPARITY)

2274 F15

Figure 15. Initial Synchronization Flow Diagram

Scrambling

The scrambled data is converted into two valid 8B/10B

code groups, constituting a complete frame. The 8B/10B

code groups are then serialized and transmitted.

To avoid spectral interference from the serial data output,

an optional data scrambler is added between the ADC

data and the 8B/10B encoder to randomize the spectrum

of the serial link. The scrambler is enabled by setting the

SCRAM pin to a high logic level. The polynomial used for

the scrambler is 1 + x + x , which is a pseudo-random

pattern repeating itself every 2 –1. Figure 16 illustrates

The receiver is required to deserialize the data, decode

the code-groups into octets and descramble them back

to the original octets using the self-aligning descrambler

shown in Figure 17. This descrambler is shown in 16-bit

parallel form, which is an efﬁcient implementation of the

14

15

14

15

the LTC2274 implementation of this polynomial in parallel

form.

(1 + x + x ) polynomial, operating at the frame clock

rate (ADC sample rate).

2274f

26

LTC2274

APPLICATIONS INFORMATION

SAMPLE_CLK

Q

D0

D1

D2

SS0

SS1

SS2

SS3

SS4

SS5

SS6

SS7

SF0

SF1

SF2

SF3

SF4

SF5

SF6

D

C

FF

Q

D

C

FF

D

C

D3

SECOND

OCTET

SECOND

SCRAMBLED

OCTET

D

C

D4

D5

D6

D

C

D

C

D

C

D7

FROM

TO 8B/10B

ENCODER

D

C

ADC

D8

D

C

D9

D10

D11

D

C

D

C

FIRST

SCRAMBLED

OCTET

FIRST

OCTET

D

C

D12

D13

D

C

D

C

D

C

D15

MSB

SF7

MSB

2274 F16

Figure 16. LTC2274 16-Bit 1 + x¹⁴+ x¹⁵Parallel Scrambler

2274f

27

LTC2274

APPLICATIONS INFORMATION

FRAME_CLK

LSB

D0

SS0

SS1

SS2

D

C

Q

FF

D1

D2

D3

D4

D5

D

C

D

C

SS3

SECOND

SCRAMBLED

OCTET

D

C

SS4

SS5

SS6

D

C

D

C

D6

D7

D

C

SS7

FROM

D

C

DESCRAMBLED

ADC DATA

8B/10B

DECODER

D8

SF0

SF1

SF2

D

C

D9

D

C

D10

D11

D12

D13

D14

D

C

SF3

FIRST

SCRAMBLED

OCTET

D

C

SF4

SF5

SF6

D

C

D

C

D

C

D15

MSB

SF7

MSB

2274 F17

Figure 17. Required 16-Bit 1 + x¹⁴+ x¹⁵Parallel Descrambler

2274f

28

LTC2274

APPLICATIONS INFORMATION

Frame Alignment Monitoring

previous frame, the LTC2274 will replace the second

code group with the control character K28.7 before

serialization. However, if a K28.7 symbol was already

transmittedinthepreviousframe,theactualcodegroup

will be transmitted.

Aftertheinitialsynchronizationhasbeenestablished,itmay

be desirable to periodically verify that frame alignment is

being maintained. The receiver may issue a synchroniza-

tion request at any time, but data will be lost during the

resynchronization interval.

• Upon receiving a K28.7 symbol, the receiver is required

to replace it with the data decoded at the same position

of the previous frame.

To verify frame alignment without the loss of data, frame

alignment monitoring is enabled by setting the FAM pin

to a high level. In this mode, predetermined data in the

second code group of the frame is substituted with the

control character K28.7. The receiver is required to detect

the K28.7 character and replace it with the original data. In

this way, the second code group may be discerned from

the ﬁrst, and the receiver is able to periodically verify the

frame alignment without the loss of data (refer to Table 1

and the ﬂow diagram of Figure 18). There are two frame

alignment monitoring modes summarized in Table 1.

FAM mode 2 is implemented when FAM is high and

SCRAM is high:

• When the data in the second code group of the current

frame equals D28.7, the LTC2274 will replace this data

with K28.7 before serialization.

• Upon receiving a K28.7 symbol, the receiver is required

to replace it with D28.7.

With FAM enabled the receiver is required to search for

the presence of K28.7 symbols in the data stream. If two

successive K28.7 symbols are detected at the same posi-

tion other than the assumed end of frame, the receiver will

realign its frame boundary to the new position.

FAM mode 1 is implemented when FAM is high, and

SCRAM is low:

• When the data in the second code group of the current

frame equals the data in the second code group of the

Table 1. Frame Alignment Monitoring Modes

SCRAM PIN

DDSYNC PIN

ACTION

FAM Mode 1

Low

High

The second code group is replaced with K28.7 if

nd

it is equal to the 2 Code Group of the previous

frame

FAM Mode 2

High

The second code group is replaced with K28.7 if

it is equal to D28.7

FAM OFF

X

Low

No K28.7 substitutions will take place

2274f

29

LTC2274

APPLICATIONS INFORMATION

START

SCRAMBLE ADC DATA

IF SCRAM IS ENABLED

GENERATE 8B/10B

CODE-GROUPS 1 AND 2

NO

YES (FRAME ALIGNMENT MONITORING IS ENABLED)

IS FAM

ENABLED?

TRANSMIT

CODE GROUP 1

TRANSMIT

CODE GROUP 1

NO

YES

NO

(DATA SCRAMBLING IS ENABLED)

IS CODE

IS SCRAM

ENABLED?

TRANSMIT

CODE GROUP 2

IS CODE

GROUP 2 =

CODE GROUP 2

OF LAST

GROUP 2 =

D28.7?

YES

NO

YES

FRAME?

TRANSMIT

CODE GROUP 2

TRANSMIT

CODE GROUP 2

TRANSMIT K28.7

AS CODE GROUP 2

WAS K28.7

TRANSMITTED

IN LAST

NO

YES

FRAME?

TRANSMIT K28.7

AS CODE GROUP 2

TRANSMIT

CODE GROUP 2

END

2274 F18

Figure 18. Data Transmission Flow Diagram

PLL Operation

Serial Test Patterns

ThePLL hasbeendesignedtoaccommodate awide range

of sample rates. The SRR0 and SRR1 pins are used to

conﬁgure the PLL for the intended sample rate range.

Table 2 summarizes the sample clock ranges available

to the user.

Tofacilitatetestingoftheserialinterface,threetestpatterns

are selectable via pins PAT0 and PAT1. The available test

patterns are described in Table 3. A K28.5 comma may be

usedasafourthtestpatternbyrequestingsynchronization

+

–

through the SYNC /SYNC pins.

Table 2. Sample Rate Ranges

Table 3. Test Patterns

SRR1

SRR0

SAMPLE RATE RANGE

20Msps > FS ≥ 35Msps

30Msps > FS ≥ 65Msps

60Msps > FS ≥ 105Msps

PAT1

PAT0

TEST PATTERNS

0

1

x

0

1

0

1

ADC Data

1010101010 Pattern

(8B/10B Code Group D21.5)

9

11

1

0

1

1+ x + x Pseudo Random Pattern

14

15

1+ x + x Pseudo Random Pattern

2274f

30

LTC2274

APPLICATIONS INFORMATION

High Speed CML Outputs

Grounding and Bypassing

The CML outputs must be terminated for proper opera-

The LTC2274 require a printed circuit board with a

clean unbroken ground plane; a multilayer board with an

internal ground plane is recommended. The pinout of the

LTC2274 has been optimized for a ﬂowthrough layout so

that the interaction between inputs and digital outputs is

minimized. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track

or underneath the ADC.

tion. The OV supply voltage and the termination voltage

DD

determine the common mode output level of the CML

outputs. ForproperoperationoftheCMLdriver, theoutput

common mode voltage should be greater than 1V.

The directly-coupled termination mode of Figure 19a is

recommended when the receiver termination voltage is

within the range of 1.2V to 3.3V. When the CML outputs

are directly-coupled to the 50Ω termination resistors, the

OV supply voltage serves as the receiver termination

DD

voltage, and the output common mode voltage will be

High quality ceramic bypass capacitors should be used

approximately 200mV lower than OV .

DD

at the V

V

, and OV pins. Bypass capacitors must

DD, CM DD

be located as close to the pins as possible. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The directly-coupled differential termination of Figure 19b

maybeusedintheabsenceofareceiverterminationvoltage

within the required range. In this case, the common mode

voltage is shifted down to approximately 400mV below

The LTC2274 differential inputs should run parallel and

close to each other. The input traces should be as short

as possible to minimize capacitance and to minimize

noise pickup.

OV , requiring an OV in the range of 1.4V to 3.3V.

DD

If the serial receiver’s common mode input requirements

are not compatible with the directly-coupled termination

modes, the DC balanced 8B/10B encoded data will permit

the addition of DC blocking capacitors as shown in Figure

19c. In this AC-coupled mode, the termination voltage is

determined by the receiver’s requirements. The coupling

capacitorsshouldbeselectedappropriatelyfortheintended

operating bit-rate, usually between 1nF to 10nF. In the AC-

coupled mode, the output common mode voltage will be

Heat Transfer

Most of the heat generated by the LTC2274 is transferred

from the die through the bottom-side exposed pad. For

good electrical and thermal performance, the exposed

pad must be soldered to a large grounded pad on the PC

board. It is critical that the exposed pad and all ground

pins are connected to a ground plane of sufﬁcient area

with as many vias as possible.

approximately 400mV below OV , so the OV supply

DD

voltage should be in the range of 1.4V to 3.3V.

2274f

31

LTC2274

APPLICATIONS INFORMATION

SERIAL CML DRIVER

SERIAL CML RECEIVER

1.2V TO 3.3V

OV

DD

+

50Ω

TRANSMISSION LINE

CMLOUT

–

CMLOUT

+

–

DATA

50Ω

TRANSMISSION LINE

16mA

GND

2274 F19a

Figure 19a. CML Termination, Directly-Coupled Mode (Preferred)

SERIAL CML DRIVER

SERIAL CML RECEIVER

OV

DD

+

1.4V TO 3.3V

50Ω

TRANSMISSION LINE

CMLOUT

100Ω

–

CMLOUT

+

–

DATA

50Ω

TRANSMISSION LINE

16mA

GND

2274 F19b

Figure 19b. CML Termination, Directly-Coupled Differential Mode

2274f

32

LTC2274

APPLICATIONS INFORMATION

SERIAL CML DRIVER

SERIAL CML RECEIVER

1.4V TO 3.3V

VTERM

OV

DD

50Ω

0.01μF

TRANSMISSION LINE

+

CMLOUT

0.01μF

–

+

–

DATA

50Ω

TRANSMISSION LINE

16mA

GND

2274 F19c

Figure 19c. CML Termination, AC-Coupled Mode

2274f

33

LTC2274

TYPICAL APPLICATIONS

Silkscreen Top

Top Side

2274f

34

LTC2274

TYPICAL APPLICATIONS

Inner Layer 2

Inner Layer 3

2274f

35

LTC2274

TYPICAL APPLICATIONS

Inner Layer 4

Inner Layer 5

2274f

36

LTC2274

TYPICAL APPLICATIONS

Bottom Side

Silkscreen Bottom

2274f

37

LTC2274

TYPICAL APPLICATIONS

C C

V

G N D

C C

V

S S

V

D D

V

S C R A M P 0

S S

V

M F A

P D S E R

P D A D C

P 1

P 2

P 3

M S B I N V P 4

N C

P G A

1 T P A

0 T P A

P 5

P 6

P 7

C C

V

S S

V

P B U S 1 5

P B U S 1 4

R X D 1 5

R X D 1 4

T X D 1 5

G N D

P B U S 1 3

P B U S 1 2

R X D 1 3

R X D 1 2

T X D 1 4

T X D 1 3

T X D 1 2

T X D 1 1

G N D

P B U S 1 1

P B U S 1 0

R X D 1 1

R X D 1 0

D D

V

D D

V

P B U S 9

P B U S 8

R X D 9

R X D 8

D I T H

P 0

T X D 1 0

T X D 9

S S

V

I S M O D E P 1

P L L 0

P 2

P 3

P 4

P 5

P 6

P 7

T X D 8

R X _ C L K

R X D 7

D D

V

P L L 1

P B U S 7

R X _ E R

N C

G T X _ C L K

T X D 7

T X D 6

G N D

P B U S 6

P B U S 5

R X D 6

R X D 5

T X D 5

T X D 4

T X D 3

P B U S 4

P B U S 3

R X D 4

R X D 3

D D

V

D D

V

P B U S 2

R X D 2

T X D 2

T X D 1

T X D 0

P B U S 1

P B U S 0

R X D 1

R X D 0

M S B I N V

P G A

1 T P A

0 T P A

S C R A M

M F A

P D S E R

P D A D C

P L L 1

P L L 0

I S M O D E

D I T H

G N D

O G N D

D D

O V

G N D

D D

V

D D

V

D D

V

D D

V

•

G P

G N D

2274f

38

LTC2274

PACKAGE DESCRIPTION

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 p0.05

6.50 p0.05

5.10 p0.05

4.42 p0.05

4.50 p0.05

(4 SIDES)

4.42 p0.05

PACKAGE OUTLINE

0.25 p0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 p 0.05

R = 0.115

TYP

6.00 p 0.10

(4 SIDES)

R = 0.10

TYP

39 40

0.40 p 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.45 OR

0.35 s 45o

CHAMFER

4.42 p0.10

4.50 REF

(4-SIDES)

4.42 p0.10

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 p 0.05

0.00 – 0.05

0.50 BSC

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

2274f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

39

LTC2274

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTC1993-2

LTC1994

High Speed Differential Op Amp

800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain

Low Distortion: –94dBc at 1MHz

Low Noise, Low Distortion Fully Differential Input/

Output Ampliﬁer/Driver

LTC2215

LTC2216

LTC2217

LTC2202

LTC2203

LTC2204

LTC2205

LTC2206

LTC2207

LTC2208

LTC2209

LTC2220

LTC2220-1

LTC2224

LTC2249

LTC2250

LTC2251

LTC2252

LTC2253

LTC2254

LTC2255

LTC2284

LTC2299

LTC5512

16-Bit, 65Msps, Low Noise ADC

16-Bit, 80Msps, Low Noise ADC

16-Bit, 105Msps, Low Noise ADC

16-Bit, 10Msps, 3.3V ADC, Lowest Noise

16-Bit, 25Msps, 3.3V ADC, Lowest Noise

16-Bit, 40Msps, 3.3V ADC

700mW, 81.5dB SNR, 100dB SFDR, 64-Pin QFN

970mW, 81.3dB SNR, 100dB SFDR, 64-Pin QFN

1190mW, 81.2dB SNR, 100dB SFDR, 64-Pin QFN

140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN

220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN

480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN

590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN

725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN

900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN

1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN

1.45W, 77.1dB SNR, 100dB SFDR, 64-Pin QFN

890mW, 67.5dB SNR, 9mm × 9mm QFN Package

910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN

630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN

230mW, 73dB SNR, 5mm × 5mm QFN Package

320mW, 61.6dB SNR, 5mm × 5mm QFN Package

395mW, 61.6dB SNR, 5mm × 5mm QFN Package

320mW, 70.2dB SNR, 5mm × 5mm QFN Package

395mW, 70.2dB SNR, 5mm × 5mm QFN Package

320mW, 72.5dB SNR, 5mm × 5mm QFN Package

395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN

540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN

230mW, 71.6dB SNR, 5mm x 5mm QFN Package

DC to 3GHz, 21dBm IIP3, Integrated LO Buffer

16-Bit, 65Msps, 3.3V ADC

16-Bit, 80Msps, 3.3V ADC

16-Bit, 105Msps, 3.3V ADC

16-Bit, 130Msps, 3.3V ADC, LVDS Outputs

16-Bit, 160Msps, ADC, LVDS Outputs

12-Bit, 170Msps ADC

12-Bit, 185Msps, 3.3V ADC, LVDS Outputs

12-Bit, 135Msps, 3.3V ADC, High IF Sampling

14-Bit, 80Msps ADC

10-Bit, 105Msps ADC

10-Bit, 125Msps ADC

12-Bit, 105Msps ADC

12-Bit, 125Msps ADC

14-Bit, 105Msps ADC

14-Bit, 125Msps, 3V ADC, Lowest Power

14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk

Dual 14-Bit, 80Msps ADC

DC-3GHz High Signal Level

Downconverting Mixer

LTC5515

LTC5516

LTC5517

LTC5522

LTC5527

LTC5579

LTC6400-20

1.5 GHz to 2.5GHz Direct Conversion Quadrature

Demodulator

High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator

High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator

High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

800MHz to 1.5GHz Direct Conversion Quadrature

Demodulator

40MHz to 900MHz Direct Conversion Quadrature

Demodulator

600MHz to 2.7GHz High Linearity Downconverting

Mixer

4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,

NF = 12.5dB, 50Ω Single-Ended RF and LO Ports

400MHz to 3.7GHz High Signal Level

Downconverting Mixer

4.5V to 5.25V Supply, 23.5dBm IIP3 at 1900MHz, I = 78mA,

CC

Conversion Gain = 2dB

1.5GHz to 3.8GHz High Linearity Upconverting

Mixer

3.3V Supply, 27.3dBm OIP3 at 2.14GHz, Conversion Gain = 2.6dB at 2.14GHz

1.8GHz Low Noise, Low Distortion Differential ADC

Driver for 300MHz IF

Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package

2274f

LT 1008 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

40

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2274CUJ-TRPBF
厂家：	Linear
描述：	16-Bit, 105Msps Serial Output ADC 16位，105Msps串行输出ADC
文件：	总40页 (文件大小：897K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2274CUJ-TRPBF [Linear]

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