LTC1966_技术文档

LTC1966

Precision Micropower,

∆Σ RMS-to-DC Converter

U

FEATURES

DESCRIPTIO

The LTC^®1966 is a true RMS-to-DC converter that utilizes

an innovative patented ∆Σ computational technique. The

internaldelta-sigmacircuitryoftheLTC1966makesitsim-

pler to use, more accurate, lower power and dramatically

more flexible than conventional log-antilog RMS-to-DC

converters.

■

No-Hassle Simplicity:

True RMS-DC Conversion with Only One External

Capacitor

Delta Sigma Conversion Technology

High Accuracy:

0.1% Gain Accuracy from 50Hz to 1kHz

0.25% Total Error from 50Hz to 1kHz

High Linearity:

■

The LTC1966 accepts single ended or differential input

signals (for EMI/RFI rejection) and supports crest factors

up to 4. Common mode input range is rail-to-rail. Differ-

ential input range is 1V_PEAK, and offers unprecedented lin-

earity. Unlike previously available RMS-to-DC converters,

the superior linearity of the LTC1966 allows hassle-free

system calibration at any input voltage.

■

0.02% Linearity Allows Simple System Calibration

■

Low Supply Current:

155µA Typ, 170µA Max

Ultralow Shutdown Current:

0.1µA

Constant Bandwidth:

Independent of Input Voltage

800kHz –3dB, 6kHz ±1%

Flexible Supplies:

2.7V to 5.5V Single Supply

Up to ±5.5V Dual Supply

Flexible Inputs:

■

The LTC1966 also has a rail-to-rail output with a separate

output reference pin providing flexible level shifting. The

LTC1966 operates on a single power supply from 2.7V to

5.5V or dual supplies up to ±5.5V. A low power shutdown

mode reduces supply current to 0.5µA.

■

The LTC1966 is insensitive to PC board soldering and

stresses, as well as operating temperature. The LTC1966

is packaged in the space-saving MSOP package which is

ideal for portable applications.

Differential or Single Ended

Rail-to-Rail Common Mode Voltage Range

Up to 1V_PEAKDifferential Voltage

Flexible Output:

■

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Rail-to-Rail Output

APPLICATIO S

Separate Output Reference Pin Allows Level Shifting

Small Size:

■

True RMS Digital Multimeters and Panel Meters

■

True RMS AC + DC Measurements

Space Saving 8-Pin MSOP Package

, LTC and LT are registered trademarks of Linear Technology Corporation.

Protected under U.S. Patent Numbers 6,359,576 and 6,362,677

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TYPICAL APPLICATIO

Quantum Leap in Linearity Performance

0.2

LTC1966, ∆Σ

Single Supply RMS-to-DC Converter

0

2.7V TO 5.5V

–0.2

–0.4

V

DD

OUTPUT

LTC1966

OUT RTN

GND

IN1

IN2

C

DIFFERENTIAL

INPUT

+

–

AVE

V

OUT

–0.6

–0.8

–1.0

CONVENTIONAL

LOG/ANTILOG

1µF

1966 TA01

EN

V

SS

0.1µF

OPT. AC

COUPLING

60Hz SINEWAVES

50 100 150 200 250 300 350 400 450 500

(mV AC

0

V

)

RMS

IN

1966 TA01b

sn1966 1966fas

1

LTC1966

W W

U W

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

ORDER PART

Supply Voltage

NUMBER

TOP VIEW

V_DDto GND .............................................. –0.3 to 7V

GND

IN1

IN2

1

2

3

4

8 ENABLE

7 V

6 OUT RTN

V

_DDto V_SS............................................ –0.3V to 12V

LTC1966CMS8

LTC1966IMS8

DD

V_SSto GND............................................. –7V to 0.3V

Input Currents (Note 2) ..................................... ±10mA

Output Current (Note 3)..................................... ±10mA

ENABLE Voltage ..................... V_SS– 0.3V to V_SS+ 12V

OUT RTN Voltage.............................. V_SS– 0.3V to V_DD

Operating Temperature Range (Note 4)

5 V

V

SS

OUT

MS8 PACKAGE

8-LEAD PLASTIC MSOP

MS8 PART MARKING

T_JMAX= 150°C, θ_JA= 220°C/ W

LTTG

LTTH

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTC1966C/LTC1966I ......................... –40°C to 85°C

Specified Temperature Range (Note 5)

LTC1966C/LTC1966I ......................... –40°C to 85°C

Maximum Junction Temperature ......................... 150°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are T_A= 25°C. V_DD= 5V, V_SS= –5V, V_OUTRTN= 0V, C_AVE= 10µF, V_IN= 200mV_RMS

V_ENABLE= 0.5V unless otherwise noted.

,

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Conversion Accuracy

G

Conversion Gain Error

Output Offset Voltage

50Hz to 1kHz Input (Notes 6, 7)

(Notes 6, 7)

±0.1

±0.3

±0.4

%

ERR

●

V

OOS

0.1

0.2

0.4

mV

●

LIN

Linearity Error

50mV to 350mV (Notes 7, 8)

(Note 9)

0.02

0.15

%

ERR

PSRR

Power Supply Rejection

0.15

0.20

%/V

●

V

IOS

Input Offset Voltage

(Notes 6, 7, 10)

0.2

0.8

1.0

mV

Accuracy vs Crest Factor (CF)

CF = 4

60Hz Fundamental, 200mV

(Note 11)

●

–1

2

mV

RMS

CF = 5

–20

30

Input Characteristics

I

Input Voltage Range

Input Impedance

●

V

DD

V

VR

SS

Z

Average, Differential (Note 12)

Average, Common Mode (Note 12)

8

100

MΩ

IN

CMRRI

Input Common Mode Rejection

Maximum Input Swing

Minimum RMS Input

(Note 13)

●

7

200

5

µV/V

V

IMAX

V

IMIN

Accuracy = 1% (Note 14)

1

1.05

mV

PSRRI

Power Supply Rejection

V

DD

V

SS

Supply (Note 9)

●

250

120

600

300

µV/V

sn1966 1966fas

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LTC1966

ELECTRICAL CHARACTERISTICS

V_ENABLE= 0.5V unless otherwise noted.

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are T_A= 25°C. V_DD= 5V, V_SS= –5V, V_OUTRTN= 0V, C_AVE= 10µF, V_IN= 200mV_RMS

,

SYMBOL

Output Characteristics

OVR Output Voltage Range

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

●

V

kΩ

SS

DD

Z

Output Impedance

(Note 12)

75

85

16

95

OUT

CMRRO

Output Common Mode Rejection

Maximum Differential Output Swing

(Note 13)

200

µV/V

V

Accuracy = 2%, DC Input (Note 14)

1.0

0.9

1.05

V

OMAX

●

PSRRO

Power Supply Rejection

V

Supply (Note 9)

●

250

50

1000

500

µV/V

DD

SS

Frequency Response

f

1% Additional Error (Note 15)

10% Additional Error (Note 15)

±3dB Frequency (Note 15)

C

= 10µF

6

kHz

1P

AVE

20

10P

–3dB

800

Power Supplies

V

Positive Supply Voltage

Negative Supply Voltage

Positive Supply Current

●

2.7

5.5

0

V

DD

SS

(Note 16)

–5.5

I

IN1 = 20mV, IN2 = 0V

IN1 = 200mV, IN2 = 0V

155

158

170

µA

DD

I

Negative Supply Current

IN1 = 20mV, IN2 = 0V

●

12

20

10

µA

SS

Shutdown Characteristics

I

Supply Currents

V

= 4.5V

= 0.5V

●

0.5

–0.1

–0.05

–1

µA

DDS

SSS

IH

ENABLE

Supply Currents

–1

–0.3

–2

ENABLE Pin Current High

ENABLE Pin Current Low

ENABLE Threshold Voltage

–0.1

IL

V

= 5V, V = –5V

2.4

2.1

1.3

V

TH

DD

SS

= 5V, V = GND

SS

= 2.7V, V = GND

SS

V

ENABLE Threshold Hysteresis

0.1

V

HYS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 7: High speed automatic testing cannot be performed with 60Hz

inputs. The LTC1966 is 100% tested with DC and 10kHz input signals.

Measurements with DC inputs from 50mV to 350mV are used to calculate

Note 2: The inputs (IN1, IN2) are protected by shunt diodes to V and

SS

the four parameters: G , V , V and linearity error. Correlation tests

ERR OOS IOS

V

. If the inputs are driven beyond the rails, the current should be limited

DD

have shown that the performance limits above can be guaranteed with the

additional testing being performed to guarantee proper operation of all

internal circuitry.

Note 8: The LTC1966 is inherently very linear. Unlike older log/antilog

circuits, its behavior is the same with DC and AC inputs, and DC inputs are

used for high speed testing.

to less than 10mA.

Note 3: The LTC1966 output (V ) is high impedance and can be

OUT

overdriven, either sinking or sourcing current, to the limits stated.

Note 4: The LTC1966C/LTC1966I are guaranteed functional over the

operating temperature range of –40°C to 85°C.

Note 5: The LTC1966C is guaranteed to meet specified performance from

0°C to 70°C. The LTC1966C is designed, characterized and expected to

meet specified performance from –40°C to 85°C but is not tested nor QA

sampled at these temperatures. The LTC1966I is guaranteed to meet

specified performance from –40°C to 85°C.

Note 9: The power supply rejections of the LTC1966 are measured with

DC inputs from 50mV to 350mV. The change in accuracy from V = 2.7V

DD

to V = 5.5V with V = 0V is divided by 2.8V. The change in accuracy

DD

SS

from V = 0V to V = –5.5V with V = 5.5V is divided by 5.5V.

SS

DD

Note 10: Previous generation RMS-to-DC converters required nonlinear

input stages as well as a nonlinear core. Some parts specify a “DC reversal

error,” combining the effects of input nonlinearity and input offset voltage.

The LTC1966 behavior is simpler to characterize and the input offset

voltage is the only significant source of “DC reversal error.”

Note 6: High speed automatic testing cannot be performed with

C

= 10µF. The LTC1966 is 100% tested with C = 22nF. Correlation

AVE

tests have shown that the performance limits above can be guaranteed

with the additional testing being performed to guarantee proper operation

of all the internal circuitry.

sn1966 1966fas

3

LTC1966

ELECTRICAL CHARACTERISTICS

Note 11: High speed automatic testing cannot be performed with 60Hz

inputs. The LTC1966 is 100% tested with DC stimulus. Correlation tests

have shown that the performance limits above can be guaranteed with the

additional testing being performed to verify proper operation of all internal

circuitry.

Note 14: The LTC1966 input and output voltage swings are limited by

internal clipping. However, its ∆Σ topology is relatively tolerant of

momentary internal clipping. The input clipping is tested with a crest

factor of 2, while the output clipping is tested with a DC input.

Note 15: The LTC1966 exploits oversampling and noise shaping to reduce

the quantization noise of internal 1-bit analog-to-digital conversions. At

higher input frequencies, increasingly large portions of this noise are

aliased down to DC. Because the noise is shifted in frequency, it becomes

a low frequency rumble and is only filtered at the expense of increasingly

long settling times. The LTC1966 is inherently wideband, but the output

accuracy is degraded by this aliased noise. These specifications apply with

Note 12: The LTC1966 is a switched capacitor device and the input/output

impedance is an average impedance over many clock cycles. The input

impedance will not necessarily lead to an attenuation of the input signal

measured. Refer to the Applications Information section titled “Input

Impedance” for more information.

Note 13: The common mode rejection ratios of the LTC1966 are measured

with DC inputs from 50mV to 350mV. The input CMRR is defined as the

C

= 10µF and constitute a 3-sigma variation of the output rumble.

AVE

change in V measured between input levels of V to V + 350mV and

Note 16: The LTC1966 can operate down to 2.7V single supply but cannot

operate at ±2.7V. This additional constraint on V can be expressed

IOS

SS

input levels of V – 350mV to V divided by V – V – 350mV. The

DD

SS

output CMRR is defined as the change in V

measured with OUT RTN =

mathematically as –3 • (V – 2.7V) ≤ V ≤ Ground.

OOS

DD

SS

V

and OUT RTN = V – 350mV divided by V – V – 350mV.

SS

DD DD SS

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TYPICAL PERFOR A CE CHARACTERISTICS

Gain and Offset

vs Input Common Mode

0.5

0.4

0.5

0.4

0.5

V

DD

V

SS

= 5V

= GND

V

DD

V

SS

= 5V

= –5V

0.4

V

IOS

0.3

0.2

V

OOS

GAIN ERROR

0.1

GAIN ERROR

0

V

OOS

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

V

IOS

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

INPUT COMMON MODE (V)

–5 –4 –3 –2 –1

0

1

2

3

4

5

INPUT COMMON MODE (V)

1966 G02

1966 G03

Gain and Offset

vs Output Common Mode

0.5

0.4

0.5

0.4

0.5

V

DD

V

SS

= 5V

= GND

V

DD

V

SS

= 5V

= –5V

0.4

0.3

V

IOS

0.2

V

OOS

GAIN ERROR

V

OOS

0.1

0

GAIN ERROR

V

IOS

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

OUTPUT COMMON MODE (V)

–5 –4 –3 –2 –1

0

1

2

3

4

5

OUTPUT COMMON MODE (V)

1966 G05

1966 G06

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LTC1966

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TYPICAL PERFOR A CE CHARACTERISTICS

Gain and Offsets vs Temperature

0.5

0.4

0.5

0.4

0.5

V

DD

V

SS

= 5V

= GND

V

DD

V

SS

= 5V

= –5V

0.4

0.3

V

IOS

0.2

V

OOS

GAIN ERROR

V

OOS

0.1

GAIN ERROR

0

V

IOS

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

1966 G08

1966 G09

Gain and Offset

vs Output Common Mode

Gain and Offset

vs Input Common Mode

0.5

0.4

1.0

0.5

0.4

1.0

0.8

0.6

0.4

0.2

0

V

DD

V

SS

= 2.7V

= GND

V

DD

V

SS

= 2.7V

= GND

0.8

V

IOS

V

IOS

0.3

0.6

0.3

0.2

0.4

0.2

GAIN ERROR

0.1

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

V

OOS

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

INPUT COMMON MODE (V)

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

OUTPUT COMMON MODE (V)

1966 G01

1966 G04

Gain and Offsets vs Temperature

Gain and Offset vs V_SSSupply

0.5

0.4

1.0

0.5

0.4

0.5

V

DD

V

SS

= 2.7V

= GND

V

DD

= 5V

0.8

0.4

V

IOS

0.3

0.6

0.3

V

IOS

0.2

0.4

0.2

V

OOS

GAIN ERROR

0.1

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

V

OOS

–50 –25

0

25

50

75 100 125

–6

–5

–4

–3

(V)

–2

–1

0

TEMPERATURE (°C)

V

SS

1966 G07

1966 G11

sn1966 1966fas

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LTC1966

TYPICAL PERFOR A CE CHARACTERISTICS

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Gain and Offset vs V_DDSupply

Performance vs Crest Factor

Performance vs Large Crest Factors

0.5

0.4

1

201.0

200.8

200.6

200.4

200.2

200.0

199.8

230

FUNDAMENTAL

FREQUENCY

200mV

SCR WAVEFORMS

V

SS

= GND

RMS

0.8

C

V

= 10µF

AVE

DD

220

210

= 5V

60Hz

20Hz

0.3

0.6

O.1%/DIV

V

IOS

0.2

0.4

200

190

180

170

160

0.1

0.2

250Hz

100Hz

20Hz

60Hz

GAIN ERROR

0

100Hz

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

V

OOS

200mV

SCR WAVEFORMS

RMS

C

V

= 4.7µF

AVE

DD

= 5V

5%/DIV

150

3.5 4.0

1.0 1.5 2.0 2.5 3.0

4.5 5.0

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

2

3

5

6

7

8

1

4

CREST FACTOR

V

CREST FACTOR

DD

1966 G15

1966 G10

1966 G12

Quiescent Supply Currents

vs Supply Voltage

DC Linearity

AC Linearity

0.20

0.15

0.10

0.05

0

200

175

150

125

100

75

0.10

0.08

V

= GND

C

AVE

V

IN2

= 1µF

= GND

60HZ SINEWAVES

SS

C

AVE

V

IN2

= 1µF

= GND

I

DD

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.05

–0.10

–0.15

–0.20

50

EFFECT OF OFFSETS

MAY BE POSITIVE

OR NEGATIVE

25

0

I

SS

–25

0

50 100 150 200 250 300 350 400 450 500

(mV AC

–500

–300

–100

V

100

(mV)

300

500

0

1

2

5

6

3

4

V

IN1

)

RMS

V

SUPPLY VOLTAGE (V)

DD

IN1

1966 G13

1966 G14

1966 G16

Shutdown Currents

vs ENABLE Voltage

Quiescent Supply Currents

vs Temperature

Input Signal Bandwidth

250

200

150

100

50

1000

100

10

170

0.1%

1%

10%

ERROR

V

DD

= 5V

ERROR ERROR

V

= 5V, V = –5V

SS

DD

160

150

I

DD

= 5V, V = GND

SS

DD

–3dB

140

130

V

= 2.7V, V = GND

SS

DD

500

I

EN

250

0

15

10

V

= 5V, V = –5V

SS

DD

I

SS

0

V

= 2.7V, V = GND

SS

DD

V

= 5V, V = GND

–50

–100

–250

–500

DD

SS

5

0

1

4

6

0

1

2

3

5

100

1K

10K

100K

1M

–25

0

50

75 100 125

–50

25

INPUT SIGNAL FREQUENCY (Hz)

ENABLE PIN VOLTAGE (V)

TEMPERATURE (°C)

1966 G19

1966 G18

1966 G17

sn1966 1966fas

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LTC1966

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TYPICAL PERFOR A CE CHARACTERISTICS

DC Transfer Function Near Zero

Bandwidth to 100kHz

Input Signal Bandwidth

30

25

20

15

10

5

202

200

198

196

202

201

V

= GND

0.5%/DIV

IN2

THREE REPRESENTITIVE UNITS

C

AVE

= 47µF

200

194

192

199

198

197

196

190

188

186

184

182

0

–5

–10

1%/DIV

C

= 2.2µF

AVE

195

0

5

–20 –15 –10 –5

10 15 20

0

30

50 60 70 80 90 100

1

10

100

1000

10 20

40

V

IN1

(mV DC)

INPUT FREQUENCY (kHz)

1966 G22

1966 G20

1966 G21

Common Mode Rejection Ratio

vs Frequency

Output Accuracy

vs Signal Amplitude

110

100

90

80

70

60

50

40

30

20

10

5

AC INPUTS = 60Hz

SINEWAVES

= GND

V

DD

V

SS

= 5V

= –5V

1% ERROR

V

±5V INPUT CONVERSION

IN2

TO DC OUTPUT

0

–5

AC INPUT

–1% ERROR

V

DD

= 5V

–10

–15

–20

DC INPUT

V

DD

= 5V

AC INPUT

= 3V

V

DD

0

0.5

1

1.5

)

2

2.5

10

100

1k

10k

100k

1M

V

(V

FREQUENCY (Hz)

IN1 RMS

1966 G23

1966 G24

sn1966 1966fas

7

LTC1966

U

PI FU CTIO S

GND (Pin 1): Ground. A power return pin.

OUT RTN (Pin 6): Output Return. The output voltage is

createdrelativetothispin. TheV_OUTandOUTRTNpinsare

not balanced and this pin should be tied to a low imped-

ance, both AC and DC. Although it is typically tied to GND,

it can be tied to any arbitrary voltage, V_SS< OUT RTN <

(V_DD– Max Output). Best results are obtained when

OUT RTN = GND.

IN1 (Pin 2): Differential Input. DC coupled (polarity is

irrelevant).

IN2 (Pin 3): Differential Input. DC coupled (polarity is

irrelevant).

V

_SS(Pin 4): Negative Voltage Supply. GND to –5.5V.

V

_DD(Pin 7): Positive Voltage Supply. 2.7V to 5.5V.

V

_OUT(Pin 5): Output Voltage. This is high impedance. The

RMS averaging is accomplished with a single shunt ca-

pacitor from this node to OUT RTN. The transfer function

is given by:

ENABLE (Pin 8): An Active-Low Enable Input. LTC1966 is

debiased if open circuited or driven to V_DD. For normal

operation, pull to GND, a logic low or even V_SS.

V

OUT

– OUT RTN = Average IN2 –IN1 ²

(

)

(

)

sn1966 1966fas

8

LTC1966

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U

START

NOT

SURE

READ

RMS-TO-DC

CONVERSION

DO YOU

NEED TRUE RMS-TO-DC

CONVERSION?

FIND SOMEONE WHO DOES

AND GIVE THEM THIS

DATA SHEET

NO

YES

CONTACT LTC BY PHONE OR

AT www.linear.com AND

GET SOME NOW

DO YOU

HAVE ANY LTC1966s

YET?

NO

YES

DID

DO YOU WANT TO

KNOW HOW TO USE THE

LTC1966 FIRST?

NO

YES

YOU ALREADY TRY OUT

THE LTC1966?

YES

NO

READ THE TROUBLESHOOTING

DID

NO

GUIDE. IF NECESSARY, CALL

READ THE DESIGN COOKBOOK

YOUR CIRCUIT

WORK?

LTC FOR APPLICATIONS SUPPORT

YES

NOW DOES YOUR

READ THE TROUBLESHOOTING

GUIDE AGAIN OR CALL LTC

FOR APPLICATIONS SUPPORT

YES

RMS CIRCUIT WORK

NO

CONTACT LTC

AND PLACE YOUR ORDER

WELL ENOUGH THAT YOU

ARE READY TO BUY

THE LTC1966?

1966 TA02

sn1966 1966fas

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RMS-TO-DC CONVERSION

The last two entries of Table 1 are chopped sine waves as

is commonly created with thyristors such as SCRs and

Triacs. Figure 2a shows a typical circuit and Figure 2b

shows the resulting load voltage, switch voltage and load

currents. The power delivered to the load depends on the

firing angle, as well as any parasitic losses such as switch

“ON” voltage drop. Real circuit waveforms will also typi-

cally have significant ringing at the switching transition,

dependent on exact circuit parasitics. For the purposes of

this data sheet, “SCR Waveforms” refers to the ideal

chopped sine wave, though the LTC1966 will do faithful

RMS-to-DC conversion with real SCR waveforms as well.

Definition of RMS

RMS amplitude is the consistent, fair and standard way to

measure and compare dynamic signals of all shapes and

sizes. Simply stated, the RMS amplitude is the heating

potential of a dynamic waveform. A 1V_RMSAC waveform

willgeneratethesameheatinaresistiveloadaswill1VDC.

+

1V DC

R

–

SAME

HEAT

The case shown is for Θ = 90°, which corresponds to 50%

of available power being delivered to the load. As noted in

Table 1, when Θ = 114°, only 25% of the available power

is being delivered to the load and the power drops quickly

as Θ approaches 180°.

1V AC

RMS

1V (AC + DC) RMS

1966 F01

Figure 1

With an average rectification scheme and the typical

calibration to compensate for errors with sine waves, the

RMS level of an input sine wave is properly reported; it is

only with a non-sinusoidal waveform that errors occur.

Because of this calibration, and the output reading in

Mathematically, RMS is the “Root of the Mean of the

Square:”

V

_RMS= V²

V

_RMS, the term True-RMS got coined to denote the use of

an actual RMS-to-DC converter as opposed to a calibrated

average rectifier.

Alternatives to RMS

Other ways to quantify dynamic waveforms include peak

detection and average rectification. In both cases, an

average (DC) value results, but the value is only accurate

at the one chosen waveform type for which it is calibrated,

typically sine waves. The errors with average rectification

are shown in Table 1. Peak detection is worse in all cases

and is rarely used.

V

I

LOAD

+

–

+

–

V

LOAD

THY

+

AC

MAINS

V

LINE

–

CONTROL

1966 F02a

Figure 2a

Table 1. Errors with Average Rectification vs True RMS

V

LINE

Θ

AVERAGE

RECTIFIED

V

LOAD

WAVEFORM

Square Wave

Sine Wave

V

(V)

ERROR*

RMS

V

THY

1.000

0.900

0.866

0.637

11%

*Calibrate for 0% Error

–3.8%

I

LOAD

1966 F02b

Triangle Wave

Figure 2b

SCR at 1/2 Power,

–29.3%

Θ = 90°

SCR at 1/4 Power,

1.000

0.536

–40.4%

Θ = 114°

sn1966 1966fas

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How the LTC1966 RMS-to-DC Converter Works

How an RMS-to-DC Converter Works

TheLTC1966usesacompletelynewtopologyforRMS-to-

DC conversion, in which a ∆Σ modulator acts as the

divider, and a simple polarity switch is used as the multi-

plier¹as shown in Figure 4.

Monolithic RMS-to-DC converters use an implicit com-

putationtocalculatetheRMSvalueofaninputsignal. The

fundamental building block is an analog multiply/divide

used as shown in Figure 3. Analysis of this topology is

easy and starts by identifying the inputs and the output of

the lowpass filter. The input to the LPF is the calculation

from the multiplier/divider; (V_IN)²/V_OUT. The lowpass

filter will take the average of this to create the output,

mathematically:

V_IN

α

V_OUT

D

∆-Σ

REF

V

IN

±1

2

V

V_OUT

(

)

V

LPF

IN

OUT

V_OUT

=

,

Because V_OUTis DC,

Figure 4. Topology of LTC1966

2

V

(

)

IN

V

The ∆Σ modulator has a single-bit output whose average

duty cycle (D) will be proportional to the ratio of the input

signal divided by the output. The ∆Σ is a 2nd order

modulator with excellent linearity. The single-bit output is

used to selectively buffer or invert the input signal. Again,

this is a circuit with excellent linearity, because it operates

at only two points: ±1 gain; the average effective multipli-

cation over time will be on the straight line between these

two points. The combination of these two elements again

(

)

IN

=

, so

V_OUT

2

V

(

)

IN

V_OUT

=

, and

V_OUT

V

OUT

²= V ², or

(

)

(

)

IN

2

V_OUT

=

V

IN

= RMS V

(

)

(

)

IN

creates a lowpass filter input signal equal to (V_IN)²/V_OUT

,

which, asshownabove, resultsinRMS-to-DCconversion.

2

V

(

)

IN

The lowpass filter performs the averaging of the RMS

function and must be a lower corner frequency than the

lowest frequency of interest. For line frequency measure-

ments, this filter is simply too large to implement on-chip,

but the LTC1966 needs only one capacitor on the output to

implement the lowpass filter. The user can select this

capacitor depending on frequency range and settling time

requirements, as will be covered in the Design Cookbook

section to follow.

V_OUT

×

÷

V

LPF

IN

OUT

1966 F03

Figure 3. RMS-to-DC Converter with Implicit Computation

Unlike the prior generation RMS-to-DC converters, the

LTC1966 computation does NOT use log/antilog circuits,

which have all the same problems, and more, of log/

antilogmultipliers/dividers,i.e.,linearityispoor,theband-

widthchangeswiththesignalamplitudeandthegaindrifts

with temperature.

Thistopologyisinherentlymorestableandlinearthanlog/

antilogimplementationsprimarilybecauseallofthesignal

processing occurs in circuits with high gain op amps

operating closed loop.

¹Multiple patents pending

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More detail of the LTC1966 inner workings is shown in the

Simplified Schematic towards the end of this data sheet.

Note that the internal scalings are such that the ∆Σ output

dutycycleislimitedto0%or100%onlywhenV_INexceeds

earity in the input circuitry will typically corrupt that

transfer function far less simply because with an AC input,

the RMS-to-DC conversion will average the nonlinearity

from a whole range of input values together.

±4 • V_OUT

.

But the input nonlinearity will still cause problems in an

RMS-to-DC converter because it will corrupt the accuracy

as the input signal shape changes. Although an RMS-to-

DC converter will convert any input waveform to a DC

output, the accuracy is not necessarily as good for all

waveforms as it is with sine waves. A common way to

describe dynamic signal wave shapes is Crest Factor. The

crestfactoristheratioofthepeakvaluerelativetotheRMS

value of a waveform. A signal with a crest factor of 4, for

instance, has a peak that is four times its RMS value.

Because this peak has energy (proportional to voltage

squared)thatis16times(4²)theenergyoftheRMSvalue,

the peak is necessarily present for at most 6.25% (1/16)

of the time.

Linearity of an RMS-to-DC Converter

Linearity may seem like an odd property for a device that

implements a function that includes two very nonlinear

processes: squaring and square rooting.

However, an RMS-to-DC converter has a transfer func-

tion, RMS volts in to DC volts out, that should ideally have

a 1:1 transfer function. To the extent that the input to

output transfer function does not lie on a straight line, the

part is nonlinear.

A more complete look at linearity uses the simple model

shown in Figure 5. Here an ideal RMS core is corrupted by

both input circuitry and output circuitry that have imper-

fecttransferfunctions. Asnoted, inputoffsetisintroduced

in the input circuitry, while output offset is introduced in

the output circuitry.

The LTC1966 performs very well with crest factors of 4 or

less and will respond with reduced accuracy to signals

with higher crest factors. The high performance with crest

factors less than 4 is directly attributable to the high

linearity throughout the LTC1966.

Any nonlinearity that occurs in the output circuity will

corrupt the RMS in to DC out transfer function. A nonlin-

INPUT CIRCUITRY

IDEAL

RMS-TO-DC

CONVERTER

OUTPUT CIRCUITRY

• V

INPUT

OUTPUT

IOS

OOS

• INPUT NONLINEARITY

• OUTPUT NONLINEARITY

1966 F05

Figure 5. Linearity Model of an RMS-to-DC Converter

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DESIGN COOKBOOK

However,iftheoutputisexaminedonanoscilloscopewith

a very low frequency input, the incomplete averaging will

be seen, and this ripple will be larger than the error

depicted in Figure 6. Such an output is depicted in

Figure 7. The ripple is at twice the frequency of the input

because of the computation of the square of the input. The

typicalvaluesshown,5%peakripplewith0.05%DCerror,

occur with C_AVE= 1µF and f_INPUT= 10Hz.

The LTC1966 RMS-to-DC converter makes it easy to

implement a rather quirky function. For many applications

all that will be needed is a single capacitor for averaging,

appropriate selection of the I/O connections and power

supply bypassing. Of course, the LTC1966 also requires

power. A wide variety of power supply configurations are

shown in the Typical Applications section towards the end

of this data sheet.

IftheapplicationcallsfortheoutputoftheLTC1966tofeed

a sampling or Nyquist A/D converter (or other circuitry

that will not average out this double frequency ripple) a

larger averaging capacitor can be used. This trade-off is

depicted in Figure 8. The peak ripple error can also be

reduced by additional lowpass filtering after the LTC1966,

but the simplest solution is to use a larger averaging

capacitor.

Capacitor Value Selection

The RMS or root-mean-squared value of a signal, the root

of the mean of the square, cannot be computed without

someaveragingtoobtainthemeanfunction.TheLTC1966

true RMS-to-DC converter utilizes a single capacitor on

the output to do the low frequency averaging required for

RMS-to-DC conversion. To give an accurate measure of a

dynamic waveform, the averaging must take place over a

sufficiently long interval to average, rather than track, the

lowestfrequencysignalsofinterest.Forasingleaveraging

capacitor, the accuracy at low frequencies is depicted in

Figure 6.

²This frequency-dependent error is in additon to the static errors that affect all readings and are

therefore easy to trim or calibrate out. The “Error Analyses” section to follow discusses the effect

of static error terms.

ACTUAL OUTPUT

WITH RIPPLE

IDEAL

OUTPUT

f = 2 × f

INPUT

DC

PEAK

RIPPLE

(5%)

ERROR

(0.05%)

Figure 6 depicts the so-called “DC error” that results at a

given combination of input frequency and filter capacitor

values². It is appropriate for most applications, in which

theoutputisfedtoacircuitwithaninherentlyband-limited

frequency response, such as a dual slope/integrating A/D

converter,a∆ΣA/Dconverterorevenamechanicalanalog

meter.

DC

PEAK

AVERAGE

OF ACTUAL

OUTPUT

ERROR =

DC ERROR +

PEAK RIPPLE

(5.05%)

TIME

1966 F07

Figure 7. Output Ripple Exceeds DC Error

0

–0.2

C = 10µF

C = 4.7µF

–0.4

–0.6

C = 2.2µF

C = 0.47µF

C = 0.1µF

C = 1.0µF

C = 0.22µF

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

1

10

20

50

60

100

INPUT FREQUENCY (Hz)

1966 F06

Figure 6. DC Error vs Input Frequency

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0

–0.2

–0.4

C = 100µF

–0.6

–0.8

C = 2.2µF

C = 1µF

C = 47µF

C = 22µF

C = 10µF

C = 4.7µF

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

1

10

INPUT FREQUENCY (Hz)

20

50

60

100

1966 F08

Figure 8. Peak Error vs Input Frequency with One Cap Averaging

A 1µF capacitor is a good choice for many applications.

The peak error at 50Hz/60Hz will be <1% and the DC error

will be <0.1% with frequencies of 10Hz or more.

<0.1% gain accuracy degradation, the parallel impedance

of the capacitor leakage will need to be >1000 times the

LTC1966 output impedance. Accuracy at this level can be

hard to achieve with a ceramic capacitor, particularly with

a large value of capacitance and at high temperature.

Note that both Figure 6 and Figure 8 assume AC-coupled

waveforms with a crest factor less than 2, such as sine

waves or triangle waves. For higher crest factors and/or

AC + DC waveforms, a larger C_AVEwill generally be

required. See “Crest Factor and AC + DC Waveforms.”

For critical applications, a film capacitor, such as metal-

ized polyester, will be a much better choice. Although

more expensive, and larger for a given value, the value

stability and low leakage make metal-film capacitors a

trouble-free choice.

Capacitor Type Selection

The LTC1966 can operate with many types of capacitors.

The various types offer a wide array of sizes, tolerances,

parasitics, package styles and costs.

With any type of capacitor, the self-resonance of the

capacitor can be an issue with the switched capacitor

LTC1966. If the self-resonant frequency of the averaging

capacitor is 1MHz or less, a second smaller capacitor

should be added in parallel to reduce the impedance seen

by the LTC1966 output stage at high frequencies. A

capacitor 100 times smaller than the averaging capacitor

willtypicallybesmallenoughtobealowcostceramicwith

a high quality dielectric such as X7R or NPO/COG.

Ceramicchipcapacitorsofferlowcostandsmallsize, but

are not recommended for critical applications. The value

stability over voltage and temperature is poor with many

types of ceramic dielectrics. This will not cause an RMS-

to-DCaccuracyproblemexceptatlowfrequencies,where

it can aggravate the effects discussed in the previous

section. If a ceramic capacitor is used, it may be neces-

sary to use a much higher nominal value in order to

assure the low frequency accuracy desired.

Input Connections

The LTC1966 input is differential and DC coupled. The

LTC1966 responds to the RMS value of the differential

voltage between Pin 2 and Pin 3, including the DC portion

of that difference. However, there is no DC-coupled path

fromtheinputstoground.Therefore,atleastoneofthetwo

inputsmustbeconnectedwithaDC-returnpathtoground.

Another parasitic of ceramic capacitors is leakage, which

is again dependent on voltage and particularly tempera-

ture. If the leakage is a constant current leak, the I • R drop

of the leak multiplied by the output impedance of the

LTC1966willcreateaconstantoffsetoftheoutputvoltage.

If the leak is Ohmic, the resistor divider formed with the

LTC1966 output impedance will cause a gain error. For

Both inputs must be connected to something. If either

input is left floating, a zero volt output will result.

sn1966 1966fas

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For single-ended DC-coupled applications, simply con-

nect one of the two inputs (they are interchangeable) to

the signal, and the other to ground. This will work well for

dual supply configurations, but for single supply con-

figurations it will only work well for unipolar input sig-

nals.TheLTC1966inputvoltagerangeisfromrail-to-rail,

and when the input is driven above V_DDor below V_SS

(ground for single supply operation) the gain and offset

errors will increase substantially after just a few hundred

millivolts of overdrive. Fortunately, most single supply

circuits measuring a DC-coupled RMS value will include

some reference voltage other than ground, and the

second LTC1966 input can be connected to that point.

the coupling capacitor connected to the second input to

follow the DC average of the input voltage.

Fordifferentialinputapplications,connectthetwoinputsto

the differential signal. If AC coupling is desired, one of the

two inputs can be connected through a series capacitor.

In all of these connections, to choose the input coupling

capacitor, C_C, calculate the low frequency coupling time

constant desired, and divide by the LTC1966 differential

input impedance. Because the LTC1966 input impedance

is about 100 times its output impedance, this capacitor is

typically much smaller than the output averaging capaci-

tor. Its requirements are also much less stringent, and a

ceramic chip capacitor will usually suffice.

Forsingle-endedAC-coupledapplications,Figure9shows

three alternate topologies. The first one, shown in Figure

9a uses a coupling capacitor to one input while the other

isgrounded.ThiswillremovetheDCvoltagedifferencefrom

the input to the LTC1966, and it will therefore not be part

of the resulting output voltage. Again, this connection will

work well with dual supply configurations, but in single

supply configurations it will be necessary to raise the volt-

age on the grounded input to assure that the signal at the

active input stays within the range of V_SSto V_DD. If there

isalreadyasuitablevoltagereferenceavailable,connectthe

second input to that point. If not, a midsupply voltage can

be created with two resistors as shown in Figure 9b.

Output Connections

The LTC1966 output is differentially, but not symmetri-

cally, generated. That is to say, the RMS value that the

LTC1966computeswillbegeneratedontheoutput(Pin5)

relative to the output return (Pin 6), but these two pins are

not interchangeable. For most applications, Pin 6 will be

tied to ground (Pin 1), and this will result in the best

accuracy. However, Pin 6 can be tied to any voltage

between V_SS(Pin 4) and V_DD(Pin 7) less the maximum

output voltage swing desired. This last restriction keeps

V_OUTitself (Pin 5) within the range of V_SSto V_DD. If a

reference level other than ground is used, it should be a

low impedance, both AC and DC, for proper operation of

the LTC1966.

Finally, iftheinputvoltageisknowntobebetweenV_SSand

V_DD, it can be AC coupled by using the configuration

shown in Figure 9c. Whereas the DC return path was

provided through Pin 3 in Figures 9a and 9b, in this case,

the return path is provided on Pin 2, through the input

signal voltages. The switched capacitor action between

thetwoinputpinsoftheLTC1966willcausethevoltageon

Use of a voltage in the range of V_DD– 1V to V_DD– 1.3V can

lead to errors due to the switch dynamics as the NMOS

transistor is cut off. For this reason, it is recommended

that OUT RTN = 0V if V_DDis ≤3V.

V

DD

C

LTC1966

IN1

LTC1966

IN1

IN2

LTC1966

IN1

IN2

2

3

2

3

2

3

IN2

V

IN

V

IN

1966 F07

+

V

C

DC

–

V

SS

DD

V

OR GND

SS

R1

100k

R2

100k

(9b)

(9c)

(9a)

Figure 9. Single-Ended AC-Coupled Input Connection Alternatives

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In any configuration, the averaging capacitor should be

connected between Pins 5 and 6. The LTC1966 RMS-DC

output will be a positive voltage created at V_OUT(Pin 5)

with respect to OUT RTN (Pin 6).

Up and Running!

If you have followed along this far, you should have the

LTC1966 up and running by now! Don’t forget to enable

thedevicebygroundingPin8, ordrivingitwithalogiclow.

Power Supply Bypassing

Keep in mind that the LTC1966 output impedance is fairly

high, and that even the standard 10MΩ input impedance

ofadigitalmultimeter(DMM)ora10×scopeprobewillload

down the output enough to degrade its typical gain error

of 0.1%. In the end application circuit, either a buffer or

another component with an extremely high input imped-

ance(suchasadualslopeintegratingADC)shouldbeused.

Forlaboratoryevaluation,itmaysufficetouseabench-top

DMM with the ability to disconnect the 10MΩ shunt.

The LTC1966 is a switched capacitor device, and large

transient power supply currents will be drawn as the

switching occurs. For reliable operation, standard power

supply bypassing must be included. For single supply

operation, a 0.01µF capacitor from V_DD(Pin 7) to GND

(Pin 1) located close to the device will suffice. For dual

supplies, add a second 0.01µF capacitor from V_SS(Pin 4)

to GND (Pin 1), located close to the device. If there is a

good quality ground plane available, the capacitors can go

directly to that instead. Power supply bypass capacitors

can, of course, be inexpensive ceramic types.

If you are still having trouble, it may be helpful to skip

ahead a few pages and review the Troubleshooting Guide.

What About Response Time?

The LTC1966 needs at least 2.7V for its power supply,

more for dual supply configurations. The range of allow-

able negative supply voltages (V_SS) vs positive supply

voltages (V_DD) is shown in Figure 10. Mathematically, the

V_SSconstraint is:

With a large value averaging capacitor, the LTC1966 can

easily perform RMS-to-DC conversion on low frequency

signals. It compares quite favorably in this regard to prior-

generation products because nothing about the ∆Σ

circuitry is temperature sensitive. So the RMS result

doesn’t get distorted by signal driven thermal fluctuations

like a log-antilog circuit output does.

–3 • (V_DD– 2.7V) ≤ V_SS≤ GND

The LTC1966 has internal ESD absorption devices, which

are referenced to the V_DDand V_SSsupplies. For effective

in-circuit ESD immunity, the V_DDand V_SSpins must be

connected to a low external impedance. This can be

accomplishedwithlowimpedancepowerplanesorsimply

with the recommended 0.01µF decoupling to ground on

each supply.

However, using large value capacitors results in a slow

response time. Figure 11 shows the rising and falling step

responses with a 1µF averaging capacitor. Although they

both appear at first glance to be standard exponential-

decay type settling, they are not. This is due to the

nonlinear nature of an RMS-to-DC calculation. Also note

the change in the time scale between the two; the rising

edge is more than twice as fast to settle to a given

accuracy. Again this is a necessary consequence of RMS-

to-DC calculation.³

0

–1

LTC1966

–2

OPERATES IN THIS RANGE

–3

–4

–5

–6

Although shown with a step change between 0mV and

100mV, the same response shapes will occur with the

LTC1966 for ANY step size. This is in marked contrast to

³To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV and

100mV. At very low frequencies, the LTC1966 will essentially track the input. But as the input

frequency is increased, the average result will converge to the RMS value of the input. If the rise and

fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the RMS

value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical rise

and fall characteristics will converge to as the input frequency is increased.

2.5

3.5

4

4.5

5

5.5

3

V

(V)

DD

1966 F10

Figure 10. V_SSLimits vs V_DD

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120

C

AVE

= 1µF

C

AVE

= 1µF

100

80

60

80

60

40

20

0

40

20

0

0.2

0.4

0.6

0.8

1

0

0.1

0.2

0.3

0.4

0.5

TIME (SEC)

1966 F11b

1966 F11a

Figure 11a. LTC1966 Rising Edge with C_AVE= 1µF

Figure 11b. LTC1966 Falling Edge with C_AVE= 1µF

10

C = 0.1µF

C = 0.22µF C = 0.47µF

C = 1µF

C = 2.2µF

C = 4.7µF

C = 10µF

C = 22µF

C = 47µF

C = 100µF

1

0.1

0.01

0.1

1

10

100

SETTLING TIME (SEC)

1966 F12

Figure 12. LTC1966 Settling Time with One Cap Averaging

priorgenerationlog/antilogRMS-to-DCconverters,whose

averaging time constants are dependent on the signal

level, resulting in excruciatingly long waits for the output

to go to zero.

Figure 12 shows the settling accuracy vs settling time for

a variety of averaging capacitor values. If the capacitor

value previously selected (based on error requirements)

gives an acceptable settling time, your design is done.

The shape of the rising and falling edges will be dependent

onthetotalpercentchangeinthestep,butforlessthanthe

100% changes shown in Figure 11, the responses will be

less distorted and more like a standard exponential decay.

For example, when the input amplitude is changed from

100mV to 110mV (+10%) and back (–10%), the step

responses are essentially the same as a standard expo-

nential rise and decay between those two levels. In such

cases, the time constant of the decay will be in between

that of the rising edge and falling edge cases of Figure 11.

Therefore, the worst case is the falling edge response as

it goes to zero, and it can be used as a design guide.

But with 100µF, the settling time to even 10% is a full 38

seconds, which is a long time to wait. What can be done

about such a design? If the reason for choosing 100µF is

to keep the DC error with a 75mHz input less than 0.1%,

the answer is: not much. The settling time to 1% of 76

seconds is just 5.7 cycles of this extremely low frequency.

Averaging very low frequency signals takes a long time.

However, if the reason for choosing 100µF is to keep the

peak error with a 10Hz input less than 0.05%, there is

another way to achieve that result with a much improved

settling time.

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Reducing Ripple with a Post Filter

concern. To do this, tie all three ground symbols shown in

Figure 13 to the signal reference, as well as to the differ-

ential return for the circuitry that follows.

The output ripple is always much larger than the DC error,

so filtering out the ripple can reduce the peak error

substantially, without the large settling time penalty of

simply increasing the averaging capacitor.

Figure 14 shows an alternative 2nd order post filter, for a

net 3rd order filtering of the LTC1966 RMS calculation. It

also uses the 85kΩ output impedance of the LTC1966 as

the first resistor of a 3rd order active-RC filter, but this

topology filters without buffering so that the op amp DC

errorcharacteristics do not affectthe output. Althoughthe

outputimpedanceoftheLTC1966isincreasedfrom85kΩ

to 285kΩ, this is not an issue with an extremely high input

impedance load, such as a dual-slope integrating ADC like

the ICL7106. And it allows a generic op amp to be used,

such as the SOT-23 one shown. Furthermore, it easily

works on a single supply rail by tying the noninverting

input of the op amp to a low noise reference as optionally

shown.ThisreferencewillnotchangetheDCvoltageatthe

circuit output, although it does become the AC ground for

the filter, thus the (relatively) low noise requirement.

Figure 13 shows a basic 2nd order post filter, for a net 3rd

order filtering of the LTC1966 RMS calculation. It uses the

85kΩ output impedance of the LTC1966 as the first resis-

torofa3rdorderSallen-Keyactive-RCfilter. Thistopology

features a buffered output, which can be desirable de-

pending on the application. However, there are disadvan-

tages to this topology, the first of which is that the op amp

inputvoltageandcurrenterrorsdirectlydegradetheeffec-

tive LTC1966 V_OOS. The table inset in Figure 13 shows

these errors for four of Linear Technology’s op amps.

A second disadvantage is that the op amp output has to

operateoverthesamerangeastheLTC1966output,includ-

ingground,whichinsinglesupplyapplicationsisthenega-

tivesupply.AlthoughtheLTC1966outputwillfunctionfine

justmillivoltsfromtherail,mostopampoutputstages(and

evensomeinputstages)willnot.Thereareatleasttwoways

toaddressthis.Firstofall,theopampcanbeoperatedsplit

supply if a negative supply is available. Just the op amp

would need to do so; the LTC1966 can remain single sup-

ply. Asecondwaytoaddressthisissueistocreateasignal

referencevoltageahalfvoltorsoaboveground.Thisismost

attractive when the circuitry that follows has a differential

input, so that the tolerance of the signal reference is not a

Step Responses with a Post Filter

B

oth of the post filters, shown in Figures 13 and 14, are

optimized for additional filtering with clean step re-

sponses. The 85kΩ output impedance of the LTC1966

working into a 1µF capacitor forms a 1st order LPF with

a –3dB frequency of ~1.8Hz. The two filters have 1µF at

the LTC1966 output for easy comparison with a 1µF-only

case, and both have the same relative Bessel-like shape.

However, because of the topological differences of pole

placements between the various components within the

two filters, the net effective bandwidth for Figure 13 is

slightly higher (≈1.2 • 1.8 ≈ 2.1Hz) than with 1µF alone,

while the bandwidth for Figure 14 is somewhat lower

C1

1µF

R

B

–

+

R1

38.3k

R2

169k

LT1880

5

6

R1

200k

LTC1966

C

C2

0.1µF

5

AVE

1µF

LTC1966

C

C1

0.22µF

C2

0.22µF

AVE

R2

681k

6

1µF

OP AMP

LTC1966 V

LT1494 LT1880 LT1077 LT2050

–

±200µV

OOS

OTHER

REF VOLTAGE,

SEE TEXT

V

±375µV ±150µV ±60µV

±73µV ±329µV ±329µV ±27µV

TOTAL OFFSET ±648µV ±679µV ±589µV ±230µV

±3µV

IOS

LT1782

I

• R

B/OS

+

R

VALUE

294k

1µA

SHORT

1.2mA

294k

48µA

SHORT

750µA

B

I

SQ

1966 F13

1066 F14

Figure 14. DC Accurate Post Filter

Figure 13. Buffered Post Filter

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(≈0.7 • 1.8 ≈ 1.3Hz) than with 1µF alone. To adjust the

bandwidth of either of them, simply scale all the capaci-

tors by a common multiple, and leave the resistors

unchanged.

Figure16showsthestepresponseofthesamethreecases

withaburstof60Hzratherthan10Hz.With60Hz,theinitial

portion of the step response is free of the boost seen in

Figure 15 and the two post-filter responses have less than

1% overshoot. The 1µF-only case still has noticeable

120Hz ripple, but both filters have removed all detectable

ripple on this scale. This is to be expected; the first order

filter will reduce the ripple about 6:1 for a 6:1 change in

frequency, while the third order filters will reduce the

ripple about 6³:1 or 216:1 for a 6:1 change in frequency.

ThestepresponsesoftheLTC1966with1µF-onlyandwith

the two post filters are shown in Figure 15. This is the

rising edge RMS output response to a 10Hz input starting

at t = 0. Although the falling edge response is the worst

case for settling, the rising edge illustrates the ripple that

these post filters are designed to address, so the rising

edge makes for a better intuitive comparison.

Again, the two filter topologies have the same relative

shape, so the step response and ripple filtering trade-offs

of the two are the same, with the same performance of

each possible with the other by scaling it accordingly.

Figures 17 and 18 show the peak error vs. frequency for a

selection of capacitors for the two different filter topolo-

gies. To keep the clean step response, scale all three

capacitors within the filter. Scaling the buffered topology

of Figure 13 is simple because the capacitors are in a

10:1:10 ratio. Scaling the DC accurate topology of Figure

14canbedonewithstandardvaluecapacitors;onedecade

of scaling is shown in Table 2.

TheinitialriseoftheLTC1966willhaveenhancedslewrates

with DC and very low frequency inputs due to saturation

effectsinthe∆Σmodulator.ThisisseeninFigure15intwo

ways. First, the 1µF-only output is seen to rise very quickly

in the first 40ms. The second way this effect shows up is

thatthepostfilteroutputshaveamodestovershoot,onthe

order of 3mV to 4mV, or 3% to 4%. This is only an issue

with input frequency bursts at 50Hz or less, and even with

the overshoot, the settling to a given level of accuracy

improves due to the initial speedup.

As predicted by Figure 6, the DC error with 1µF is well

under 1mV and is not noticeable at this scale. However, as

predicted by Figure 8, the peak error with the ripple from

a10Hzinputismuchlarger,inthiscaseabout5mV.Ascan

be clearly seen, the post filters reduce this ripple. Even the

wider bandwidth of Figure 13’s filter is seen to cut the

ripple down substantially (to <1mV) while the settling to

1%happensfaster.WiththenarrowerbandwidthofFigure

14’s filter, the step response is somewhat slower, but the

double frequency output ripple is just 180µV.

Table 2: One Decade of Capacitor Scaling for Figure 14 with EIA

Standard Values

C

C = C =

1 2

AVE

1µF

0.22µF

0.33µF

0.47µF

0.68µF

1µF

1.5µF

2.2µF

3.3µF

4.7µF

6.8µF

1.5µF

200mV/

DIV

200mV/

DIV

INPUT

BURST

INPUT

BURST

0

1µF ONLY

FIGURE 13

FIGURE 14

1µF ONLY

FIGURE 13

FIGURE 14

20mV/

DIV

20mV/

DIV

STEP

RESPONSE

STEP

RESPONSE

0

1966 F16

1966 F15

100ms/DIV

Figure 16. Step Responses with 60Hz Burst

Figure 15. Step Responses with 10Hz Burst

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0

–0.2

C = 10µF

–0.4

–0.6

C = 4.7µF

C = 2.2µF

C = 1.0µF

C = 0.47µF

C = 0.22µF

C = 0.1µF

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

1

10

INPUT FREQUENCY (Hz)

100

1966 F17

Figure 17. Peak Error vs Input Frequency with Buffered Post Filter

0

C = 10µF

C = 4.7µF

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

C = 2.2µF

C = 1.0µF

C = 0.47µF

C = 0.22µF

C = 0.1µF

1

10

INPUT FREQUENCY (Hz)

100

1966 F18

Figure 18. Peak Error vs Input Frequency with DC-Accurate Post Filter

Figures 19 and 20 show the settling time versus settling

accuracy for the Buffered and DC accurate post filters,

respectively. The different curves represent different

scalings of the filters, as indicated by the C_AVEvalue.

These are comparable to the curves in Figure 12 (single

capacitor case), with somewhat less settling time for the

buffered post filter, and somewhat more settling time for

the DC-accurate post filter. These differences are due to

the change in overall bandwidth as mentioned earlier.

Although the settling times for the post-filtered configura-

tions shown on Figures 19 and 20 are not that much

different from those with a single capacitor, the point of

using a post filter is that the settling times are far better for

a given level peak error. The filters dramatically reduce the

low frequency averaging ripple with far less impact on

settling time.

Crest Factor and AC + DC Waveforms

In the preceding discussion, the waveform was assumed

to be AC coupled, with a modest crest factor. Both

assumptions ease the requirements for the averaging

capacitor. With an AC-coupled sine wave, the calculation

engine squares the input, so the averaging filter that

follows is required to filter twice the input frequency,

makingitsjobeasier.ButwithasinewavethatincludesDC

offset, thesquareoftheinputhasfrequencycontentatthe

The other difference is the settling behavior of the filters

belowthe1%level. Unlikethecaseofa1storderfilter, any

3rd order filter can have overshoot and ringing. The filter

designs presented here have minimal overshoot and

ringing, but are somewhat sensitive to component mis-

matches. Even the ±12% tolerance of the LTC1966 output

impedance can be enough to cause some ringing. The

dashed lines indicate what can happen when ±5% capaci-

tors and ±1% resistors are used.

input frequency and the filter must average out that lower

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10

C = 0.1µF

C = 0.22µF C = 0.47µF C = 1.0µF

C = 2.2µF

C = 4.7µF

C = 10µF

C = 22µF

C = 47µF

C = 100µF

1

0.1

0.01

0.1

1

10

100

SETTLING TIME (SEC)

1066 F14

Figure 19. Settling Time with Buffered Post Filter

10

C = 0.1µF

C = 0.22µF C = 0.47µF

C = 1.0µF

C = 2.2µF

C = 4.7µF

C = 10µF

C = 22µF

C = 47µF C = 100µF

1

0.1

0.01

0.1

1

10

100

SETTLING TIME (SEC)

1066 F20

Figure 20. Settling Time with DC-Accurate Post Filter

frequency. So with AC + DC waveforms, the required

value for C_AVEshould be based on half of the lowest input

frequency, using the same design curves presented in

Figures 6, 8, 17 and 18.

using the same design curves presented in Figures 6, 8,

17 and 18. For the worst case of square top pulse trains,

that are always either zero volts or the peak voltage, base

the selection on the lowest fundamental input frequency

divided by twice as much:

Crest factor, which is the peak to RMS ratio of a dynamic

signal, also effects the required C_AVEvalue. With a higher

crestfactor,moreoftheenergyinthesignalisconcentrated

into a smaller portion of the waveform, and the averaging

has to ride out the long lull in signal activity. For busy

waveforms, such as a sum of sine waves, ECG traces or

SCR-chopped sine waves, the required value for C_AVE

shouldbebasedonthelowestfundamentalinputfrequency

divided as such:

f

INPUT(MIN)

f_DESIGN

=

6 • CF – 2

The effects of crest factor and DC offsets are cumulative.

So for example, a 10% duty cycle pulse train from 0V_PEAK

to 1V_PEAK(CF = √10 = 3.16) repeating at 16.67ms (60Hz)

inputiseffectivelyonly30HzduetotheDCasymmetryand

is effectively only:

30

f

INPUT(MIN)

f_DESIGN

=

= 3.78Hz

f_DESIGN

=

6 • 3.16 – 2

3• CF – 2

for the purposes of Figures 6, 8, 17 and 18.

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Obviously,theeffectofcrestfactorissomewhatsimplified

above given the factor of two difference based on a

subjective description of the waveform type. The results

will vary somewhat based on actual crest factor and

waveform dynamics and the type of filtering used. The

above method is conservative for some cases and about

right for others.

of that conversion. The LTC1966 specifications include

three basic static error terms, V_OOS, V_IOSand GAIN. The

output offset is an error that simply adds to (or subtracts

from) the voltage at the output. The conversion gain of the

LTC1966 is nominally 1.000 V_DCOUT/V_RMSINand the gain

error reflects the extent to which this conversion gain is

not perfectly unity. Both of these affect the results in a

fairly obvious way.

The LTC1966 works well with signals whose crest factor

is 4 or less. At higher crest factors, the internal ∆Σ

modulatorwillsaturate,andresultswillvarydependingon

the exact frequency, shape and (to a lesser extent) ampli-

tude of the input waveform. The output voltage could be

higher or lower than the actual RMS of the input signal.

Input offset on the other hand, despite its conceptual

simplicity, effects the output in a nonobvious way. As its

name implies, it is a constant error voltage that adds

directly with the input. And it is the sum of the input and

V

_IOSthat is RMS converted.

The ∆Σ modulator may also saturate when signals with

crest factors less than 4 are used with insufficient averag-

ing. This will only occur when the output droops to less

than 1/4 of the input voltage peak. For instance, a DC-

coupled pulse train with a crest factor of 4 has a duty cycle

of 6.25% and a 1V_PEAKinput is 250mV_RMS. If this input is

50Hz, repeating every 20ms, and C_AVE= 1µF, the output

will droop during the inactive 93.75% of the waveform.

This droop is calculated as:

This means that the effect of V_IOSis warped by the

nonlinear RMS conversion. With 0.2mV (typ) V_IOS, and a

200mV_RMSACinput, theRMScalculationwilladdtheDC

and AC terms in an RMS fashion and the effect is

negligible:

2

V_OUT= √(200mV AC) + (0.2mV DC)

= 200.0001mV

= 200mV + 1/2ppm

But with 10× less AC input, the error caused by V_IOSis

100× larger:

INACTIVE TIME

1– e⁻

V_RMS

2

2 • Z

• C

AVE

V_MIN

=

OUT

2

V_OUT= √(20mV AC) + (0.2mV DC)

= 20.001mV

For the LTC1966, whose output impedance (Z_OUT) is

85kΩ, this droop works out to –5.22%, so the output

would be reduced to 237mV at the end of the inactive

portion of the input. When the input signal again climbs to

1V_PEAK, the peak/output ratio is 4.22.

= 20mV + 50ppm

This phenomena, although small, is one source of the

LTC1966’s residual nonlinearity.

On the other hand, if the input is DC coupled, the input

offset voltage adds directly. With +200mV and a +0.2mV

V_IOS, a 200.2mV output will result, an error of 0.1% or

1000ppm. WithDCinputs, theerrorcausedbyV_IOScanbe

positive or negative depending if the two have the same or

opposing polarity.

With C_AVE= 10µF, the droop is only –0.548% to 248.6mV

andthepeak/outputratioisjust4.022, whichtheLTC1966

has enough margin to handle without error.

For crest factors less than 3.5, the selection of C_AVEas

previously described should be sufficient to avoid this

droop and modulator saturation effect. But with crest

factors above 3.5, the droop should also be checked for

each design.

The total conversion error with a sine wave input using the

typical values of the LTC1966 static errors is computed as

follows:

2

V_OUT=(√(500mVAC) +(0.2mVDC) )•1.001+0.1mV

= 500.600mV

Error Analyses

Once the RMS-to-DC conversion circuit is working, it is

time to take a step back and do an analysis of the accuracy

= 500mV + 0.120%

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2

V_OUT= (√(50mV AC) + (0.2mV DC) ) • 1.001 + 0.1mV have a –3dB frequency of 800kHz or so. However, the

= 50.150mV

= 50mV + 0.301%

switched capacitor circuitry samples the inputs at a mod-

est 100kHz nominal. The response versus frequency is

depicted in the Typical Performance Characteristics titled

Input Signal Bandwidth. Although there is a pattern to the

response versus frequency that repeats every sample fre-

quency, the errors are not overwhelming. This is because

LTC1966 RMS calculation is inherently wideband, operat-

ing properly with minimal oversampling, or even

undersampling, using several proprietary techniques to

exploit the fact that the RMS value of an aliased signal is

thesameastheRMSvalueoftheoriginalsignal. However,

a fundamental feature of the ∆Σ modulator is that sample

estimationnoiseisshapedsuchthatminimalnoiseoccurs

with input frequencies much less than the sampling fre-

quency,butsuchnoisepeakswheninputfrequencyreaches

half the sampling frequency. Fortunately the LTC1966

output averaging filter greatly reduces this error, but the

RMS-to-DC topology frequency shifts the noise to low

(baseband) frequencies. So with input frequencies above

5kHz to 10kHz, the output will slowly wander around ±a

few percent.

2

V

_OUT= (√(5mV AC) + (0.2mV DC) ) • 1.001 + 0.1mV

= 5.109mV

= 5mV + 2.18%

As can be seen, the gain term dominates with large inputs,

while the offset terms become significant with smaller

inputs. In fact, 5mV is the minimum RMS level needed to

keep the LTC1966 calculation core functioning normally,

so this represents the worst-case of usable input levels.

Using the worst-case values of the LTC1966 static errors,

the total conversion error is:

2

V

_OUT=(√(500mVAC) +(0.8mVDC) )•1.003+0.2mV

= 501.70mV

= 500mV + 0.340%

2

V_OUT= (√(50mV AC) + (0.8mV DC) ) • 1.003 + 0.2mV

= 50.356mV

= 50mV + 0.713%

2

V_OUT= (√(5mV AC) + (0.8mV DC) ) • 1.003 + 0.2mV

Input Impedance

= 5.279mV

= 5mV + 5.57%

The LTC1966 true RMS-to-DC converter utilizes a 2.5pF

capacitor to sample the input at a nominal 100kHz sample

frequency. This accounts for the 8MΩ input impedance.

See Figure 21 for the equivalent analog input circuit. Note

however, that the 8MΩ input impedance does not directly

affect the input sampling accuracy. For instance, if a 100k

source resistance is used to drive the LTC1966, the

sampling action of the input stage will drag down the

voltage seen at the input pins with small spikes at every

sampleclockedgeasthesamplecapacitorisconnectedto

be charged. The time constant of this combination is

These static error terms are in addition to dynamic error

terms that depend on the input signal. See the Design

CookbookforadiscussionoftheDCconversionerrorwith

low frequency AC inputs. The LTC1966 bandwidth limita-

tions cause additional errors with high frequency inputs.

Another dynamic error is due to crest factor. The LTC1966

performance versus crest factor is shown in the Typical

Performance Characteristics.

Output Errors Versus Frequency

V

DD

As mentioned in the design cookbook, the LTC1966 per-

formsverywellwithlowfrequencyandverylowfrequency

inputs, provided a large enough averaging capacitor is

used.

I

IN1

R

(TYP)

SW

6k

IN1

V

_IN1− V

C

IN2

EQ

I IN1

=

(

)

AVG

2.5pF

(TYP)

R_EQ

− V

V

DD

V

SS

IN2

IN1

I IN2

(

R_EQ= 8MΩ

=

)

I

IN2

R_EQ

R

(TYP)

SW

6k

However,theLTC1966willhaveadditionaldynamicerrors

as the input frequency is increased. The LTC1966 is de-

signed for high accuracy RMS-to-DC conversion of sig-

nals into the audible range. The input sampling amplifiers

IN2

C

EQ

2.5pF

(TYP)

1966 F21

V

SS

Figure 21. LTC1966 Equivalent Analog Input Circuit

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Output Impedance

small, 2.5pF•100kΩ=250ns, andduringthe2.5µsperiod

devoted to sampling, ten time constants elapse. This

allowseachsampletosettletowithin46ppmanditisthese

samples that are used to compute the RMS value.

The LTC1966 output impedance during operation is simi-

larly due to a switched capacitor action. In this case, 59pF

ofon-chipcapacitanceoperatingat100kHztranslatesinto

170kΩ. The closed-loop RMS-to-DC calculation cuts that

in half to the nominal 85kΩ specified.

This is a much higher accuracy than the LTC1966 conver-

sion limits, and far better than the accuracy computed via

the simplistic resistive divider model:

In order to create a DC result, a large averaging capacitor

is required. Capacitive loading and time constants are not

an issue on the output.

However, resistive loading is an issue and the 10MΩ

impedance of a DMM or 10× scope probe will drag the

output down by –0.85% typ.

R_IN

V = V_SOURCE

IN

R_IN+R_SOURCE

8MΩ

8MΩ +100kΩ

During shutdown, the switching action is halted and a

fixed 30k resistor shunts V_OUTto OUT RTN so that C_AVEis

discharged.

= V_SOURCE

= V_SOURCE– 1.25%

Interfacing with an ADC

The LTC1966 output impedance and the RMS averaging

ripple need to be considered when using an analog-to-

digital converter (ADC) to digitize the LTC1966 RMS

result.

This resistive divider calculation does give the correct

model of what voltage is seen at the input terminals by a

parallel load averaged over a several clock cycles, which is

what a large shunt capacitor will do—average the current

spikes over several clock cycles.

The simplest configuration is to connect the LTC1966

directly to the input of a type 7106/7136 ADC as shown in

Figure 22a. These devices are designed specifically for

DVM/DPM use and include display drivers for a 3 1/2 digit

LCD segmented display. Using a dual-slope conversion,

theinputissampledoveralongintegrationwindow,which

results in rejection of line frequency ripple when integra-

tion time is an integer number of line cycles. Finally, these

parts have an input impedance in the GΩ range, with

specified input leakage of 10pA to 20pA. Such a leakage,

combined with the LTC1966 output impedance, results in

just 1µV to 2µV of additional output offset voltage.

Whenhighsourceimpedancesareused,caremustbetaken

to minimize shunt capacitance at the LTC1966 input so as

not to increase the settling time. Shunt capacitance of just

2.5pF will double the input settling time constant and the

error in the above example grows from 46ppm to 0.67%

(6700ppm). A 13pF scope probe will increase the error to

almost 20%. As a consequence, it is important to not try

tofiltertheinputwithlargeinputcapacitancesunlessdriven

by a low impedance. Keep time constant <<2.5µs.

When the LTC1966 is driven by op amp outputs, whose

low DC impedance can be compromised by sharp capaci-

tive load switching, a small series resistor may be added.

A 10k resistor will easily settle with the 2.5pF input

sampling capacitor to within 1ppm.

Another type of ADC that has inherent rejection of RMS

averaging ripple is an oversampling ∆Σ ADC such as the

LTC2420. Its input impedance is 6.5MΩ, but only when it

is sampling. Since this occurs only half the time at most,

if it directly loads the LTC1966, a gain error of –0.54% to

–0.73% results. In fact, the LTC2420 DC input current is

not zero at 0V, but rather at one half its reference, so both

These are important points to consider both during design

anddebug.Duringlabdebug,andevenproductiontesting,

a high value series resistor to any test point is advisable.

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The DC-accurate filter of Figure 14 is attractive from an

error standpoint, but it increases the impedance at the

ADC input. In most cases, the buffered post filter of

Figure 13 will be more appropriate for use with Nyquist

analog-to-digital converters.

LTC1966

7106 TYPE

5

6

31

30

OUTPUT

IN HI

C

AVE

OUT RTN

IN LO

1966 F22a

Figure 22a. Interfacing to DVM/DPM ADC

SYSTEM CALIBRATION

LTC1966

LTC2420

V SDO

IN

5

6

3

4

OUTPUT

OUT RTN

The LTC1966 static accuracy can be improved with end-

system calibration. Traditionally, calibration has been

done at the factory, or at a service depot only, typically

using manually adjusted potentiometers. Increasingly,

systems are being designed for electronic calibration

where the accuracy corrections are implemented in digital

code wherever possible, and with calibration DACs where

necessary. Additionally, many systems are now designed

for self calibration, in which the calibration occurs inside

the machine, automatically without user intervention.

SERIAL

DATA

C

AVE

GND SCK

CS

1966 F22b

DIGITALLY CORRECT

LOADING ERRORS

Figure 22b. Interfacing to LTC2420

an output offset and a gain error will result. These errors

will vary from part to part, but with a specific LTC1966 and

LTC2420 combination, the errors will be fixed, varying

less than ±0.05% over temperature. So a system that has

digital calibration can be quite accurate despite the nomi-

nal gain and offset error. With 20 bits of resolution, this

part is more accurate than the LTC1966, but the extra

resolution is helpful because it reduces nonlinearity at the

LSB transitions as a digital gain correction is made.

Furthermore, its small size and ease of use make it

attractive.

Whatever calibration scheme is used, the linearity of the

LTC1966 will improve the calibrated accuracy over that

achievablewitholderlog/antilogRMS-to-DCconverters.

Additionally, calibration using DC reference voltages are

essentially as accurate with the LTC1966 as those using

ACreferencevoltages.Olderlog/antilogRMS-to-DCcon-

vertersrequirednonlinearinputstages(rectifiers)whose

linearity would typically render DC-based calibration

unworkable.

ThisconnectionisshowninFigure22b,wheretheLTC2420

issettocontinuouslyconvertbygroundingtheCSpin.The

gain error will be less if CS is driven at a slower rate,

however, the rate should either be consistent or at a rate

low enough that the LTC1966 and its output capacitor

have fully settled by the beginning of each conversion, so

that the loading errors are consistent.

The following are four suggested calibration methods.

Implementations of the suggested adjustments are de-

pendentonthesystemdesign,butinmanycases,gainand

output offset can be corrected in the digital domain, and

will include the effect of all gains and offsets from the

LTC1966 output through the ADC. Input offset voltage, on

the other hand, will have to be corrected with adjustment

to the actual analog input to the LTC1966.

ThelowpowerconsumptionoftheLTC1966makesitwell-

suited for battery-powered applications, and its slow

output (DC) makes it an ideal candidate for a micropower

ADC. Figure10inApplicationNote75, forinstance, details

a 10-bit ADC with a 35ms conversion time that uses just

29µA of supply current. Such an ADC may also be of use

within a 4mA to 20mA loop.

AC-Only, 1 Point

The dominant error at full scale will be caused by the gain

error, and by applying a full-scale sine wave input, this

errorcanbemeasuredandcorrectedfor. Unlikeolderlog/

antilog RMS-to-DC converters, the correction should be

made for zero error at full scale to minimize errors

Other types of ADCs sample the input signal once and

perform a conversion on that one sample. With these

ADCs (Nyquist ADCs), a post filter will be needed in most

cases to reduce the peak error with low input frequencies.

throughout the dynamic range.

sn1966 1966fas

25

LTC1966

W U U

U

APPLICATIO S I FOR ATIO

The best frequency for the calibration signal is roughly ten

times the –0.1% DC error frequency. For 1µF, –0.1% DC

erroroccursat8Hz,so80Hzisagoodcalibrationfrequency,

although anywhere from 60Hz to 100Hz should suffice.

that the LTC1966 input offset voltage plays a role. It is

therefore suggested that a DC-based calibration scheme

check at least two points: ±full scale. Applying the –full-

scale input can be done by physically inverting the voltage

or by applying the same +full-scale input to the opposite

LTC1966 input.

The trade-off here is that on the one hand, the DC error is

input frequency dependent, so a calibration signal fre-

quency high enough to make the DC error negligible

should be used. On the other hand, as low a frequency as

can be used is best to avoid attenuation of the calibrated

AC signal, either from parasitic RC loading or insufficient

op amp gain. For instance, with a 1kHz calibration signal,

a 1MHz op amp will typically only have 60dB of open-loop

gain,soitcouldattenuatethecalibrationsignalafull0.1%.

For an otherwise AC-coupled application, only the gain

term may be worth correcting for, but for DC-coupled

applications, the input offset voltage can also be calcu-

lated and corrected for.

The calculations of the error terms for a 200mV full-scale

case are:

Reading at 200mV +Reading at – 200mV

Gain =

400mV

AC-Only, 2 Point

The next most significant error for AC-coupled applica-

tions will be the effect of output offset voltage, noticeable

at the bottom end of the input scale. This too can be

calibrated out if two measurements are made, one with a

full-scale sine wave input and a second with a sine wave

input (of the same frequency) at 10% of full scale. The

trade-off in selecting this second level is that it should be

small enough that the gain error effect becomes small

compared to the gain error effect at full scale, while on the

otherhand,notusingsosmallaninputthattheinputoffset

voltage becomes an issue.

Reading at – 200mV – Reading at 200mV

Input Offset =

2•Gain

Note: Calculation of and correction for input offset voltage

are the only way in which the two LTC1966 inputs (IN1,

IN2) are distinguishable from each other. The calculation

above assumes the standard definition of offset; that a

positive offset is the case of a positive voltage error inside

the device that must be corrected by applying a like

negative voltage outside. The offset is referred to which-

ever pin is driven positive for the +full-scale reading.

The calculations of the error terms for a 200mV full-scale

case are:

DC, 3 Point

One more point is needed with a DC calibration scheme to

determine output offset voltage: +10% of full scale.

Reading at 200mV – Reading at 20mV

Gain =

180mV

The calculation of the input offset is the same as for the

2-point calibration above, while the gain and output offset

are calculated for a 200mV full-scale case as:

Reading at 20mV

Output Offset =

– 20mV

Gain

Reading at 200mV –Reading at 20mV

DC, 2 Point

Gain =

180mV

DC-based calibration is preferable in many cases because

aDCvoltageofknown,goodaccuracyiseasiertogenerate

than such an AC calibration voltage. The only down side is

Output Offset =

Reading at 200mV +Reading at – 200mV – 400mV •Gain

2

sn1966 1966fas

26

LTC1966

W U U

APPLICATIO S I FOR ATIO

U

TROUBLESHOOTING GUIDE

4. Gain is low by a few percent, along with other screwy

results.

Top Ten LTC1966 Application Mistakes

– Probably tried to use output in a floating, differential

manner.

1. Circuit won’t work–Dead On Arrival–no power drawn.

– Probably forgot to enable the LTC1966 by pulling

Pin 8 low.

Solution: Tie Pin 6 to a low impedance. See “Output

Connections” in the Design Cookbook.

Solution: Tie Pin 8 to Pin 1.

GROUND PIN 6

2. Circuit won’t work, but draws power. Zero or very

little output, single-ended input application.

– Probably didn’t connect both input pins.

LTC1966

TYPE 7136

ADC

5

6

31

30

V

HI

Solution: Tie both inputs to something. See “Input

Connections” in the Design Cookbook.

OUT

OUT RTN

LO

CONNECT PIN 3

1966 TS04

2

IN1

5. Offsets perceived to be out of specification because 0V

in ≠ 0V out.

LTC1966

3

– The offsets are not specified at 0V in. No RMS-to-

DCconverterworkswellat0duetoadivide-by-zero

calculation.

IN2

NC

1966 TS02

Solution: Measure V_IOS/V_OOSby extrapolating read-

ings > ±5mV_DC.

3. Screwy results, particularly with respect to linearity

or high crest factors; differential input application.

– Probably AC-coupled both input pins.

6. Linearity perceived to be out of specification particu-

larly with small input signals.

– This could again be due to using 0V in as one of the

measurement points.

Solution: Make at least one input DC-coupled. See

“Input Connections” in the Design Cookbook.

Solution: Check Linearity from 5mV_RMSto

500mV_RMS

.

DC-COUPLE ONE INPUT

DC-CONNECT ONE INPUT

–

The input offset voltage can cause small AC linear

ityerrorsatlowinputamplitudesaswell.See“Error

Analyses” section.

2

IN1

Possible Solution: Include a trim for input offset.

LTC1966

3

IN2

1966 TS03

sn1966 1966fas

27

LTC1966

W U U

U

APPLICATIO S I FOR ATIO

7. Output is noisy with >10kHz inputs.

10. Gain is low by 1% or more, no other problems.

– Probably due to circuit loading. With a DMM or a

10× scope probe, Z_IN= 10MΩ. The LTC1966

output is 85kΩ, resulting in –0.85% gain error.

Output impedance is higher with the DC accurate

post filter.

– This is a fundamental characteristic of this topol-

ogy. The LTC1966 is designed to work very well

withinputsof1kHzorless. Itworksokayashighas

1MHz, but it is limited by aliased ∆Σ noise.

Solution: Bandwidth limit the input or digitally filter

the resulting output.

Solution: Remove the shunt loading or buffer the

output.

8. Large errors occur at crest factors approaching, but

less than 4.

– Loading can also be caused by cheap averaging

capacitors.

– Insufficient averaging.

Solution: Increase C_AVE. See “Crest Factor and AC +

DC Waveforms” section for discussion of output

droop.

Solution: Use a high quality metal film capacitor

for C_AVE

.

LOADING DRAGS DOWN GAIN

9. Screwyresults,errors>speclimits,typically1%to5%.

– High impedance (85kΩ) and high accuracy (0.1%)

require clean boards! Flux residue, finger grime, etc.

all wreak havoc at this level.

mV

LTC1966

5

6

Solution: Wash the board.

DCV

V

OUT

85k

10M

OUT RTN

KEEP BOARD CLEAN

DMM

IN

200mV

RMS

–0.85%

1966 TS10

LTC1966

sn1966 1966fas

28

LTC1966

U

TYPICAL APPLICATIO S

±5V Supplies, Differential, DC-Coupled

5V Single Supply, Differential, AC-Coupled

RMS-to-DC Converter

5V

V

DD

LTC1966

DC + AC

AC INPUTS

PEAK

DIFFERENTIAL)

IN1

IN2 OUT RTN

GND EN

V

DC OUTPUT

IN1

V

DC OUTPUT

OUT

IN2 OUT RTN

GND EN

INPUTS

C

AVE

1µF

(1V

AVE

(1V

PEAK

DIFFERENTIAL)

1µF

V

C

SS

C

0.1µF

1966 TA05

1966 TA03

–5V

2.7V Single Supply, Single Ended, AC-Coupled

RMS-to-DC Converter with Shutdown

2.7V/3V CMOS

2.7V

OFF

ON

EN

LTC1966

IN1

IN2 OUT RTN

GND

V

DD

AC INPUT

V

DC OUTPUT

OUT

(1V

)

C

PEAK

AVE

1µF

C

V

SS

0.1µF

1966 TA04

Single Supply RMS Current Measurement

+

V

IN1

LTC1966

AC CURRENT

75A MAX

50Hz TO 400Hz

V

V = 4mV /A

OUT DC RMS

T1 10Ω

OUT

C

AVE

IN2 OUT RTN

GND EN

1µF

V

SS

100k

1966 TA08

0.1µF

T1: CR MAGNETICS CR8348-2500-N

www.crmagnetics.com

sn1966 1966fas

29

LTC1966

W

SI PLIFIED SCHE ATIC

V

DD

C12

GND

V

SS

C1

Y1

Y2

∫

C2

IN1

IN2

2nd ORDER ∆Σ MODULATOR

C7

C3

C4

C5

C9

OUTPUT

OUT RTN

+

–

C

C11

AVE

A1

A2

–

C8

1966 SS

C6

C10

CLOSED

DURING

SHUTDOWN

30k

BLEED RESISTOR

FOR C

EN

AVE

TO BIAS CONTROL

sn1966 1966fas

30

LTC1966

U

PACKAGE DESCRIPTIO

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

0.889 ± 0.127

(.035 ± .005)

5.23

(.206)

MIN

3.2 – 3.45

(.126 – .136)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.52

(.206)

REF

0.65

(.0256)

BSC

0.42 ± 0.04

(.0165 ± .0015)

TYP

8

7 6

5

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

NOTE 4

4.90 ± 0.15

(1.93 ± .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4

0.53 ± 0.015

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.077)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.13 ± 0.076

(.005 ± .003)

0.65

(.0256)

BSC

MSOP (MS8) 0802

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

sn1966 1966fas

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.

31

LTC1966

U

TYPICAL APPLICATIO S

±2.5V Supplies, Single Ended, DC-Coupled

RMS Noise Measurement

RMS-to-DC Converter with Shutdown

0.1µF

X7R

2.5V

5V

≥2V

–2.5V

VOLTAGE

NOISE IN

OFF ON

5V

≤–2V

1mV

RMS

DC

NOISE

V

DD

V

=

OUT

EN

LTC1966

IN1

IN2 OUT RTN

V

DD

1µV

+

LTC1966

IN1

IN2 OUT RTN

GND EN

10k

1/2

LTC6203

DC + AC

INPUT

(1V

V

OUT

100Ω

C

1µF

AVE

V

DC OUTPUT

OUT

C

AVE

)

PEAK

–

1µF

V

SS

V

GND

–5V

100k

SS

0.1µF

1966 TA10

–5V

100Ω

1.5µF

1966 TA06

–2.5V

BW ≈ 1kHz TO 100kHz

INPUT SENSITIVITY = 1µV

TYP

RMS

Battery-Powered Single-Ended AC-Coupled

RMS-to-DC Converter

75A Current Measurement

AC INPUT

(1V

PEAK

)

5V

V

DD

C

9V

IN1

0.1µF

LTC1966

IN1

IN2 OUT RTN

GND EN

LTC1966

AC CURRENT

75A MAX

50Hz TO 400Hz

DC

OUTPUT

V

OUT

DC RMS

V

OUT

V

T1 10Ω

OUT

4mV /A

C

AVE

C

AVE

1µF

IN2 OUT RTN

GND EN

1µF

0.1µF

X7R

GND

V

SS

V

SS

LT1175CS8-5

SHDN

OUT

–5V

V

IN

SENSE

T1: CR MAGNETICS CR8348-2500-N

www.crmagnetics.com

1966 TA09

1966 TA07

RELATED PARTS

PART NUMBER

LT^®1077

DESCRIPTION

Micropower, Single Supply Precision Op Amp

COMMENTS

48µA I , 60µV V

, 450pA I

OS(MAX) OS(MAX)

SY

LT1175-5

LT1494

Negative, –5V Fixed, Micropower LDO Regulator

1.5µA Max, Precision Rail-to-Rail I/O Op Amp

General Purpose SOT-23 Rail-to-Rail Op Amp

SOT-23 Rail-to-Rail Output Precision Op Amp

Zero Drift Op Amp in SOT-23

45µA I , Available in SO-8 or SOT-223

Q

375µV V

, 100pA I

OS(MAX) OS(MAX)

LT1782

40µA I , 800µV V

, 2nA I

OS(MAX) OS(MAX)

SY

LT1880

1.2mA I , 150µV V

, 900pA I

OS(MAX)

SY

OS(MAX)

LTC2050

750µA I , 3µV V

, 75pA I

SY

OS(MAX)

B(MAX)

LT2178/LT2178A

LTC2402

17µA Max, Single Supply Precision Dual Op Amp

2-Channel, 24-bit, Micropower, No Latency ∆Σ^TMADC

20-bit, Micropower, No Latency ∆Σ ADC in SO-8

2-Channel, 20-bit, Micropower, No Latency ∆Σ ADC

14µA I , 120µV V

, 350pA I

SY

OS(MAX)

200µA I , 4ppm INL, 10ppm TUE

SY

LTC2420

200µA I , 8ppm INL, 16ppm TUE

SY

LTC2422

Dual channel version of LTC2420

No Latency ∆Σ is a trademark of Linear Technology Corporation.

sn1966 1966fas

LT/TP 1002 1K REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2001


型号：	LTC1966
厂家：	Linear
描述：	Precision Micropower, SIGMA RMS-to-DC Converter 精密微，适马RMS至DC转换器转换器
文件：	总32页 (文件大小：446K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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