LTC1877IMS8#PBF [Linear]
LTC1877 - High Efficiency Monolithic Synchronous Step-Down Regulator; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC1877IMS8#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1877 - High Efficiency Monolithic Synchronous Step-Down Regulator; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总18页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1877
High Efficiency
Monolithic Synchronous
Step-Down Regulator
FEATURES
DESCRIPTION
The LTC®1877 s a high efficiency monolithic synchronous
buck regulator using a constant-frequency, current mode
architecture. Supplycurrentduringoperationisonly10μA
and drops to < 1μA in shutdown. The 2.65V to 10V input
voltage range makes the LTC1877 ideally suited for both
singleanddualLi-Ionbattery-poweredapplications.100%
duty cycle provides low dropout operation, extending bat-
tery life in portable systems.
n
High Efficiency: Up to 95%
n
Very Low Quiescent Current: Only 10μA
During Operation
n
600mA Output Current at V = 5V
IN
n
2.65V to 10V Input Voltage Range
n
550kHz Constant-Frequency Operation
n
No Schottky Diode Required
n
Low Dropout Operation: 100% Duty Cycle
n
Synchronizable from 400kHz to 700kHz
Switching frequency is internally set at 550kHz, allowing
the use of small surface mount inductors and capacitors.
For noise sensitive applications the LTC1877 can be exter-
nally synchronized from 400kHz to 700kHz. Burst Mode
operation is inhibited during synchronization or when the
SYNC/MODE pin is pulled low, preventing low frequency
ripple from interfering with audio circuitry.
Selectable Burst Mode® Operation or
n
Pulse-Skipping Mode
n
0.8V Reference Allows Low Output Voltages
n
Shutdown Mode Draws < 1μA Supply Current
n
2% Output Voltage Accuracy
n
Current Mode Control for Excellent Line and Load
Transient Response
n
The internal synchronous switch increases efficiency
and eliminates the need for an external Schottky diode.
Low output voltages are easily supported with the 0.8V
feedback reference voltage. The LTC1877 is available in a
space saving 8-lead MSOP package. Lower input voltage
applications (less than 7V abs max) should refer to the
LTC1878 data sheet.
Overcurrent and Overtemperature Protected
n
Available in 8-Lead MSOP Package
APPLICATIONS
n
Cellular Telephones
n
Wireless Modems
n
Personal Information Appliances
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
n
Portable Instruments
n
Distributed Power Systems
n
Battery-Powered Equipment
Efficiency vs Output Current
TYPICAL APPLICATION
High Efficiency Step-Down Converter
10μH*
100
V
IN
= 3.6V
95
90
85
80
75
70
65
60
55
50
V
IN
†
5
7
6
1
2
V
OUT
3.3V
SW
SYNC
LTC1877
2.65V
TO 10V
V
IN
= 10V
20pF
10μF**
CER
+
V
IN
V
IN
= 7.2V
47μF***
RUN
887k
280k
V
IN
= 5V
3
V
FB
I
TH
GND
4
220pF
V
= 3.3V
OUT
L = 10μH
*TOKO D62CB A920CY-100M
Burst Mode OPERATION
**TAIYO-YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
0.1
1000
1.0
10
100
†V
CONNECTED TO V FOR 2.65V < V < 3.3V
1877 TA01
OUT
IN IN
OUTPUT CURRENT (mA)
1877 TA02
1877fb
1
LTC1877
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Input Supply Voltage (V )..........................–0.3V to 11V
TH
TOP VIEW
IN
I , PLL LPF Voltage................................. –0.3V to 2.7V
RUN 1
8 PLL LPF
7 SYNC/MODE
I
TH
2
3
4
RUN, V Voltages ...................................... –0.3V to V
FB
IN
IN
V
FB
6 V
5 SW
IN
GND
SYNC/MODE Voltage .................................. –0.3V to V
MS8 PACKAGE
8-LEAD PLASTIC MSOP
SW Voltage ................................... –0.3V to (V + 0.3V)
IN
P-Channel MOSFET Source Current (DC)............ 800mA
N-Channel MOSFET Sink Current (DC)................ 800mA
Peak SW Sink and Source Current ..........................1.5A
Operating Temperature Range (Note 2).....–40°C to 85°C
Junction Temperature (Note 3) ............................ 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
T
JMAX
= 125°C, θ = 150°C/W
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC1877EMS8#PBF
LTC1877IMS8#PBF
TAPE AND REEL
PART MARKING
LTLU
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
TEMPERATURE RANGE
LTC1877EMS8#TRPBF
LTC1877IMS8#TRPBF
–40°C to 85°C
–40°C to 85°C
LTLV
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
I
Feedback Current
Regulated Output Voltage
(Note 4)
4
30
nA
VFB
V
(Note 4) 0°C ≤ T ≤ 85°C
(Note 4) –40°C ≤ T ≤ 85°C
0.784
0.74
0.8
0.8
0.816
0.84
V
V
FB
A
l
l
A
ΔV
ΔV
Output Overvoltage Lockout
ΔV
OVL
= V
– V
FB
20
50
110
mV
OVL
OVL
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
IN
= 2.65V to 10V (Note 4)
0.05
0.15
%/V
FB
l
l
V
Measured in Servo Loop; V = 0.9V to 1.2V
Measured in Servo Loop; V = 1.6V to 1.2V
0.1
–0.1
0.5
–0.5
%
%
LOADREG
ITH
ITH
l
V
IN
Input Voltage Range
2.65
10
V
I
Input DC Bias Current
Pulse-Skipping Mode
Burst Mode Operation
Shutdown
(Note 5)
Q
2.65V < V < 10V, V
= 0V, I = 0A
OUT
230
10
0
350
15
1
μA
μA
μA
IN
SYNC/MODE
V
V
= V , I
= 0A
SYNC/MODE
RUN
IN OUT
= 0V, V = 10V
IN
f
f
Oscillator Frequency
V
FB
V
FB
= 0.8V
= 0V
495
400
550
80
605
kHz
kHz
OSC
SYNC Capture Range
700
kHz
SYNC
1877fb
2
LTC1877
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
PLL LPF
l
l
f
f
< f
> f
3
–3
10
–10
20
–20
μA
μA
PLLIN
PLLIN
OSC
OSC
R
R
R
R
of P-Channel MOSFET
of N-Channel MOSFET
I
I
= 100mA
0.65
0.75
1.0
0.85
0.95
1.25
1
Ω
Ω
A
PFET
DS(ON)
SW
SW
= –100mA
NFET
DS(ON)
I
I
Peak Inductor Current
SW Leakage
V
= 0.7V, Duty Cycle < 35%
0.8
0.3
0.3
PK
LSW
FB
V
= 0V, V = 0V or 8.5V, V = 8.5V
0.01
1.0
μA
V
RUN
SW
IN
l
l
V
SYNC/MODE Threshold
SYNC/MODE Leakage Current
RUN Threshold
1.5
1
SYNC/MODE
SYNC/MODE
I
0.01
0.7
μA
V
V
1.5
1
RUN
I
RUN Input Current
0.01
μA
RUN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: T is calculated from the ambient temperature T and power
J A
dissipation P according to the following formulas:
D
LTC1877EMS8: T = T + (P )(150°C/W)
J
A
D
Note 4: The LTC1877 is tested in a feedback loop which servos V to the
FB
Note 2: The LTC1877E is guaranteed to meet specifications from 0°C to
85°C. Specifications over the –40°C to 85°C operating temperature range
are assured by design, characterization and correlation with statistical
process controls. The LTC1877I is guaranteed over the full –40°C to 85°C
operating temperature range.
balance point for the error amplifier (V = 1.2V).
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
ITH
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Input Voltage
Efficiency vs Output Current
Efficiency vs Output Current
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
95
90
85
80
75
70
65
60
55
V
IN
= 3.6V
I
= 100mA
LOAD
I
= 10mA
LOAD
L = 15μH
L = 10μH
V
IN
= 7.2V
V
IN
= 7.2V
I
= 300mA
LOAD
I
= 1mA
LOAD
V
IN
= 3.6V
I
= 0.1mA
LOAD
PULSE-SKIPPING MODE
Burst Mode OPERATION
V
OUT
= 2.5V
V
V
= 10V
IN
OUT
L = 10μH
Burst Mode OPERATION
V
= 2.5V
OUT
= 3.3V
L = 10μH
Burst Mode OPERATION
0
2
6
8
10
12
4
0.1
1000
0.1
1000
1.0
10
100
1.0
10
100
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
1877 G01
1877 G02
1877 G03
1877fb
3
LTC1877
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Efficiency vs Output Current
Reference Voltage vs Temperature
95
90
85
80
75
70
65
60
55
50
0.814
0.809
0.804
0.799
0.794
0.789
0.784
605
595
585
575
565
555
545
535
525
515
505
495
V
IN
= 5V
V
IN
= 5V
V
IN
= 3.6V
V
IN
= 10V
V
= 7.2V
IN
V
IN
= 5V
L = 10μH
V
OUT
= 2.5V
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
50
75
100 125
–50 –25
0
25
75
0.1
1000
1.0
10
100
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
1877 G05
1877 G06
1877 G04
Oscillator Frequency
vs Supply Voltage
Output Voltage vs Load Current
RDS(ON) vs Input Voltage
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
2.44
2.43
605
595
585
575
565
555
545
535
525
515
505
495
1.2
1.0
0.8
0.6
0.4
0.2
0
PULSE-SKIPPING MODE
V
= 4.2V
IN
L = 10μH
SYNCHRONOUS
SWITCH
MAIN SWITCH
0
200
400
600
800
0
2
4
6
8
10
12
0
1
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
SUPPLY VOLTAGE (V)
1877 G08
1877 G07
1877 G09
DC Supply Current vs Temperature
RDS(ON) vs Temperature
DC Supply Current vs Input Voltage
1.4
1.2
1.0
0.8
0.6
0.4
0.2
250
200
150
100
50
300
250
200
150
100
50
V
IN
= 5V
PULSE-SKIPPING MODE
PULSE-SKIPPING MODE
V
OUT
= 1.8V
V
IN
= 3V
V
IN
= 5V
SYNCHRONOUS SWITCH
MAIN SWITCH
Burst Mode OPERATION
Burst Mode OPERATION
50
TEMPERATURE (°C)
0
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
2
4
6
8
10
100 125
–50 –25
0
25
75
INPUT VOLTAGE (V)
1877 G10
1877 G11
1877 G11b
1877fb
4
LTC1877
TYPICAL PERFORMANCE CHARACTERISTICS
Switch Leakage vs Temperature
Switch Leakage vs Input Voltage
Burst Mode Operation
1400
1200
1000
800
600
400
200
0
16
14
12
10
8
V
= 10V
RUN = 0V
IN
RUN = 0V
SW
5V/DIV
MAIN SWITCH
V
OUT
SYNCHRONOUS
SWITCH
20mV/DIV
AC COUPLED
6
SYNCHRONOUS
4
I
L
SWITCH
200mA/DIV
2
MAIN SWITCH
0
1877 G14
2
4
8
10μs/DIV
L = 10μH
25
50
75
100 125
0
10
–50 –25
0
6
V
V
C
= 5V
= 1.5V
TEMPERATURE (°C)
INPUT VOLTAGE (V)
IN
C
LOAD
= 47μF
= 50mA
OUT
IN
OUT
1877 G12
1877 G13
= 10μF
I
Start-Up from Shutdown
Load Step Response
RUN
5V/DIV
V
OUT
50mV/DIV
AC COUPLED
V
OUT
1V/DIV
I
L
500mA/DIV
I
L
500mA/DIV
I
TH
1V/DIV
1877 G16
1877 G15
50μs/DIV
40μs/DIV
V
V
= 5V
OUT
C
C
I
= 10μF
V
V
= 5V
OUT
C
C
I
= 10μF
IN
IN
IN
IN
= 1.5V
= 47μF
= 500mA
= 1.5V
= 47μF
OUT
OUT
L = 10μH
L = 10μH
= 50mA TO 500mA
LOAD
LOAD
PULSE-SKIPPING MODE
Load Step Response
Load Step Response
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC COUPLED
AC COUPLED
I
I
10Ms/DIV
L
L
500mA/DIV
500mA/DIV
I
I
TH
1V/DIV
TH
1V/DIV
1877 G18
1877 G17
40μs/DIV
20μs/DIV
V
V
= 5V
OUT
C
C
LOAD
= 10μF
V
V
= 5V
OUT
C
C
= 10μF
IN
IN
IN
IN
= 1.5V
= 1.5V
= 47μF
= 47μF
OUT
OUT
L = 10μH
I
= 50mA TO 500mA
L = 10μH
I
= 200mA TO 500mA
LOAD
Burst Mode OPERATION
PULSE-SKIPPING MODE
1877fb
5
LTC1877
PIN FUNCTIONS
RUN (Pin 1): Run Control Input. Forcing this pin below
0.4V shuts down the LTC1877. In shutdown, all functions
are disabled drawing <1μA supply current. Forcing this
pin above 1.2V enables the LTC1877. Do not leave RUN
floating.
V (Pin 6): Main Supply Pin. Must be closely decoupled
IN
to GND, Pin 4.
SYNC/MODE (Pin 7): External Clock Synchronization
and Mode Select Input. To synchronize with an external
clock, apply a clock with a frequency between 400kHz
I (Pin2):ErrorAmplifierCompensationPoint.Thecurrent
and 700kHz. To select Burst Mode operation, tie to V .
TH
IN
comparator threshold increases with this control voltage.
Grounding this pin selects pulse-skipping mode. Do not
Nominal voltage range for this pin is from 0.5V to 1.9V.
leave this pin floating.
V
(Pin 3): Feedback Pin. Receives the feedback voltage
PLLLPF(Pin8):OutputofthePhaseDetectorandControl
Input of Oscillator. Connect a series RC lowpass network
from this pin to ground if externally synchronized. If un-
used, this pin may be left open.
FB
from an external resistive divider across the output.
GND (Pin 4): Ground Pin.
SW (Pin 5): Switch Node Connection to Inductor. This pin
connectstothedrainsoftheinternalmainandsynchronous
power MOSFET switches.
1877fb
6
LTC1877
FUNCTIONAL DIAGRAM
V
IN
BURST
DEFEAT
Y = “0” ONLY WHEN X IS A CONSTANT “1”
Y
X
PLL LPF
8
SLOPE
COMP
SYNC/MODE
7
0.8V
VCO
OSC
0.6V
3
–
V
IN
6
FREQ
SHIFT
+
–
+
V
FB
EN
–
+
SLEEP
+
–
V
0.8V
REF
6Ω
+
–
0.55V
I
COMP
EA
BURST
SLEEP
V
IN
7
Q
S
V
IN
g
= 0.5m
m
R
Q
SWITCHING
LOGIC
AND
I
2
RS LATCH
TH
V
IN
ANTI
SHOOT-
THRU
BLANKING
CIRCUIT
RUN
1
SW
5
4
0.8V REF
–
OVDET
+
0.85V
SHUTDOWN
+
–
I
RCMP
GND
1877 BD
1877fb
7
LTC1877
(Refer to Functional Diagram)
OPERATION
The LTC1877 uses a constant-frequency, current mode
step-down architecture. Both the main (P-channel MOS-
FET) and synchronous (N-channel MOSFET) switches are
internal. During normal operation, the internal top power
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the current comparator,
then disconnected from the output of the EA amplifier and
parked a diode voltage above ground.
In sleep mode, both power MOSFETs are held off and a
majority of the internal circuitry is partially turned off,
reducing the quiescent current to 10μA. The load current
is now being supplied solely from the output capacitor.
I
, resets the RS latch. The peak inductor current at
COMP
which I
When the output voltage drops, the I pin reconnects
TH
resets the RS latch is controlled by the volt-
TH
COMP
to the output of the EA amplifier and the top MOSFET is
age on the I pin, which is the output of error amplifier
EA. The V pin, described in the Pin Functions section,
again turned on and this process repeats.
FB
allows EA to receive an output feedback voltage from an
externalresistivedivider. Whentheloadcurrentincreases,
it causes a slight decrease in the feedback voltage relative
Short-Circuit Protection
When the output is shorted to ground, the frequency of
the oscillator is reduced to about 80kHz, one-seventh the
nominal frequency. This frequency foldback ensures that
the inductor current has ample time to decay, thereby
preventingrunaway.Theoscillator’sfrequencywillprogres-
sively increase to 550kHz (or the synchronized frequency)
to the 0.8V reference, which in turn, causes the I voltage
TH
to increase until the average inductor current matches the
new load current. While the top MOSFET is off, the bottom
MOSFETisturnedonuntileithertheinductorcurrentstarts
to reverse as indicated by the current reversal comparator
when V rises above 0.3V.
FB
I , or the beginning of the next clock cycle.
RCMP
Comparator OVDET guards against transient overshoots
> 6.25% by turning the main switch off and keeping it off
until the fault is removed.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC1877 to
allowtheinternaloscillatortobesynchronizedtoanexternal
source connected to the SYNC/MODE pin. The output of
the phase detector at the PLL LPF pin operates over a 0V
to 2.4V range corresponding to 400kHz to 700kHz. When
locked, the PLL aligns the turn-on of the top MOSFET to
the rising edge of the synchronizing signal.
Burst Mode Operation
The LTC1877 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to V or connect it to a logic
IN
When the LTC1877 is clocked by an external source, Burst
Mode operation is disabled; the LTC1877 then operates in
PWMpulse-skippingmode. Inthismode, whentheoutput
high (V
> 1.5V). To disable Burst Mode opera-
SYNC/MODE
tion and enable PWM pulse-skipping mode, connect the
SYNC/MODE pin to GND. In this mode, the efficiency is
lower at light loads, but becomes comparable to Burst
Mode operation when the output load exceeds 50mA. The
advantage of pulse-skipping mode is lower output ripple
and less interference to audio circuitry.
load is very low, current comparator I
may remain
COMP
trippedforseveralcyclesandforcethemainswitchtostay
off for the same number of cycles. Increasing the output
load slightly allows constant-frequency PWM operation
to resume. This mode exhibits low output ripple as well
as low audio noise and reduced RF interference while
providing reasonable low current efficiency.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 250mA,
even though the voltage at the I pin indicates a lower
TH
Frequency synchronization is inhibited when the feedback
value. The voltage at the I pin drops when the inductor’s
TH
voltage V is below 0.6V. This prevents the external clock
FB
averagecurrentisgreaterthantheloadrequirement.Asthe
from interfering with the frequency foldback for short-
I
voltage drops below approximately 0.55V, the BURST
TH
circuit protection.
comparator trips, causing the internal sleep line to go
high and forces off both power MOSFETs. The I pin is
TH
1877fb
8
LTC1877
OPERATION
Dropout Operation
Another important detail to remember is that at low input
supply voltages, the R
of the P-channel switch in-
DS(ON)
Whentheinputsupplyvoltagedecreasestowardtheoutput
voltage, the duty cycle increases toward the maximum
on-time.Furtherreductionofthesupplyvoltageforcesthe
main switch to remain on for more than one cycle until it
reaches 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
creases. Therefore, the user should calculate the power
dissipation when the LTC1877 is used at 100% duty cycle
with a low input voltage (see Thermal Considerations in
the Applications Information section).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant-fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
addingacompensatingramptotheinductorcurrentsignal
at duty cycles in excess of 40%. As a result, the maximum
inductor peak current is reduced for duty cycles >40%.
This is shown in the decrease of the inductor peak current
as a function of duty cycle graph in Figure 2.
Low Supply Operation
TheLTC1877isdesignedtooperatedowntoaninputsupply
voltage of 2.65V although the maximum allowable output
current is reduced at this low voltage. Figure 1 shows the
reduction in the maximum output current as a function of
input voltage for various output voltages.
1200
1100
V
= 5V
IN
V
OUT
= 2.5V
1000
800
600
400
200
0
1000
900
800
700
600
V
OUT
= 1.5V
V
= 5V
OUT
V
OUT
= 3.3V
L = 10μH
10 12
0
4
6
8
2
0
20
40
60
80
100
V
IN
(V)
DUTY CYCLE (%)
1877 F01
1877 F02
Figure 1. Maximum Output Current vs Input Voltage
Figure 2. Maximum Inductor Peak Current vs Duty Cycle
APPLICATIONS INFORMATION
The basic LTC1877 application circuit is shown on the first
page. External component selection is driven by the load
requirement and begins with the selection of L followed
The operating frequency and inductor selection are inter-
relatedinthathigheroperatingfrequenciesallowtheuseof
smallerinductorandcapacitorvalues. However, operating
at a higher frequency generally results in lower efficiency
because of increased internal gate charge losses.
by C and C
.
IN
OUT
Inductor Value Calculation
The inductor value has a direct effect on ripple current.
The inductor selection will depend on the operating fre-
quency of the LTC1877. The internal nominal frequency is
550kHz, but can be externally synchronized from 400kHz
to 700kHz.
The ripple current ΔI decreases with higher inductance
L
or frequency and increases with higher V or V
.
IN
OUT
⎛
⎞
VOUT
V
IN
1
ΔIL =
VOUT 1−
⎜
⎟
f L
( )( )
⎝
⎠
(1)
1877fb
9
LTC1877
APPLICATIONS INFORMATION
Accepting larger values of ΔI allows the use of low in-
C and C
Selection
L
IN
OUT
ductance, but results in higher output voltage ripple and
Incontinuousmode,thesourcecurrentofthetopMOSFET
greater core losses. A reasonable starting point for setting
is a square wave of duty cycle V /V . To prevent large
OUT IN
ripple current is ΔI = 0.4(I
).
L
MAX
voltage transients, a low ESR input capacitor sized for the
TheinductorvaluealsohasaneffectonBurstModeopera-
tion. The transition to low current operation begins when
the inductor current peaks fall to approximately 250mA.
maximumRMScurrentmustbeused.ThemaximumRMS
capacitor current is given by:
1/2
⎡
⎤
V
V − V
IN
OUT
(
)
⎦
⎣
OUT
C
IN
required I
≅ I
Lower inductor values (higher ΔI ) will cause this to occur
L
RMS OMAX
V
IN
at lower load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
This formula has a maximum at V = 2V , where I
RMS
= I /2. This simple worst-case condition is commonly
IN
OUT
OUT
used for design because even significant deviations do
not offer much relief. Note the capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of
life. This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
size or height requirements in the design. Always consult
the manufacturer if there is any question.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mμ cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple ΔV
is determined by:
OUT
⎛
⎞
1
ΔVOUT ≅ ΔI ESR+
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
⎜
⎟
L
8fCOUT
⎝
⎠
where f = operating frequency, C
= output capacitance
OUT
and ΔI = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ΔI increases
L
with input voltage. For the LTC1877, the general rule for
proper operation is:
C
required ESR < 0.25Ω
OUT
KoolMμ(fromMagnetics,Inc.)isaverygood,lowlosscore
material for toroids with a soft saturation characteristic.
Molypermalloy is slightly more efficient at high (>200kHz)
switching frequencies but quite a bit more expensive. To-
roids are very space efficient, especially when you can use
several layers of wire, while inductors wound on bobbins
are generally easier to surface mount. New designs for
surface mount inductors are available from Coiltronics,
Coilcraft, Dale and Sumida.
Thechoiceofusingasmalleroutputcapacitanceincreases
the output ripple voltage due to the frequency dependent
term but can be compensated for by using capacitor(s) of
very low ESR to maintain low ripple voltage. The I pin
TH
compensation components can be optimized to provide
stable high performance transient response regardless of
the output capacitor selected.
ESR is a direct function of the volume of the capacitor.
ManufacturerssuchasTaiyoYuden,AVX,Sprague,Kemet
and Sanyo should be considered for high performance ca-
1877fb
10
LTC1877
APPLICATIONS INFORMATION
pacitors.ThePOSCAPsolidelectrolyticcapacitoravailable
fromSanyoisanexcellentchoiceforoutputbulkcapacitors
due to its low ESR/size ratio. Once the ESR requirement
Theoutputofthephasedetectorisapairofcomplementary
current sources charging or discharging the external filter
network on the PLL LPF pin. The relationship between the
voltage on the PLL LPF pin and operating frequency is
shown in Figure 4. A simplified block diagram is shown
in Figure 5.
for C
has been met, the RMS current rating generally
OUT
far exceeds the I
requirement.
RIPPLE(P-P)
When using tantalum capacitors, it is critical that they are
surge tested for use in switching power supplies. A good
choice is the AVX TPS series of surface mount tantalum,
availableincaseheightsrangingfrom2mmto4mm.Other
capacitor types include KEMET T510 and T495 series and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
If the external frequency (V
) is greater than
SYNC/MODE
550kHz, the center frequency, current is sourced con-
tinuously, pulling up the PLL LPF pin. When the external
frequencyislessthan550kHz,currentissunkcontinuously,
pulling down the PLL LPF pin. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time cor-
responding to the phase difference. Thus, the voltage on
the PLL LPF pin is adjusted until the phase and frequency
of the external and internal oscillators are identical. At
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
800
700
600
500
400
300
⎛
⎞
⎟
⎠
R2
R1
VOUT = 0.8V 1+
⎜
⎝
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing, as shown in Figure 3.
0.8V b V
b 10V
OUT
R2
V
FB
LTC1877
R1
0
0.8
VPLL LPF (V)
1.2
1.6
2.0
0.4
GND
1877 F04
1877 F03
Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin
Figure 3. Setting the LTC1877 Output Voltage
R
Phase-Locked Loop and Frequency Synchronization
LP
2.4V
PHASE
C
LP
The LTC1877 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edgeofanexternalfrequencysource.Thefrequencyrange
of the voltage-controlled oscillator is 400kHz to 700kHz.
The phase detector used is an edge sensitive digital type
thatprovideszerodegreesphaseshiftbetweentheexternal
and internal oscillators. This type of phase detector will
not lock up on input frequencies close to the harmonics
of the V center frequency. The PLL hold-in range Δf is
DETECTOR
PLL LPF
SYNC/
MODE
DIGITAL
PHASE/
VCO
FREQUENCY
DETECTOR
1877 F05
CO
H
equal to the capture range, Δf = Δf = 150kHz.
H
C
Figure 5. Phase-Locked Loop Block Diagram
1877fb
11
LTC1877
APPLICATIONS INFORMATION
this stable operating point the phase comparator output
I
= f(Q + Q ) where Q and Q are the gate
GATECHG T B T B
is high impedance and the filter capacitor C holds the
charges of the internal top and bottom switches. Both
the DC bias and gate charge losses are proportional
LP
voltage.
to V and thus their effects will be more pronounced
at higher supply voltages.
IN
The loop filter components C and R smooth out the
LP
LP
current pulses from the phase detector and provide a
2
2. I
R losses are calculated from the resistances of the
stable input to the voltage controlled oscillator. The filter
internal switches, R , and external inductor R . In
component’s C and R determine how fast the loop
LP
LP
SW
L
acquires lock. Typically R = 10k and C is 2200pF
continuous mode, the average output current flow-
ing through inductor L is chopped between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
LP
LP
to 0.01μF. When not synchronized to an external clock,
the internal connection to the V is disconnected. This
CO
disallows setting the internal oscillator frequency by a DC
pin.
top and bottom MOSFET R
(DC) as follows:
and the duty cycle
voltage on the V
PLL LPF
DS(ON)
Efficiency Considerations
R
SW
= (R
)(DC) + (R (1 – DC)
DS(ON)TOP DS(ON)BOT)
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
The R
for both the top and bottom MOSFETs can
DS(ON)
be obtained from the Typical Performance Character-
2
istics curves. Thus, to obtain I R losses, simply add
R
to R and multiply the result by the square of the
SW
L
average output current.
Efficiency = 100% – (L1 + L2 + L3 + ...)
Other losses including C and C
ESR dissipative los-
OUT
IN
where L1, L2, etc. are the individual losses as a percent-
age of input power.
ses and inductor core losses generally account for less
than 2% total additional loss.
1
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
V
= 4.2V
IN
L = 10μH
V
V
V
= 1.5V
= 2.5V
= 3.3V
OUT
OUT
OUT
0.1
0.01
the losses in LTC1877 circuits: V quiescent current and
IN
2
I R losses. The V quiescent current loss dominates the
IN
Burst Mode OPERATION
efficiency loss at very low load currents, whereas the
2
I R loss dominates the efficiency loss at medium to high
0.001
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence, as illustrated
in Figure 6.
0.0001
0.00001
0.1
1
10
100
1000
1. The V quiescent current is due to two components:
LOAD CURRENT (mA)
IN
1877 F06
the DC bias current as given in the Electrical Charac-
teristics section and the internal main switch and syn-
chronous switch gate charge currents. The gate charge
current results from switching the gate capacitance
of the internal power MOSFET switches. Each time
the gate is switched from high to low to high again, a
Figure 6. Power Lost vs Load Current
Thermal Considerations
InmostapplicationstheLTC1877doesnotdissipatemuch
heatduetoitshighefficiency.But,inapplicationswherethe
LTC1877 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
packet of charge dQ moves from V to ground. The
IN
resulting dQ/dt is the current out of V that is typically
IN
larger than the DC bias current. In continuous mode,
the heat dissipated may exceed the maximum junction
1877fb
12
LTC1877
APPLICATIONS INFORMATION
temperatureofthepart.Ifthejunctiontemperaturereaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
signal. The regulator loop then acts to return V
steady-state value. During this recovery time V
to its
OUT
OUT
can be
monitored for overshoot or ringing that would indicate a
stability problem. The internal compensation provides
adequate compensation for most applications. But if ad-
To avoid the LTC1877 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
ditional compensation is required, the I pin can be used
TH
for external compensation using R , C , as shown in
C
C1
Figure 7. The 220pF capacitor, C , is typically needed for
C2
noise decoupling.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
T = (P )(θ )
R
D
JA
where P is the power dissipated by the regulator and θ
D
JA
lel with C , causing a rapid drop in V . No regulator
is the thermal resistance from the junction of the die to
the ambient temperature.
OUT
OUT
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
The junction temperature, T , is given by:
J
T = T + T
R
J
A
(25 • C
). Thus, a 10μF capacitor charging to 3.3V
LOAD
where T is the ambient temperature.
A
would require a 250μs rise time, limiting the charging
current to about 130mA.
As an example, consider the LTC1877 in dropout at an
input voltage of 3V, a load current of 500mA, and an am-
bient temperature of 70°C. From the typical performance
PC Board Layout Checklist
graph of switch resistance, the R
switch at 70°C is approximately 0.9Ω. Therefore, power
dissipated by the part is:
of the P-channel
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC1877. These items are also illustrated graphically
in the layout diagram of Figure 7. Check the following in
your layout:
DS(ON)
2
P = I
D
• R
= 0.225W
LOAD
DS(ON)
For the MSOP package, the θ is 150°C/W. Thus, the
JA
1. Are the signal and power grounds segregated? The
LTC1877 signal ground consists of the resistive divider,
the optional compensation network (R and C ) and
junction temperature of the regulator is:
T = 70°C + (0.225)(150) = 104°C
J
C
C1
C . The power ground consists of the (–) plate of C ,
C2
IN
which is below the maximum junction temperature of
125°C.
the(–)plateofC andPin4oftheLTC1877.Thepower
OUT
groundtracesshouldbekeptshort,directandwide.The
signal ground and power ground should converge to a
common node in a star-ground configuration.
Notethatathighersupplyvoltages,thejunctiontemperature
is lower due to reduced switch resistance (R
).
DS(ON)
2. Does the V pin connect directly to the feedback resis-
FB
Checking Transient Response
tors? The resistive divider R1/R2 must be connected
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
between the (+) plate of C
and signal ground.
OUT
3. Does the (+) plate of C connect to V as closely as
IN
IN
possible? This capacitor provides the AC current to the
internal power MOSFETs.
When a load step occurs, V
immediately shifts by an
OUT
amountequalto(ΔI
•ESR), whereESRistheeffective
LOAD
series resistance of C . ΔI
also begins to charge
4. Keep the switching node SW away from sensitive small
OUT
LOAD
signal nodes.
or discharge C , which generates a feedback error
OUT
1877fb
13
LTC1877
APPLICATIONS INFORMATION
Design Example
A 15μH inductor works well for this application. For best
efficiency choose a 1A inductor with less than 0.25Ω
series resistance.
As a design example, assume the LTC1877 is used in a
singlelithium-ionbattery-poweredcellularphoneapplica-
tion. The input voltage will be operating from a maximum
of 4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both
low and high load currents is important. Output voltage
is 2.5V. With this information we can calculate L using
Equation (1),
C
will require an RMS current rating of at least 0.15A
IN
at temperature and C
will require an ESR of less than
OUT
0.25Ω. In most applications, the requirements for these
capacitors are fairly similar.
For the feedback resistors, choose R1 = 412k. R2 can then
be calculated from Equation (2) to be:
⎛
⎞
⎛
⎜
⎝
⎞
VOUT
0.8
1
VOUT
V
IN
R2 =
– 1 R1= 875.5k; use 887k
L =
VOUT 1−
⎟
⎜
⎟
⎠
f ΔI
( )(
⎝
⎠
)
L
(3)
Figure 8 shows the complete circuit along with its ef-
ficiency curve.
Substituting V
= 2.5V, V = 4.2V, ΔI =120mA and
f = 550kHz in Equation (3) gives:
OUT
IN
L
⎛
⎞
⎟
⎠
2.5V
550kHz(120mA)
2.5V
4.2V
L =
1−
= 15.3μH
⎜
⎝
C
C2
LTC1877
OPTIONAL
1
2
3
4
8
RUN
PLL LPF
C
C1
R
C
7
6
5
I
TH
SYNC/MODE
BOLD LINES INDICATE
HIGH CURRENT PATHS
V
V
IN
FB
+
L1
GND
SW
R1
R2
+
+
V
V
IN
OUT
C
IN
C
OUT
–
–
1877 F07
Figure 7. LTC1877 Layout Diagram
95
V
IN
V
IN
= 3.0V
2.7V TO 4.2V
10μF**
CER
90
85
80
75
70
65
60
55
50
1
8
RUN
PLL LPF
220pF
2
7
I
SYNC/MODE
LTC1877
TH
V
= 3.6V
IN
3
4
6
5
V
IN
= 4.2V
V
FB
V
IN
15μH*
V
OUT
GND
SW
2.5V
+
47μF***
887k
20pF
412k
V
= 2.5V
1877 F08a
OUT
L = 15μH
*SUMIDA CD54-150
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
1877 F08b
Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example
1877fb
14
LTC1877
TYPICAL APPLICATIONS
Dual Lithium-Ion to 2.5V/0.6A Regulator
Using All Ceramic Capacitors
4-to 6-Cell NiCd/NiMH to 1.8V/0.6A Regulator
Using All Ceramic Capacitors
1
2
1
2
8
7
8
RUN
RUN
PLL LPF
SYNC/MODE
LTC1877
PLL LPF
V
7
V
IN
IN
I
TH
I
TH
SYNC/MODE
b 8.4V
b 9V
C
10μF
CER
**
C **
IN
10μF
CER
IN
220pF
220pF
LTC1877
3
4
3
4
6
5
6
5
V
FB
V
FB
V
V
IN
IN
V
V
OUT
OUT
GND
GND
SW
SW
2.5V/0.6A
1.8V/0.6A
15μH*
10μH*
20pF
887k
412k
C
22μF
CER
***
887k
698k
20pF
OUT
C
22μF
CER
***
OUT
*SUMIDA CD54-150
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***TAIYO YUDEN CERAMIC JMK325BJ226MM
*TOKO D62CB A920CY-100M
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***TAIYO YUDEN CERAMIC JMK325BJ226MM
1877 TA03
1877 TA04
Externally Synchronized 2.5V/0.6A Regulator
Using All Ceramic Capacitors
Low Noise 2.5V/0.3A Regulator
V
V
IN
IN
4V
2.85V
TO 10V
TO 10V
0.01μF
1
2
8
7
1
2
8
C
10μF
CER
**
IN
C
10μF
CER
**
RUN
PLL LPF
SYNC/MODE
LTC1877
RUN
IN
PLL LPF
EXT
7
I
TH
CLOCK
700kHz
I
TH
SYNC/MODE
10k
220pF
220pF
LTC1877
6
3
4
6
5
3
4
V
V
V
FB
V
IN
FB
IN
V
OUT
2.5V/
0.6A
5
V
OUT
GND
SW
GND
SW
2.5V/0.3A
10μH*
15μH*
20pF
887k
412k
20pF
887k
412k
C
47μF
6.3V
***
OUT
C
22μF
CER
***
OUT
*TOKO D62CB A920CY-100M
*SUMIDA CD54-150
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***TAIYO YUDEN CERAMIC JMK325BJ226MM
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
1877 TA05
1877 TA06
1877fb
15
LTC1877
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
0.889 0.ꢀꢁ7
(.035 .005)
5.ꢁ3
3.ꢁ0 – 3.45
(.ꢁ0ꢂ)
(.ꢀꢁꢂ – .ꢀ3ꢂ)
MIN
3.00 0.ꢀ0ꢁ
(.ꢀꢀ8 .004)
(NOTE 3)
0.5ꢁ
(.0ꢁ05)
REF
0.ꢂ5
(.0ꢁ5ꢂ)
BSC
0.4ꢁ 0.038
(.0ꢀꢂ5 .00ꢀ5)
TYP
8
7 ꢂ 5
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.ꢀ0ꢁ
(.ꢀꢀ8 .004)
(NOTE 4)
4.90 0.ꢀ5ꢁ
(.ꢀ93 .00ꢂ)
DETAIL “A”
0.ꢁ54
(.0ꢀ0)
0° – ꢂ° TYP
GAUGE PLANE
ꢀ
ꢁ
3
4
0.53 0.ꢀ5ꢁ
(.0ꢁꢀ .00ꢂ)
ꢀ.ꢀ0
(.043)
MAX
0.8ꢂ
(.034)
REF
DETAIL “A”
0.ꢀ8
(.007)
SEATING
PLANE
0.ꢁꢁ – 0.38
0.ꢀ0ꢀꢂ 0.0508
(.009 – .0ꢀ5)
(.004 .00ꢁ)
0.ꢂ5
(.0ꢁ5ꢂ)
BSC
TYP
MSOP (MS8) 0307 REV F
NOTE:
ꢀ. DIMENSIONS IN MILLIMETER/(INCH)
ꢁ. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.ꢀ0ꢁmm (.004") MAX
1877fb
16
LTC1877
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
11/11 Part marking for LTC1877IMS8 corrected from LTLU to LTLV
2
1877fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC1877
TYPICAL APPLICATION
Single Lithium-Ion to 3.3V/0.3A Regulator
V
+
–
IN
Li-Ion BATTERY
3V TO 4.2V
1
2
8
7
10μF**
RUN
PLL LPF
SYNC/MODE
LTC1877
I
TH
220pF
3
4
6
5
V
V
FB
IN
V
OUT
GND
SW
3.3V/0.25A
10μH*
20pF
887k
47μF***
280k
1877 TA07
*TOKO D62CB A920CY-100M
**TAIYO YUDEN CERAMIC LMK325BJ106MN
***SANYO POSCAP 6TPA47M
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1174/LTC1174-3.3/
LTC1174-5
High Efficiency Step-Down and Inverting DC/DC Converters
Monolithic Switching Regulators, I
to 450mA,
OUT
Burst Mode Operation
LTC1265
1.2A, High Efficiency Step-Down DC/DC Converter
1.5A, 500kHz Step-Down Switching Regulators
Constant Off-Time, Monolithic, Burst Mode Operation
High Frequency, Small Inductor, High Efficiency
LT®1375/LT1376
LTC1436/LTC1436-PLL
LTC1474/LTC1475
LTC1504A
High Efficiency, Low Noise, Synchronous Step-Down Converters 24-Pin Narrow SSOP
Low Quiescent Current Step-Down DC/DC Converters
Monolithic Synchronous Step-Down Switching Regulator
Low Input Voltage Current Mode Step-Down DC/DC Controller
Low Voltage, High Efficiency Step-Down DC/DC Converter
Monolithic, I to 250mA, I = 10μA, 8-Pin MSOP
OUT Q
Low Cost, Voltage Mode I
to 500mA, V : 4V to 10V
IN
OUT
LTC1622
High Frequency, High Efficiency, 8-Pin MSOP
LTC1626
Monolithic, Constant Off-Time, I
to 600mA, Low Supply
OUT
Voltage Range: 2.5V to 6V
LTC1627
LTC1701
LTC1707
Monolithic Synchronous Step-Down Switching Regulator
Monolithic Current Mode Step-Down Switching Regulator
Monolithic Synchronous Step-Down Switching Regulator
Constant Frequency, I
to 500mA, Secondary Winding
OUT
Regulation, V : 2.65V to 8.5V
IN
Constant Off-Time, I
IN
to 500mA, 1MHz Operation,
OUT
V : 2.5V to 5.5V
1.19V V Pin, Constant Frequency, I
to 600mA,
REF
OUT
V : 2.65V to 8.5V
IN
LTC1735
LTC1772
LTC1878
High Efficiency, Synchronous Step-Down Converter
Low Input Voltage Current Mode Step-Down DC/DC Controller
High Efficiency Monolithic Step-Down Regulator
16-Pin SO and SSOP, V Up to 36V, Fault Protection
IN
550kHz, 6-Pin SOT-23, I
Up to 5A, V : 2.2V to 10V
IN
OUT
550kHz, MS8, V Up to 6V, I = 10μA, I to 600mA
OUT
IN
Q
1877fb
LT 1111 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
●
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© LINEAR TECHNOLOGY CORPORATION 2000
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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