LTC1865LAIS8 [Linear]
μPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; μPower ， 3V ， 16位，下150ksps 1和2通道ADC ，采用MSOP
| 型号： | LTC1865LAIS8 |
| 厂家： | 
Linear |
| 描述： | μPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| 文件： | 总16页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1864L/LTC1865L
µPower, 3V, 16-Bit, 150ksps
1- and 2-Channel ADCs in MSOP
U
FEATURES
DESCRIPTIO
The LTC®1864L/LTC1865L are 16-bit A/D converters that
are offered in MSOP and SO-8 packages and operate on a
single 3V supply. At 150ksps, the supply current is only
450µA. The supply current drops at lower speeds because
the LTC1864L/LTC1865L automatically power down
between conversions. These 16-bit switched capacitor
successiveapproximationADCsincludesample-and-holds.
The LTC1864L has a differential analog input with an
external reference pin. The LTC1865L offers a software-
selectable2-channelMUXandanexternalreferencepinon
the MSOP version.
■
16-Bit 150ksps ADCs in MSOP Package
■
Single 3V Supply
■
Low Supply Current: 450µA (Typ)
Auto Shutdown Reduces Supply Current
to 10µA at 1ksps
True Differential Inputs
■
■
■
1-Channel (LTC1864L) or 2-Channel (LTC1865L)
Versions
SPI/MICROWIRETM Compatible Serial I/O
■
■
16-Bit Upgrade to 12-Bit LTC1285/LTC1288
■
Pin Compatible with 12-Bit LTC1860L/LTC1861L
■
No Minimum Data Transfer Rate
The 3-wire, serial I/O, small MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
U
APPLICATIO S
■
High Speed Data Acquisition
■
Portable or Compact Instrumentation
These ADCs can be used in ratiometric applications or
with external references. The high impedance analog
inputs and the ability to operate with reduced spans down
to 1V full scale allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
■
Low Power Battery-Operated Instrumentation
Isolated and/or Remote Data Acquisition
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
U
TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
Single 3V Supply, 150ksps, 16-Bit Sampling ADC
1000
CONV LOW = 2µs
T
= 25°C
A
1µF
V
= 2.7V
CC
100
3V
LTC1864L
10
1
1
2
3
4
8
7
6
V
V
CC
REF
+
IN
IN
SCK
SDO
ANALOG INPUT
0V TO 3V
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
5
GND
CONV
1864 TA01
0.1
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
1864L/65L TA02
sn18645L 18645Lfs
1
LTC1864L/LTC1865L
W W U W
ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Operating Temperature Range
Supply Voltage (VCC) ................................................. 7V
Ground Voltage Difference
LTC1864LC/LTC1865LC/
LTC1864LAC/LTC1865LAC .................... 0°C to 70°C
LTC1864LI/LTC1865LI/
LTC1864LAI/LTC1865LAI ................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
AGND, DGND LTC1865L MSOP Package ......... ±0.3V
Analog Input ............... (GND – 0.3V) to (VCC + 0.3V)
Digital Input ................................(GND – 0.3V) to 7V
Digital Output .............. (GND – 0.3V) to (VCC + 0.3V)
Power Dissipation.............................................. 400mW
U W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
LTC1865LCMS
LTC1864LCMS8
LTC1864LIMS8
LTC1864LACMS8
LTC1864LAIMS8
CONV
CH0
1
2
3
4
5
10
9
V
V
SCK
SDO
SDI
V
IN
1
2
3
4
8 V
CC
REF
CC
REF
+
7 SCK
LTC1865LIMS
LTC1865LACMS
LTC1865LAIMS
CH1
8
6 SDO
5 CONV
IN¯
AGND
DGND
7
6
GND
MS8 PACKAGE
MS PACKAGE
10-LEAD PLASTIC MSOP
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTC7
MS PART MARKING
LTJ4
TJMAX = 150°C, θJA = 210°C/W
TJMAX = 150°C, θJA = 210°C/W
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CONV
CH0
V
CC
V
V
CC
REF
+
LTC1864LCS8
LTC1864LIS8
LTC1864LACS8
LTC1864LAIS8
LTC1865LCS8
LTC1865LIS8
LTC1865LACS8
LTC1865LAIS8
SCK
SDO
SDI
IN
IN
SCK
–
CH1
SDO
CONV
GND
GND
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
S8 PART MARKING
TJMAX = 150°C, θJA = 175°C/W
TJMAX = 150°C, θJA = 175°C/W
1864L 1864LA
1864LI 864LAI
1865L 1865LA
1865LI 865LAI
Consult LTC Marketing for parts specified with wider operating temperature ranges.
U
U W
CO VERTER A D ULTIPLEXER CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
●
LTC1864L/LTC1865L
LTC1864LA/LTC1865LA
PARAMETER
Resolution
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Bits
●
16
16
No Missing Codes Resolution
INL
●
●
14
15
Bits
(Note 3)
±8
±6
LSB
Transition Noise
Gain Error
2
2
LSB
RMS
●
±20
±20
mV
sn18645L 18645Lfs
2
LTC1864L/LTC1865L
CO VERTER A D ULTIPLEXER CHARACTERISTICS
U
U W
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1864L/LTC1865L
LTC1864LA/LTC1865LA
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
mV
Offset Error
●
●
±2
±5
±2
±5
+
–
Input Differential Voltage
Range
V
= IN – IN
0
V
REF
0
V
REF
V
IN
+
Absolute Input Range
IN Input
–0.05
–0.05
V
+ 0.05
–0.05
–0.05
V
+ 0.05
V
V
CC
V
CC
V
–
IN Input
/2
/2
CC
CC
V
Input Range
LTC1864L SO-8 and MSOP, LTC1865L MSOP
1
V
1
V
CC
V
REF
CC
Analog Input Leakage Current (Note 4)
●
±1
±1
µA
C
Input Capacitance
In Sample Mode
During Conversion
12
5
12
5
pF
pF
IN
U W
DY A IC ACCURACY
TA = 25°C. VCC = 3V, VREF = 3V, fSAMPLE = 150kHz, unless otherwise noted.
LTC1864L/LTC1865L
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
dB
SNR
Signal-to-Noise Ratio
82
S/(N + D) Signal-to-Noise Plus Distortion Ratio
1kHz Input Signal
82
dB
THD
Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal
Full Power Bandwidth
92
dB
10
MHz
kHz
Full Linear Bandwidth
S/(N + D) ≥ 75dB
20
U
DIGITAL A DDCELECTRICALCHARACTERISTICS
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
LTC1864L/LTC1865L
SYMBOL PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
V
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.3V
= 2.7V
●
●
●
●
1.9
CC
CC
IN
0.45
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
OH
V
CC
V
CC
= 2.7V, I = 10µA
= 2.7V, I = 360µA
●
●
2.3
2.1
2.6
2.45
V
V
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 2.7V, I = 400µA
●
●
0.3
V
µA
OL
CC
O
I
I
I
I
CONV = V
±3
OZ
CC
V
OUT
V
OUT
= 0V
–6.5
6.5
mA
mA
SOURCE
SINK
= V
CC
Reference Current (LTC1864L SO-8 and
MSOP, LTC1865L MSOP)
CONV = V
●
●
0.001
0.01
3
0.1
µA
mA
REF
CC
f
= f
SMPL
SMPL(MAX)
I
Supply Current
CONV = V After Conversion
●
●
0.5
0.45
10
1.0
µA
mA
CC
CC
f
= f
SMPL
SMPL(MAX)
P
D
Power Dissipation
f
= f
SMPL(MAX)
1.22
mW
SMPL
sn18645L 18645Lfs
3
LTC1864L/LTC1865L
W U
U
U
U
W
RECO E DED OPERATI G CO DITIO S The ● denotes specifications which apply over the
full operating temperature range, otherwise specifications are TA = 25°C.
LTC1864L/LTC1865L
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
3.6
8
UNITS
V
V
Supply Voltage
2.7
CC
f
t
t
Clock Frequency
●
DC
MHz
µs
SCK
CYC
SMPL
Total Cycle Time
16 • SCK + t
CONV
Analog Input Sampling Time (Note 5)
LTC1864L
LTC1865L
16
14
SCK
SCK
t
Setup Time CONV↓ Before First SCK↑
(See Figure 1)
60
ns
suCONV
t
t
t
t
t
Hold Time SDI After SCK↑
Setup Time SDI Stable Before SCK↑
SCK High Time
LTC1865L
LTC1865L
30
30
ns
ns
hDI
suDI
f
f
= f
SCK(MAX)
= f
SCK(MAX)
45%
45%
1/f
1/f
WHCLK
WLCLK
WHCONV
SCK
SCK
SCK
SCK Low Time
SCK
CONV High Time Between Data
Transfer Cycles
t
µs
CONV
t
t
CONV Low Time During Data Transfer
16
26
SCK
ns
WLCONV
hCONV
Hold Time CONV Low After Last SCK↑
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are TA = 25°C. VCC = 2.7V, VREF = 2.5V, fSCK = fSCK(MAX) as defined in Recommended Operating
Conditions, unless otherwise noted.
LTC1864L/LTC1865L
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
µs
t
f
t
Conversion Time (See Figure 1)
Maximum Sampling Frequency
Delay Time, SCK↓ to SDO Data Valid
●
●
3.7
4.66
CONV
150
kHz
SMPL(MAX)
dDO
C
= 20pF
45
55
60
ns
ns
LOAD
●
●
●
●
t
t
t
Delay Time, CONV↑ to SDO Hi-Z
55
35
15
120
120
ns
ns
ns
dis
en
Delay Time, CONV↓to SDO Enabled
C
C
= 20pF
= 20pF
LOAD
LOAD
Time Output Data Remains
Valid After SCK↓
5
hDO
t
t
SDO Rise Time
SDO Fall Time
C
C
= 20pF
= 20pF
25
12
ns
ns
r
f
LOAD
LOAD
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Assumes f
= f
In the case of the LTC1864L SCK does
SCK(MAX)
Note 2: All voltage values are with respect to GND.
SCK
not have to be clocked during this time if the SDO data word is not
desired. In the case of the LTC1865L a minimum of 2 clocks are required
on the SCK input after CONV falls to configure the MUX during this time.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
sn18645L 18645Lfs
4
LTC1864L/LTC1865L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Sampling
Sleep Current vs Temperature
Frequency
Supply Current vs Temperature
1000
100
600
500
400
300
200
100
0
20
CONV LOW = 2µs
f
V
V
= 150kHz
= 2.7V
CC
f
V
V
= 150kHz
= 2.7V
REF
S
S
CC
T
= 25°C
CC
A
V
= 2.7V
= 2.5V
REF
= 2.5V
15
10
5
10
1
0
0.1
50
TEMPERATURE (°C)
100 125
0.01
0.1
1
10
100
1000
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
SAMPLING FREQUENCY (kHz)
1864L/65L G02
1864L/65L G01
1864L/65L G03
Reference Current vs
Sampling Rate
Reference Current vs
Temperature
Reference Current vs
Reference Voltage
25
20
15
10
5
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
f
V
V
= 150kHz
= 2.7V
REF
CONV LOW = 2µs
f
= 150kHz
T = 25°C
A
S
CC
S
T
= 25°C
A
CC
REF
= 2.5V
V
V
= 2.7V
V
= 3.6V
CC
= 2.5V
0
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
25
75
100
125
150
0
0.5
1.5 2.0 2.5 3.0 3.5 4.0
50
1.0
SAMPLING FREQUENCY (kHz)
REFERENCE VOLTAGE (V)
1864L/65L G05
1864L/65L G04
1864L/65L G06
Analog Input Leakage Current vs
Temperature
Typical INL Curve
Typical DNL Curve
100
75
50
25
0
4
2
1
CONV = 0V
V
V
f
= 2.7V
= 2.5V
V
V
f
= 2.7V
= 2.5V
CC
REF
S
CC
REF
S
V
V
= 2.7V
CC
= 2.5V
REF
= 150kHz
= 150kHz
2
0
0
–2
–4
–1
–2
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
32768
CODE
49152
32768
CODE
49152
0
65536
0
65536
16384
16384
1864L/65L G09
1865 G02
1865 G03
sn18645L 18645Lfs
5
LTC1864L/LTC1865L
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Change in Gain Error vs
Reference Voltage
Change in Offset vs
Reference Voltage
Change in Offset vs Temperature
5
4
5
4
20
15
V
V
= 2.7V
CC
= 2.5V
REF
f
= 150kHz
f
= 150kHz
S
= 25°C
A
S
A
T
= 25°C
T
V
V
= 3.6V
= 3.6V
CC
CC
3
3
10
2
2
5
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–5
–10
–15
–20
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
2
3
2
3
0
4
0
4
1
1
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1864L/65L G11
1864L/65L G10
1864L/65L G12
Histogram of 4096 Conversions
of a DC Input Voltage
Change in Gain Error vs
Temperature
4096 Point FFT Nonaveraged
5
4
0
–10
–20
–30
–40
–50
–60
–70
–80
1200
1000
800
600
400
200
0
f
= 125kHz
V
V
= 2.7V
= 2.5V
S
A
CC
REF
1040
T
= 25°C
V
V
V
= 3V
CC
IN
3
= 0.946045kHz
= 3V
2
REF
689
648
1
576
0
–1
–2
–3
–4
–5
407
–90
291
–100
–110
–120
–130
169
152
52
45
20
7
0
0 0
50
TEMPERATURE (°C)
100 125
0
30
45
–50 –25
0
25
75
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
5
10 15 20 25
35 40
50 55
60
65
CODE
INPUT FREQUENCY (kHz)
1864L/65L G15
1864L/65L G14
1864L/65L G13
SFDR vs Input Frequency
SINAD vs Input Frequency
THD vs Input Frequency
100
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
90
80
70
60
50
40
30
20
10
0
f
= 125kHz
S
A
T
= 25°C
SNR
V
V
V
= 3V
CC
IN
= 0dB
= 3V
REF
SINAD
f
= 125kHz
= 25°C
= 3V
= 0dB
= 3V
f
T
V
V
V
= 125kHz
= 25°C
= 3V
S
S
A
CC
T
A
CC
IN
REF
V
V
V
= 0dB
= 3V
IN
REF
1
10
INPUT FREQUENCY (kHz)
100
1
10
INPUT FREQUENCY (kHz)
100
1
10
INPUT FREQUENCY (kHz)
100
1864L/65L G17
1864L/65L G16
1864L/65L G18
sn18645L 18645Lfs
6
LTC1864L/LTC1865L
U
U
U
PI FU CTIO S
LTC1864L
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN+, IN– (Pins 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
CC (Pin 8): Positive Supply. This supply must be kept
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
free of noise and ripple by bypassing directly to the
analog ground plane.
LTC1865L (MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK(Pin8):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
VCC (Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied
directly to an analog ground plane.
VREF (Pin 10): Reference Input. The reference input de-
fines the span of the A/D converter and must be kept free
of noise with respect to AGND.
DGND (Pin 5): Digital Ground. DGND should be tied
directly to an analog ground plane.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
LTC1865L (SO-8 Package)
SDI (Pin 5): Digital Data Input. The A/D configuration
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK(Pin7):ShiftClockInput. Thisclocksynchronizesthe
serial data transfer.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. VREF is tied internally to this pin.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
sn18645L 18645Lfs
7
LTC1864L/LTC1865L
U
U
W
FUNCTIONAL BLOCK DIAGRA
V
CC
(SDI) SCK
CONV
PIN NAMES IN
PARENTHESES
REFER TO LTC1865L
SDO
SERIAL
PORT
CONVERT
CLK
BIAS AND
SHUTDOWN
DATA IN
16 BITS
+
IN
+
–
(CH0)
16-BIT
SAMPLING
ADC
DATA OUT
–
IN
(CH1)
1864/65 BD
GND
V
REF
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
V
OH
SDO
V
OL
V
t
WAVEFORM 2, t
en
3k
CC dis
SDO
t
dis
WAVEFORM 1
t
r
t
f
1864 TC04
20pF
1864 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
V
CONV
IH
SDO
1864 TC03
SDO
WAVEFORM 1
(SEE NOTE 1)
90%
10%
t
en
t
dis
SDO
WAVEFORM 2
(SEE NOTE 2)
Voltage Waveforms for SDO Delay Times, tdDO and thDO
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
SCK
V
IL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
t
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
dDO
1864 TC05
t
hDO
V
V
OH
OL
SDO
1864 TC02
sn18645L 18645Lfs
8
LTC1864L/LTC1865L
W U U
APPLICATIO S I FOR ATIO
LTC1864L OPERATION
U
Analog Inputs
TheLTC1864Lhasaunipolardifferentialanaloginput.The
converter will measure the voltage between the “IN+” and
“IN–” inputs. A zero code will occur when IN+ minus IN–
equals zero. Full scale occurs when IN+ minus IN– equals
VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
isgroundedandVREF istiedtoVCC, arail-to-railinputspan
will result on “IN+” as shown in Figure 3.
Operating Sequence
The LTC1864L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1864L goes into sleep mode drawing only leakage
current. On the falling edge of CONV, the LTC1864L goes
into sample mode and SDO is enabled. SCK synchronizes
the data transfer with each bit being transmitted from SDO
on the falling SCK edge. The receiving system should
capture the data from SDO on the rising edge of SCK. After
completing the data transfer, if further SCK clocks are
applied with CONV low, SDO will output zeros indefinitely.
See Figure 1.
Reference Input
The voltage on the reference input of the LTC1864L
defines the full-scale range of the A/D converter. The
LTC1864LcanoperatewithreferencevoltagesfromVCC to
1V.
CONV
t
SMPL
8
SLEEP MODE
t
CONV
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16
DON'T CARE
Hi-Z
SCK
SDO
B14
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
B15
B13
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1854 F01
Figure 1. LTC1864L Operating Sequence
1µF
V
CC
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
LTC1864L
•
•
•
1
2
3
4
8
7
6
V
V
CC
REF
+
V
= 0V TO V
CC
IN
IN
SCK
SDO
IN
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
–
V *
IN
5
GND
CONV
1864 F03
+
–
*V = IN – IN
IN
1864 F02
Figure 2. LTC1864L Transfer Curve
Figure 3. LTC1864L with Rail-to-Rail Input Span
sn18645L 18645Lfs
9
LTC1864L/LTC1865L
W U U
U
APPLICATIO S I FOR ATIO
LTC1865L OPERATION
single-ended mode, all input channels are measured with
respect to GND. A zero code will occur when the “+” input
minus the “–” input equals zero. Full scale occurs when
the “+” input minus the “–” input equals VREF minus
1LSB. See Figure 5. Both the “+” and “–” inputs are
sampled at the same time so common mode noise is
rejected. The input span in the SO-8 package is fixed at
VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Operating Sequence
The LTC1865L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1865L goes into sleep mode drawing only leakage
current. The LTC1865L’s 2-bit data word is clocked into
the SDI input on the rising edge of SCK after CONV goes
low. AdditionalinputsontheSDIpinarethenignoreduntil
the next CONV cycle. The shift clock (SCK) synchronizes
the data transfer with each bit being transmitted on the
falling SCK edge and captured on the rising SCK edge in
both transmitting and receiving systems. The data is
transmitted and received simultaneously (full duplex).
After completing the data transfer, if further SCK clocks
are applied with CONV low, SDO will output zeros indefi-
nitely. See Figure 4.
Reference Input
The reference input of the LTC1865L SO-8 package is
internally tied to VCC. The span of the A/D converter is
therefore equal to VCC. The voltage on the reference input
of the LTC1865L MSOP package defines the span of the
A/D converter. The LTC1865L MSOP package can operate
with reference voltages from 1V to VCC.
Table 1. Multiplexer Channel Selection
Analog Inputs
MUX ADDRESS
CHANNEL #
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the
“+” and “–” signs in the selected row of Table 1. In
SGL/DIFF ODD/SIGN
0
1
GND
1
1
0
0
0
1
0
1
+
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
+
–
+
+
–
1864 TBL1
CONV
t
SMPL
SLEEP MODE
t
CONV
SDI
S/D O/S
DON’T CARE
DON'T CARE
DON’T CARE
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
SCK
SDO
B0*
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B14
B15
B13
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1864 F04
Figure 4. LTC1865L Operating Sequence
sn18645L 18645Lfs
10
LTC1864L/LTC1865L
W U U
APPLICATIO S I FOR ATIO
U
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with a
minimum of 1µF tantalum. Keep the bypass capacitor
leads as short as possible.
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1864L/LTC1865L should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluatethedevice.Toachievetheoptimumperformance,
use a printed circuit board. The ground pins (AGND and
DGND for the LTC1865L MSOP package and GND for the
LTC1864L and LTC1865L SO-8 package) should be tied
directly to the analog ground plane with minimum lead
length.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1864L/
LTC1865L have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem if source resistances are less than 200Ω or high
speed op amps are used (e.g., the LT®1211, LT1469,
LT1807, LT1810, LT1630, LT1226orLT1215). Butiflarge
source resistances are used, or if slow settling op amps
drive the inputs, take care to ensure the transients caused
by the current spikes settle completely before the conver-
sion begins.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
*
V
IN
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*V = (SELECTED “+” CHANNEL) –
IN
1864 F05
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
Figure 5. LTC1865L Transfer Curve
sn18645L 18645Lfs
11
LTC1864L/LTC1865L
W U U
U
APPLICATIO S I FOR ATIO
sn18645L 18645Lfs
12
LTC1864L/LTC1865L
W U U
APPLICATIO S I FOR ATIO
U
Component Side Silk Screen for LTC1864L Evaluation Circuit
Component Side Showing Traces
(Note Wider Traces on Analog Side)
Bottom Side Showing Traces
(Note Almost No Analog Traces on Board Bottom)
Ground Layer with Separate Analog and Digital Grounds
Supply Layer with 5V Digital Supply and Analog Ground Repeated
sn18645L 18645Lfs
13
LTC1864L/LTC1865L
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.206)
REF
0.65
(.0256)
BSC
0.42 ± 0.04
(.0165 ± .0015)
TYP
8
7 6 5
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.077)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.13 ± 0.076
(.005 ± .003)
0.65
(.0256)
BSC
MSOP (MS8) 0802
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn18645L 18645Lfs
14
LTC1864L/LTC1865L
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
7
5
8
6
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
2
3
4
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.01
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.13 ± 0.076
(.005 ± .003)
MSOP (MS) 0802
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn18645L 18645Lfs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
15
LTC1864L/LTC1865L
U
TYPICAL APPLICATIO
Tiny 2-Chip Data Acquisition System
1µF
3V
3V
0.1µF
8
V
V
REF
CC
+
4
499Ω
3
1
+
IN
IN
SCK
LTC1864L
V
LTC6910-1
IN
5
–
270pF
–
6
SDO
7
2
GND
CONV
AGND
1µF
ADC
CONTROL
GAIN
CONTROL
LTC6910-1 (IN TSOT-23 PACKAGE) COMPACTLY ADDS 40dB OF INPUT GAIN
RANGE TO THE LTC1864L (IN MSOP 8-PIN PACKAGE). SINGLE 3V SUPPLY
1864L/65L TA03
RELATED PARTS
PART NUMBER
12-Bit Serial I/O ADCs
LTC1860L/LTC1861L
LTC1860/LTC1861
14-Bit Serial I/O ADCs
LTC1417
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
150ksps
250ksps
1.22mW
4.25mW
Pin Compatible with LTC1864L/LTC1865L
Pin Compatible with LTC1864/LTC1865
400ksps
200ksps
20mW
15mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V
Serial/Parallel I/O, Internal Reference, 5V or ±5V
LTC1418
16-Bit Serial I/O ADCs
LTC1609
200ksps
250ksps
65mW
Configurable Bipolar or Unipolar Input Ranges, 5V
MSOP, SO-8, 1- and 2-Channel, 5V Supply
LTC1864/LTC1865
References
4.25mW
LT1460
Micropower Precision Series Reference
Micropower Low Dropout Reference
Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23
60µA Supply Current, 10ppm/°C, SOT-23
LT1790
Op Amps
LT1468/LT1469
LT1806/LT1807
LT1809/LT1810
Single/Dual 90MHz, 16-Bit Accurate Op Amps
Single/Dual 325MHz Low Noise Op Amps
Single/Dual 180MHz Low Distortion Op Amps
22V/µs Slew Rate, 75µV/125µV Offset
140V/µs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion
350V/µs Slew Rate, –90dBc Distortion at 5MHz
sn18645L 18645Lfs
LT/TP 0403 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2001
相关型号：
LTC1865LAIS8#PBF
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LTC1865LAIS8#TRPBF
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LTC1865LCMS#PBF
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C
Linear
LTC1865LCMS#TRPBF
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C
Linear
LTC1865LCS8#PBF
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC1865LCS8#TR
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC1865LCS8#TRPBF
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC1865LIS8#PBF
LTC1865L - µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明