LTC1864IS8#TRPBF [Linear]
LTC1864 - µPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in SOIC; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC1864IS8#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1864 - µPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in SOIC; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1864/LTC1865
µPower, 16-Bit, 250ksps
1- and 2-Channel
ADCs in MSOP
FEATURES
DESCRIPTION
The LTC®1864/LTC1865 are 16-bit A/D converters that
are offered in MSOP and SO-8 packages and operate
on a single 5V supply. At 250ksps, the supply current is
only 850μA. The supply current drops at lower speeds
becausetheLTC1864/LTC1865automaticallypowerdown
between conversions. These 16-bit switched capacitor
successive approximation ADCs include sample-and-
holds. The LTC1864 has a differential analog input with an
adjustable reference pin. The LTC1865 offers a software-
selectable 2-channel MUX and an adjustable reference pin
on the MSOP version.
n
16-Bit 250ksps ADCs in MSOP Package
n
Single 5V Supply
n
Low Supply Current: 850μA (Typ)
Auto Shutdown Reduces Supply Current
n
to 2μA at 1ksps
True Differential Inputs
1-Channel (LTC1864) or 2-Channel (LTC1865)
n
n
Versions
n
SPI/MICROWIRE™ Compatible Serial I/O
n
16-Bit Upgrade to 12-Bit LTC1286/LTC1298
n
Pin Compatible with 12-Bit LTC1860/LTC1861
n
Guaranteed Operation to +125°C (MSOP Package)
The 3-wire, serial I/O, small MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
ADCs ideal choices for compact, low power, high speed
systems.
APPLICATIONS
n
High Speed Data Acquisition
Portable or Compact Instrumentation
Low Power Battery-Operated Instrumentation
Isolated and/or Remote Data Acquisition
TheseADCscanbeusedinratiometricapplicationsorwith
external references. The high impedance analog inputs
and the ability to operate with reduced spans down to
1V full scale, allow direct connection to signal sources
in many applications, eliminating the need for external
gain stages.
n
n
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
Single 5V Supply, 250ksps, 16-Bit Sampling ADC
Supply Current vs Sampling Frequency
1000
1μF
5V
100
10
LTC1864
1
2
3
4
8
7
6
V
V
CC
REF
+
1
IN
IN
SCK
SDO
ANALOG INPUT
0V TO 5V
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
5
0.1
GND
CONV
18645 TA01
0.01
0.01
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
18645 TA02
18645fb
1
LTC1864/LTC1865
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltage (V ) .................................................7V
Operating Temperature Range
CC
Ground Voltage Difference
LTC1864C/LTC1865C/
AGND, DGND LTC1865 MSOP Package............ 0.3V
LTC1864AC/LTC1865AC...........................0°C to 70°C
LTC1864I/LTC1865I/
LTC1864AI/LTC1865AI ...................... –40°C to 85°C
LTC1864H/LTC1865H
Analog Input ................ (GND – 0.3V) to (V + 0.3V)
CC
Digital Input ................................ (GND – 0.3V) to 7V
Digital Output .............. (GND – 0.3V) to (V + 0.3V)
CC
Power Dissipation.............................................. 400mW
LTC1864AH/LTC1865AH ................. –40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C
PIN CONFIGURATION
LTC1864
LTC1865
TOP VIEW
TOP VIEW
CONV
CH0
1
2
3
4
5
10
9
V
V
SCK
SDO
SDI
REF
CC
V
1
2
3
4
8 V
CC
REF
+
IN
7 SCK
CH1
8
6 SDO
5 CONV
IN¯
AGND
DGND
7
6
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS PACKAGE
10-LEAD PLASTIC MSOP
T
= 150°C, θ = 210°C/W
JMAX
JA
T
= 150°C, θ = 210°C/W
JMAX
JA
LTC1864
LTC1865
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
CONV
CH0
1
2
3
4
8
7
6
5
V
V
V
CC
REF
CC
+
IN
IN
SCK
SCK
–
SDO
CONV
CH1
SDO
SDI
GND
GND
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PACKAGE
8-LEAD PLASTIC SO
T
= 150°C, θ = 175°C/W
T
= 150°C, θ = 175°C/W
JMAX JA
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC1864CMS8#PBF
LTC1864IMS8#PBF
LTC1864HMS8#PBF
LTC1864ACMS8#PBF
LTC1864AIMS8#PBF
LTC1864AHMS8#PBF
LTC1864CS8#PBF
LTC1864IS8#PBF
TAPE AND REEL
PART MARKING
LTHQ
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic SO
TEMPERATURE RANGE
0°C to 70°C
LTC1864CMS8#TRPBF
LTC1864IMS8#TRPBF
LTC1864HMS8#TRPBF
LTHQ
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTHQ
LTC1864ACMS8#TRPBF LTHQ
LTC1864AIMS8#TRPBF LTHQ
LTC1864AHMS8#TRPBF LTHQ
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC1864CS8#TRPBF
LTC1864IS8#TRPBF
LTC1864ACS8#TRPBF
LTC1684AIS8#TRPBF
LTC1865CMS#TRPBF
LTC1865IMS#TRPBF
1864
1864I
1864A
1864AI
LTHS
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
LTC1864ACS8#PBF
LTC1684AIS8#PBF
LTC1865CMS#PBF
LTC1865IMS#PBF
8-Lead Plastic SO
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
10-Lead Plastic MSOP
10-Lead Plastic MSOP
LTHS
–40°C to 85°C
18645fb
2
LTC1864/LTC1865
ORDER INFORMATION
LEAD FREE FINISH
LTC1865HMS#PBF
LTC1865ACMS#PBF
LTC1865AIMS#PBF
LTC1865AHMS#PBF
LTC1865CS8#PBF
LTC1865IS8#PBF
LTC1865ACS8#PBF
LTC1865AIS8#PBF
LEAD BASED FINISH
LTC1864CMS8
LTC1864IMS8
TAPE AND REEL
PART MARKING
LTHS
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
0°C to 70°C
LTC1865HMS#TRPBF
LTC1865ACMS#TRPBF
LTC1865AIMS#TRPBF
LTC1865AHMS#TRPBF
LTC1865CS8#TRPBF
LTC1865IS8#TRPBF
LTC1865ACS8#TRPBF
LTC1865AIS8#TRPBF
TAPE AND REEL
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
8-Lead Plastic SO
LTHS
LTHS
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTHS
1865
1865I
1865A
1865AI
PART MARKING
LTHQ
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
8-Lead Plastic SO
8-Lead Plastic SO
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
PACKAGE DESCRIPTION
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic SO
LTC1864CMS8#TR
LTC1864IMS8#TR
LTC1864HMS8#TR
LTC1864ACMS8#TR
LTC1864AIMS8#TR
LTC1864AHMS8#TR
LTC1864CS8#TR
LTHQ
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC1864HMS8
LTC1864ACMS8
LTC1864AIMS8
LTC1864AHMS8
LTC1864CS8
LTHQ
LTHQ
LTHQ
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTHQ
1864
LTC1864IS8
LTC1864IS8#TR
1864I
1864A
1864AI
LTHS
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
LTC1864ACS8
LTC1864ACS8#TR
LTC1684AIS8#TR
LTC1865CMS#TR
LTC1865IMS#TR
8-Lead Plastic SO
LTC1684AIS8
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
LTC1865CMS
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
8-Lead Plastic SO
LTC1865IMS
LTHS
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC1865HMS
LTC1865HMS#TR
LTC1865ACMS#TR
LTC1865AIMS#TR
LTC1865AHMS#TR
LTC1865CS8#TR
LTHS
LTC1865ACMS
LTC1865AIMS
LTHS
LTHS
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC1865AHMS
LTC1865CS8
LTHS
1865
LTC1865IS8
LTC1865IS8#TR
1865I
1865A
1865AI
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
LTC1865ACS8
LTC1865ACS8#TR
LTC1865AIS8#TR
8-Lead Plastic SO
LTC1865AIS8
8-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
18645fb
3
LTC1864/LTC1865
CONVERTER AND MULTIPILEXER CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1864/LTC1865
LTC1864A/LTC1865A
PARAMETER
CONDITIONS
MIN
16
TYP
MAX
MIN
16
TYP
MAX
UNITS
Bits
l
l
Resolution
No Missing Codes Resolution
INL
14
15
Bits
l
l
(Note 3)
H-Grade (Note 3)
8
8.5
6
6.5
LSB
LSB
Transition Noise
Gain Error
1.1
1.1
LSB
RMS
l
20
20
mV
l
l
Offset Error
LTC1864 SO-8 and MSOP, LTC1865 MSOP
LTC1865 SO-8
2
3
5
7
2
3
5
7
mV
mV
+
–
l
Input Differential Voltage Range V = IN – IN
0
V
REF
0
V
REF
V
IN
+
Absolute Input Range
IN Input
–0.05
–0.05
V
CC
V
+ 0.05 –0.05
CC
V
CC
V
+ 0.05
CC
V
V
–
IN Input
/2
–0.05
/2
V
REF
Input Range
LTC1864 SO-8 and MSOP,
LTC1865 MSOP
1
V
CC
1
V
CC
V
l
Analog Input Leakage Current
Input Capacitance
(Note 4)
1
1
μA
C
In Sample Mode
During Conversion
12
5
12
5
pF
pF
IN
DYNAMIC ACCURACY
TA = 25°C. VCC = 5V, VREF = 5V, fSAMPLE = 250kHz, unless otherwise noted.
LTC1864/LTC1865
SYMBOL
SNR
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Signal-to-Noise Ratio
87
dB
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
10kHz Input Signal
100kHz Input Signal
83
76
dB
dB
THD
Total Harmonic Distortion Up to 5th Harmonic 10kHz Input Signal
100kHz Input Signal
88
77
dB
dB
Full Power Bandwidth
20
MHz
kHz
Full Linear Bandwidth
S/(N+D) ≥ 75dB
125
18645fb
4
LTC1864/LTC1865
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1864/LTC1865
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
l
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 5.25V
= 4.75V
2.4
IH
IL
CC
CC
IN
V
0.8
2.5
V
I
I
= V
μA
μA
IH
CC
= 0V
–2.5
IL
IN
l
l
V
V
CC
V
CC
= 4.75V, I = 10μA
= 4.75V, I = 360μA
4.5
2.4
4.74
4.72
V
V
OH
OL
O
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
CC
= 4.75V, I = 1.6mA
●
●
0.4
3
V
μA
O
I
I
I
I
CONV = V
CC
OZ
V
= 0V
–25
20
mA
mA
SOURCE
SINK
OUT
OUT
V
= V
CC
Reference Current (LTC1864 SO-8 and MSOP, CONV = VCC
LTC1865 MSOP)
●
●
0.001
0.05
3
0.1
μA
mA
REF
f
= f
SMPL
SMPL(MAX)
I
Supply Current
CONV = V After Conversion
●
●
●
0.001
0.001
0.85
3
5
1.3
μA
μA
mA
CC
CC
CONV = V After Conversion, H-Grade
CC
f
= f
SMPL
SMPL(MAX)
P
Power Dissipation
f
= f
4.25
mW
D
SMPL
SMPL(MAX)
18645fb
5
LTC1864/LTC1865
RECOMMENDED OPERATING CONDITIONS
The ● denotes specifications which apply over the
full operating temperature range, otherwise specifications are TA = 25°C.
LTC1864/LTC1865
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
Clock Frequency
4.75
5.25
V
CC
f
●
●
20
16.7
MHz
MHz
SCK
H-Grade
t
t
Total Cycle Time
16 • SCK + t
μs
CYC
CONV
Analog Input Sampling Time
LTC1864 (Note 5)
LTC1865 (Note 5)
16
14
SCK
SCK
SMPL
t
Setup Time CONV↓ Before First SCK↑
60
65
30
30
ns
ns
suCONV
(See Figure 1)
H-Grade
LTC1865
LTC1865
t
t
t
t
t
Hold Time SDI After SCK↑
Setup Time SSDI Stable Before SCK↑
SCK High Time
15
15
ns
ns
hDI
suDI
f
f
= f
= f
40%
40%
1/f
1/f
WHCLK
WLCLK
WHCONV
SCK
SCK
SCK(MAX)
SCK(MAX)
SCK
SCK Low Time
SCK
CONV High Time Between Data Transfer
Cycles
(Note 5)
t
μs
CONV
t
t
CONV Low Time During Data Transfer
(Note 5)
16
SCK
ns
WLCONV
Hold Time CONV Low After Last SCK↑
13
hCONV
18645fb
6
LTC1864/LTC1865
TIMING CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions,
unless otherwise noted.
LTC1864/LTC1865
SYMBOL
PARAMETER
CONDITIONS
H-Grade
MIN
TYP
MAX
UNITS
t
f
t
Conversion Time (See Figure 1)
●
●
2.75
2.75
3.2
3.3
μs
μs
CONV
Maximum Sampling Frequency
●
●
250
234
kHz
kHz
SMPL(MAX)
dDO
H-Grade
Delay Time, SCK↓ to SDO Data Valid
C
LOAD
C
LOAD
C
LOAD
= 20pF
15
20
25
30
ns
ns
ns
= 20pF
●
●
= 20pF, H-Grade
t
t
Delay Time, CONV↑ to SDO Hi-Z
●
●
30
30
60
65
ns
ns
dis
en
H-Grade
Delay Time, CONV↓ to SDO Enabled
C
LOAD
C
LOAD
= 20pF
= 20pF, H-Grade
●
●
30
30
60
65
ns
ns
t
t
t
Time Output Data Remains Valid After SCK↓ C
= 20pF
= 20pF
= 20pF
●
5
10
8
ns
ns
ns
hDO
LOAD
LOAD
LOAD
SDO Rise Time
SDO Fall Time
C
C
r
f
4
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
Note 5: Guaranteed by design, not subject to test.
Note 2: All voltage values are with respect to GND.
18645fb
7
LTC1864/LTC1865
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sampling
Frequency
Supply Current vs Temperature
Sleep Current vs Temperature
1000
800
600
400
200
0
1000
900
800
700
600
500
400
300
200
100
0
1000
100
10
CONV = V = 5V
CC
V
A
= 5V
CC
T
= 25°C
CONV LOW = 800ns
1
V
V
f
= 5V
CC
0.1
= 5V
REF
= 250kHz
SAMPLE
CONV HIGH = 3.2μS
50
75 100 125
TEMPERATURE (°C)
0.01
–50
0
25
–25
–50
0
25
50
75
125
–25
100
0.01
0.1
1.0
10
100
1000
TEMPERATURE (°C)
SAMPLING FREQUENCY (kHz)
18645 G02
18645 G03
18645 G01
Reference Current vs
Sampling Rate
Reference Current vs
Temperature
Reference Current vs
Reference Voltage
55
54
53
52
51
50
49
48
47
46
45
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
V
f
= 5V
= 5V
V
T
S
= 5V
V
T
= 5V
= 25°C
= 5V
CC
REF
CC
A
CC
= 25°C
A
= 250kHz
f
= 250kHz
V
REF
S
CONV LOW = 800ns
0
1
2
3
4
5
0
50
100
150
200
250
–50
0
25
50
75
125
–25
100
V
(V)
SAMPLE RATE (kHz)
TEMPERATURE (°C)
REF
18645 G06
18645 G04
18645 G05
Analog Input Leakage Current vs
Temperature
Typical INL Curve
Typical DNL Curve
4
2
2
1
100
75
50
25
0
V
V
= 5V
= 5V
V
T
= 5V
V
T
= 5V
CC
REF
CONV = 0V
CC
A
CC
A
V
= 25°C
= 25°C
V
= 5V
= 5V
REF
REF
0
0
–2
–4
–1
–2
0
16384
32768
CODE
65536
49152
0
16384
32768
CODE
65536
–25
0
25
50
75
125
49152
–50
100
TEMPERATURE (°C)
18645 G07
18645 G08
18645 G09
18645fb
8
LTC1864/LTC1865
TYPICAL PERFORMANCE CHARACTERISTICS
Change in Offset Error vs
Reference Voltage
Change in Gain Error vs
Change in Offset vs Temperature
Reference Voltage
20
75
50
25
0
5
4
V
T
= 5V
V
V
= 5V
= 5V
V
T
= 5V
CC
A
CC
REF
CC
= 25°C
= 25°C
15
10
A
3
2
5
1
0
0
–1
–2
–3
–4
–5
–5
–10
–15
–20
–25
0
2
3
4
5
0
1
2
3
4
5
1
–50
0
25
50
75 100 125
–25
REFERENCE VOLTAGE(V)
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
18645 G12
18645 G10
18645 G11
Change in Gain Error vs
Temperature
Histogram of 4096 Conversions of
a DC Input Voltage
4096 Point FFT Nonaveraged
5
4
1800
1600
1400
1200
1000
800
600
400
200
0
0
–20
V
T
= 5V
V
V
= 5V
= 5V
CC
A
f
f
V
V
T
= 203.125kHz
= 99.72763kHz
CC
REF
S
IN
= 25°C
1534
V
= 5V
REF
= 5V
CC
3
= 5V
REF
–40
2
= 25°C
1178
A
1
–60
0
729
–80
–1
–2
–3
–4
–5
516
2
–100
–120
–140
127
0
0
12
3
0
0
5
0
CODE
–4 –3 –2 –1
1
4
–50
0
25
50
75 100 125
–25
0
40
60
80
100
120
20
TEMPERATURE (°C)
FREQUENCY (kHz)
18645 G14
18645 G13
18645 G15
SINAD vs Frequency
THD vs Frequency
SFDR vs Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
SNR
SINAD
V
= 5V
REF
= 25°C
V
V
T
= 5V
= 5V
V
= 5V
CC
CC
REF
CC
V
T
= 5V
V
T
= 5V
REF
= 25°C
= 25°C
A
A
A
V = 0dB
V
= 0dB
V
= 0dB
IN
IN
IN
1
10
100
1000
1
10
100
1000
1
10
100
1000
F
(kHz)
F
(kHz)
F
(kHz)
IN
IN
IN
18645 G17
18645 G16
18645 G18
18645fb
9
LTC1864/LTC1865
PIN FUNCTIONS
LTC1864
V
(Pin 1): Reference Input. The reference input defines
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
REF
the span of the A/D converter and must be kept free of
noise with respect to GND.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
+
–
IN , IN (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
(Pin 8): Positive Supply. This supply must be kept
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
frCeCe of noise and ripple by bypassing directly to the
analog ground plane.
LTC1865 (MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 8): Shift Clock Input. This clock synchronizes
the serial data transfer.
V
(Pin 9): Positive Supply. This supply must be kept
frCeCe of noise and ripple by bypassing directly to the
analog ground plane.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND(Pin4):AnalogGround.AGNDshouldbetieddirectly
to an analog ground plane.
V
(Pin10):ReferenceInput.Thereferenceinputdefines
REF
the span of the A/D converter and must be kept free of
DGND(Pin5):DigitalGround.DGNDshouldbetieddirectly
to an analog ground plane.
noise with respect to AGND.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
LTC1865 (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
V
(Pin 8): Positive Supply. This supply must be kept
frCeCeofnoiseandripplebybypassingdirectlytotheanalog
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
ground plane. V is tied internally to this pin.
REF
18645fb
10
LTC1864/LTC1865
FUNCTIONAL BLOCK DIAGRAM
V
(SDI) SCK
CONV
CC
PIN NAMES IN
PARENTHESES
REFER TO LTC1865
SDO
SERIAL
PORT
CONVERT
CLK
BIAS AND
SHUTDOWN
DATA IN
16 BITS
+
IN
+
(CH0)
16-BIT
SAMPLING
ADC
DATA OUT
–
IN
–
(CH1)
18645 BD
GND
V
REF
18645fb
11
LTC1864/LTC1865
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
V
OH
SDO
V
OL
V
t
WAVEFORM 2, t
3k
CC dis
en
SDO
t
r
t
f
18645 TC04
t
WAVEFORM 1
dis
20pF
18645 TC01
Voltage Waveforms for ten
Voltage Waveforms for tdis
CONV
V
CONV
IH
SDO
18645 TC03
SDO
WAVEFORM 1
(SEE NOTE 1)
90%
10%
t
en
t
dis
SDO
WAVEFORM 2
(SEE NOTE 2)
Voltage Waveforms for SDO Delay Times,tdDO and thDO
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
SCK
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
V
IL
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
t
18645 TC05
dDO
t
hDO
V
V
OH
SDO
OL
18645 TC02
18645fb
12
LTC1864/LTC1865
APPLICATIONS INFORMATION
LTC1864 OPERATION
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
Operating Sequence
+
converter will measure the voltage between the “IN ”
–
+
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t
and “IN ” inputs. A zero code will occur when IN minus
–
+
–
, the conversion is
CONV
IN equals zero. Full scale occurs when IN minus IN
+
finished. If CONV is left high after this time, the LTC1864
goesintosleepmodedrawingonlyleakagecurrent. Onthe
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
equals V minus 1LSB. See Figure 2. Both the “IN ” and
REF
–
“IN ” inputs are sampled at the same time, so common
–
mode noise on the inputs is rejected by the ADC. If “IN ”
is grounded and V
span will result on “IN ” as shown in Figure 3.
is tied to V , a rail-to-rail input
REF
CC
+
Reference Input
The voltage on the reference input of the LTC1864 defines
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from V to 1V.
CC
t
suCONV
CONV
t
SMPL
8
SLEEP MODE
t
CONV
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16
SCK
SDO
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2 B1 B0*
B15 B14 B13 B12
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
18645 F01
Figure 1. LTC1864 Operating Sequence
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1μF
V
CC
•
•
•
LTC1864
V
1
2
3
4
8
7
6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V
V
*
REF
CC
IN
+
V
= 0V TO V
CC
IN
IN
SCK
IN
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
–
+
–
SDO
*V = IN – IN
IN
5
GND
CONV
18645 F02
18645 F03
Figure 2. LTC1864 Transfer Curve
Figure 3. LTC1864 with Rail-to-Rail Input Span
18645fb
13
LTC1864/LTC1865
APPLICATIONS INFORMATION
LTC1865 OPERATION
single-ended mode, all input channels are measured
with respect to GND. A zero code will occur when the
“+” input minus the “–” input equals zero. Full scale oc-
curs when the “+” input minus the “–” input equals VREF
minus 1LSB. See Figure 5. Both the “+” and “–” inputs
are sampled at the same time so common mode noise
is rejected. The input span in the SO-8 package is fixed
at VREF = VCC. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Operating Sequence
The LTC1865 conversion cycle begins with the rising edge
of CONV. After a period equal to t
, the conversion is
CONV
finished. If CONV is left high after this time, the LTC1865
goes into sleep mode drawing only leakage current. The
LTC1865’s 2-bit data word is clocked into the SDI input
on the rising edge of SCK after CONV goes low. Additional
inputs on the SDI pin are then ignored until the next CONV
cycle. Theshiftclock(SCK)synchronizesthedatatransfer
witheachbitbeingtransmittedonthefallingSCKedgeand
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex). After completing the data
transfer, if further SCK clocks are applied with CONV low,
SDO will output zeros indefinitely. See Figure 4.
Reference Input
The reference input of the LTC1865 SO-8 package is
internally tied to V . The span of the A/D converter is
CC
therefore equal to V . The voltage on the reference
CC
input of the LTC1865 MSOP package defines the span
of the A/D converter. The LTC1865 MSOP package can
operate with reference voltages from 1V to V .
CC
Analog Inputs
Table 1. Multiplexer Channel Selection
The two bits of the input word (SDI) assign the MUX
configuration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
MUX ADDRESS
CHANNEL #
SGL/DIFF ODD/SIGN
0
1
GND
1
1
0
0
0
1
0
1
+
–
–
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
+
–
+
+
–
18645 TBL1
CONV
t
SMPL
SLEEP MODE
t
CONV
SDI
S/D O/S
DON’T CARE
DON’T CARE
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
SCK
SDO
B0*
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B14
B15
B13
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
18645 F04
Figure 4. LTC1865 Operating Sequence
18645fb
14
LTC1864/LTC1865
APPLICATIONS INFORMATION
GENERAL ANALOG CONSIDERATIONS
induce errors or noise in the output code. Bypass the V
CC
and V
pins directly to the analog ground plane with
REF
Grounding
a minimum of 1μF tantalum. Keep the bypass capacitor
leads as short as possible.
The LTC1864/LTC1865 should be used with an analog
groundplaneandsinglepointgroundingtechniques.Donot
use wire wrapping techniques to breadboard and evaluate
the device. To achieve the optimum performance, use a
printed circuit board. The ground pins (AGND and DGND
for the LTC1865 MSOP package and GND for the LTC1864
and LTC1865 SO-8 package) should be tied directly to the
analog ground plane with minimum lead length.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniquesused,theanaloginputsoftheLTC1864/LTC1865
have capacitive switching input current spikes. These cur-
rent spikes settle quickly and do not cause a problem if
source resistances are less than 200Ω or high speed op
ampsareused(e.g.,theLT®1211,LT1469,LT1807,LT1810,
LT1630,LT1226orLT1215).Butiflargesourceresistances
are used, or if slow settling op amps drive the inputs, take
care to ensure the transients caused by the current spikes
settle completely before the conversion begins.
Bypassing
For good performance, the V and V pins must be free
CC
REF
of noise and ripple. Any changes in the V /V voltage
CC REF
with respect to ground during the conversion cycle can
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
*
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V
IN
*V = (SELECTED “+” CHANNEL) –
IN
18645 F05
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
Figure 5. LTC1865 Transfer Curve
18645fb
15
LTC1864/LTC1865
APPLICATIONS INFORMATION
18645fb
16
LTC1864/LTC1865
APPLICATIONS INFORMATION
Component Side Silk Screen for LTC1864 Evaluation Circuit
Component Side Showing Traces
(Note Sider Traces on Analog Side)
Bottom Side Showing Traces
(Note Almost No Analog Traces on Board Bottom)
Ground Layer with Separate Analog and Digital Grounds
Supply Layer with 5V Digital Supply and
Analog Ground Repeated
18645fb
17
LTC1864/LTC1865
APPLICATIONS INFORMATION
U11
5V
AN
5V
DIG
15V
LT1121CST-5
R4
2Ω
1
3
V
V
OUT
IN
C26
GND
2
10μF
6.3V
1206
5V
AN
C3
10μF
6.3V
1206
C4
0.1μF
5V
5V
DIG
15V
DIG
LTC1485
RO V
RN1
330
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1V to 5V REFERENCE
0V to V INPUT
V
IN
IN
V
CC
SCK
SDO
REF
CC
B
A
1
2
3
4
8
7
6
5
+
–
REF
RE
DE
DI
GND
CONV
GND
120Ω
U3
LTC1864CMS8
ANALOG GROUND PLANE
4 CONDUCTOR
TELEPHONE WIRES
TO RECEIVER
C23
0.1μF
C24
0.1μF
5V
DIG
5V
DIG
4
2
1
500Ω
5V
5
U12A
U12B
16
16
74AC109
2
74AC109
U9B
74AC00
3
6
7
14
10
9
V
V
CC
CC
J
K
Q
Q
J
K
Q
Q
3
4
1
5
13
12
15
11
MC74VHC1G66
CLK
CLK
CLR
PRE
CLR
PRE
8
8
GND
5V
GND
5V
DIG
DIG
U9A
74AC00
C16
0.1μF
C17
0.1μF
5V
5V
DIG
DIG
5V
DIG
74AC74
Q
74AC86
U6
U7
C18
PRE
D
CLK
CLR
5V
DIG
74HC163AD
74HC163AD
0.1μF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
RESET
CLK
P0
P1
P2
P3
ENP
GND
RESET
CLK
P0
P1
P2
P3
ENP
GND
V
RCO
V
CC
RCO
CC
15
14
13
12
11
10
9
U10
Q
LTC1799
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
100k
5
4
1
2
3
+
V
5V
DIG
OUT
DIV
GND
SET
74AC74
Q
ENT
LO
ENT
LO
PRE
D
CLK
CLR
U13C
74AC32
Q
CLK
18645 AI2
U13B
74AC32
Figure 6. LTC1864 Manchester Transmitter
18645fb
18
LTC1864/LTC1865
APPLICATIONS INFORMATION
V
V
V
CC
CC
CC
IC3A
IC2B
IC4B
74AC08
74AC74
74AC74
IC2A
5
6
IC6D
IC5C
4
IC4A
74AC08
9
8
10
12
11
13
PRE
D
CLK
CLR
Q
74AC74
V
V
CC
74AC32
CC IC1A
74AC74
PRE
D
CLK
CLR
Q
2
3
1
74AC86
5
6
4
PRE
D
CLK
CLR
Q
CLK
CLK
2
3
1
5
6
4
2
3
1
PRE
D
CLK
CLR
Q
CLK
Q
DATA IN
CLK
Q
9
8
Q
10
PRE
D
CLK
Q
12
11
13
Q
CLK
IC6C
74LS32D
CLR
DATA
Q
DATA
IC1B
74AC74
V
IC3B
CC
IC4D
74AC08
74AC74
IC4C
74AC08
10
12
11
13
9
8
PRE
D
CLK
CLR
Q
STROBE
CLK
Q
IC8
74AC595
RECEIVE CLOCK AT
8 X TRANSMIT
CLOCK FREQUENCY
14
15
1
2
3
4
5
6
7
9
SER
SCK
SCL
RCK
8
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
D15
D14
D13
D12
D11
D10
D9
11
10
12
13
U1
LTC1485
V
CC
V
CC
1
2
3
4
8
7
6
5
RO
RE
DE
DI
V
CC
B
A
D8
GND
OPTIONAL SERIAL TO
PARALLEL CONVERTER
V
CC
IC9
15V SUPPLY TO
TRANSMITTER
74AC595
14
11
10
12
13
15
1
2
3
4
5
6
7
9
SER
SCK
SCL
RCK
8
QA
QB
QC
QD
QE
QF
QG
QH
QHIN
D7
D6
D5
D4
D3
D2
D1
D0
STROBE
IC7B
74AC109
4 CONDUCTOR
TELEPHONE WIRES
TO TRANSMITTER
R1
120Ω
11
10
Q
PRE
14
J
12
CLK
13
K
DATA
15
9
CLR
Q
18645 AI3
Figure 7. LTC1864 Manchester Receiver
18645fb
19
LTC1864/LTC1865
APPLICATIONS INFORMATION
Transmit LTC1864 Data Over Modular Telephone Wire
Using Simple Transmitter/Receiver
zeros, a start bit, followed by the 16 data bits (one sample
every 48 clock cycles) at a clock frequency of 1MHz set by
the LTC1799 oscillator. Sending at least 18 zeros before
each start bit ensures that if synchronization is lost, the
receiver can resynchronize to a start bit under all condi-
tions. The serial to parallel converter shown in Figure 7
requires 18 zeros to avoid triggering on data bits.
Figure 6 shows a simple Manchester encoder and dif-
ferential transmitter suitable for use with the LTC1864.
This circuit allows transmission of data over inexpensive
telephone wire. This is useful for measuring a remote
sensor, particularlywhenthecostofpreservingtheanalog
signal over a long distance is high.
The Manchester receiver shown in Figure 7 was adopted
from Xilinx application note 17-30 and would typically be
implemented in an FPGA. The decoder clock frequency is
nominally 8 times the transmit clock frequency and is very
tolerant of frequency errors. The outputs of the decoder
are data and a strobe that indicates a valid data bit. The
data can be deserialized using shift registers as shown.
The start bit resets the J-K/flip-flop on its way into the
Manchester encoding is a clock signal that is modulated
by exclusive ORing with the data signal. The resulting
signal contains both clock and data information and has
anaveragedutycycleof50%, thatalsoallowstransformer
coupling. In practice, generating a Manchester encoded
signal with an XOR gate will often produce glitches due
to the skew between data and clock transitions. The D
flip-flops in this encoder retime the clock and data such
that the respective edges are closely aligned, effectively
suppressing glitches. The retimed data and clock are then
XORed to produce the Manchester encoded data, which
is interfaced to telephone wire with an LTC1485 RS485
transceiver.
first shift register. When it appears at the QH output of
IN
the second shift register, it sets the flip-flop that loads the
parallel data into the output register.
With AC family CMOS logic at 5V the receiver clock fre-
quencyislimitedto20MHz;thecorrespondingtransmitter
clock frequency is 2.5MHz. If the receiver is implemented
in an FPGA that can be clocked at 160MHz, the LTC1864
can be clocked at its rated clock frequency of 20MHz.
In order to synchronize to incoming data, the receiver
needs a sequence to indicate the start of a data word. The
transmitter schematic shows logic that will produce 31
18645fb
20
LTC1864/LTC1865
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.52
(.206)
REF
8
7 6 5
5.23
3.2 – 3.45
(.206)
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.1
(.192 ± .004)
(.126 – .136)
MIN
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.65
(.0256)
BSC
0.42 ± 0.04
(.0165 ± .0015)
TYP
1
2
3
4
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.077)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
0.13 ± 0.05
(.005 ± .002)
0.65
(.0256)
BCS
MSOP (MS8) 1001
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
18645fb
21
LTC1864/LTC1865
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
5.23
3.00 ± 0.102
(.118 ± .004)
NOTE 4
3.2 – 3.45
(.206)
4.88 ± 0.10
(.192 ± .004)
(.126 – .136)
MIN
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
1
2
3
4 5
0.53 ± 0.01
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
MSOP (MS) 1001
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
0.50
(.0197)
TYP
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
18645fb
22
LTC1864/LTC1865
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
18645fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1864/LTC1865
TYPICAL APPLICATION
Sample Two Channels Simultaneously with a Single Input ADC
4096 Point FFT of Output
0
10
20
30
40
50
60
70
80
f
f
f
= 7.507324kHz AT 530mV
= 45.007324kHz AT 1.7V
1
2
S
P-P
P-P
5V
0.1μF
f
= 100kHz
1
+
(0V TO 0.66V)
0.1μF
0.1μF
1μF
1μF
4.096V
REF
100Ω
1/2
LT1492
4.096V
REF
–
100pF
5k
5k
20k
5pF
8
1
28.7k
V
REF
7
6
5
CC
90
10k
2
3
SCK
+
100
110
120
130
IN
10k
1μF
LTC1864
SDO
–
IN
5V
CONV
GND
4
0.1μF
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
0.1μF
f
8
2
+
(0V TO 2V)
100Ω
1/2
LT1492
18645 TA03b
–
100pF
4
18645 TA03a
RELATED PARTS
PART NUMBER
14-Bit Serial I/O ADCs
LTC1417
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
400ksps
200ksps
20mW
15mW
16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or 5V
Serial/Parallel I/O, Internal Reference, 5V or 5V
LTC1418
16-Bit Serial I/O ADCs
LTC1609
200ksps
65mW
Configurable Bipolar or Unipolar Input Ranges, 5V
References
LT1460
Micropower Precision Series Reference
Micropower Low Dropout Reference
Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23
60μA Supply Current, 10ppm/°C, SOT-23
LT1790
Op Amps
LT1468/LT1469
LT1806/LT1807
LT1809/LT1810
Single/Dual 90MHz, 16-Bit Accurate Op Amps
Single/Dual 325MHz Low Noise Op Amps
Single/Dual 180MHz Low Distortion Op Amps
22V/μs Slew Rate, 75μV/125μV Offset
140V/μs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion
350V/μs Slew Rate, –90dBc Distortion at 5MHz
18645fb
LT 1207 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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