LTC1702AIGN#TRPBF [Linear]
LTC1702A - Dual 550kHz Synchronous 2-Phase Switching Regulator Controller; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC1702AIGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1702A - Dual 550kHz Synchronous 2-Phase Switching Regulator Controller; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C 信息通信管理 开关 光电二极管 |
| 文件： | 总36页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1702A
Dual 550kHz Synchronous
2-Phase Switching Regulator Controller
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FEATURES
DESCRIPTIO
The LTC®1702A is a dual switching regulator controller
■
Pin Compatible with the LTC1702 with Improved
Current Limit Control
Two Sides Run Out-of-Phase to Minimize CIN
No External Current Sense Resistors
Excellent Output Regulation: 1% Total Output
Accuracy
Two Independent Controllers in One Package
All N-Channel External MOSFET Architecture
550kHz Switching Frequency Minimizes External
Component Size
1A to 25A Output Current per Channel
High Efficiency over Wide Load Current Range
Less Than 100µA Shutdown Current
Small 24-Pin Narrow SSOP Package
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optimized for high efficiency with low input voltages. It
includestwocomplete,on-chip,independentswitchingregu-
lator controllers each designed to drive a pair of external N-
channel MOSFETs in a voltage mode feedback, synchronous
buck configuration. The LTC1702A uses a constant-fre-
quency, true PWM design switching at 550kHz, minimizing
external component size and cost and maximizing load
transient performance. The synchronous buck architecture
automatically shifts to discontinuous and then to Burst
Mode® operation as the output load decreases, ensuring
maximum efficiency over a wide range of load currents.
■
■
■
■
■
■
■
■
■
■
The LTC1702A features an onboard reference trimmed to
0.5% and can provide better than 1% regulation at the
converteroutputs.Open-drainlogicoutputsindicatewhether
eitheroutputhasrisentowithin5%ofthefinaloutputvoltage
and an optional latching FAULT mode protects the load if the
output rises 15% above the intended voltage. Each channel
can be enabled independently; with both channels disabled,
the LTC1702A shuts down and supply current drops below
100µA.
APPLICATIO S
■
■
■
■
Microprocessor, DSP Core and I/O Supplies
Multiple Logic Supply Generator
Distributed Power Applications
High Efficiency Power Conversion
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 6144194.
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TYPICAL APPLICATIO
Dual Output High Power 3.3V/2.5V Logic Supply
V
IN
= 5V ±10%
C
IN
, C
: PANASONIC EEFUE0G181R
: KEMET TS10X337M010AS
OUT1 OUT2
+
D1
C
IN
C
10Ω 10µF
330µF
×3
D2
D1, D2: MOTOROLA MBR0520LT1
D3, D4: MOTOROLA MBRS320T3
L1, L2: SUMIDA CEP125-1R0
1µF
11.8k
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Q1 TO Q8: FAIRCHILD FDS6670A
PV
I
MAX2
1µF
CC
1µF
1µF
10µF
BOOST1
BG1
BOOST2
BG2
3
Q1
Q3
Q2
Q4
Q5
Q7
Q6
Q8
4
L1
1µH
L2
TG1
TG2
1µH
V
V
OUT2
OUT1
2.5V
AT 15A
5
3.3V
SW1
SW2
11.8k
AT 15A
6
D3
D4
I
PGND
PGOOD2
FAULT
RUN/SS2
COMP2
FB2
+
C
MAX1
OUT1
1µF
LTC1702A
180µF
×4
7
1.2k
1.6k
PGOOD1
FCB
8
+
C
OUT2
15.8k
1%
10k
1%
820pF
1µF
180µF
×4
680pF
9
RUN/SS
COMP1
SGND
FB1
1µF
10
11
12
1µF
4.99k
1%
4.75k
1%
47k
680pF
68k
3300pF
V
IN
10k
V
IN
27pF
27pF
V
CC
10k
PWRGD2
FAULT
PWRGD1
1702 TA01
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LTC1702A
W W U W
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
Supply Voltage
1
2
I
MAX2
24
23
22
21
20
19
18
17
16
15
14
13
PV
CC
VCC........................................................................................... 7V
BOOSTn............................................................... 15V
BOOSTn – SWn .................................................... 7V
Input Voltage
BOOST2
BG2
BOOST1
BG1
3
4
TG2
TG1
5
SW2
SW1
SWn .......................................................... –1V to 8V
All Other Inputs ......................... –0.3V to VCC + 0.3V
Peak Output Current < 10µs
TGn, BGn ............................................................... 5A
Operating Temperature Range
LTC1702AC ............................................. 0°C to 70°C
LTC1702AI ........................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
6
PGND
PGOOD2
FAULT
RUN/SS2
COMP2
FB2
I
MAX1
7
PGOOD1
FCB
8
9
RUN/SS1
COMP1
SGND
10
11
12
V
FB1
CC
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/ W
ORDER PART NUMBER
LTC1702ACGN
LTC1702AIGN
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
V
CC
= 5V unless otherwise specified. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
V
V
Supply Voltage
CC
●
●
●
3
3
7
7
7
V
V
V
CC
PV
BV
PV Supply Voltage
(Note 2)
CC
CC
CC
BOOST Pin Voltage
V
– V (Note 2)
2.7
BOOST
SW
I
V
Supply Current
Test Circuit 1, C = 0pF
RUN/SS1 = RUN/SS2 = 0V (Note 5)
●
●
2.2
30
8
100
mA
µA
CC
CC
L
IPV
PV Supply Current
CC
Test Circuit 1, C = 0pF (Note 4)
RUN/SS1 = RUN/SS2 = 0V (Note 5)
●
●
2.2
6
6
100
mA
µA
CC
L
I
BOOST Pin Current
Feedback Voltage
Test Circuit 1, C = 0pF (Note 4)
RUN/SS1 = RUN/SS2 = 0V
●
●
1.3
0.1
3
10
mA
µA
BOOST
L
V
Test Circuit 1, C = 0pF, LTC1702AC
●
●
0.792
0.790
0.800
0.800
0.808
0.810
V
V
FB
L
Test Circuit 1, C = 0pF, LTC1702AI
L
∆V
Feedback Voltage Line Regulation
Feedback Current
V
= 3V to 7V
CC
●
●
●
±0.005
±0.001
0.1
± 0.05
±1
%/V
µA
FB
I
FB
∆V
OUT
Output Voltage Load Regulation
(Note 6)
± 0.2
%
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LTC1702A
ELECTRICAL CHARACTERISTICS
The
CC
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
V
= 5V unless otherwise specified. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.8
MAX
UNITS
V
V
FCB Threshold
●
0.75
0.85
FCB
∆V
FCB Feedback Hysteresis
FCB Pin Current
20
mV
µA
FCB
I
●
●
± 0.001
0.55
–3.5
1
±1
0.65
–6
FCB
V
RUN/SS Pin RUN Threshold
Soft-Start Source Current
Maximum Soft-Start Sink Current
0.45
–2
V
RUN
I
RUN/SSn = 0V
µA
SS
V
V
= 0V, V = –0.5V
mA
µA
IMAX
IMAX
SW
I
I
Source Current
MAX
= 0V
●
●
–12
475
–10
–8
MAX
Switching Characteristics
f
Oscillator Frequency
Converter 2 Oscillator Phase
Minimum Duty Cycle
Maximum Duty Cycle
Driver Nonoverlap
Test Circuit 1, C = 0pF
550
180
750
kHz
DEG
%
OSC
L
Φ
Relative to Converter 1 (Note 6)
OSC2
DC
DC
●
●
●
●
0
MIN
87
90
40
12
93
100
80
%
MAX
t
Test Circuit 1, C = 2000pF (Note 7)
ns
NOV
L
t , t
r
Driver Rise/Fall Time
Test Circuit 1, C = 2000pF (Note 7)
ns
f
L
Feedback Amplifier
A
FB DC Gain
●
●
74
±3
85
25
dB
MHz
mA
VFB
GBW
FB Gain Bandwidth
FB Sink/Source Current
I
± 10
ERR
Status Outputs
V
V
PGOOD Trip Point
V
Relative to Regulated V
●
●
●
–10
–5
0.03
±0.1
100
15
–2
0.1
±1
%
V
PGOOD
OLPG
FB
OUT
PGOOD Output Low Voltage
PGOOD Output Leakage
PGOOD Delay Time
PGOOD = 1mA
I
t
µA
µs
%
V
PGOOD
PGOOD
V
V
< V
to PGOOD (Note 7)
FB
PGOOD
V
V
FAULT Trip Point
Relative to Regulated V
●
●
10
20
FAULT
OLF
FB
OUT
FAULT Output Low Voltage
FAULT Output Current
FAULT Delay Time
I
= 1mA
= 0V
0.03
–10
25
0.1
FAULT
I
t
V
V
µA
µs
FAULT
FAULT
FAULT
> V
to FAULT (Note 7)
FB
FAULT
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
Note 5: Supply current in shutdown is dominated by external MOSFET
leakage and may be significantly higher than the quiescent current drawn
by the LTC1702A, especially at elevated temperature.
Note 2: PV and BV (V
– V ) must be greater than V
of
GS(ON)
CC
CC BOOST
SW
the external MOSFETs used to ensure proper operation.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 6: This parameter is guaranteed by correlation and is not tested
directly.
Note 7: Rise and fall times are measured using 10% and 90% levels. Delay
and nonoverlap times are measured using 50% levels.
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LTC1702A
TYPICAL PERFOR A CE CHARACTERISTICS
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MOSFET Driver Supply Current
vs Gate Capacitance
Efficiency vs Load Current
Transient Response
100
90
35
30
V
IN
= 5V
TEST CIRCUIT 1
ONE DRIVER LOADED
MULTIPLY BY # OF ACTIVE
DRIVERS TO OBTAIN TOTAL
DRIVER SUPPLY CURRENT
VIN = 5V
V
OUT
= 3.3V
V
OUT = 1.8V
ILOAD = 0A-10A-0A
±2.2% MAX DEVIATION
V
V
= 2.5V
= 1.6V
OUT
OUT
25
20
15
10
5
IL
20mV/DIV
80
70
0
1702A G02
0
5
10
15
10µs/DIV
2000
4000
10000
0
6000
8000
LOAD CURRENT (A)
GATE CAPACITANCE (pF)
1702A G01
1702A G03
Normalized Oscillator Frequency
vs Temperature
Supply Current vs Temperature
Driver R vs Temperature
ON
2.5
2.0
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.6
V
CC
= 5V
V
V
= 5V
BOOST
PVCC
TEST CIRCUIT 1
L
– V = 5V
SW
C
= 0pF
2.4
2.2
PV
CC
1.5
1.0
V
CC
2.0
1.8
1.6
1.4
1.2
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
BOOST1, BOOST2
1.0
–25
0
50
75 100 125
–50
0
25
50
75
125
–50
0
25
50
75
125
–50
25
100
100
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1702A G04
1702A G05
1702A G06
RUN/SS Source Current
vs Temperature
Nonoverlap Time vs Temperature
Driver Rise/Fall vs Temperature
15
14
13
12
11
12
5.0
4.5
4.0
3.5
70
60
TEST CIRCUIT 1
V
CC
= 5V
TEST CIRCUIT 1
C
= 2000pF
C
= 2000pF
L
L
TG FALLING EDGE
BG RISING EDGE
50
40
30
20
10
BG FALLING EDGE
TG RISING EDGE
3.0
2.5
2.0
0
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
1702A G09
1702A G07
1702A G08
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LTC1702A
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PIN FUNCTIONS
PVCC (Pin 1): Driver Power Supply Input. PVCC provides
power to the two BGn output drivers. PVCC must be
connected to a voltage high enough to fully turn on the
external MOSFETs QB1 and QB2. PVCC should generally
be connected directly to VIN. PVCC requires at least a 1µF
bypass capacitor directly to PGND.
controller1.IfthevoltagedropacrossthebottomMOSFET,
QB1, exceeds the magnitude of the voltage at IMAX1
,
controller 1 will go into current limit. The IMAX1 pin has an
internal 10µA current source pull-up, allowing the current
threshold to be set with a single external resistor to PGND.
See the Current Limit Programming section for more
information on choosing RIMAX
.
BOOST1 (Pin 2): Controller 1 Top Gate Driver Supply. The
BOOST1 pin supplies power to the floating TG1 driver.
BOOST1 should be bypassed to SW1 with a 1µF capacitor.
An additional Schottky diode from VIN to BOOST1 pin will
create a complete floating charge-pumped supply at
BOOST1. No other external supplies are required. A 5Ω to
10Ωresistorinserieswiththispincanhelpcontrolringing
at the switch node. See the EXTERNAL COMPONENTS
SELECTION/MOSFET Series Resistors section for more
information.
PGOOD1 (Pin 7): Controller 1 Power Good. PGOOD1 is an
open-drain logic output. PGOOD1 will pull low whenever
FB1falls5%belowitsprogrammedvalue.WhenRUN/SS1
is low (side 1 shut down), PGOOD1 will go high.
FCB (Pin 8): Force Continuous Bar. The FCB pin forces
both converters to maintain continuous synchronous
operation regardless of load when the voltage at FCB
drops below 0.8V. FCB is normally tied to VCC. To force
continuous operation, tie FCB to SGND. FCB can also be
connected to a feedback resistor divider from a secondary
winding on one converter’s inductor to generate a third
regulated output voltage. Do not leave FCB floating.
BG1 (Pin 3): Controller 1 Bottom Gate Drive. The BG1 pin
drives the gate of the bottom N-channel synchronous
switch MOSFET, QB1. BG1 is designed to drive up to
10,000pF of gate capacitance directly. If RUN/SS1 goes
low, BG1 will go low, turning off QB1. If FAULT mode is
tripped, BG1 will go high and stay high, keeping QB1 on
until the VCC is cycled. BG1 should be directly connected
to the MOSFET gate. Do not use a series resistor. See the
EXTERNAL COMPONENTS SELECTION/MOSFET Series
Resistors section for more information.
RUN/SS1 (Pin 9): Controller 1 Run/Soft-start. Pulling
RUN/SS1 to SGND will disable controller 1 and turn off
both of its external MOSFET switches. Pulling both
RUN/SS pins down will shut down the entire LTC1702A,
dropping the quiescent supply current below 100µA. A
capacitor from RUN/SS1 to SGND will control the turn-on
time and rate of rise of the controller 1 output voltage at
power-up. An internal 3.5µA current source pull-up at
RUN/SS1 pin sets the turn-on time at approximately
500ms/µF.
TG1(Pin4):Controller1TopGateDrive.TheTG1pindrives
thegateofthetopN-channelMOSFET,QT1.TheTG1driver
draws power from the BOOST1 pin and returns to the SW1
pin, providingtruefloatingdrivetoQT1. TG1isdesignedto
drive up to 10,000pF of gate capacitance directly. In
shutdown or fault modes, TG1 will go low. TG1 should be
directly connected to the MOSFET gate. Do not use a series
resistor. See the EXTERNAL COMPONENTS SELECTION/
MOSFET Series Resistors section for more information.
COMP1 (Pin 10): Controller 1 Loop Compensation. The
COMP1 pin is connected directly to the output of the first
controller’s error amplifier and the input to the PWM
comparator. An RC network is used at the COMP1 pin to
compensate the feedback loop for optimum transient
response.
SW1 (Pin 5): Controller 1 Switching Node. SW1 should be
connected to the switching node of converter 1. The TG1
driver ground returns to SW1, providing floating gate
drive to the top N-channel MOSFET switch, QT1. The
voltage at SW1 is compared to IMAX1 by the current limit
comparator while the bottom MOSFET, QB1, is on.
SGND (Pin 11): Signal Ground. All internal low power
circuitry returns to the SGND pin. Connect to a low
impedance ground, separated from the PGND node. All
feedback,compensationandsoft-startconnectionsshould
return to SGND. SGND and PGND should connect only at
a single point, near the PGND pin and the negative plate of
the CIN bypass capacitor.
IMAX1 (Pin 6): Controller 1 Current Limit Set. The IMAX1
pin sets the current limit comparator threshold for
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LTC1702A
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PIN FUNCTIONS
FB1 (Pin 12): Controller 1 Feedback Input. FB1 should be
connected through a resistor network to VOUT1 to set the
output voltage. The loop compensation network for con-
troller 1 also connects to FB1.
turning on the bottom MOSFET switches and pulling down
the high output voltage. The LTC1702A will remain latched
in this state until the power is cycled. When FAULT mode
is active, the FAULT pin will be pulled up with an internal
10µA current source. Tying FAULT directly to PGND will
disable latched FAULT mode and will allow the LTC1702A
to resume normal operation when the overvoltage fault is
removed.
VCC (Pin 13): Power Supply Input. All internal circuits
except the output drivers are powered from this pin. VCC
should be connected to a low noise power supply voltage
between 3V and 7V and should be bypassed to SGND with
atleasta1µFcapacitorincloseproximitytotheLTC1702A.
PGOOD2(Pin18):Controller2PowerGood.SeePGOOD1.
FB2 (Pin 14): Controller 2 Feedback Input. See FB1.
PGND (Pin 19): Power Ground. The BGn drivers return to
this pin. Connect PGND to a high current ground node in
close proximity to the sources of external MOSFETs, QB1
and QB2, and the VIN and VOUT bypass capacitors.
COMP2 (Pin 15): Controller 2 Loop Compensation. See
COMP1.
RUN/SS2 (Pin 16): Controller 2 Run/Soft-start. See RUN/
SS1.
SW2 (Pin 20): Controller 2 Switching Node. See SW1.
TG2 (Pin 21): Controller 2 Top Gate Drive. See TG1.
BG2 (Pin 22): Controller 2 Bottom Gate Drive. See BG1.
FAULT (Pin 17): Output Overvoltage Fault (Latched). The
FAULT pin is an open-drain output with an internal 10µA
pull-up. If either regulated output voltage rises more than
15% above its programmed value for more than 25µs, the
FAULT output will go high and the entire LTC1702A will be
disabled. When FAULT is high, both BG pins will go high,
BOOST2 (Pin 23): Controller 2 Top Gate Driver Supply.
See BOOST1.
IMAX2 (Pin 24): Controller 2 Current Limit Set. See IMAX1
.
W
BLOCK DIAGRAM
PV
CC
FCB
V
CC
BOOST1,2
TG1,2
BURST
LOGIC
DRIVE
LOGIC
SW1,2
BG1,2
PGND
90% DUTY CYCLE
OSC
SGND
1V
P-P
550kHz
DIS
3.5µA
100µs
DELAY
PGOOD1,2
FAULT
SOFT
START
RUN/SS1,2
COMP1,2
25µs
DELAY
PGOOD
I
LIM
10µA
FB
FLT
+
–
FROM
I
MAX1,2
OTHER
800mV
760mV
920mV
CONTROLLER
FB1,2
SHUTDOWN TO
THIS CONTROLLER
1702A BD
SHUTDOWN TO
ENTIRE CHIP
550mV
FROM
OTHER
CONTROLLER
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LTC1702A
TEST CIRCUIT
Test Circuit 1
5V
+
I
I
I
I
BOOST2
BOOST1
CC
PVCC
0.1µF
100µF
V
PV
CC
CC
BOOST1
BOOST2
f
OSC
MEASURED
TG1
TG2
5V
BG1
BG2
SW1
SW2
5V
C
C
C
C
L
L
L
L
10k
I
I
MAX2
MAX1
LTC1702A
10k
FCB
V
V
PGOOD1
PGOOD2
FAULT
V
PGOOD1
PGOOD2
FAULT
RUN/SS1
COMP1
RUN/SS2
COMP2
FB2
2k
2k
V
FB1
V
FB2
FB1
GND
PGND
1702A TC
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APPLICATIONS INFORMATION
OVERVIEW
controllersallow,improvingstabilityandmaximizingtran-
sient response. The 800mV internal reference allows
regulated output voltages as low as 800mV without exter-
nal level shifting amplifiers.
The LTC1702A is a dual, step-down (buck), voltage mode
feedback switching regulator controller. It is designed to
be used in a synchronous switching architecture with two
external N-channel MOSFETs per channel. It is intended to
operate from a low voltage input supply (7V maximum)
and provide a high power, high efficiency, precisely regu-
lated output voltage. Several features make it particularly
suitedformicroprocessorsupplyregulation.Outputregu-
lation is extremely tight, with DC line and load regulation
and initial accuracy better than 1%, and total regulation
including transient response inside of 3% with a properly
designed circuit. The 550kHz switching frequency allows
theuseofphysicallysmall,lowvalueexternalcomponents
without compromising performance.
The LTC1702A’s synchronous switching logic transitions
automatically into Burst Mode operation, maximizing effi-
ciency with light loads. Onboard power-good and over-
voltage (OV) fault flags indicate when the output is in
regulation or an OV fault has occurred. The OV flag can be
set to latch the device off when an OV fault has occurred,
or to automatically resume operation when the fault is
removed.
The LTC1702A takes a low input voltage and generates
two lower output voltages at very high currents. Its
strengths are small size, unmatched regulation and tran-
sient response and high efficiency. This combination
makes it ideal for providing multiple low voltage logic
supplies to microprocessors or high density ASICs, in
systemsusinga“2-step”regulationarchitecturecommon
in portable and advanced desktop computers.
The LTC1702A’s internal feedback amplifier is a 25MHz
gain-bandwidth op amp, allowing the use of complex
multipole/zero compensation networks. This allows the
feedback loop to maintain acceptable phase margin at
higher frequencies than traditional switching regulator
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LTC1702A
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APPLICATIONS INFORMATION
2-Step Conversion
regulation system happens in the 5V supply, which is
usuallylocatedawayfromtheCPU. Thepowerlosttoheat
in the LTC1702A section of the system is relatively low,
minimizing the added heat near the CPU.
“2-step” architectures use a primary regulator to convert
the input power source (batteries or AC line voltage) to an
intermediate supply voltage, often 5V. This intermediate
voltage is then converted to the low voltage, high current
supplies required by the system using a secondary regu-
lator—the LTC1702A. 2-step conversion eliminates the
need for a single converter that converts a high input
voltage to a very low output voltage, often an awkward
design challenge. It also fits naturally into systems that
continue to use the 5V supply to power portions of their
circuitry, or have excess 5V capacity available as newer
circuit designs shift the current load to lower voltage
supplies.
See the Optimizing Performance section for a detailed
explanation of how to calculate system efficiency.
2-Phase Operation
The LTC1702A dual switching regulator controller also
features the considerable benefits of 2-phase operation.
Notebook computers, hand-held terminals and automo-
tive electronics all benefit from the lower input filtering
requirement, reduced electromagnetic interference (EMI)
and increased efficiency associated with 2-phase
operation.
Each regulator in a typical 2-step system maintains a
relativelylowstep-downratio(5:1orless), runningathigh
efficiency while maintaining a reasonable duty cycle. In
contrast, a regulator taking a single step from a high input
voltage to a 1.xV or 2.xV output must run at a very narrow
duty cycle, mandating trade-offs in external component
values and compromising efficiency and transient
response. The efficiency loss can exceed that of using a
2-step solution (see the 2-Step Efficiency Calculation
section and Figure 14). Further complicating the calcula-
tion is the fact that many systems draw a significant
fraction of their total power off the intermediate 5V supply,
bypassing the low voltage supply. 2-step solutions using
the LTC1702A usually match or exceed the total system
efficiency of single-step solutions, and provide the addi-
tional benefits of improved transient response, reduced
PCB area and simplified power trace routing.
Why the need for 2-phase operation? Up until the
LTC1702A, constant-frequency dual switching regulators
operatedbothchannelsinphase(i.e., single-phaseopera-
tion). This means that both topside MOSFETs turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitorsandincreasingbothEMIandlossesintheinput
capacitor and input power supply.
With2-phaseoperation,thetwochannelsoftheLTC1702A
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the switches,
greatlyreducingtheoverlaptimewheretheyaddtogether.
The result is a significant reduction in total RMS input
current, which in turn allows less expensive input capaci-
tors to be used, reduces shielding requirements for EMI
and improves real world operating efficiency.
2-stepregulationcanbuyadvantagesinthermalmanage-
ment as well. Power dissipation in the LTC1702A portion
of a 2-step circuit is lower than it would be in a typical 1-
step converter, even in cases where the 1-step converter
has higher total efficiency than the 2-step system. In a
typical microprocessor core supply regulator, for ex-
ample, the regulator is usually located right next to the
CPU. In a 1-step design, all of the power dissipated by the
core regulator is right there next to the hot CPU, aggravat-
ing thermal management. In a 2-step LTC1702A design,
a significant percentage of the power lost in the core
Figure 7 shows example waveforms for a single switching
regulator channel versus a 2-phase LTC1702A system
with both sides switching. A single-phase dual regulator
with both sides operating would exhibit double the single
sidenumbers.Inthisexample,2-phaseoperationreduced
the RMS input current from 9.3ARMS (2 × 4.66ARMS) to
4.8ARMS. While this is an impressive reduction in itself,
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2
rememberthatthepowerlossesareproportionaltoIRMS
,
High Efficiency
meaning that the actual power wasted is reduced by a
factorof3.75.Thereducedinputripplevoltagealsomeans
less power is lost in the input power path, which could
include batteries, switches, trace/connector resistances
andprotectioncircuitry. Improvementsinbothconducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
The LTC1702A uses a synchronous step-down (buck)
architecture, with two external N-channel MOSFETs per
output. A floating topside driver and a simple external
charge pump provide full gate drive to the upper MOSFET.
The voltage mode feedback loop and MOSFET VDS current
limit sensing remove the need for an external current
sense resistor, eliminating an external component and a
source of power loss in the high current path. Properly
designed circuits using low gate charge MOSFETs are
capable of efficiencies exceeding 90% over a wide range
of output voltages.
Small Footprint
The LTC1702A operates at a 550kHz switching frequency,
allowing it to use low value inductors without generating
excessive ripple currents. Because the inductor stores
less energy per cycle, the physical size of the inductor can
be reduced without risking core saturation, saving PCB
board space. The high operating frequency also means
less energy is stored in the output capacitors between
cycles, minimizing their required value and size. The
remaining components, including the 150mil SSOP-24
LTC1702A, are tiny, allowing an entire dual-output
LTC1702A circuit to be constructed in 1.5in2 of PCB
space. Further, this space is generally located right next to
the microprocessor or in some similarly congested area,
where PCB real estate is at a premium. The fact that the
LTC1702A runs off the 5V supply, often available from a
power plane, is an added benefit in portable systems —it
does not require a dedicated supply line running from the
battery.
ARCHITECTURE DETAILS
The LTC1702A dual switching regulator controller in-
cludes two identical, independent regulator channels. The
two sides of the chip and their corresponding external
components act independently of each other with the
exception of the common input bypass capacitor and the
FCB and FAULT pins, which affect both channels. In the
following discussions, when a pin is referred to without
mentioningwhichsideisinvolved, thatdiscussionapplies
equally to both sides.
Switching Architecture
Each half of the LTC1702A is designed to operate as a
synchronous buck converter (Figure 1). Each channel
includes two high power MOSFET gate drivers to control
external N-channel MOSFETs QT and QB. These drivers
have 0.5Ω output impedances and can carry well over an
Fast Transient Response
TheLTC1702Ausesafast25MHzGBWopampasanerror
amplifier. This allows the compensation network to be
designed with several poles and zeros in a more flexible
configuration than with a typical gm feedback amplifier.
The high bandwidth of the amplifier, coupled with the high
switching frequency and the low values of the external
inductor and output capacitor, allow very high loop cross-
over frequencies. The low inductor value is the other half
of the equation—with a typical value on the order of 1µH,
the inductor allows very fast di/dt slew rates. The result is
superior transient response compared with conventional
solutions.
V
IN
+
C
C
IN
QT
QB
TG
L
EXT
LTC1702A
PGND
SW
BG
V
OUT
+
OUT
1702A F01
Figure 1. Synchronous Buck Architecture
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back loop components can be similarly tightly specified.
Noise generated by the circuit will always be in a known
frequency band with the 550kHz frequency designed to
leavethe455kHzIFbandfreeofinterference.Subharmonic
oscillation and slope compensation, common headaches
with constant frequency current mode switchers, are
absent in voltage mode designs like the LTC1702A.
amp of continuous current with peak currents up to 5A to
slew large MOSFET gates quickly. The external MOSFETs
are connected with the drain of QT attached to the input
supply and the source of QT at the switching node SW. QB
is the synchronous rectifier with its drain at SW and its
source at PGND. SW is connected to one end of the
inductor,withtheotherendconnectedtoVOUT.Theoutput
capacitor is connected from VOUT to PGND.
During the time that QT is on, its source (the SW pin) is at
VIN. VIN is also the power supply for the LTC1702A. How-
ever, QT requires VIN + VGS(ON) at its gate to achieve
minimum RON. This presents a problem for the
LTC1702A— it needs to generate a gate drive signal at TG
higher than its highest supply voltage. To get around this,
the TG driver runs from floating supplies, with its negative
supply attached to SW and its power supply at BOOST.
This allows it to slew up and down with the source of QT.
In combination with a simple external charge pump (Fig-
ure 2), this allows the LTC1702A to completely enhance
the gate of QT without requiring an additional, higher
supply voltage.
When a switching cycle begins, QB is turned off and QT is
turned on. SW rises almost immediately to VIN and the
inductor current begins to increase. When the PWM pulse
finishes, QTturnsoffandonenonoverlapintervallater, QB
turnson. NowSWdropstoPGNDandtheinductorcurrent
decreases. The cycle repeats with the next tick of the
master clock. The percentage of time spent in each mode
is controlled by the duty cycle of the PWM signal, which in
turn is controlled by the feedback amplifier. The master
clock generates a 1VP-P, 550kHz sawtooth waveform and
turns QT once every 1.8µs. In a typical application with a
5Vinputanda1.6Voutput, thedutycyclewillbesetat1.6/
5 × 100% or 32% by the feedback loop. This will give
roughly a 575ns on-time for QT and a 1.22µs on-time for
QB.
The two channels of the LTC1702A run from a common
clock, with the phasing chosen to be 180° from side 1 to
side 2. This has the effect of doubling the frequency of the
switching pulses seen by the input bypass capacitor, sig-
nificantly lowering the RMS current seen by the capacitor
andreducingthevaluerequired(seethe2-Phasesection).
This constant frequency operation brings with it a couple
of benefits. Inductor and capacitor values can be chosen
with a precise operating frequency in mind and the feed-
V
IN
+
+
D
C
CP
IN
PV
BOOST
TG
CC
C
CP
1µF
QT
L
EXT
SW
V
OUT
BG
QB
C
OUT
LTC1702A
PGND
1702A F02
Figure 2. Floating TG Driver Supply
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Feedback Amplifier
PGOOD Flags
Each side of the LTC1702A senses the output voltage at
VOUT with an internal feedback op amp (see Block Dia-
gram). This is a real op amp with a low impedance output,
85dBopen-loopgainand25MHzgain-bandwidthproduct.
The positive input is connected internally to an 800mV
reference, while the negative input is connected to the FB
pin. The output is connected to COMP, which is in turn
connected to the soft-start circuitry and from there to the
PWM generator.
PGOOD is an open-drain output, allowing it to be wire-
ORed with other open-drain/open-collector signals. An
external pull-up resistor is required for PGOOD to swing
high. Any time the FB pin is more than 5% below the
programmed value for more than 100µs, PGOOD will pull
low, indicating that the output is out of regulation. PGOOD
remains active during soft-start and current limit. The
100µs delay ensures that short output transient glitches
that are successfully “caught” by the PGOOD comparator
don’t cause momentary glitches at the PGOOD pin.
Unlike many regulators that use a resistor divider con-
nectedtoahighimpedancefeedbackinput, theLTC1702A
is designed to use an inverting summing amplifier topol-
ogy with the FB pin configured as a virtual ground. This
allows flexibility in choosing pole and zero locations not
available with simple gm configurations. In particular, it
allows the use of “type 3” compensation, which provides
a phase boost at the LC pole frequency and significantly
improves loop phase margin (see Figure 3). The Feedback
Loop/Compensation section contains a detailed explana-
tion of type 3 feedback loops.
When either side of the LTC1702A is in shutdown, its
associated PGOOD pin will go high. This behavior allows
a valid PGOOD reading when the two PGOOD pins are tied
together, even if one side is shut down. It also reduces
quiescent current by eliminating the excess current drawn
by the pull-up at the PGOOD pin. As soon as the RUN/SS
pin rises above the shutdown threshold and the side
comes out of shutdown, the PGOOD pin will pull low until
the output voltage is valid. If both sides are shut down at
the same time, both PGOOD pins will go high. To avoid
confusion, if either side of the LTC1702A is shut down, the
host system should ignore the associated PGOOD pin.
C3
R3
0.8V
+
–
COMP
FB
R1
FB
V
OUT
R
B
C2
C1
R2
1702A F03
Figure 3. “Type 3” Feedback Loop
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SHUTDOWN/SOFT-START
limit increases linearly between 1V and 2V, reaching its
final value of 90% when RUN/SS is above 2V. Somewhere
before this point, the feedback amplifier will assume
control of the loop and the output will come into regula-
tion. (See Figure 4).
EachhalfoftheLTC1702AhasaRUN/SSpin. TheRUN/SS
pins perform two functions: when pulled to ground, each
shuts down its half of the LTC1702A, and each acts as a
conventional soft-start pin, enforcing a maximum duty
cycle limit proportional to the voltage at RUN/SS. An
internal 3.5µA current source pull-up is connected to each
RUN/SS pin, allowing a soft-start ramp to be generated
with a single external capacitor to ground. The 3.5µA
current sources are active even when the LTC1702A is
shut down, ensuring the device will start when any exter-
nal pull-down at RUN/SS is released. Either side can be
shut down without affecting the operation of the other
side. If both sides are shut down at the same time, the
LTC1702A goes into a micropower sleep mode, and
quiescent current drops below 100µA. Entering sleep
mode also resets the FAULT latch, if it was set.
CURRENT LIMIT
The LTC1702A includes an onboard current limit that
engages when the maximum output current exceeds a
user-programmed level. It works by sensing the voltage
drop across QB during the time that QB is on and compar-
ing that voltage to a user-programmed voltage at IMAX
.
Since QB looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current
flowinginit. Inabuckconverter, theaveragecurrentinthe
inductor is equal to the output current. This current also
flows through QB during its on-time. Thus, by watching
the voltage across QB, the LTC1702A can monitor the
output current.
Each RUN/SS pin shuts down its half of the LTC1702A
when it falls below about 0.55V. The maximum duty cycle
V
OUT
0V
5V
V
2V
2V
RUN/SS
1.0V
0.55V
0V
LTC1702A ENABLED
RUN/SS CONTROLS
DUTY CYCLE
RUN/SS CONTROLS
DUTY CYCLE
COMP CONTROLS DUTY CYCLE
START-UP
NORMAL OPERATION
CURRENT LIMIT
1702A F04
Figure 4. Soft-Start Operation in Start-Up and Current Limit
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Any time QB is on and the current flowing to the output is
reasonably large, the SW node at the drain of QB will be
somewhat negative with respect to PGND. The LTC1702A
senses this voltage and inverts it to allow it to compare the
sensed voltage with a positive voltage at the IMAX pin. The
IMAX pin includes a trimmed 10µA pull-up, enabling the
Note that even brief overcurrent excursions will fire the
current limit circuit, quickly removing power to the load. If
the ability to withstand larger overcurrent surges without
tripping off is desired, consider using the pin-compatible
LTC1702, which provides this capability in exchange for
increased stress on the power MOSFETs.
usertosetthevoltageatIMAX withasingleresistor, RIMAX
,
Power MOSFET RDS(ON) varies from MOSFET to MOSFET,
limiting the accuracy obtainable from the LTC1702A cur-
rentlimitloop. Additionally, ringingontheSWnodedueto
parasitics can add to the apparent current, causing the
loop to engage early. The LTC1702A current limit is
designed primarily as a disaster prevention, “no blow up”
circuit, and is not useful as a precision current regulator.
It should typically be set around 50% above the maximum
expected normal output current to prevent component
tolerances from encroaching on the normal current range.
See the Current Limit Programming section for advice on
to ground. The LTC1702A compares the two inputs and
limits the output current when the magnitude of the
negative voltage at the SW pin is greater than the voltage
at IMAX
.
The LTC1702A current limit detector connects to an inter-
nal circuit that discharges the soft-start capacitor quickly
if activated. The soft-start sink current depends on the
overdrive presented to the current limit detector. If the
regulator output is short circuited, the soft-start sink
current is typically 1mA. With a soft-start capacitor less
than 0.01µF, the current-limit detector compensation is
slightly under damped. With an instantaneous short-
circuit, the current-limit detector fires and the soft-start
capacitor rapidly discharges to ground. Depending on the
current limit behavior of the regulator powering the
LTC1702A, current in the switch inductor of the shorted
output can exceed 100A before the soft-start capacitor is
discharged. This high input current surge also pulls down
the input voltage to the LTC1702A and all other circuits
connected to the LTC1702A input. After the soft-start
capacitor is discharged, the output is turned off and the
LTC1702Abeginsanewsoft-startcycle.Iftheovercurrent
condition persists, the current limit detector fires again
and the cycle repeats. With a soft-start capacitor greater
than 0.01µF, the current limit detector compensation is
slightly over damped. With an instantaneous short-circuit
condition, the soft-start capacitor is again quickly dis-
charged. However, the SS pin does not pull to ground but
only discharges until the current limit loop is in regulation.
Short-circuit current is limited to the programmed current
limit level. In this scenario, the LTC1702A regulates in
current limit and does not rerun soft-start cycles. There-
fore,theusermustbalancethetradeoffbetweensoft-start
time required for the system versus desired current limit
behavior. Consult the Current Limit Programming section
for more information.
choosing a valve for RIMAX
.
DISCONTINUOUS/Burst Mode OPERATION
Theory of operation
The LTC1702A switching logic has three modes of opera-
tion. Under heavy loads, it operates as a fully synchro-
nous, continuous conduction switching regulator. In this
modeofoperation(“continuous”mode), thecurrentinthe
inductorflowsinthepositivedirection(towardtheoutput)
during the entire switching cycle, constantly supplying
current to the load. In this mode, the synchronous switch
(QB) is on whenever QT is off, so the current always flows
through a low impedance switch, minimizing voltage drop
and power loss. This is the most efficient mode of opera-
tion at heavy loads, where the resistive losses in the power
devices are the dominant loss term.
Continuous mode works efficiently when the load current
is greater than half of the ripple current in the inductor. In
abuckconverterliketheLTC1702A, theaveragecurrentin
the inductor (averaged over one switching cycle) is equal
to the load current. The ripple current is the difference
between the maximum and the minimum current during a
switching cycle (see Figure 5a). The ripple current
depends on inductor value, clock frequency and output
voltage, but is constant regardless of load as long as the
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LTC1702A remains in continuous mode. See the Inductor
Selection section for a detailed description of ripple
current.
operation:discontinuousmode(Figure5b).Indiscontinu-
ous mode, the LTC1702A detects when the inductor
current approaches zero and turns off QB for the remain-
der of the switch cycle. During this time, the voltage at the
SW pin will float about VOUT, the voltage across the
inductor will be zero, and the inductor current remains
zero until the next switching cycle begins and QT turns on
again. This prevents current from flowing backwards in
QB, eliminating that power loss term. It also reduces the
ripple current in the inductor as the output current ap-
proaches zero.
As the output load current decreases in continuous mode,
theaveragecurrentintheinductorwillreachapointwhere
it drops below half the ripple current. At this point, the
inductor current will reverse during a portion of the
switching cycle, or begin to flow from the output back to
the input. This does not adversely affect regulation, but
does cause additional losses as a portion of the inductor
current flows back and forth through the resistive power
switches, giving away a little more power each time and
lowering the efficiency. There are some benefits to allow-
ing this reverse current flow: the circuit will maintain
regulation even if the load current drops below zero (the
load supplies current to the LTC1702A) and the output
ripple voltage and frequency remain constant at all loads,
easing filtering requirements. Circuits that take advantage
of this behavior can force the LTC1702A to operate in
continuous mode at all loads by tying the FCB (Force
Continuous Bar) pin to ground.
TheLTC1702Adetectsthattheinductorcurrenthasreached
zero by monitoring the voltage at the SW pin while QB is
on. SinceQBactslikearesistor, SWshouldideallyberight
at0Vwhentheinductorcurrentreacheszero.Inreality,the
SW node will ring to some degree immediately after it is
switched to ground by QB, causing some uncertainty as to
the actual moment the average current in QB goes to zero.
The LTC1702A minimizes this effect by ignoring the SW
node for a fixed 50ns after QB turns on when the ringing
is most severe, and by including a few millivolts offset in
the comparator that monitors the SW node. Despite these
precautions, some combinations of inductor and layout
parasiticscancausetheLTC1702Atoenterdiscontinuous
mode erratically. In many cases, the time that QB turns off
will correspond to a peak in the ringing waveform at the
SW pin (Figure 6). This erratic operation isn’t pretty, but
retains much of the efficiency benefit of discontinuous
mode and maintains regulation at all times.
Discontinuous Mode
To minimize the efficiency loss due to reverse current flow
atlightloads, theLTC1702Aswitchestoasecondmodeof
I
RIPPLE
I
AVERAGE
DISCONTINUOUS
COMPARATOR
TURNS OFF BG
V
SW
0V
TIME
TIME
1702A F05a
Figure 5a. Continuous Mode
50ns
BLANK
TIME
5V
0V
V
BG
1702A F06
TIME
I
RIPPLE
Figure 6. Ringing at SW Causes Discontinuous
Comparator to Trip Early
I
AVERAGE
TIME
1702A F05b
Figure 5b. Discontinuous Mode
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Burst Mode Operation
This does not affect output regulation but does reduce
efficiency at low output currents. The FCB pin threshold is
specified at 0.8V ±50mV, and includes 20mV of hyster-
esis, allowing it to be used as a precision small-signal
comparator.
Discontinuous mode removes the resistive loss drop term
in QB, but the LTC1702A is still switching QT and QB on
and off once a cycle. Each time an external MOSFET is
turned on, the internal driver must charge its gate to VCC.
Each time it is turned off, that charge is lost to ground. At
the high switching frequencies that the LTC1702A oper-
ates at, the charge lost to the gates can add up to tens of
milliampsfromVCC. Astheloadcurrentcontinuestodrop,
thisquicklybecomethedominantpowerlossterm, reduc-
ing efficiency once again.
Paralleling Outputs
Synchronous regulators (like the LTC1702A) are known
for their bullheadedness when their outputs are paralleled
with other regulators. In particular, a synchronous regu-
lator paralleled with another regulator whose output is
slightlyhigher(perhapsjustbymillivolts)willhappilysink
amps of current attempting to pull its own output back
down to what it thinks is the right value.
Once again, the LTC1702A switches to a new mode to
minimize efficiency loss: Burst Mode operation. As the
circuit goes deeper and deeper into discontinuous mode,
the QB on-time reduces. When the load drops to the point
that the output begins to rise, the LTC1702A senses this
rise and shuts both QT and QB off completely, skipping
several switching cycles until the output falls back into
range. It then resumes switching in discontinuous mode
and the burst sequence repeats. The total deviation from
the regulated output is within the 1% regulation tolerance
of the LTC1702A.
The LTC1702A discontinuous mode allows it to be paral-
leled with another regulator without fighting. A typical
system might use the LTC1702A as a primary regulator
and a small LDO as a backup regulator to keep SRAM alive
when the main power is off. When the LTC1702A is shut
down(bypullingRUN/SStoground), bothQTandQBturn
off and the output goes into a high impedance state,
allowing the smaller regulator to support the output volt-
age. However, if the LTC1702A is powered back up in
continuous mode, it will begin a soft-start cycle with a low
duty cycle, pulling the output down and corrupting the
data stored in SRAM. The solution is to tie FCB high,
allowing the device to start in discontinuous mode. Any
reversecurrentflowinQBwilltripthediscontinuousmode
circuitry, preventing the LTC1702A from pulling down the
output. The Typical Applications section shows an ex-
ample of such a circuit.
InBurstModeoperation, bothresistivelossandswitching
loss are minimized while keeping the output in regulation.
As the load current falls to zero in Burst Mode operation,
themostsignificantlosstermbecomesthe3mAquiescent
current drawn by each side of the LTC1702A—usually
much less than the minimum load current in a typical low
voltage logic system. Burst Mode operation maximizes
efficiency at low load currents, but can cause low fre-
quency ripple in the output voltage as the cycle-skipping
circuitry switches on and off.
OVERVOLTAGE FAULT
FCB Pin
The LTC1702A includes a single overvoltage fault flag for
both channels: FAULT. FAULT is an open-drain output
with an internal 10µA pull-up. If either FB pin rises more
than 15% above the nominal 800mV value for more than
25µs, the overvoltage comparator will trip, setting an
internal latch. This latch releases the pull-down at FAULT,
allowing the 10µA pull-up to take it high. When FAULT
goes high, the LTC1702A stops all switching, turns both
QB (bottom synchronous) MOSFETs on continuously and
Insomecircumstances, itisdesirabletocontrolordisable
discontinuousandBurstModeoperations.TheFCB(Force
Continuous Bar) pin allows the user to do this. When the
FCB pin is high, the LTC1702A is allowed to enter discon-
tinuous and Burst Mode operations at either side as
required. If FCB is taken low, discontinuous and Burst
Mode operations are disabled and both sides of the
LTC1702A run in continuous mode regardless of load.
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remainsinthisstateuntil bothRUN/SSpinsarepulledlow
simultaneously, the power supply is recycled, or the
FAULT pin is pulled low externally. This behavior is in-
tended to protect a potentially expensive load from over-
voltage damage at all costs. Under some conditions, this
behavior can cause the output voltage to undershoot
below ground. If latched FAULT mode is used, a Schottky
diode should be added with its cathode at the output and
its anode at ground to clamp the negative voltage to a safe
level and prevent possible damage to the load and the
output capacitors.
the other hand, voltage breakdown requirements in a
typicalLTC1702Acircuitareprettytame:the7Vmaximum
input voltage limits the VDS and VGS the MOSFETs can see
to safe levels for most devices.
Low RDS(ON)
RDS(ON) calculations are pretty straightforward. RDS(ON) is
the resistance from the drain to the source of the MOSFET
when the gate is fully on. Many MOSFETs have RDS(ON)
specified at 4.5V gate drive—this is the right number to
use in LTC1702A circuits running from a 5V supply. As
current flows through this resistance while the MOSFET is
on, it generates I2R watts of heat, where I is the current
flowing (usually equal to the output current) and R is the
MOSFET RDS(ON). This heat is only generated when the
MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
In some circuits, the OV latch can be a liability. Consider
a circuit where the output voltage at one channel may be
changed on the fly by switching in different feedback
resistors. A downward adjustment of greater than 15%
willfirethefaultlatch,disablingbothsidesoftheLTC1702A
untilthepowerisrecycled.Incircuitssuchasthis,thefault
latch can be disabled by grounding the FAULT pin. The
internal latch will still be set the first time the output
exceeds +15%, but the 10µA current source pull-up will
not be able to pull FAULT high, and the LTC1702A will
ignore the latch and continue normal operation. FAULT
can also be pulled down with external open-collector logic
to restart a fault-latched LTC1702A as an alternative to
recycling the power. Note that this will not reset the
internal latch; if the external pull-down is released, the
LTC1702A will reenter FAULT mode. To reset the latch,
pull both RUN/SS pins low simultaneously or cycle the
input power.
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter—both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost are at a maximum. Lowering
RDS(ON) improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET RDS(ON) becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1702A circuit, allowing the use of small, sur-
face mount MOSFETs without heat sinks.
EXTERNAL COMPONENT SELECTION
POWER MOSFETs
Gate Charge
Getting peak efficiency out of the LTC1702A depends
strongly on the external MOSFETs used. The LTC1702A
requires at least two external MOSFETs per side—more if
one or more of the MOSFETs are paralleled to lower on-
resistance. To work efficiently, these MOSFETs must
exhibit low RDS(ON) at 5V VGS (3.3V VGS if the PVCC input
supplyis3.3V)tominimizeresistivepowerlosswhilethey
are conducting current. They must also have low gate
charge to minimize transition losses during switching. On
Gate charge is amount of charge (essentially, the number
of electrons) that the LTC1702A needs to put into the gate
of an external MOSFET to turn it on. The easiest way to
visualize gate charge is to think of it as a capacitance from
the gate pin of the MOSFET to SW (for QT) or to PGND (for
QB). This capacitance is composed of MOSFET channel
charge,actualparasiticdrain-sourcecapacitanceandMiller-
multipliedgate-draincapacitance,butcanbeapproximated
as a single capacitance from gate to source. Regardless of
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where the charge is going, the fact remains that it all has
to come out of VCC to turn the MOSFET gate on, and when
the MOSFET is turned back off, that charge all ends up at
ground.Inthemeanwhile,ittravelsthroughtheLTC1702A’s
gate drivers, heating them up. More power lost!
MOSFET Gate Series Resistors
Traditional switching regulator designs often include re-
sistorsinserieswiththeexternalMOSFETgatestocontrol
gate rise and fall time, usually to control ringing at the
switching node. In LTC1702A applications, such resistors
prevent the onboard drivers from turning off the external
MOSFETs quickly, causing shoot through currents and
erratic operation when both top and bottom MOSFETs are
on simultaneously. Gate resistors are not recommended
inLTC1702Aapplications. Insomecases, longPCBtraces
can add enough impedance to the gate to hinder turn off.
Keep gate traces as short and wide as practical.
Inthiscase,thepowerislostinlittlebite-sizedchunks,one
chunk per switch per cycle, with the size of the chunk set
bythegatechargeoftheMOSFET. EverytimetheMOSFET
switches, another chunk is lost. Clearly, the faster the
clock runs, the more important gate charge becomes as a
lossterm.Old-fashionedswitchersthatranat20kHzcould
pretty much ignore gate charge as a loss term; in the
550kHz LTC1702A, gate charge loss can be a significant
efficiency penalty. Gate charge loss can be the dominant
loss term at medium load currents, especially with large
MOSFETs. Gate charge loss is also the primary cause of
power dissipation in the LTC1702A itself.
Switch node ringing can be reduced by adding a low value
resistor (usually 5Ω to 10Ω) in series with the BOOST pin.
This will slow TG rise time without affecting MOSFET turn
off, allowing the LTC1702A to keep shoot through current
under control. This resistor will typically improve the
waveform at the switch node but it reduces efficiency and
increases power dissipation in the top MOSFET. Use with
caution.
TG Charge Pump
There’sanothernuanceofMOSFETdrivethattheLTC1702A
needs to get around. The LTC1702A is designed to use N-
channel MOSFETs for both QT and QB, primarily because
N-channel MOSFETs generally cost less and have lower
INPUT SUPPLY
RDS(ON) than similar P-channel MOSFETs. Turning QB on
The BiCMOS process that allows the LTC1702A to include
large MOSFET drivers on-chip also limits the maximum
input voltage to 7V. This limits the practical maximum
input supply to a loosely regulated 5V or 6V rail. The
LTC1702A will operate properly with input supplies down
toabout3V, soatypical3.3Vsupplycanalsobeusedifthe
externalMOSFETsarechosenappropriately(seethePower
MOSFETs section).
is no big deal since the source of QB is attached to PGND;
theLTC1702AjustswitchestheBGpinbetweenPGNDand
VCC. Driving QT is another matter. The source of QT is
connected to SW which rises to VCC when QT is on. To
keep QT on, the LTC1702A must get TG one MOSFET
VGS(ON) above VCC. It does this by utilizing a floating driver
with the negative lead of the driver attached to SW (the
source of QT) and the VCC lead of the driver coming out
separately at BOOST. An external 1µF capacitor CCP con-
nected between SW and BOOST (Figure 2) supplies power
to BOOST when SW is high, and recharges itself through
At the same time, the input supply needs to supply several
amps of current without excessive voltage drop. The input
supply must have regulation adequate to prevent sudden
load changes from causing the LTC1702A input voltage to
dip. In most typical applications where the LTC1702A is
generating a secondary low voltage logic supply, all of
these input conditions are met by the main system logic
supply when fortified with an input bypass capacitor.
DCP when SW is low. This simple charge pump keeps the
TG driver alive even as it swings well above VCC. The value
of the bootstrap capacitor CCP needs to be at least 100
times that of the total input capacitance of the topside
MOSFET(s). For very large external MOSFETs (or multiple
MOSFETs in parallel), CCP may need to be increased over
the 1µF value.
Input Bypass
A typical LTC1702A circuit running from a 5V logic supply
might provide 1.6V at 10A at one of its outputs. 5V to 1.6V
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implies a duty cycle of 32%, which means QT is on 32%
of each switching cycle. During QT’s on-time, the current
drawn from the input equals the load current and during
the rest of the cycle, the current drawn from the input is
near zero. This 0A to 10A, 32% duty cycle pulse train adds
up to 4.7ARMS at the input. At 550kHz, switching cycles
last about 1.8µs—most system logic supplies have no
hope of regulating output current with that kind of speed.
A local input bypass capacitor is required to make up the
difference and prevent the input supply from dropping
drastically when QT kicks on. This capacitor is usually
chosen for RMS ripple current capability and ESR as well
as value.
Calculating RMS Current in CIN
A buck regulator like the LTC1702A draws pulses of
current from the input capacitor during normal opera-
tion. The input capacitor sees this as AC current, and
dissipates power proportional to the RMS value of the
input current waveform. To properly specify the capaci-
tor, we need to know the RMS value of the input current.
Calculating the approximate RMS value of a pulse train
with a fixed duty cycle is straightforward, but the
LTC1702A complicates matters by running two sides
simultaneously and out of phase, creating a complex
waveform at the input.
To calculate the approximate RMS value of the input
current, we first need to calculate the average DC value
with both sides of the LTC1702A operating at maximum
load. Over a single period, the system will spend some
time with one top switch on and the other off, perhaps
some time with both switches on, and perhaps some
time with both switches off. During the time each top
switch is on, the current will equal that side’s full load
output current. When both switches are on, the total
current will be the sum of the two full load currents, and
when both are off, the current is effectively zero. Multiply
each current value by the percentage of the period that
the current condition lasts, and sum the results—this is
the average DC current value.
The input bypass capacitor in an LTC1702A circuit is
common to both channels. Consider our 10A example
case with the other side of the LTC1702A disabled. The
input bypass capacitor gets exercised in three ways: its
ESR must be low enough to keep the initial drop as QT
turns on within reason (100mV or so); its RMS current
capability must be adequate to withstand the 4.6ARMS
ripple current at the input and the capacitance must be
large enough to maintain the input voltage until the input
supply can make up the difference. Generally, a capacitor
that meets the first two parameters will have far more
capacitance than is required to keep capacitance-based
droop under control. In our example, we need 0.01Ω ESR
to keep the input drop under 100mV with a 10A current
step and 4.6ARMS ripple current capacity to avoid over-
heatingthecapacitor.Theserequirementscanbemetwith
multiple low ESR tantalum or electrolytic capacitors in
parallel, or with a large monolithic ceramic capacitor.
As an example, consider a circuit that takes a 5V input
and generates 3.3V at 3A at side 1 and 1.6V at 10A at
side 2. When a cycle starts, TG1 turns on and 3A flows
50%
16% 16% 18%
The two sides of the LTC1702A run off a single master
clock and are wired 180° out of phase with each other to
significantly reduce the total capacitance/ESR needed at
the input. Assuming 100mV of ripple and 10A output
current, we needed an ESR of 0.01Ω and 4.7A ripple
current capability for one side. Now, assume both sides
are running simultaneously with identical loading. If the
two sides switched in phase, all the loading conditions
would double and we’d need enough capacitance for
9.4ARMS and 0.005Ω ESR. With the two sides out of
phase, the input current is 4.8ARMS—barely larger than
the single case (Figure 7)! The peak current deltas are still
only10A, requiringthesame0.01ΩESRrating. Aslongas
13
10
5.2
3
I
AVE
0
0
A
B
C
D
TIME
1702A SB1
Figure SB1. Average Current Calculation
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from CIN (time point A). 50% of the way through, TG2
turns on and the total current is 13A (time point B).
Shortly thereafter, TG1 turns off and the current drops to
10A (time point C). Finally, TG2 turns off and the current
spends a short time at 0 before TG1 turns on again (time
point D).
–2.182 • 0.5 + 7.822 • 0.16 +
(
(
) (
)
IRMS
=
4.822 • 0.16 + –5.182 • 0.18
) (
)
= 4.55ARMS
Ifthecircuitislikelytospendtimewithonesideoperating
and the other side shut down, the RMS current will need
to be calculated for each possible case (side 1 on, side 2
off; side 1 off, side 2 on; both sides on). The capacitor
must be sized to withstand the largest RMS current of the
three—sometimes this occurs with one side shut down!
IAVG = 3A • 0.5 + 13A • 0.16 +
(
) (
)
10A • 0.16 + 0A • 0.18 = 5.18A
(
) (
)
Now we can calculate the RMS current. Using the same
waveform we used to calculate the average DC current,
subtract the average current from each of the DC values.
Square each current term and multiply the squares by the
same period percentages we used to calculate the aver-
age DC current. Sum the results and take the square root.
The result is the approximate RMS current as seen by the
input capacitor with both sides of the LTC1702A at full
load. Actual RMS current will differ due to inductor ripple
current and resistive losses, but this approximate value is
adequate for input capacitor calculation purposes.
Side1only:
IAVE1 = 3A • 0.67 + 0A • 0.33 = 2.01A
(
) (
)
2
IRMS1
=
1 • 0.67 + –22 • 0.33 = 1.42ARMS
(
) (
)
Side 2 only:
IAVE2 = 10A • 0.32 + 0A • 0.68 = 3.2A
(
) (
)
IRMS2
=
6.82 • 0.32 + –3.22 • 0.68
(
) (
)
50%
16% 16% 18%
7.8
4.8
= 4.66ARMS > 4.55ARMS
Consider the case where both sides are operating at the
same load, with a 50% duty cycle at each side. The RMS
current with both sides running is near zero, while the
RMS current with one side active is 1/2 the total load
current of that side. The 2-phase, 5V to 2.5V circuit in the
applications section takes advantage of this phenom-
enon, allowingittosupply40Aofoutputcurrentwithonly
120µF of input capacitance (and only 40µF of output
capacitance!).
0
–2.2
–5.2
0
A
B
TIME
C
D
1702A SB2
Figure SB2. AC Current Calculation
the capacitor we chose for the single side application can
support the slightly higher 4.8ARMS current, we can add
the second channel without changing the input capacitor
at all. As a general rule, an input bypass capacitor capable
of supporting the larger output current channel can sup-
port both channels running simultaneously (see the
2-Phase Operation section for more details).
caution here. Generic tantalum capacitors have a destruc-
tive failure mechanism when they are subjected to large
RMScurrents(likethoseseenattheinputof aLTC1702A).
At some random time after they are turned on, they can
blow up for no apparent reason. The capacitor manufac-
turers are aware of this and sell special “surge tested”
tantalum capacitors specifically designed for use with
switching regulators. When choosing a tantalum input
capacitor, make sure that it is rated to carry the RMS
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Tantalum capacitors are a popular choice as input capaci-
tors for LTC1702A applications, but they deserve a special
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32%
10A
INDUCTOR
Q1 CURRENT, SIDE 1 ONLY
The inductor in a typical LTC1702A circuit is chosen
primarily for value and saturation current. The inductor
value sets the ripple current, which is commonly chosen
at around 40% of the anticipated full load current. Ripple
current is set by:
(FOR 1-PHASE, 2 SIDES:
MULTIPLY CURRENT BY 2)
68%
68%
0
32%
6.8A
CURRENT IN C , SIDE 1 ONLY
IN
RMS
I
= 4.66A
, (1-PHASE,
CIN
2 SIDES: I = 9.3A
)
0
CIN
RMS
–3.2A
tON(Q2)
V
OUT
(
)
IRIPPLE
=
32% 18% 32% 18%
32% 18% 32% 18%
L
10A
0
Q11 CURRENT
Q21 CURRENT
BOTH SIDES EQUAL LOAD
2-PHASE OPERATION
In our hypothetical 1.6V, 10A example, we'd set the ripple
current to 40% of 10A or 4A, and the inductor value would
be:
3.6A
0
CURRENT IN C
,
IN
BOTH SIDES EQUAL LOAD
tON(Q2)
V
1.2µs 1.6V
(
)
(
)(
)
= 0.5µH
OUT
I
= 4.8A
CIN
RMS
L =
=
1702A F07
–6.4A
IRIPPLE
4A
1.6V
5V
⎛
⎝
⎞
⎟
⎠
Figure 7. RMS Input Current
with tON(Q2) = 1−
/550kHz = 1.2µs
⎜
current that the LTC1702A will draw. If the data sheet
doesn’t give an RMS current rating, chances are the
capacitor isn’t surge tested. Don’t use it!
The inductor must not saturate at the expected peak
current. In this case, if the current limit was set to 15A, the
inductor should be rated to withstand 15A + 1/2 IRIPPLE
or 17A without saturating.
,
OUTPUT BYPASS CAPACITOR
The output bypass capacitor has quite different require-
ments from the input capacitor. The ripple current at the
output of a buck regulator like the LTC1702A is much
lower than at the input, due to the fact that the inductor
current is constantly flowing at the output whenever the
LTC1702A is operating in continuous mode. The primary
concern at the output is capacitor ESR. Fast load current
transitions at the output will appear as voltage across the
ESRoftheoutputbypasscapacitoruntilthefeedbackloop
intheLTC1702Acanchangetheinductorcurrenttomatch
the new load current value. This ESR step at the output is
often the single largest budget item in the load regulation
calculation. As an example, our hypothetical 1.6V, 10A
switcher with a 0.01Ω ESR output capacitor would expe-
rience a 100mV step at the output with a 0 to 10A load
step—a 6.3% output change!
FEEDBACK LOOP/COMPENSATION1
Feedback Loop Types
In a typical LTC1702A circuit, the feedback loop consists
of the modulator, the external inductor and output capaci-
tor, and the feedback amplifier and its compensation
network. Allofthesecomponentsaffectloopbehaviorand
need to be accounted for in the loop compensation. The
modulator consists of the internal PWM generator, the
output MOSFET drivers and the external MOSFETs them-
selves. From a feedback loop point of view, it looks like a
linear voltage transfer function from COMP to SW and has
a gain roughly equal to the input voltage. It has fairly
benign AC behavior at typical loop compensation frequen-
cies with significant phase shift appearing at half the
switching frequency.
Usually the solution is to parallel several capacitors at the
output. For example, to keep the transient response inside
of 3% with the previous design, we’d need an output ESR
better than 0.0048Ω. This can be met with three 0.014Ω,
470µF low ESR tantalum capacitors in parallel.
Theexternalinductor/outputcapacitorcombinationmakes
a more significant contribution to loop behavior. These
components cause a second order LC roll-off at the
1The information in this section is based on the paper “The K Factor: A New Mathematical Tool for
Stability Analysis and Synthesis” by H. Dean Venable, Venable Industries, Inc. For complete paper,
see “Reference Reading #4” at www.linear-tech.com.
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output, with the attendant 180° phase shift. This roll-off is
what filters the PWM waveform, resulting in the desired
DC output voltage, but the phase shift complicates the
loop compensation if the gain is still higher than unity at
the pole frequency. Eventually (usually well above the LC
pole frequency), the reactance of the output capacitor will
approach its ESR, and the roll-off due to the capacitor will
stop, leaving 6dB/octave and 90° of phase shift (Figure 8).
So far, the AC response of the loop is pretty well out of the
user’scontrol.Themodulatorisafundamentalpieceofthe
LTC1702A design, and the external L and C are usually
chosen based on the regulation and load current require-
ments without considering the AC loop response. The
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and some-
thing less than 360° phase shift at the point that the loop
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 9). This “type 1”
configuration is stable but transient response will be less
than exceptional if the LC pole is at a low frequency.
GAIN
(dB)
PHASE
(DEG)
GAIN
A
V
–12dB/OCT
0
0
Figure 10 shows an improved “type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of
phase shift. This allows the loop to remain stable with 90°
more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
–90
PHASE
–180
–6dB/OCT
1702A F08
C2
Figure 8. Transfer Function of Buck Modulator
C1
R2
C1
R1
–
+
IN
R1
OUT
–
+
IN
R
B
OUT
R
B
1702A F10a
V
REF
1702A F09a
V
REF
Figure 9a. Type 1 Amplifier Schematic Diagram
Figure 10a. Type 2 Amplifier Schematic Diagram
GAIN
(dB)
PHASE
(DEG)
GAIN
(dB)
PHASE
(DEG)
–6dB/OCT
GAIN
GAIN
0
0
0
0
–6dB/OCT
–6dB/OCT
–90
–180
–90
–180
PHASE
PHASE
–270
–270
1702A F10b
1702A F09b
Figure 9b. Type 1 Amplifier Transfer Function
Figure 10b. Type 2 Amplifier Transfer Function
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tors need type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
foranextendedfrequencyrange. LTC1702Acircuitsusing
conventional switching grade electrolytic output capaci-
tors can often get acceptable phase margin with type 2
compensation.
Feedback Component Selection
Selecting the R and C values for a typical type 2 or type 3
loopisanontrivialtask.Theapplicationsshowninthisdata
sheet show typical values, optimized for the power com-
ponentsshown.Theyshouldgiveacceptableperformance
with similar power components, but can be way off if even
one major power component is changed significantly.
Applicationsthatrequireoptimizedtransientresponsewill
need to recalculate the compensation values specifically
forthecircuitinquestion.Theunderlyingmathematicsare
complex, but the component values can be calculated in a
straightforward manner if we know the gain and phase of
the modulator at the crossover frequency.
“Type 3” loops (Figure 11) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
wellabovetheinitialLCroll-off. Aswithatype2circuit, the
loop should cross through 0dB in the middle of the phase
bump to maximize phase margin. Many LTC1702A cir-
cuits using low ESR tantalum or OS-CON output capaci-
C2
Modulator gain and phase can be measured directly from
a breadboard, or can be simulated if the appropriate
parasitic values are known. Measurement will give more
accurateresults,butsimulationcanoftengetcloseenough
to give a working system. To measure the modulator gain
andphasedirectly,wireupabreadboardwithanLTC1702A
and the actual MOSFETs, inductor, and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
the LTC1702A, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple type 1 loop, with a 10k resistor from
C3
R3
C1
R2
R1
–
+
IN
OUT
R
B
1702A F11a
V
REF
Figure 11a. Type 3 Amplifier Schematic Diagram
V
OUT to FB and a 0.1µF feedback capacitor from COMP to
FB. Choose the bias resistor (RB) as required to set the
desired output voltage. Disconnect RB from ground and
connect it to a signal generator or to the source output of
a network analyzer (Figure 12) to inject a test signal into
the loop. Measure the gain and phase from the COMP pin
to the output node at the positive terminal of the output
capacitor. Make sure the analyzer’s input is AC coupled so
that the DC voltages present at both the COMP and VOUT
nodes don’t corrupt the measurements or damage the
analyzer.
GAIN
(dB)
PHASE
(DEG)
–6dB/OCT
+6dB/OCT
–6dB/OCT
GAIN
0
0
–90
–180
PHASE
–270
1702A F11b
Figure 11B. Type 3 Amplifier Transfer Function
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5V
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 8. Choose the crossover frequency in the rising
or flat parts of the phase curve, beyond the external LC
poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be –GAIN to make the loop gain 0dB at this
frequency.Nowcalculatetheneededphaseboost,assum-
ing 60° as a target phase margin:
+
10Ω MBR0530T
C
IN
+
10µF
V
PV
CC
CC
BOOST2
1µF
QT
QB
TG
L
EXT
1/2 LTC1702A
V
V
COMP
TO
OUT
TO
COMP
SW
0.1µF
ANALYZER
ANALYZER
+
FB
BG
C
OUT
NC
RUN/SS
FCB
R
B
10k
FAULT
PGND
AC
SOURCE
FROM
SGND
BOOST = –(PHASE + 30°)
ANALYZER
1702A F12
If the required BOOST is less than 60°, a type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require type 3
loops for satisfactory performance.
Figure 12. Modulator Gain/Phase Measurement Set-Up
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and gener-
ate an AC plot of V(VOUT)/V(COMP) in dB and phase of
V(OUT) in degrees. Refer to your SPICE manual for details
of how to generate this plot.
Finally, choose a convenient resistor value for R1 (10k is
usuallyagoodvalue). Nowcalculatetheremainingvalues:
(K is a constant used in the calculations)
ƒ = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in absolute
gain)
*1702A modulator gain/phase
* 2001 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other SPICE
simulators
©
Type 2 Loop:
⎛
⎞
BOOST
2
1
K = Tan
+ 45°
*MOSFETs
⎜
⎟
⎝
⎠
rfet mod sw 0.02
;MOSFET rdson
C2 =
*inductor
2πƒGKR1
lext sw out1 1u
rl out1 out 0.005
;inductor value
;inductor series R
C1= C2 K2 – 1
(
)
*output cap
K
cout out out2 1000u
resr out2 0 0.01
;capacitor value
;capacitor ESR
R2 =
RB =
2πƒC1
VREF R1
*1702A internals
emod mod 0 comp 0 5
vstim comp 0 0 ac 1
.ac dec 100 1k 1meg
.probe
( )
;3.3 for 3.3V supply
;ac stimulus
VOUT – VREF
.end
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chosenproperly.TheCFtermisanapproximatefactorthat
corrects for errors caused by ringing on the switch node
(illustrated in Figure 6). This correction factor will change
depending on the layout and the components used, but
–10mV is usually a good starting point. However, to
provide adequate margin and to accommodate for offsets
and external variations, it is recommended that VPROG be
calculated with CF = –10 ± 50mV. VPROG is then pro-
grammed at the IMAX pin using the internal 10µA pull-up
and an external resistor:
Type 3 Loop:
⎛
⎞
BOOST
4
K = Tan2
C2 =
+ 45°
⎜
⎟
⎝
1
⎠
2πƒGR1
C1= C2 K – 1
(
)
K
R2 =
R3 =
RILIM = VPROG/10µA
2πƒC1
R1
TheresultingvalueofRILIM shouldbecheckedinanactual
circuit to ensure that the ILIM circuit kicks in as expected.
MOSFET RDS(ON) specs are like horsepower ratings in
automobiles, and should be taken with a grain of salt.
Circuits that use very low values for RIMAX (<10k) should
be checked carefully, since small changes in RIMAX can
cause large ILIM changes. If VPROG is set too low, the
LTC1702A may fail to start up.
K – 1
(
)
1
C3 =
RB =
2πƒ K R3
VREF R1
( )
VOUT – VREF
Accuracy Trade-Offs
The VDS sensing scheme used in the LTC1702A is not
particularly accurate, primarily due to uncertainty in the
RDS(ON) from MOSFET to MOSFET. A second error term
arises from the ringing present at the SW pin, which
causes the VDS to look larger than (ILOAD)(RDS(ON)) at the
beginning of QB’s on-time. These inaccuracies do not
preventtheLTC1702Acurrentlimitcircuitfromprotecting
itself and the load from damaging overcurrent conditions,
but they do prevent the user from setting the current limit
to a tight tolerance if more than one copy of the circuit is
being built. The 50% factor in the current setting equation
above reflects the margin necessary to ensure that the
circuitwillstayoutofcurrentlimitatthemaximumnormal
load, even with a hot MOSFET that is running quite a bit
higher than its RDS(ON) spec.
CURRENT LIMIT PROGRAMMING
ProgrammingthecurrentlimitontheLTC1702Aisstraight-
forward. The IMAX pin sets the current limit by setting the
maximum allowable voltage drop across QB (the bottom
MOSFET) before the current limit circuit engages. The
voltage across QB is set by its on-resistance and the
current flowing in the inductor, which is the same as the
output current. The LTC1702A current limit circuit inverts
the voltage at IMAX before comparing it with the negative
voltage across QB, allowing the current limit to be set with
a positive voltage.
Tosetthecurrentlimit,calculatetheexpectedvoltagedrop
across QB at the maximum desired current:
VPROG = I
R
(
+ CF
(
)
)
LIM
DS(ON)
FCB OPERATION/SECONDARY WINDINGS
ILIM should be chosen to be quite a bit higher than the
expected operating current, to allow for MOSFET RDS(ON)
changes with temperature. Setting ILIM to 150% of the
maximumnormaloperatingcurrentisusuallysafeandwill
adequately protect the power components if they are
The FCB pin can be used in conjunction with a secondary
winding on one side of the LTC1702A to generate a third
regulated voltage output. This output can be directly
regulated at the FCB pin. In theory, a fourth output could
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V
IN
POWER GOOD/FAULT FLAGS
V
OUT(AUX)
+
The PGOOD pins report the status of the output voltage at
their respective outputs. Each is an open-drain output that
pulls low until the FB pin rises to (VREF – 5%), indicating
that the output voltage has risen to within 5% of the
programmed output voltage. Each PGOOD pin can inter-
facedirectlytostandardlogicinputsifanappropriatepull-
up resistor is added, or the two pins can be tied together
with a single pull-up to give a “both good” signal. Each
PGOOD pin includes an internal 100µs delay to prevent
glitches at the output from indicating false PGOOD
signals.
C
IN
+
+
C
C
QT
TG
LTC1702A
BG
OUT(AUX)
V
OUT
QB
FCB
OUT
R
R
FCB1
FCB2
1702A F08
Figure 13. Regulating an Auxiliary Output with the FCB Pin
The FAULT pin is an additional open-drain output that
indicates if one or both of the outputs has exceeded 15%
of its programmed output voltage. FAULT includes an
internal 10µA pull-up to VCC and does not require an
external pull-up to interface to standard logic. FAULT pulls
low in normal operation, and releases when a overvoltage
fault is detected.
be added, either unregulated or with additional external
circuitry at the FCB pin.
The extra auxiliary output is taken from a second winding
on the core of the inductor on one channel, converting it
intoatransformer(Figure13).Theauxiliaryoutputvoltage
is set by the main output voltage and the turns ratio of the
extra winding to the primary winding. Load regulation at
the auxiliary output will be relatively good as long as the
mainoutputisrunningincontinuousmode. Astheloadon
the main channel drops and the LTC1702A switches to
discontinuous or Burst Mode operation, the auxiliary
output will not be able to maintain regulation, especially if
the load at the auxiliary output remains heavy.
When an overvoltage fault occurs, an internal latch sets
and FAULT goes high, disabling the LTC1702A until the
latch is cleared by recycling the power or pulling both
RUN/SS pins low simultaneously. Alternately, the FAULT
pin can be pulled back low externally with an open-
collector/open-drain device or an NFET or NPN, which will
allow the LTC1702A to resume normal operation, but will
not reset the latch. If the pull-down is later removed, the
LTC1702A will latch off again unless the latch is reset by
cycling the power or RUN/SS pins.
To avoid this, the auxiliary output voltage can be divided
downwithaconventionalfeedbackresistorstringwiththe
divided auxiliary output voltage fed back to the FCB pin
(Figure 13). The FCB pin threshold is trimmed to 800mV
with 10mV of hysteresis, allowing fairly precise control of
the auxiliary voltage. If the LTC1702A is in discontinuous
or Burst Mode operation and the auxiliary output voltage
drops, the FCB pin will trip and the LTC1702A will resume
continuous operation regardless of the load on the main
output. The FCB pin removes the requirement that power
must be drawn from the inductor primary in order to
extractpowerfromtheauxiliarywindings. Withtheloopin
continuous mode, the auxiliary outputs may be loaded
withoutregardtotheprimaryload.NotethatiftheLTC1702A
is already running in continuous mode and the auxiliary
output drops due to excessive loading, no additional
action can be taken by the LTC1702A to regulate the
auxiliary output.
NotethatboththePGOODpinsandtheFAULTpinmonitor
the output voltages by watching the FB pins. During
normaloperation, eachFBpinisheldatavirtualgroundby
the feedback amplifier, and changes at the output will not
appear at FB. This is not an issue with a properly designed
circuit, since the virtual ground at FB implies that the
output voltage is under control. If the feedback amplifier
loses control of the output, the virtual ground disappears
and the PGOOD circuit can see any output changes. This
occurs whenever the soft-start or current limit circuits are
active or any time the feedback amplifier output (the
COMP pin) hits a rail or is in slew limit.
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OPTIMIZING PERFORMANCE
either system can generate it from the 3.3V output using
an LDO linear regulator, without the 75% linear efficiency
making much of an impact on total system efficiency.
2-Step Conversion
The LTC1702A is ideally suited for use in 2-step conver-
sion systems. 2-step systems use a primary regulator to
convert the input power source (batteries or AC line
voltage) to an intermediate supply voltage, often 5V. The
LTC1702A then converts the intermediate voltage to the
low voltage, high current supplies required by the system.
Compared to a 1-step converter that converts a high input
voltage directly to a very low output voltage, the 2-step
converter exhibits superior transient response, smaller
component size and equivalent efficiency. Thermal man-
agement and layout complexity are also improved with a
2-step approach.
Clearly, the 5V and 3.3V sections of the two schemes are
equivalent. The 2-step system draws additional power
from the 5V and 3.3V outputs, but the regulation tech-
niques and trade-offs at these outputs are similar. The
difference lies in the way the 1.8V and 1.5V supplies are
generated. For example, the 2-step system converts 3.3V
to 1.5V with a 45% duty cycle. During the QT on-time, the
voltage across the inductor is 1.8V and during the QB on-
time, the voltage is 1.5V, giving roughly symmetrical
transientresponsetopositiveandnegativeloadsteps.The
1.8V maximum voltage across the inductor allows the use
of a small 0.47µH inductor while keeping ripple current
under 4A (40% of the 10A maximum load). By contrast,
the 1-step converter is converting 15V to 1.5V, requiring
just a 10% duty cycle. Inductor voltages are now 13.5V
when QT is on and 1.5V when QB is on, giving vastly
different di/dt values and correspondingly skewed tran-
sient response with positive and negative current steps.
The narrow 10% duty cycle usually requires a lower
switching frequency, which in turn requires a higher value
inductor and larger output capacitor. Parasitic losses due
to the large voltage swing at the source of QT cost
efficiency, eliminating any advantage the 1-step conver-
sion might have had.
A typical notebook computer supply might use a 4-cell Li-
Ion battery pack as an input supply with a 15V nominal
terminalvoltage.Thelogiccircuitsrequire5V/3Aand3.3V/
5A to power system board logic, and 2.5V/0.5A, 1.8V/2A
and 1.5V/10A to power the CPU. A typical 2-step conver-
sion system would use a step-down switcher (perhaps an
LTC1628 or two LTC1625s) to convert 15V to 5V and
another to convert 15V to 3.3V (Figure 14). One channel of
the LTC1702A would generate the 1.5V supply using the
3.3V supply as the input and the other channel would gen-
erate 1.8V using the 5V supply as the input. The corre-
sponding1-stepsystemwouldusefoursimilarstep-down
switchers, each using 15V as the input supply and gener-
ating one of the four output voltages. Since the 2.5V sup-
ply represents a small fraction of the total output power,
Note that power dissipation in the LTC1702A portion of a
2-step circuit is lower than it would be in a typical 1-step
converter, even in cases where the 1-step converter has
higher total efficiency than the 2-step system. In a typical
microprocessor core supply regulator, for example, the
regulator is usually located right next to the CPU. In a
1-step design, all of the power dissipated by the core
regulator is right there next to the hot CPU, aggravating
thermal management. In a 2-step LTC1702A design, a
significant percentage of the power lost in the core regu-
lation system happens in the 5V or 3.3V supply, which is
usually away from the CPU. The power lost to heat in the
LTC1702Asectionofthesystemisrelativelylow,minimiz-
ing the heat near the CPU.
V
BAT
15V
5V/3A
1.8V/2A
1.5V/10A
LTC1628*
LTC1702A
LDO
3.3V/5A
2.5V/0.5A
*OR TWO LTC1625s
1702A F14
Figure 14. 2-Step Conversion Block Diagram
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2-Step Efficiency Calculation
Maximizing High Load Current Efficiency
Calculating the efficiency of a 2-step converter system
involves some subtleties. Simply multiplying the effi-
ciency of the primary 5V or 3.3V supply by the efficiency
of the 1.8V or 1.5V supply underestimates the actual
efficiency, since a significant fraction of the total power is
drawn from the 3.3V and 5V rails in a typical system. The
correct way to calculate system efficiency is to calculate
the power lost in each stage of the converter, and divide
the total output power from all outputs by the sum of the
output power plus the power lost:
Efficiency at high load currents (when the LTC1702A is
operating in continuous mode) is primarily controlled by
the resistance of the components in the power path (QT,
QB, LEXT) and power lost in the gate drive circuits due to
MOSFET gate charge. Maximizing efficiency in this region
of operation is as simple as minimizing these terms.
The behavior of the load over time affects the efficiency
strategy. Parasitic resistances in the MOSFETs and the
inductor set the maximum output current the circuit can
supply without burning up. A typical efficiency curve
(Figure 15) shows that peak efficiency occurs near 30% of
this maximum current. If the load current will vary around
theefficiencypeakandwillspendrelativelylittletimeatthe
maximumload, choosingcomponentssothattheaverage
load is at the efficiency peak is a good idea. This puts the
maximum load well beyond the efficiency peak, but usu-
ally gives the greatest system efficiency over time, which
translates to the longest run time in a battery-powered
system. If the load is expected to be relatively constant at
the maximum level, the components should be chosen so
that this load lands at the peak efficiency point, well below
the maximum possible output of the converter.
Efficiency =
TotalOutputPower
TotalOutputPower+ TotalPowerLost
100%
(
)
In our example 2-step system, the total output power is:
Total output power =
15W + 16.5W + 1.25W + 3.6W + 15W = 51.35W
corresponding to 5V, 3.3V, 2.5V, 1.8V and 1.5V output
voltages.
Assuming the LTC1702A provides 90% efficiency at each
output, the additional load on the 5V and 3.3V supplies is:
1.5V: 15W/90% = 16.6W/3.3V = 5A from 3.3V
1.8V: 3.6W/90% = 4W/5V = 0.8A from 5V
2.5V: 1.25W/75% = 1.66W/3.3V = 0.5A from 3.3V
100
V
IN
= 5V
V
= 3.3V
OUT
If the 5V and 3.3V supplies are each 94% efficient, the
power lost in each supply is:
V
V
= 2.5V
= 1.6V
OUT
OUT
90
80
70
1.5V: 17.55W – 15W = 2.55W
1.8V: 4.26W – 3.6W = 0.66W
2.5V: 1.77W – 1.25W = 0.52W
3.3V: 17.55W – 16.5W = 1.05W
5V: 15.96W – 15W = 0.96W
0
5
10
15
Total loss = 5.74W
LOAD CURRENT (A)
1702A G01
Total system efficiency =
51.35W/(51.35W + 5.74W) = 90%
Figure 15. Typical LTC1702A Efficiency Curves
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Maximizing Low Load Current Efficiency
offset. This accounts for 1% error at the output with a 5V
input supply. The feedback voltage line regulation spec
addsanadditional0.05%/Vtermthataccountsforchange
in reference output with change in input supply voltage.
With a 5V supply, the errors contributed by the LTC1702A
itself add up to no more than 1% DC error at the output.
Low load current efficiency depends strongly on proper
operation in discontinuous and Burst Mode operations. In
anideallyoptimizedsystem, discontinuousmodereduces
conduction losses but not switching losses, since each
power MOSFET still switches on and off once per cycle. In
a typical system, there is additional loss in discontinuous
mode due to a small amount of residual current left in the
inductor when QB turns off. This current gets dissipated
acrossthebodydiodeofeitherQTorQB. SomeLTC1702A
systems lose as much to body diode conduction as they
save in MOSFET conduction. The real efficiency benefit of
discontinuousmodehappenswhenBurstModeoperation
is invoked. At typical power levels, when Burst Mode
operation is activated, gate drive is the dominant loss
term. Burst Mode operation turns off all output switching
for several clock cycles in a row, significantly cutting gate
drive losses. As the load current in Burst Mode operation
falls toward zero, the current drawn by the circuit falls to
the LTC1702A’s background quiescent level—about 3mA
per channel.
The output voltage setting resistors (R1 and RB in
Figure 3) are the other major contributor to DC error. At a
typical1.xVoutputvoltage, theresistorsareofroughlythe
same value, which tends to halve their error terms, im-
proving accuracy. Still, using 1% resistors for R1 and RB
will add 1% to the total output error budget, equal to that
of all errors due to the LTC1702A combined. Using 0.1%
resistors in just those two positions can nearly halve the
DC output error for very little additional cost.
Load Regulation
Load regulation is affected by feedback voltage, feedback
amplifier gain and external ground drops in the feedback
path. Feedback voltage is covered above and is within 1%
over temperature. A full-range load step might require a
10% duty cycle change to keep the output constant,
requiring the COMP pin to move about 100mV. With
amplifier gain at 85dB, this adds up to only a 10µV shift at
FB, negligible compared to the reference accuracy terms.
Tomaximizelowloadefficiency, makesuretheLTC1702A
is allowed to enter discontinuous and Burst Mode opera-
tion as cleanly as possible. FCB must be above its 0.8V
threshold. Minimize ringing at the SW node so that the
discontinuous comparator leaves as little residual current
in the inductor as possible when QB turns off. It helps to
connect the SW pin of the LTC1702A as close to the drain
of QB as possible. An RC snubber network can also be
added from SW to PGND.
External ground drops aren’t so negligible. The LTC1702A
can sense the positive end of the output voltage by
attaching the feedback resistor directly at the load, but it
cannot do the same with the ground lead. Just 0.001Ω of
resistanceinthegroundleadat10Aloadwillcausea10mV
error in the output voltage—as much as all the other DC
errors put together. Proper layout becomes essential to
achieving optimum load regulation from the LTC1702A.
See the Layout/Troubleshooting section for more infor-
mation. A properly laid out LTC1702A circuit should move
less than a millivolt at the output from zero to full load.
REGULATION OVER COMPONENT TOLERANCE/
TEMPERATURE
DC Regulation Accuracy
The LTC1702A initial DC output accuracy depends mainly
on internal reference accuracy, op amp offset and external
resistor accuracy. Two LTC1702A specs come into play:
feedbackvoltageandfeedbackvoltagelineregulation. The
feedback voltage spec is 800mV ± 8mV over the full
temperature range, and is specified at the FB pin, which
encompasses both reference accuracy and any op amp
TRANSIENT RESPONSE
Transient response is the other half of the regulation
equation. The LTC1702A can keep the DC output voltage
constant to within 1% when averaged over hundreds of
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cycles. Over just a few cycles, however, the external
components conspire to limit the speed that the output
can move. Consider our typical 5V to 1.6V circuit, sub-
jected to a 1A to 5A load transient. Initially, the loop is in
regulation and the DC current in the output capacitor is
zero. Suddenly, an extra 4A start flowing out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A)(CESR)voltage step at
the output; with a typical 0.015Ω output capacitor ESR,
thisisa60mVstepattheoutput,or3.8%(fora1.6Voutput
voltage).
Note that the output voltage will stop dropping before the
inductor current reaches this new output current level.
Recall that any practical output capacitor looks like a pure
capacitance in series with some amount of ESR. When a
load transient hits, virtually all of the initial voltage drop at
the output is due to IR drop across the ESR. The output
capacitance begins to discharge at the same time and
continuesuntiltheinductorcurrentrisestomatchthenew
output current level.
The output voltage, however, will turn around and start
heading the right way before this happens. The next time
the top MOSFET turns on, the inductor current will begin
increasing linearly. This increasing current flows almost
entirely into the capacitor, going through the ESR as it
does so (Figure 16). Positive di/dt in the inductor causes
positive dv/dt in the ESR, regardless of what the “pure”
capacitance is doing. The output voltage will turn around
when the positive dv/dt across the ESR exceeds the
negativedv/dtacrossthepurecapacitance.Iftheexpected
load step (∆I) is known, an optimum inductor value can be
chosen:
Very quickly, the feedback loop will realize that something
has changed and will move at the bandwidth allowed by
the external compensation network towards a new duty
cycle. If the bandwidth is set to 50kHz, the COMP pin will
get to 60% of the way to 90% duty cycle in 3µs. Now the
inductor is seeing 3.5V across itself for a large portion of
the cycle, and its current will increase from 1A at a rate set
by di/dt = V/L. If the inductor value is 0.5µH, the di/dt will
be 3.5V/0.5µH or 7A/µs. Sometime in the next few micro-
secondsaftertheswitchcyclebegins,theinductorcurrent
will have risen to the 5A level of the load current and the
output capacitor will stop losing charge.
ESR
∆I
L ≤ V – VOUT •C •
IN
I
L
I
OUT
I
L
I
OUT
V
ESR
V
ESR
V
CAP
V
V
CAP
I
L
OUT
V
V
OUT
SW
V
OUT
L
V
OUT(NOMINAL)
+
V
ESR
–
C
I
OUT
OUT
+
V
CAP
1702A F16b
–
TRANSIENT
HITS
I
L
> I
OUT
TIME
1702A F16a
V
OUT
TURNS
AROUND
Figure 16a. Capacitor Parasitics
Affecting Transient Recovery
Figure 16b. Transient Recovery Curves
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MakingLsmallerthanthisoptimumvalueyieldslittleorno
improvement in transient response. As the output voltage
recovers, the inductor current will briefly rise above the
leveloftheoutputcurrenttoreplenishthechargelostfrom
the output capacitor. With a properly compensated loop,
the entire recovery time will be inside of 10µs.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC1702A to
recoveraftertheoutputvoltagehasdroppedduetooutput
capacitor ESR. Optimizing loop compensation entails
maintaining the highest possible loop bandwidth while
ensuring loop stability. The Feedback Component Selec-
tionsectiondescribesindetailhowtodesignanoptimized
feedback loop, appropriate for most LTC1702A systems.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirelycontrolledbytheESRofthecapacitorandamounts
to most of the total voltage drop. To minimize this drop,
reduce the ESR as much as possible by choosing low ESR
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
Voltage Positioning
If the load transients consist primarily of load steps from
near zero load to full load and back, the transient response
can be traded off against DC regulation performance by
using a technique known as “voltage positioning.” The
goal is to intentionally compromise the DC regulation loop
such that the output rides near the maximum allowable
value (often +5%) with no load and near the minimum
allowable value at maximum load. With the load at zero,
any transient that comes along will be a current increase
whichwillcausetheoutputvoltagetofall. Sincetheoutput
voltage is initially at a high value, it can fall further before
V
IN
MAXIMUM
+5%
NOM
–5%
ALLOWABLE
V
OUT
TRANSIENT
LTC1702A
FB
V
OUT
MAX
0
LOAD
CURRENT
1702 F17a
1702A F17b
Figure 17a. Standard Regulator
Figure 17b. Standard Regulator—Transient Response
V
IN
+5%
NOM
–5%
MAXIMUM
ALLOWABLE
TRANSIENT
V
OUT
≈2× FIGURE 17b
LTC1702A
FB
V
OUT
MAX
0
LOAD
CURRENT
1702A F17c
1702A F17d
Figure 17c. Voltage Positioning Regulator
Figure 17d. Positioning Regulator—Transient Response
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itgoesoutofspec.Similarly,atfullload,theoutputcurrent
can only decrease, causing a positive shift in the output
voltage; the initial low value allows it to rise further before
the spec is exceeded. The primary benefit of voltage
positioning is it increases the allowable ESR of the output
capacitors, saving cost. An additional bonus is that at
maximum load, the output voltage is near the minimum
allowable, decreasing the power dissipated in the load.
this measurement with the 20MHz bandwidth limit on the
oscilloscopeturnedontolimithighfrequencynoise. Note
thatmicroprocessormanufacturerstypicallyspecifyripple
≤20MHz, as energy above 20MHz is generally radiated
and not conducted and will not affect the load even if it
appears at the output capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test, and switch it on and off while
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC1702A and the transient generator
must be minimized.
Implementing voltage positioning is as simple as creating
an intentional resistance in the output path to generate the
required voltage drop. This resistance can be a low value
resistor, a length of PCB trace, or even the parasitic
resistance of the inductor if an appropriate filter is used. If
the LTC1702A senses the output voltage upstream from
the resistance (Figure 17), the output voltage will move
with load as I • R, where I is the load current and R is the
value of the resistance. If the feedback network is then
reset to regulate near the upper edge of the specified
tolerance, the output voltage will ride high when ILOAD is
low and will ride low when ILOAD is high. Compared to a
traditional regulator, a voltage positioning regulator can
theoretically stand as much as twice the ESR drop across
the output capacitor while maintaining output voltage
regulation.Thismeanssmaller,cheaperoutputcapacitors
can be used while keeping the output voltage within
acceptable limits.
Figure 18 shows an example of a simple transient genera-
tor. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
togetthedesiredvalue.Thisgivesanoninductiveresistive
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC1702A
circuits. SoldertheMOSFETandtheresistor(s)ascloseto
the output of the LTC1702A circuit as possible and set up
thesignalgeneratortopulseata100Hzratewitha5%duty
cycle. This pulses the LTC1702A with 500µs transients
10ms apart, adequate for viewing the entire transient
recovery time for both positive and negative transitions
while keeping the load resistor cool.
Measurement Techniques
Measuring transient response presents a challenge in
two respects: obtaining an accurate measurement and
generating a suitable transient to use to test the circuit.
Output measurements should be taken with a scope
probedirectly across the output capacitor. Proper high
frequencyprobingtechniquesshouldbeused. Inparticu-
lar, don’t use the 6" ground lead that comes with the
probe! Use an adapter that fits on the tip of the probe and
has a short ground clip to ensure that inductance in the
ground path doesn’t cause a bigger spike than the tran-
sient signal being measured. Conveniently, the typical
probe tip ground clip is spaced just right to span the leads
of a typical output capacitor. In general, it is best to take
LTC1702A
V
OUT
R
LOAD
LOCATE CLOSE
TO THE OUTPUT
IRFZ44 OR
EQUIVALENT
PULSE
GENERATOR
50Ω
1702A F18
0V TO 10V
100Hz, 5%
DUTY CYCLE
Figure 18. Transient Load Generator
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31
LTC1702A
U
W U U
APPLICATIONS INFORMATION
FAULT BEHAVIOR
never programmed to step down by more than 15% in any
single step. The safest strategy is to step the output down
by 10% or less at a time and wait for the output to settle
to the new value before taking subsequent steps.
Changing the Output Voltage on the Fly
Someapplicationsuseaswitchingschemeattachedtothe
feedback resistors to allow the system to adjust the
LTC1702A output voltage. The voltage can be changed on
the fly if desired, but care must be taken to avoid tripping
theovervoltagefaultcircuit. Steppingthevoltageupwards
abruptly is safe, but stepping down quickly by more than
15% can leave the system in a state where the output
voltageisstillattheoldhigherlevel, butthefeedbacknode
is set to expect a new, substantially lower voltage. If this
condition persists for more than 10µs, the overvoltage
fault circuitry will fire and latch off the LTC1702A.
VID Applications
Certain microprocessors specify a set of codes that corre-
spond to power supply voltages required from the regula-
torsystem. Ifthesecodesarechangedonthefly, thesame
caveats as above apply. In addition, the switching matrix
that programs the output voltage may vary its resistance
significantly over the entire span of output voltages,
potentiallychangingtheloopcompensationifthecircuitis
not designed properly. With a typical type 3 feedback loop
(Figure3), makesurethattheRB resistorismodifiedtoset
the output voltage. The R1 resistor must stay constant to
ensure that the loop compensation is not affected.
The simplest solution is to disable the fault circuit by
grounding the FAULT pin. Systems that must keep the
fault circuit active should ensure that the output voltage is
U
TYPICAL APPLICATIONS
3.3V , 2.5V/1.8V Output Power Supply
IN
V
IN
3.3V
D1, D2: MOTOROLA MBR0520LT1
D3: MOTOROLA MBRS320T3
+
C1
470µF
×2
± 5%
R1
10Ω
D2
C4
D1
C1: KEMET T510X477M006AS
10µF
C12, C20: PANASONIC EEFUE0G181R
L1: SUMIDA CEP1254712-T007
L2: SUMIDA CDRH744734-JPS023
Q1A, Q1B, Q2A, Q2B: SILICONIX Si9804
Q3, Q4: 1/2 SILICONIX Si4966
C2
1µF
C5
1µF
R8
25.5k
C6
1µF
C8
1µF
PV
CC
I
MAX2
BOOST1 BOOST2
C3
1µF
BG1
TG1
SW1
BG2
TG2
Q2A
Q1A
L1
L2
Q2B
Q1B
Q3
0.68µH
1µH
V
V
2.5V
5A
OUT2
OUT1
1.8V
SW2
LTC1702A
R2 28.7k
12A
D3
Q4
+
I
PGND
+
C12
MAX1
R10
2.4k
C20
180µF
R3
4.3k
180µF
PGOOD1 PGOOD2
FCB FAULT
RUN/SS RUN/SS2
×3
C21
1µF
R12
R4
C11
820pF
C19
1000pF
C15
10k
10.7k
1%
C16 1µF
C7 1µF
1µF
1%
GND
GND
V
IN
10k
V
R13
4.99k
1%
IN
R5
COMP2
FB2
COMP1
SGND
FB1
8.06k
10k
1%
PGOOD2
FAULT
PGOOD1
V
CC
R9 27k
R7 68k
C17
100pF
C18
1000pF
C9
20pF
C10
100pF
1702A TA02
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32
LTC1702A
U
TYPICAL APPLICATIONS
1702afa
33
LTC1702A
U
TYPICAL APPLICATIONS
1702afa
34
LTC1702A
U
PACKAGE DESCRIPTION
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1702afa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
35
LTC1702A
TYPICAL APPLICATION
U
Low Cost Dual Supply with 2.5V Keepalive
V
IN
IN OUT
LT1761
5V
+
±10%
1µF
10Ω
C
IN
16.2k
0.1%
GND ADJ
MBR0530T
+
4.75k
0.1%
10µF
10k
V
CC
PV
CC
0.1%
16.9k
0.1%
FB2
BOOST2
TG2
330pF
56pF
68k
1µF
QT2
V
L2
OUT2
COMP2
2.5V/7A
SW2
2.45V/100mA
STANDBY
+
RUN/SS2
RUN/SS1
QB2
BG2
1k
1k
C
36.5k
OUT2
QSS1
I
MAX2
FAULT
0.1µF
QSS2
STBY/ON
MBR0530T
1µF
LTC1702A
BOOST1
QT1B
QB1B
FB1
220pF
TG1
SW1
BG1
QT1A
QB1A
20k
1%
L1
39pF
56k
V
OUT1
COMP1
FCB
1.8V
20A
+
C
OUT1
16k
1%
15k
I
MAX1
PGND
SGND
1702A TA04
QSS1, QSS2: MOTOROLA MMBT3904LT1
QT1A, QT1B, QB1A, QB1B: FAIRCHILD FDS6670A
QT2, QB2: 1/2 SILICONIX Si4966
C
C
C
= SANYO 10MV1200GX (6 IN PARALLEL)
IN
= SANYO 6MV1500GX (8 IN PARALLEL)
= SANYO 6MV1500GX (3 IN PARALLEL)
OUT1
OUT2
L1: 1µH SUMIDA CEP125-1R0MC-H
L2: 2.2µH COILTRONICS UP2B-2R2
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC1530
High Power Synchronous Step-Down Controller
No R
TM Current Mode Synchronous Step-Down Controller
SO-8 with Current Limit. No R
Required
SENSE
LTC1625/
LTC1778
Above 95% Efficiency, Needs No R
Fits SO-8 Footprint
, 16-Lead SSOP Package
SENSE
SENSE
LTC1628
LTC1703
Dual High Efficiency 2-Phase Synchronous Step-Down Controller Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V ≤ V ≤ 36V
IN
Dual 550kHz Synchronous 2-Phase Switching Regulator Controller LTC1702 with 5-Bit Mobile VID for Mobile Pentium® Processor
with Mobile VID
Systems
LTC1706-XX
VID Voltage Programmer
Adds 5-Bit Mobile VID to 0.8V Referenced Switching
Regulators
LTC1709
LTC1736
LTC1873
LTC1876
2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controller
Current Mode, V to 36V, I
Up to 42A
IN
OUT
Synchronous Step-Down Controller with 5-Bit Mobile VID Control Fault Protection, PowerGood, 3.5V to 36V Input, Current Mode
Dual Synchronous Switching Regulator with 5-Bit Desktop VID 1.3V to 3.5V Programmable Core Output Plus I/O Output
No Auxiliary 5V Supply Required, 2.5V ≤ V ≤ 36V, 0.85V ≤ V
2.5V ≤ V , High Power, 2-Phase, Dual Output, Synchronous
,
IN
IN
OUT
Step-Down Controller
I
Up to 20A
OUT
LTC1929
2-Phase, Synchronous High Efficiency Converter
Current Mode Ensures Accurate Current Sensing,
Up to 36V, I Up to 40A
V
IN
OUT
No R
is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
SENSE
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LT 0306 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
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