LTC1642IGN#TRPBF [Linear]
LTC1642 - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC1642IGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1642 - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 控制器 |
| 文件： | 总12页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fina l Ele c tric a l Sp e c ific a tio ns
LTC1642
Ho t Swa p Co ntro lle r
Ma y 1999
U
DESCRIPTIO
FEATURES
■
Single Channel Positive NFET Driver
Programmable Undervoltage and Overvoltage
Protection
Foldback Current Limit
Adjustable Current Limit Time-Out
Latch Off or Automatic Retry on Current Fault
Driver for SCR Crowbar on Overvoltage
Programmable Reset Timer
The LTC®1642 is a 16-pin Hot SwapTM controller that
allows a board to be safely inserted and removed from a
live backplane. Using an external N-channel pass transis-
tor, the board supply voltage can be ramped up at a
programmable rate. A high side switch driver controls the
N-channel gate for supply voltages ranging from 2.97V to
16.5V.
■
■
■
■
■
■
TheSENSEpinallows foldbacklimitingoftheloadcurrent,
with circuit breaker action after a programmable delay
time. The delay allows the part to power-up in current
limit. The CRWBR output can be used to trigger an SCR
for crowbar load protection after a programmable delay if
the input supply exceeds a programmable voltage. The
RESET output can be used to generate a system reset with
programmable delay when the supply voltage falls below
a programmable voltage. The ON pin can be used to cycle
the board power. The LTC1642 is available in the 16-pin
SSOP package.
■
Reference Output with Uncommitted Comparator
■
V : 2.97V to 16.5V Normal Operation, Protected
CC
Against Surges to 33V.
16-Pin SSOP Package
■
U
APPLICATIO S
■
Hot Board Insertion
Electronic Circuit Breaker
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
R1
0.010Ω
5%
Q1
FDR9410A
12V
AT 2.5A
12V
+
C7
0.1µF
C
R5
110k
1%
LOAD
R2
100Ω
5%
R8
330Ω
5%
R3
107k
1%
C1
0.047µF
LATCH OFF: FLOAT FAULT
16
15
14
AUTOMATIC RETRY: TIE FAULT TO ON
V
SENSE
GATE
CC
5
POWER-GOOD = 11.4V
RESET
10
4
7
COMPOUT
ON
FB
1
Q3
MCR
12DC
UNDERVOLTAGE = 10.8V
CRWBR
LTC1642
D1
R6
12
11
13
–
1N4148
2.87k
6
9
COMP
Q2
2N2222
FAULT
OV
1%
+
COMP
R4
13k
1%
OVERVOLTAGE = 13.2V
REF
R9
220Ω
5%
R7
11.3k
GND
BRK TMR
2
C3
0.33µF
RST TMR
C5
0.1µF
8
3
1%
RESET TIME = 200ms
C2
C6
0.01µF
CURRENT LIMIT TIME = 20ms
0.33µF
1642 TA01
CROWBAR TIME = 90µs
R9 REQUIRED ONLY WITH SENSITIVE GATE SCRs,
NOT NEEDED WITH MCR12
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.
1
LTC1642
W W U W
U W
PACKAGE/ORDER I FOR ATIO
U
ABSOLUTE AXI U RATI GS
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Supply Voltage (V ) .................................–0.3V to 33V
CC
CRWBR
BRK TMR
RST TMR
ON
1
2
3
4
5
6
7
8
16
15 SENSE
V
CC
SENSE Pin ................................... –0.3V to (V + 0.3V)
CC
GATE Pin ...................................................–0.3V to 27V
All Other Pins ..........................................–0.3V to 16.5V
Operating Temperature Range
LTC1642C ............................................... 0°C to 70°C
LTC1642I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LTC1642CGN
LTC1642IGN
14
13
12
11
10
9
GATE
REF
–
RESET
FAULT
FB
COMP
COMP
+
COMPOUT
OV
GND
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 130°C/W
Consult factory for Military grade parts.
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
ON = V
MIN
TYP
1.25
2.73
2.50
230
MAX
3.0
UNITS
mA
V
I
CC
V
CC
Supply Current
●
●
●
CC
V
LKHI
V
Undervoltage Lockout (Low to High)
Undervoltage Lockout (High to Low)
Undervoltage Lockout Hysteresis
CC
2.55
2.35
2.95
2.80
CC
V
LKLO
V
CC
V
V
LKHYST
V
mV
V
V
CC
Operating Voltage Range
2.97
16.5
1.232
15
V
FB
FB Pin Voltage Threshold (FB Falling)
FB Pin Threshold Line Regulation
FB Pin Voltage Threshold Hysteresis
OV Pin Voltage Threshold (OV Rising)
OV Pin Threshold Line Regulation
OV Pin Voltage Theshold Hysteresis
RST TMR Pin Voltage Threshold (RST TMR Rising)
RST TMR Pin Threshold Line Regulation
RST TMR Pin Current
●
●
1.208
1.220
V
∆V
2.97V ≤ V ≤ 16.5V
5
mV
mV
V
FB
CC
V
FBHST
3
1.220
5
V
OV
●
●
1.208
1.200
1.232
15
∆V
2.97V ≤ V ≤ 16.5V
mV
mV
V
OV
CC
V
OVHYST
3
V
RST
●
●
●
1.220
5
1.250
15
∆V
2.97V ≤ V ≤ 16.5V
mV
RST
CC
I
Timer On
–2.5
–2.0
10
–1.5
µA
mA
RST
Timer Off, V
= 1.5V
RSTTMR
V
BRK TMR Pin Voltage Threshold (BRK TMR Rising)
BRK TMR Pin Threshold Line Regulation
BRK TMR Pin Current
●
●
●
1.200
1.220
5
1.250
15
V
BRK
∆V
2.97V ≤ V ≤ 16.5V
mV
BRK
CC
I
Timer On
–30
375
–20
10
–15
µA
mA
BRK
Timer Off, V
= 1.5V
BRKTMR
V
CR
CRWBR Pin Voltage Theshold
CRWBR Pin Threshold Line Regulation
CRWBR Pin Current
●
●
410
4
425
15
mV
mV
∆V
2.97V ≤ V ≤ 16.5V
CC
CR
I
CR
CRWBR On, V
= 0V
●
●
–60
–45
–1500
2.3
–30
–1000
µA
µA
mA
CRWBR
CRWBR On, V
= 2.1V
= 1.5V
CRWBR
CRWBR Off, V
CRWBR
2
LTC1642
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
CC = 5V unless otherwise specified.
V
SYMBOL
PARAMETER
CONDITIONS
= (V – V
MIN
TYP
MAX
UNITS
V
CB
Circuit Breaker Trip Voltage
V
), V = GND
●
●
15
45
25
52.5
36
60
mV
mV
CB
CC
SENSE
FB
V
= (V – V
), V = 1V
CB
CC
SENSE
FB
I
CP
GATE Pin Output Current
Charge Pump On, V
= GND
= 5V
●
–30
–25
10
–20
µA
mA
GATE
Charge Pump Off, V
GATE
∆V
GATE
External N-Channel Gate Drive
V
– V V = 3V
CC, CC
●
●
●
4.5
10
4.5
5.9
11.5
8.5
8.0
14
18
V
V
V
GATE
V
– V
V = 5V
GATE
CC, CC
V
GATE
– V
V = 15V
CC, CC
V
ON Pin Threshold (Low to High)
ON Pin Threshold (High to Low)
ON Pin Hysteresis
1.30
1.20
1.34
1.22
110
1.38
1.26
V
V
ONHI
V
ONLO
●
●
V
ONHYST
mV
V
V
OL
Output Low Voltage
RESET, FAULT, COMPOUT I = 1.5mA
0.4
O
I
Logic Output Pull-Up Current
Reference Output Voltage
Reference Line Regulation
Reference Load Regulation
Reference Short-Circuit Current
Comparator Offset Voltage
Comparator Hysteresis
RESET, FAULT = GND
No Load
–15
1.220
5
µA
V
PU
V
●
●
●
1.208
1.232
15
REF
∆V
2.97V ≤ V ≤ 16.5V, No Load
mV
mV
mA
mV
mV
LNR
CC
∆V
I = 0mA to –1mA, Sourcing Only
O
2.5
7.5
LDR
I
V
REF
= 0V
4.5
RSC
V
V
CM
= V
REF
●
±10
COS
V
V
CM
= V
REF
3
CHYST
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
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PI FU CTIO S
CRWBR (Pin 1): Combination Overvoltage Timer and
Crowbar Circuit Trigger. The timer sets the overvoltage
timeneededtotriggerthecrowbarcircuit.Tousethetimer
connect a capacitor C to ground; the trigger time is
9ms•C(µF). When the timer is off an internal N-channel
when the pin begins sourcing 20µA and the pin voltage
increases at a rate of 20/C(µF) Volts/second. When the pin
reaches 1.23V the GATE pin is pulled to ground and the
FAULT output is asserted until the chip is reset. To allow
the part to remain in current limit indefinitely ground BRK
pulls the pin to ground. The timer is started when the OV TMR.
comparator trips. A 45µA current source is connected
RST TMR (Pin 3): Analog System Timer. To use the timer
from V to the CRWBR pin, and the voltage increases at
CC
connect a capacitor from RST TMR to ground. This timer
sets the delayfrom the ONpingoinghightothe start ofthe
GATEpin’s ramp;italsosets thedelayfromoutputvoltage
good, as sensedbytheFBpin, toRESETgoinghigh. When
the timer is off, an internal N-channel shorts RST TMR to
ground. When the timer is turned on a 2µA current from
a rate of 45/C(µF) Volts/second. When the voltage reaches
410mVthecurrentsourcedbythepinincreases to1.5mA.
Boost this current with an NPN emitter follower to trigger
a crowbar SCR.
BRK TMR (Pin 2): Analog Timer which Limits the Time the
Part Remains In Current Limit. To use the timer connect a
capacitor from BRK TMR to ground. BRK TMR is pulled to
ground until the sense resistor current reaches its limit,
V is connected and the RST TMR pin voltage starts to
CC
ramp up at a rate of 2/C(µF) Volts/second. The timer trips
when the voltage reaches 1.23V.
3
LTC1642
U
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PI FU CTIO S
ON (Pin 4): Control. When ON is low the GATE pin is
grounded and FAULT goes high. The GATE pin voltage
starts ramping up one RST TMR timing cycle after ON
goes high. Pulsing the ON pin low for at least 2µs also
resets the chip when it latches off after a sustained
overvoltageorcurrentlimit. Thethresholdonalowtohigh
transition is 1.34V with 110mV of hysteresis.
COMP– (Pin 12): Uncommitted Comparator’s Inverting
Input.
REF (Pin 13): The Reference Voltage Output, 1.232V
±2%. To ensure stability the pin should be bypassed with
a 0.1µF compensation capacitor. For V = 5V it can
CC
source 1mA.
GATE (Pin 14): High Side Gate Drive for the External
N-Channel.Aninternalchargepumpprovides atleast4.5V
of gate drive, but can only source 25µA. The pin requires
an external series RC network to ground to compensate
the current limit loop, and to limit the maximum voltage
rampwhichis dV/dt(V/s)=25/C(µF).GATEis immediately
pulledtogroundwhentheovervoltagecomparatortrips or
the input supply is below the undervoltage lockout trip
point. During current limit the GATE voltage is adjusted to
RESET (Pin 5): Open Drain Output. RESET is pulled low if
the voltage at the FB pin is below its trip point and goes
high one timing cycle after the FB voltage exceeds its trip
point plus 3mV of hysteresis. RESET has a weak pull-up to
one diode drop below V ; an external resistor can pull the
CC
pin above V .
CC
FAULT (Pin 6): Open Drain Output. FAULT is pulled low
when the part latches itself off following a sustained
overvoltage or current limit. It goes high 2µs after the ON maintain constant load current until the BRK TMR pin
pin goes low. FAULT has a weak pull-up to one diode drop
below V ; an external resistor can pull the pin above V .
trips, when the pin is pulled to ground until the chip is
reset.
CC
CC
FB (Pin 7): Noninverting Input to An Analog Comparator;
the inverting input is tied to the 1.23V internal reference.
The FB comparator can be used with an external resistive
SENSE(Pin15):CurrentLimitSet. Tousethecurrentlimit
place a sense resistor in the supply path between V and
CC
SENSE. Should the drop across the resistor exceed a
divider to monitor the output supply voltage. When the FB threshold voltage the GATE pin is adjusted to maintain a
voltage is lower than 1.23V the RESET pin is pulled low.
RESETgoes highonesystemtimingcycleafterthevoltage
at FB exceeds its threshold by 3mV of hysteresis. A low
pass filter at the comparator’s output prevents negative
voltage glitches from triggering a false reset.
constant load current and the timer at the BRK TMR pin is
started. To protect the external FET from thermal damage
the circuit breaker trips after the BRK TMR timing cycle. A
foldback feature makes the current limit decrease as the
voltage at FB approaches ground. Figure 3 quantifies the
relationship. To disable the current limit short SENSE to
GND (Pin 8): Chip Ground.
V .
CC
OV (Pin 9): Analog Input Used to Monitor Overvoltages.
WhenthevoltageonOVexceeds its trippointtheGATEpin
is pulled low immediately and the CRWBR timer starts. If
OV remains above its trip point (minus 3mV of hysteresis)
long enough for CRWBR to reach its trip point the part
latches offuntilresetbypulsingtheONpinlow;otherwise,
the GATE pin begins ramping up one RST TMR timing
cycle after OV goes below its trip point.
V (Pin 16): Positive Supply Voltage; between 2.97V and
16.5V in normal operation. An internal undervoltage lock-
CC
out circuit holds the GATE pin at ground until V exceeds
CC
2.73V. If VCC exceeds 16.5V an internal shunt regulator
protects the chip from V and SENSE pin voltages up to
CC
33V. When the internal shunt regulator is active and the
chargepumpis ontheGATEpinvoltagewillusuallybelow
butthis is notguaranteed;usetheOVpintoensurethatthe
COMPOUT (Pin 10): Uncommitted Comparator’s Open
Drain Output.
pass device is off. The V pin also provides a Kelvin
CC
connection to the high side of the SENSE resistor.
COMP+ (Pin 11): Uncommitted Comparator’s Noninvert-
ing Input.
4
LTC1642
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APPLICATIO S I FOR ATIO
Hot Circuit Insertion
The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
When a circuit board is inserted into a live backplane its
supplybypass capacitors candrawlargecurrents fromthe
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642 limits the charging currents drawn by a
board’s capacitors, allowing safe insertion in a live
backplane.
2µAcurrentsourcefeedingRSTTMRfromV ;aninternal
CC
comparator, with the positive input tied to RST TMR and
the negative input tied to the 1.23V reference; and an
NMOS pull-down. In standby, the NMOS holds RST TMR
at ground; when the timer starts the NMOS turns off and
the RST TMR voltage ramps up as the current source
charges the capacitor. When RST TMR reaches 1.23V the
timer comparator trips; the GATE voltage begins ramping
andRSTTMRreturns toground. Theramptime∆tneeded
to trip the comparator is : ∆t(ms) = 615•C1(µF).
Power Supply Ramping
In the circuit shown in Figure 1 the LTC1642 and the
external N-channel pass transistor Q1 work together to
limit charging currents. When power is first applied to V
CC
V
IN
the chip holds Q1’s gate at ground. After a programmable
delay a 25µA current source begins to charge the external
capacitor C2, generating a voltage ramp of 25µA/C2 V/s at
the GATE pin. Because Q1 acts as a source follower while
its gate ramps, the current charging the board’s bypass
capacitance CLOAD is limited to 25µA•CLOAD/C2.
RST TMR
GATE
SLOPE = 25µA/C(V/s)
An internal charge pump supplies the 25µA gate current,
ensuring sufficient gate drive to Q1. At 3V V the mini-
CC
V
OUT
mum gate drive is 4.5V; at 5V V the minimum is 10V; at
CC
15V V the minimum is again 4.5V, due to a Zener clamp
CC
1642 F02
TIME
from the GATE pin to ground. Resistor R3 limits this
Zener’s transient current during board insertion and re-
moval and protects against high frequency FET oscilla-
tions.
Figure 2. Supply Control Timing
Powering-Up In Current Limit
R2
0.010Ω
Q1
FDR9410A
V
IN
Ramping the GATE pin voltage indirectly limits the charg-
ing current to I = 25µA•CLOAD/C2, where C2 is the external
capacitor connected to the GATE and CLOAD is the load
capacitance. If the value of CLOAD is uncertain, then a
worst-case design can often result in needlessly long
ramp times, and it may be better to limit the charging
current directly.
12V
2.5A
V
OUT
+
16
15
C
LOAD
C7
0.1µF
R1
10k
R3
100Ω
V
SENSE
CC
4
2
14
ON
GATE
R4
330Ω
LTC1642
C2
0.047µF
5
BRK TMR
RESET
Current Limiting and Solid-State Circuit Breaker
RST TMR
3
GND
8
The board current can be limited by connecting a sense
C4
0.33µF
C1
0.33µF
resistor between the LTC1642’s V and SENSE pins. An
CC
1642 F01
internal servo loop adjusts the GATE pin voltage such that
Q1 acts as a constant current source if the voltage drop
across the sense resistor reaches a limit. The voltage limit
across the sense resistor increases as the output charges
ALL RESISTORS ±5% UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 20ms
Figure 1. Supply Control Circuitry
5
LTC1642
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APPLICATIO S I FOR ATIO
up; this “foldback” limiting tends to keep the power
dissipation in the N-channel pass transistor constant. The
output voltage is sensed at the FB pin. The limiting sense
resistor voltage is 23mV when FB is grounded, but in-
creases gradually to 53mV when FB exceeds 1V; Figure 3
shows the full dependence.
The servo loop controlling Q1 during current limit has a
unity-gain frequency of about 125kHz; in Figure 1 R4,
togetherwithC2, providecompensation. Toensurestabil-
ity the product 1/(2•π•R4•C2) should be kept below the
unity-gain frequency, and C2 should be more than Q1’s
gate-source capacitance. The values shown in Figure 1,
0.047µF and 330Ω, are a starting point.
When the sense resistor voltage reaches its limit, a circuit
breaker timer starts. This timer uses the BRK TMR pin and
has a 1.23V threshold. If BRK TMR reaches 1.23V the
timer comparator trips, tripping the circuit breaker; if the
sense resistor voltage falls below its limit before the
comparator trips the GATE voltage begins ramping back
up immediately. The ramp time ∆t needed to trip the
comparator is ∆t(ms) = 62•C(µF), where C is the external
capacitance.
Typical waveforms during a load short to ground are
shown in Figure 4. The load is shorted to ground at time 1.
The GATE voltage drops until the load current equals its
maximum limit, and the circuit breaker timer starts. The
short is cleared at time 2, before the timer trips. The BRK
TMR pin returns to ground, and the GATE voltage begins
ramping up. At time 3 the load is shorted again and at time
4 the timer trips, pulling the GATE to ground and asserting
FAULT. Although the short is cleared at time 5, FAULT
doesn’t go high until the ON pin is pulled low at time 6. At
time 7 ON goes high and the system timer starts. When it
trips at time 8 the GATE voltage begins ramping.
Once the circuit breaker trips, GATE and FAULT remain at
ground until the chip is restarted. To restart, hold the ON
pin low for at least 2µs and FAULT will go high. Then take
ON high again and the GATE will ramp up after a system
timing cycle. Or, configure the LTC1642 to restart itself
after the circuit breaker trips by connecting FAULT to the
ON pin.
6
1
2
3
4 5
7
8
I
LOAD
70
60
50
40
30
20
10
0
I
LIMIT
0A
GATE
GATE
V
OUT
1.23V
BRK TMR
FAULT
ON
0
100 200 300 400 500 600 700 800 9001000
FB PIN VOLTAGE (mV)
1.23V
RST TMR
1642 F04
1642 F03
Figure 3. Maximum Sense Resistor Voltage vs FB Voltage
Figure 4. Current Limit and Circuit Breaker Timing
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LTC1642
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APPLICATIO S I FOR ATIO
Automatic Restart After a Current Fault
node. The external pull-up resistor at the ON pin may be
omitted because FAULT provides a weak pull-up.
The LTC1642 will automatically attempt to restart itself
after the circuit breaker opens if the FAULT output is tied
to the ON pin. The circuit is shown in Figure 5, and the
waveforms during a load short in Figure 6.
Undervoltage Lockout
An internal undervoltage lockout circuit holds the charge
pump off until V exceeds 2.73V. If V falls below 2.5V,
CC
CC
During a continuous current limit such as a load short, the
N-channel pass transistor’s duty cycle is equal to the
circuit breaker timer period, divided by the sum of the
circuit breaker and system timer periods. If FAULT is tied
to ON then open drain logic should be used to drive the
it turns off the charge pump and clears overvoltage and
current limit faults.
For higher lockout thresholds tie the ON pin to a resistor
divider driven from V , as shown in Figure 7. This
CC
circuit keeps the charge pump off until V exceeds
CC
Q1
FDR9410A
R2
0.010Ω
(1+R1/R5)•1.34V, and also turns it off if V falls below
V
CC
IN
12V
V
OUT
(1+R1/R5)•1.23V.
2.5A
+
16
15
C
LOAD
C7
0.1µF
R3
100Ω
V
SENSE
R1
CC
4
6
14
ON
GATE
1
2
3
4
5
6
R4
330Ω
FAULT
LTC1642
C2
0.047µF
9
2
GATE
OV
Q3
MCR
12DC
1
BRK TMR CRWBR
Q2
2N2222
V
OUT
R5
RST TMR
3
GND
8
1.23V
BRK TMR
C4
0.33µF
C1
0.33µF
C5
1642 F05
ON/FAULT
RST TMR
ALL RESISTORS ±5% UNLESS NOTED
C4
1.23V
SHORT-CIRCUIT DUTY CYCLE =
= 9%
C4 + 10 • C1
1642 F06
Figure 5. Automatic Restart Circuit
Figure 6. Automatic Retry Following a Load Short
R2
Q1
0.010Ω
FDR9410A
V
IN
V
OUT
12V
2.5A
+
C7
0.1µF
16
15
SENSE
C
LOAD
V
R1
464k
1%
CC
R3
100Ω
LTC1642
UNDERVOLTAGE
LOCKOUT
14
4
GATE
ON
THRESHOLD = 10.7V
C2
0.047µF
R5
60.4k
1%
R4
330Ω
RST TMR
3
GND
8
C1
0.33µF
1642 F07
ALL RESISTORS ±5% UNLESS NOTED
Figure 7. Setting a Higher Undervoltage Lockout
7
LTC1642
U
W U U
APPLICATIO S I FOR ATIO
R2
0.010Ω
Q1
FDR9410A
Overvoltage Protection
V
12V
IN
V
OUT
The LTC1642 can protect a load from overvoltages by
turning off the pass transistor if the supply voltage ex-
ceeds a programmable limit, and by triggering a crowbar
SCR if the overvoltage lasts longer than a programmable
time. The part can also be configured to automatically
restart when the overvoltage clears.
2.5A
+
C7
R1
127k
1%
16
15
C
LOAD
0.1µF
R3
100Ω
V
SENSE
CC
9
OV
14
GATE
R5
12.4k
1%
R4
330Ω
LTC1642
C2
0.047µF
Q2
2N2222
4
The overvoltage protection circuitry is shown in Figure 8.
The external components comprise a resistor divider
driving the OV pin, timing capacitor C5, NPN emitter
follower Q2, and crowbar SCR Q3. Because the MCR12DC
is not a sensitive-gate device, the optional resistor shunt-
ing the SCR gate to ground is omitted. The internal
components comprise a comparator, 1.23V bandgap ref-
erence, two current sources, and a timer at the CRWBR
ON
Q3
MCR12DC
6
1
FAULT
CRWBR
RST TMR
3
GND
8
C5
0.01µF
C1
0.33µF
1642 F08
ALL RESISTORS ±5% UNLESS NOTED
OV COMPARATOR TRIPS AT V = 13.85V
IN
RESET TIME = 200ms
pin.WhenV exceeds (1+R1/R5)•1.23Vthecomparator’s
CC
CROWBAR DELAY TIME = 90µs
output is high and internal logic pulls the GATE down and
starts the timer. This timer has a 0.410V threshold and
uses the CRWBR pin; when CRWBR reaches 0.410V the
Figure 8. Overvoltage Protection Circuitry
1
2
3
4
5 6 7
8
timer comparator trips, and the current sourced from V
CC
V
CC
increases to 1.5mA. Emitter follower Q2 boosts this cur-
rent to trigger crowbar SCR Q3. The ramp time ∆t needed
to trip the comparator is : ∆t(ms) = 9.1•C5(µF).
0V
OV
1.23V
0V
OncetheCRWBRtimertrips theLTC1642latches off:after
the overvoltage clears GATE and FAULT remain at ground
andCRWBRcontinues sourcing1.5mA.Torestartthepart
aftertheovervoltageclears, holdtheONpinlowforatleast
2µs and then bring it high. The GATE voltage will begin
ramping up one system timing cycle later. The part will
restart itself if FAULT and ON are connected: GATE begins
ramping up one system timing cycle after the overvoltage
clears.
GATE
0V
V
OUT
V
CC
Figure 9 shows typical waveforms when the divider is
0.41V
1.23V
CRWBR
driven from V . The OV comparator goes high at time 1,
CC
causing the chip to pull the GATE pin to ground and start
the CRWBR timer. At time 2, before the timer’s compara-
tor trips, OV falls below its threshold; the timer resets and
GATE begins charging one system timing cycle later at
time 3. Another overvoltage begins at time 4, and at time
5theCRWBRtimertrips;FAULTgoes lowandtheCRWBR
pin begins sourcing 1.5mA. Even after OV falls below
1.23V at time 6, GATE and FAULT stay low, and CRWBR
continues to source 1.5mA. FAULT goes high when ON
RST TMR
ON
FAULT
1642 F09
Figure 9. Overvoltage Timing (High Side)
8
LTC1642
U
W U U
APPLICATIO S I FOR ATIO
goes low at time 7, and GATE begins charging at time 8,
The OV and FB Comparators
one RST TMR cycle after FAULT goes high.
The propagation delay through the OV and FB compara-
tors on low to high transitions depends strongly on the
differential input voltage. The relationship is shown in
Figure 11. The minimum propagation delay for large
overdrives is about 20µs. In addition the comparators
have 3mV of hysteresis.
Figure 10 shows typical waveforms when the OV divider is
driven from the N-channel’s low side. Because the voltage
drivingthedividercollapses aftertheOVcomparatortrips,
FAULT stays high and CRWBR stays near ground, which
prevents thepinfromtriggeringanSCR.TheGATEvoltage
begins ramping up after a RST TMR timing cycle.
Internal Voltage Clamp Protection
Automatic Restart
The LTC1642 includes a shunt regulator to protect itself
If there is an overvoltage, and the resistor divider feeding
OV is connected to the output of the N-channel pass
transistor, the LTC1642 will automatically restart even if
FAULT is not tied to ON. If the divider is connected to the
input side, the LTC1642 will restart itself only if FAULT is
tied to ON, and only after the overvoltage clears.
from V and SENSE pin voltages up to 33V. The regulator
CC
turns on when V exceeds 16.5V and limits most of the
CC
chip’s circuitry to 15V. When it is on the chip functions
normally with one exception: if the charge pump is on, the
GATE voltage is usually near ground but this is not
guaranteed.UsetheOVpintoensurethatGATEis grounded.
The pull-up voltage on the RESET and FAULT pins follows
V until the shunt regulator turns on. When the regulator
CC
is on the pull-up voltage is 14.4V.
1
2
3
4
5
6 7
70
60
50
40
30
20
10
0
V
CC
0V
1.23V
OV
0V
GATE
V
OUT
0.41V
1.23V
CRWBR
RST TMR
0
40
80
120
160
200
240
OV OVERDRIVE (mV)
FAULT
1642 F11
0V
1642 F10
Figure 11. OV Comparator Propagation Delay vs
Overdrive Voltage
Figure 10. Overvoltage Timing (Low Side)
9
LTC1642
U
W U U
APPLICATIO S I FOR ATIO
R2
0.010Ω
Q1
FDR9410A
Undervoltage Monitor
V
12V
IN
V
OUT
TheLTC1642willassertRESETifamonitoredvoltagefalls
below a programmable minimum. When the monitored
voltage has exceeded its minimum for at least one system
timing cycle, RESET goes high. The monitoring circuitry
comprises an internal 1.23V bandgap reference, an inter-
nal precision voltage comparator and an external resistive
divider to monitor the output supply voltage. The circuit is
shown in Figure 12, and typical waveforms in Figure 13.
When the voltage at the FB pin rises above its reset
threshold (1.23V), the comparator output goes low and a
timing cycle starts (times 1 and 5). Following the cycle
RESET is pulled high.
2.5A
+
16
15
C
LOAD
R3
100Ω
V
SENSE
CC
4
14
ON
GATE
R7
95.3k
1%
R4
330Ω
LTC1642
C2
0.047µF
7
5
FB
R6
12.4k
1%
RESET
RST TMR GND
3
8
C1
0.33µF
At time 2 the voltage at FB drops below the comparator’s
threshold and RESET is pulled low. If the FB pin rises
above the reset threshold for less than a timing cycle the
RESET output will remain low (time 3 to time 4). The 15µA
1642 F12
ALL RESISTORS ±5% UNLESS NOTED.
FB COMPARATOR TRIPS AT V = 10.7V
OUT
Figure 12. Undervoltage Monitoring Circuitry
pull-up current source to V on RESET has a series diode
CC
so the pin can be pulled above V by an external pull-up
CC
resistor without forcing current back into the supply.
1
2
3
4
5
V1
V2 V1
V2
Reference
V
OUT
V1
The LTC1642’s internal voltage reference is buffered and
brought out to the REF pin. The buffer amplifier should be
compensated with a capacitor connected between REF
and ground. If no DC current is drawn from REF, 0.1µF
ensures an adequate phase margin, but the minimum
compensation increases if REF sources a substantial DC
current, as shown in Figure 14.
RST TMR
RESET
1642 F13
Figure 13. Supply Monitor Waveforms
10.0
Uncommitted Comparator
4.0
2.0
The uncommitted comparator has an open drain output.
The comparator has 3mV of hysteresis: the output goes
high when the differential input voltage exceeds 1.5mV
and goes low when the differential input is less than
–1.5mV.
1.0
0.4
0.2
0.1
100µA
1mA
10mA
REFERENCE CURRENT
1642 F14
Figure 14. Minimum REF Compensation vs REF Current
10
LTC1642
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.025
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
GN16 (SSOP) 0398
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
11
LTC1642
U
TYPICAL APPLICATIO
5V To 3.3V Hot Swap Supply Using the LTC1430
C16
330µF
6.3V
KEMET
TANT
C17
330µF
6.3V
KEMET
TANT
+
+
5
6
7
8
D2
C13
1µF
MBR0530T1
R9
51Ω
4
Q4
U2
LTC1430CS
Si4412DY
7
8
5
6
2
1
4
3
PV
PV
CC2 CC1
L1
3.5µH
1
5
2
6
3
7
C15
0.1µF
G2
G1
FB
SHDN
COMP
CDRH1273R5
3.3V
OUT
GND
AT 5A
8
R11
16.5k
1%
C8
15µF
10V
KEMET
TANT
R10
12k
D1
+
R13
MBRS130T3
17.4k
1%
4
C9
270pF
Q5
Si4412DY
C18
680pF
C10
330µF
6.3V
KEMET
TANT
C11
330µF
6.3V
KEMET
TANT
C12
330µF
6.3V
KEMET
TANT
+
+
+
C14
2200pF
C7
0.1µF
1
2
3
R12
10.2k
1%
R14
12.1k
1%
Q1
R1, 0.005Ω
MTB50N06V
5V
R5
36.5k
1%
R3
32.4k
1%
R2
100Ω
R8
330Ω
LATCH OFF: FLOAT FAULT
C1
47nF
C6
0.1µF
AUTOMATIC RETRY: TIE FAULT TO ON
16
15
14
V
SENSE
GATE
CC
5
5V POWER-GOOD = 4.75V
RESET
FB
10
4
7
3.3V POWER-GOOD = 3.00V
UNDERVOLTAGE = 4.49V
COMPOUT
ON
1
Q3
U1
CRWBR
MCR
12DC
R6
2.55k
1%
D3
1N4148
LTC1642
6
12
11
13
–
COMP
Q2
2N2222
FAULT
OV
+
9
COMP
OVERVOLTAGE = 5.47V
REF
R4
13k
1%
C5
0.01µF
R7
11.3k
1%
GND
BRK TMR
2
C3
0.33µF
RST TMR
C4
0.1µF
8
3
C2
0.33µF
1642 TA02
ALL RESISTORS 5% UNLESS OTHERWISE NOTED
RESET TIME = 200ms
CURRENT LIMIT TIME =20ms
CROWBAR TIME = 90µs
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Hot Swap Controller
Hot Swap Controller
Multiple Supplies
Single Supply in SO-8
Negative High Voltage Supplies
3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1422
LT1640
Negative Voltage Hot Swap Controller
PCI-Bus Hot Swap Controller
LTC1643
1642is, sn1642 LT/TP 0599 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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