LTC1642ACGN#TRPBF [Linear]
LTC1642A - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC1642ACGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1642A - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管 |
| 文件： | 总16页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1642A
Hot Swap Controller
U
DESCRIPTIO
FEATURES
The LTC®1642A is a 16-pin Hot SwapTM controller that
allows a board to be safely inserted and removed from a
live backplane. Using an external N-Channel pass transis-
tor, the board supply voltage can be ramped up at an
adjustable rate. A high side switch driver controls the
N-Channel gate for supply voltages ranging from 2.97V
to 16.5V.
■
Adjustable Undervoltage and Overvoltage
Protection
■
Foldback Current Limit
■
Adjustable Current Limit Time-Out
VCC: 2.97V to 16.5V Normal Operation, Protected
■
Against Surges to 33V
Single Channel NFET Driver
■
■
Latch Off or Automatic Retry on Current Fault
TheSENSEpinallowsfoldbacklimitingoftheloadcurrent,
with circuit breaker action after an adjustable delay time.
The delay allows the part to power-up in current limit. The
CRWBR output can be used to trigger an SCR for crowbar
protection of the load if the input supply exceeds an
adjustable threshold. The RESET output can generate a
system reset with adjustable delay when the supply volt-
age falls below an adjustable threshold. The ON pin cycles
the board power. The LTC1642A is available in the 16-pin
SSOP package.
■
Driver for SCR Crowbar on Overvoltage
■
Adjustable Reset Timer
■
Reference Output with Uncommitted Comparator
■
16-Pin SSOP Package
U
APPLICATIO S
■
Hot Board Insertion
■
Electronic Circuit Breaker
InfiniBandTM Systems
■
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Hot Swap is a trademark of Linear
Technology Corporation.
U
TYPICAL APPLICATIO
0.010Ω
5%
BACKPLANE
12V
PLUG-IN CARD
FDS6630A
12V
AT 2.5A
+
C
(SHORT PIN)
LOAD
110k
1%
100Ω
5%
330Ω
5%
1N4705
18V
107k
1%
0.047µF
V
SENSE
GATE
CC
POWER-GOOD = 11.4V
RESET
FB
UV = 10.8V
ON
LTC1642A
MCR
12DC
CRWBR
2.87k
1%
–
2N2222
COMP
FAULT
OV
+
COMP
13k
1%
COMPOUT
REF
OV = 13.2V
GND BRK TMR
RST TMR
11.3k
1%
0.33µF
0.33µF
0.1µF
0.01µF
1642a TA01
GND
1642af
1
LTC1642A
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
Supply Voltage (VCC) .................................–0.3V to 33V
SENSE Pin ................................... –0.3V to (VCC + 0.3V)
ON, FB, OV, COMP+, COMP–
RESET, FAULT, COMPOUT .....................–0.3V to 18.5V
Operating Temperature Range
LTC1642AC ............................................. 0°C to 70°C
LTC1642AI ......................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
CRWBR
BRK TMR
RST TMR
ON
1
2
3
4
5
6
7
8
16
15 SENSE
V
CC
LTC1642ACGN
LTC1642AIGN
14
13
12
11
10
9
GATE
REF
–
+
RESET
FAULT
FB
COMP
COMP
GN PART
MARKING
COMPOUT
OV
GND
1642A
1642AI
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 130°C/W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
DC ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C.
A
V
CC
= 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
16.5
3.0
UNITS
V
V
CC
Operating Voltage Range
●
●
●
●
2.97
I
V
CC
V
CC
V
CC
V
CC
Supply Current
ON = V
1.25
2.73
2.50
230
1.220
5
mA
V
CC
CC
V
V
V
V
Undervoltage Lockout
Undervoltage Lockout
Undervoltage Lockout Hysteresis
V
V
Rising
Falling
2.55
2.35
2.95
2.95
LKHI
LKLO
LKHYST
FB
CC
V
CC
mV
V
FB Pin Voltage Threshold
FB Falling
FB Falling, 2.97V ≤ V ≤ 16.5V
●
●
1.208
1.208
1.200
1.232
15
∆V
FB Pin Threshold Supply Variation
FB Pin Voltage Threshold Hysteresis
FB Pin Input Current
mV
mV
µA
V
FB
CC
V
3
FBHST
FB(IN)
I
V
OV
= 5V
●
●
●
0
±1
1.232
15
V
OV
OV Pin Voltage Threshold
OV Rising
OV Rising, 2.97V ≤ V ≤ 16.5V
1.220
5
∆V
OV Pin Threshold Supply Variation
OV Pin Voltage Theshold Hysteresis
OV Pin Input Current
mV
mV
µA
V
OV
CC
V
3
OVHYST
OV(IN)
I
V
FB
= 5V
●
●
●
●
0
±1
1.250
15
V
RST
RST TMR Pin Voltage Threshold
RST TMR Pin Threshold Supply Variation
RST TMR Pin Current
RST TMR Rising
1.220
5
∆V
RST TMR Rising, 2.97V ≤ V ≤ 16.5V
mV
RST
BRK
CR
CC
I
Timer On
–1.5
–2.0
10
–2.5
µA
mA
RST
Timer Off, V
= 1.5V
RSTTMR
V
BRK
BRK TMR Pin Voltage Threshold
BRK TMR Pin Threshold Supply Variation
BRK TMR Pin Current
BRK TMR Rising
●
●
●
1.200
1.220
5
1.250
15
V
∆V
BRK TMR Rising, 2.97V ≤ V ≤ 16.5V
mV
CC
I
Timer On
–15
375
–20
10
–30
µA
mA
BRK
Timer Off, V
= 1.5V
BRKTMR
V
CR
CRWBR Pin Voltage Theshold
CRWBR Pin Threshold Supply Variation
CRWBR Pin Current
CRWBR Rising
2.97V ≤ V ≤ 16.5V
●
●
410
4
425
15
mV
mV
∆V
CC
I
CRWBR On, V
CRWBR On, V
CRWBR Off, V
= 0V
= 2.1V
= 1.5V
●
●
–30
–1000
–45
–1500
2.3
–60
µA
µA
mA
CR
CRWBR
CRWBR
CRWBR
1642af
2
LTC1642A
DC ELECTRICAL CHARACTERISTICS
The
CC
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C.
A
V
= 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Circuit Breaker Trip Voltage
V
V
= (V – V
), V = GND
●
●
15
45
25
52.5
36
60
mV
mV
CB
CB
CB
CC
SENSE
SENSE
FB
= (V – V
), V = 1V
CC
FB
2.97V ≤ V ≤ 16.5V,
CC
V
V
= (V – V
), V = GND
●
●
12
42
25
52.5
39
63
mV
mV
CB
CC
SENSE
SENSE
FB
= (V – V
), V = 1V
CB
CC
FB
I
I
SENSE Pin Input Bias Current
GATE Pin Output Current
V
= V = 16.5V
SENSE
●
●
0.5
µA
SENSE
GATE
CC
Charge Pump On, V
Charge Pump Off, V
= GND
= 5V
–20
–25
10
–30
µA
mA
GATE
GATE
∆V
GATE
External N-Channel Gate Drive
V
V
V
V
– V
– V
– V
– V
V
= 2.97V
= 5V
= 15V (0°C to 70°C)
= 15V (–40°C to 85°C)
●
●
●
●
4.5
10
6.5
6
5.9
11.5
8.5
8.0
14
18
18
V
V
V
V
GATE
GATE
GATE
GATE
CC, CC
V
CC, CC
V
CC, CC
V
8.5
CC, CC
V
V
V
ON Pin Threshold
ON Pin Threshold
ON Pin Hysteresis
ON Pin Input Current
Output Low Voltage
ON Rising
ON Falling
1.30
1.20
1.34
1.22
110
0
1.38
1.26
V
V
ONHI
●
ONLO
mV
µA
ONHYST
ON(IN)
I
V
= 5V
●
●
±1
ON
V
RESET, FAULT, COMPOUT I = 1.54mA
RESET, FAULT I = 5mA
0.4
2
V
V
OL
OL
O
I
Logic Output Pull-Up Current
Reference Output Voltage
Reference Supply Variation
Reference Load Regulation
Reference Short-Circuit Current
Comparator Offset Voltage
Comparator Hysteresis
RESET, FAULT = GND
No Load
–15
1.220
5
µA
V
PU
V
●
●
●
1.208
1.232
15
REF
∆V
∆V
2.97V ≤ V ≤ 16.5V, No Load
mV
mV
mA
mV
mV
LNR
CC
I = 0mA to –1mA, Sourcing Only
O
2.5
7.5
LDR
I
V
V
= 0V
4.5
RSC
REF
CM
V
V
= V
●
±10
COS
CHYST
REF
V
= V
3
CM
REF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
I
vs Temperature
∆V
vs V
CC
∆V
vs Temperature
GATE
GATE
GATE
30
29
28
27
26
25
24
23
22
21
20
16
14
12
10
8
15
12
9
V
V
V
V
= 3V
T
= 25°C
CC
CC
CC
CC
A
= 5V
V
= 12V
CC
= 12V
= 15V
V
= 5V
CC
V
V
= 15V
= 3V
CC
CC
6
6
4
3
2
V
= 0V
GATE
0
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
3
6
9
12
15
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
1642a G03
1642a G04
1642a G26
1642af
3
LTC1642A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
GATE Pull-Down Current (Current
Limit Active)
CRWBR-TMR Threshold Voltage
vs Temperature
I
Pull-Up Current vs V
GATE
CC
128
112
96
80
64
48
32
16
0
25
20
15
10
5
405
404
403
402
401
400
399
398
397
396
395
T
A
= 25°C
V
= 12V
CC
V
= 5V
CC
V
= 5V
CC
V
= 3.3V
CC
V
T
= 0V
6
GATE
A
= 25°C
0
0
4
8
12
16
20
24
3
9
12
15
–50 –25
0
25
50
75 100 125
V
(V)
V
CC
(V)
GATE
TEMPERATURE (°C)
1642a G36
1642a G23
1642a G05
CRWBR Driver Current vs
Temperature
FB Threshold Voltage vs
Temperature
CRWBR Driver Current vs V
CC
1.45
1.44
1.43
1.42
1.41
1.40
1.39
1.38
1.226
1.224
1.222
1.220
1.218
1.216
1.214
2.0
1.6
1.2
0.8
0.4
0
V
CC
= 5V
V = 5V
CC
T
= 25°C
A
FB RISING
FB FALLING
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
3
6
9
12
15
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
1642a G13
1642a G06
1642a G35
OV Threshold Voltage vs
Temperature
FB Threshold Voltage vs V
CC
OV Threshold Voltage vs V
CC
1.232
1.228
1.224
1.220
1.216
1.212
1.208
1.226
1.232
1.228
1.224
1.220
1.216
1.212
1.208
V = 5V
CC
T
A
= 25°C
T
= 25°C
A
FB RISING
OV RISING
1.224
1.222
1.220
1.218
1.216
1.214
OV RISING
FB FALLING
OV FALLING
OV FALLING
–50 –25
0
25
50
75 100 125
3
6
9
12
15
3
6
9
12
15
TEMPERATURE (°C)
V
CC
(V)
V
(V)
CC
1642a G07
1642a G27
1642a G28
1642af
4
LTC1642A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
FAULT and RESET V vs
FAULT and RESET Pull-Up Current
(I ) vs V
FAULT and RESET V vs
OL
Temperature
OL
Temperature
OH
CC
600
500
400
300
200
100
0
160
140
120
100
80
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
I
= 1.54mA
I
= 5mA
OL
OL
T
= –55°C
A
V
= 3V
CC
T
= 25°C
A
V
= 5V
CC
V
= 3V
CC
60
V
V
= 12V
= 15V
V
= 5V
CC
CC
CC
40
T
A
= 125°C
V
V
= 12V
= 15V
CC
CC
20
0
–50 –25
0
25
50
75 100 125
3
6
9
12
15
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
V
(V)
TEMPERATURE (°C)
CC
1642a G16
1642a G14
1642a G17
Current Limit Threshold Voltage
(Full Foldback) vs Temperature
Current Limit Threshold Voltage
(Nominal) vs Temperature
ON Pin Threshold Voltage vs
Temperature
27.5
27.0
26.5
26.0
25.5
25.0
24.5
57.0
56.5
56.0
55.5
55.0
54.5
54.0
53.5
1.40
1.36
1.32
1.28
1.24
1.20
FB = 0V
FB = 1V
V
= 12V
CC
V
= 15V
CC
ON RISING
V
= 15V
CC
V
= 12V
V
= 12V
CC
CC
V
= 5V
CC
V
= 5V
CC
V
= 3V
CC
V
= 3V
ON FALLING
CC
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1642a G20
1642a G21
1642a G22
I
CC
vs V
V
REF
vs V
Reference O/P Impedance
CC
CC
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
20
10
0
1.232
1.228
1.224
1.220
1.216
1.212
1.208
T
= 25°C
T
A
= 25°C
T
A
= 25°C
A
V
= 5V
= 0V
ON
V
V
= 5V
CC
CC
V
= 12V,
15V
CC
= 3.3V
V
ON
–42
0
2.5
5
7.5 10 12.5 15 17.5 20
(mA)
0
25
50
3
6
9
12
15
I
V
(V)
V
(V)
REF
CC
CC
1642a G37
1642a G25
1642a G24
1642af
5
LTC1642A
U
U
U
PI FU CTIO S
CRWBR (Pin 1): Overvoltage Crowbar Circuit Timer and
Trigger. This pin controls an external overvoltage crowbar
circuit. A capacitor from the pin to ground sets a 9ms/µF
delay after an overvoltage occurs until an external SCR is
triggered. See Applications Information. Ground the
CRWBR pin if unused.
RESET (Pin 5): Open Drain Reset Output. RESET is pulled
lowifthevoltageattheFBpinisbelowitstrippoint. RESET
goes high one RESET timing cycle after the FB voltage
exceeds its trip point plus 3mV of hysteresis. RESET has
aweakpull-uptoonediodedropbelowVCC andanexternal
resistor can pull the pin above VCC. A 21V zener clamp
limits the voltage at this pin. The pin can be safely tied to
BRK TMR (Pin 2): Circuit Breaker Timer. Connect a
capacitor from BRK TMR to ground to set a 60ms/µF delay
from the time the sense resistor current reaches its limit
until the FET is shut off. FAULT output is then asserted and
the FET remains off until the chip is reset. Ground BRK
TMRtoallowtheparttoremainincurrentlimitindefinitely.
V
CC > 21V through a series resistor that limits the current
below 1mA.
FAULT (Pin 6): Open Drain Fault Output. FAULT is pulled
low when the part turns off following a sustained overvolt-
age or current limit. It goes high 2µs after the ON pin goes
low. FAULT has a weak pull-up to one diode drop below
RST TMR (Pin 3): Analog System/Reset Timer. A capaci-
tor from this pin to ground sets a 0.6s/µF delay from the
ON pin going high to the start of the GATE pin’s ramp. It
alsosetsthedelayfromoutputvoltagegood, assensedby
the FB pin, to RESET going high.
V
CC and an external resistor can pull the pin above VCC. A
21V zener clamp limits the voltage at this pin. The pin can
be safely tied to VCC > 21V through a series resistor that
limits the current below 1mA.
FB (Pin 7): Output Voltage Monitor and Foldback Input.
The FB comparator can be used with an external resistive
divider to monitor the output supply voltage. When the FB
voltage is lower than 1.22V the RESET pin is pulled low.
RESETgoeshighonesystemtimingcycleafterthevoltage
at FB exceeds its threshold by 3mV of hysteresis. A low
pass filter at the comparator’s output prevents negative
voltage glitches from triggering a false reset.
ON (Pin 4): ON Control Input. When ON is low the GATE
pin is grounded and FAULT goes high. The GATE pin
voltage starts ramping up one RST TMR timing cycle after
ONgoeshigh.PulsingtheONpinlowforatleast2µsresets
the chip if it latches off after a sustained overvoltage or
current limit. The threshold for a low to high transition is
1.34V with 110mV of hysteresis. A 21V zener clamp limits
the voltage at this pin. The pin can be safely tied to VCC
>
21V through a series resistor that limits the current below
1mA.
GND (Pin 8): Chip Ground.
1642af
6
LTC1642A
U
U
U
PI FU CTIO S
OV (Pin 9): Overvoltage Input. When the voltage on OV
exceeds its trip point the GATE pin is pulled low immedi-
ately and the CRWBR timer starts. If OV remains above its
trip point (minus 3mV of hysteresis) long enough for
CRWBR to reach its trip point, then the part turns off until
reset by pulsing the ON pin low. Otherwise, the GATE pin
begins ramping up one RST TMR timing cycle after OV
goes below its trip point. Ground the OV pin to disable
overvoltage protection.
immediately pulled to ground when the overvoltage com-
parator trips or the input supply is below the undervoltage
lockout trip point. During current limit the GATE voltage is
adjusted to maintain constant load current until the circuit
breaker timer trips. At that point GATE is pulled to ground
until the chip is reset. Clamp the GATE pin with a zener
diode to ground if the supply is 8V or higher. For the 8V to
12V range use an 18V zener (1N4705), and for supplies
exceeding 12V use a 20V zener (TOSHIBA 02DZ20Y).
COMPOUT (Pin 10): Uncommitted Comparator’s Open
SENSE (Pin 15): Current Sense Input. To use the current
limit place a sense resistor in the supply path between VCC
and SENSE. When the drop across the resistor exceeds a
threshold voltage, the GATE pin is adjusted to maintain a
constant load current and the circuit breaker timer is
started. A foldback feature reduces the current limit as the
voltage at FB approaches ground. Short SENSE to VCC to
disable the current limiting.
Drain Output.
COMP+ (Pin 11): Uncommitted Comparator’s Noninvert-
ing Input.
COMP– (Pin 12): Uncommitted Comparator’s Inverting
Input.
REF (Pin 13): Reference Voltage Output. The 1.22V ±1%
reference should be bypassed with a 0.1µF compensation
capacitor. For VCC = 5V it can source 1mA.
VCC (Pin 16): Positive Supply Voltage. An internal under-
voltage lockout circuit holds the GATE pin at ground until
VCC exceeds 2.73V. If VCC exceeds 16.5V an internal shunt
regulator protects the chip from VCC and SENSE pin
voltages up to 33V. In this case the GATE pin voltage will
usually be low but this is not guaranteed; use the OV pin
to ensure that the pass device is off. The VCC pin also
provides a high side connection to the SENSE resistor.
GATE (Pin 14): Gate Drive for the External N-Channel
MOSFET. An internal charge pump provides at least 4.5V
of gate drive and sources 25µA. The pin requires an
external series RC network to ground to compensate the
current limit loop and to limit the ramp rate. A resistor of
100Ω is also recommended in series with the MOSFET
gate to suppress high frequency oscillations. GATE is
1642af
7
LTC1642A
W
BLOCK DIAGRA
GATE
14
CRWBR
1
V
16
V
CC
CC
21.5V
21V
+
–
+
–
1.22V
CHARGE PUMP
25µA
23mV TO 53mV
13 REF
21V
45µA
1.5mA
+
–
–
+
0.41V
SENSE 15
V
FB
OV
ON
7
9
4
–
+
CC
RISING
DELAY
15µs TO
100µs
21V
21V
21V
1.22V
1.22V
1.22V
2.7V
10µA AT 5V
RESET
5
+
–
RISING
DELAY
15µs TO
100µs
21V
LOGIC
V
+
–
CC
RISING
DELAY
2µs
10µA AT 5V
FAULT
V
6
+
–
CC
RISING
DELAY
10µs
21V
20µA
2µA
10 COMPOUT
21V
+
COMP 11
+
–
+
–
+
–
–
COMP 12
1.22V
1.22V
21V
21V
21V
21V
2
3
BRK TMR
RST TMR
1642a BD
1642af
8
LTC1642A
U
W U U
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
2µAcurrentsourcefeedingRSTTMRfromVCC;aninternal
comparator, with the noninverting input tied to RST TMR
and the inverting input tied to the 1.22V reference; and an
internal NMOS pull-down. In standby, the NMOS holds
RST TMR at ground. When the timer starts the NMOS
turnsoffandtheRSTTMRvoltagerampsupasthecurrent
source charges the capacitor. When RST TMR reaches
1.22Vthetimercomparatortrips, theGATEvoltagebegins
ramping up and RST TMR returns to ground. The timer
delay is:
When a circuit board is inserted into a live backplane its
supplybypasscapacitorscandrawlargecurrentsfromthe
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642A limits the charging currents drawn by a
board’s capacitors, allowing safe insertion into a live
backplane.
In the circuit shown in Figure 1 the LTC1642A and the
external NMOS pass transistor Q1 work together to limit
charging currents. Waveforms at board insertion are
shown in Figure 2. When power is first applied to VCC the
chip holds Q1’s gate at ground. After an adjustable delay
a 25µA current source begins to charge the external
capacitor C2, so choose C2 to limit the inrush current
IINRUSH charging the board’s bypass capacitance CLOAD
according to the equation:
t
RSTTMR = (615ms/µF) C1.
The second RST TMR cycle indicates that VOUT is within
tolerance; it is discussed in the Undervoltage Monitor
section.
OV
10V/DIV
25µA
C2 = CLOAD
•
RST TMR
2V/DIV
IINRUSH
An internal charge pump supplies the 25µA gate current,
ensuringsufficientgatedrivetoQ1.At3VVCC theminimum
gatedriveis4.5V;at5VVCC theminimumis10V;at15VVCC
the minimum is again 6.5V, due to an internal zener clamp
fromtheGATEpintoground.ResistorR3limitsthiszener’s
transient current during board insertion and removal and
protects against high frequency oscillations in Q1. D1
provides additional protection against supply spikes.
GATE
20V/DIV
VOUT
20V/DIV
100ms/DIV
1642a F02
Figure 2. Timing at Board Insertion
R2
Q1
0.010Ω
FDS6630A
V
IN
Powering-Up in Current Limit
12V
V
OUT
2.5A
+
Ramping the GATE pin voltage limits the current to I =
25µA • CLOAD/C2, where C2 is the external capacitor
connected to the GATE and CLOAD is the load capacitance.
IfthevalueofCLOAD isuncertain, thenaworst-casedesign
can often result in needlessly long ramp times, and it may
be better to limit the charging current by powering up in
current limit.
16
15
SENSE
C
LOAD
R7
R3
V
CC
24k
100Ω
4
2
14
ON
GATE
R4
330Ω
C2
0.047µF
D1
1N4705
18V
LTC1642A
6
BRK TMR
RST TMR
3
FAULT
GND
8
R10
30k
ALL RESISTORS ±5% UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 10ms
C4
0.33µF
C1
0.33µF
Current Limiting and Solid-State Circuit Breaker
The current can be limited by connecting a sense resistor
between the LTC1642A’s VCC and SENSE pins. When the
1642a F01
Figure 1. Supply Control Circuitry
voltage drop across this resistor reaches a limiting value,
1642af
9
LTC1642A
U
W U U
APPLICATIO S I FOR ATIO
an internal servo loop adjusts the GATE pin voltage such
thatQ1actsasaconstantcurrentsource. Thevoltagelimit
across R2 increases as the output charges; this foldback
in the current limit helps to even out Q1’s power dissipa-
tion. The output is sensed at the FB pin. When FB is
grounded, the sense voltage is limited to 26mV. When FB
is greater than 0.7V, the limit is 56mV and the full depen-
dence is shown in Figure 3.
pin low for at least 2µs and FAULT will go high. Then take
ON high again and the GATE will ramp up after a system
timing cycle. Or, configure the LTC1642A to restart itself
after the circuit breaker trips by connecting FAULT to the
ON pin, as shown in the next section.
The servo loop controlling Q1 during current limit has a
unity-gain frequency of about 125kHz. In Figure 1, R4 and
C2 provide compensation. To ensure stability the product
1/(2 • π • R4 • C2) should be kept below the unity-gain
frequency, and C2 should be more than Q1’s input capaci-
tance CISS. A good starting point for C2 is 0.047µF and R4
is 330Ω. Keep R4 ≥ 100Ω.
When the sense resistor voltage is 3mV below its limit, the
circuit breaker timer starts. Once BRK TMR reaches its
threshold,thecircuitbreakeropens,theGATEpinispulled
to ground (cutting off Q1) and FAULT is asserted.
TheparameterVCB specifiedintheDCelectricalcharacter-
istics refers to the voltage difference between the VCC and
SENSE pins needed to start the circuit breaker timer. The
limiting value maintained by the servo loop is 3mV higher
than VCB.
Typical waveforms during a load short to ground are
shown in Figure 4. The load is shorted to ground at time 1.
The GATE voltage drops until the load current equals its
maximum limit, and the circuit breaker timer starts. The
short is cleared at time 2, before the timer trips. The BRK
TMR pin returns to ground, and the GATE voltage begins
ramping up. At time 3 the load is shorted again and at time
4 the timer trips, pulling the GATE to ground and asserting
FAULT. Although the short is cleared at time 5, FAULT
doesn’t go high until the ON pin is pulled low at time 6. At
time 7 ON goes high and the system timer starts. When it
trips at time 8 the GATE voltage begins ramping.
Should the sense resistor voltage drop below its limit
before the timer trips, the GATE voltage begins ramping
back up immediately and the BRK TMR pin returns to
ground.However,duetotheslowgateramp,Q1continues
to dissipate substantial power for some time. Connecting
R10 in series with timing capacitor C4 (as shown in
Figure 1) ensures that the circuit breaker trips in the event
of repetitive, but brief, load shorts. The delay before the
circuit breaker opens is:
To disable current limit and electronic circuit breaker
protection, tie the SENSE pin to VCC, the BRK TMR pin to
GND and omit compensating resistor R4.
tBRKTMR = C4 (61kΩ – R10).
t
1
t
3
t
5
2
4
t
6
t
Once the circuit breaker trips, GATE and FAULT remain at
ground until the chip is restarted. To restart, hold the ON
t
t
t
8
7
ILOAD
GATE
5A/DIV
70
60
50
40
30
20
10
0
20V/DIV
VOUT
20V/DIV
2V/DIV
BRK TMR
FAULT
ON
20V/DIV
20V/DIV
2V/DIV
RST TMR
40ms/DIV
1642a F04
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FB PIN VOLTAGE (mV)
1
Figure 4. Current Limit and Circuit Breaker Timing
Figure 3. Foldback Current Limi1t642a F03
1642af
10
LTC1642A
U
W
U U
APPLICATIO S I FOR ATIO
Q1
FDS6630A
Automatic Restart After the Circuit Breaker Opens
R2
0.015Ω
V
IN
12V
V
OUT
The LTC1642A will automatically attempt to restart itself
after the circuit breaker opens if the FAULT output is tied
to the ON pin. The circuit is shown in Figure 5. Diode D1
blockstheweakFAULTpull-upcurrentsourcefromunbal-
ancing the R6-R5 divider.
2.5A
+
16
15
SENSE
R6
464k
1%
C
LOAD
R3
V
CC
100Ω
4
6
14
ON
FAULT
LTC1642A
GATE
R4
330Ω
D2
1N4705
18V
D1
1N4148
During a continuous current limit such as a load short,
Q1’s duty cycle is equal to the circuit breaker timer period,
divided by the sum of the circuit breaker and system timer
periods:
C2
0.047µF
R5
60.4k
1%
2
BRK TMR
R10
30k
RST TMR
3
GND
8
C4
0.33µF
C1
0.33µF
C4
Short-Circuit Duty Cycle =
C4 + 10•C1
1642a F05
ALL RESISTORS ±5% UNLESS NOTED
Figure 5. Automatic Restart Circuit
The duty cycle is 9% for the Figure 5 circuit. Waveforms
during a load short are shown in Figure 6.
Undervoltage Lockout
VGATE
20V/DIV
An internal undervoltage lockout circuit holds the charge
pump off until VCC exceeds 2.73V. If VCC falls below 2.5V,
it turns off the charge pump and clears overvoltage and
current limit faults.
VOUT
10V/DIV
VBRKTMR
1V/DIV
For higher lockout thresholds tie the ON pin to a resistor
divider driven from VCC, as shown in Figure 7. This
circuit keeps the charge pump off until VCC exceeds
(1+R6/R5) • 1.34V, and also turns it off if VCC falls below
(1+R6/R5) • 1.22V.
VRSTTMR
1V/DIV
40ms/DIV
1642a F06
Figure 6. Automatic Retry Following a Load Short
R2
Q1
0.015Ω
FDS6630A
V
IN
V
12V
OUT
2.5A
+
16
15
SENSE
C
LOAD
V
R6
464k
1%
CC
R3
100Ω
LTC1642A
UNDERVOLTAGE
LOCKOUT
THRESHOLD = 10.7V
14
4
GATE
ON
D1
1N4705
18V
R4
330Ω
R5
60.4k
1%
RST TMR
3
GND
8
C1
0.33µF
C2
0.047µF
1642a F07
ALL RESISTORS ±5% UNLESS NOTED
Figure 7. Setting a Higher Undervoltage Lockout
1642af
11
LTC1642A
U
W
U U
APPLICATIO S I FOR ATIO
Overvoltage Protection
Once the CRWBR timer trips the LTC1642A latches off:
after the overvoltage clears GATE and FAULT remain at
groundandCRWBRcontinuessourcing1.5mA. Torestart
the part after the overvoltage clears, hold the ON pin low
foratleast2µsandthenbringithigh.TheGATEvoltagewill
begin ramping up one system timing cycle later. The part
will restart itself if FAULT and ON are connected.
The LTC1642A can protect a load from overvoltages by
turning off the pass transistor if the supply voltage ex-
ceedsanadjustablelimit, andbytriggeringacrowbarSCR
if the overvoltage lasts longer than an adjustable time. The
part can also be configured to automatically restart when
the overvoltage clears.
Figure 9 shows typical waveforms when the divider is
driven from VCC. The OV comparator goes high at time 1,
causing the chip to pull the GATE pin to ground and start
the CRWBR timer. At time 2, before the timer’s compara-
tor trips, OV falls below its threshold; the timer resets and
GATE begins charging one system timing cycle later at
time 3. Another overvoltage begins at time 4, and at time
5theCRWBRtimertrips;FAULTgoeslowandtheCRWBR
pin begins sourcing 1.5mA. Even after OV falls below
1.22V at time 6, GATE and FAULT stay low, and CRWBR
continues to source 1.5mA. FAULT goes high when ON
goes low at time 7, and GATE begins charging at time 8,
one RST TMR cycle after FAULT goes high.
The overvoltage protection circuitry is shown in Figure 8.
The external components comprise a resistor divider
driving the OV pin, timing capacitor C5, NPN emitter
follower Q2, and crowbar SCR Q3. Because the MCR12DC
is not a sensitive-gate device, the optional resistor shunt-
ing the SCR gate to ground is omitted. The internal
components comprise a comparator, 1.22V bandgap ref-
erence, two current sources, and a timer at the CRWBR
pin.WhenVCCexceeds(1+R6/R5)•1.22Vthecomparator’s
output goes high and internal logic turns off Q1 and starts
the timer. This timer has a 0.410V threshold and uses the
CRWBR pin; when CRWBR reaches 0.410V the timer
comparator trips, and the current sourced from VCC in-
creases to 1.5mA. Emitter follower Q2 boosts this current
to trigger crowbar SCR Q3. The ramp time ∆t needed to
trip the comparator is:
Figure 10 shows typical waveforms when the OV divider is
driven from the N-Channel’s output side. Because the
voltagedrivingthedividercollapsesaftertheOVcompara-
tortrips,FAULTstayshighandCRWBRstaysnearground,
which prevents the pin from triggering an SCR. The GATE
voltage begins ramping up after a RST TMR timing cycle.
tCRWBR = 9.1(ms/µF) C5
R2
Q1
V
0.015Ω
FDS6630A
IN
To disable overvoltage protection completely, tie the OV
andCRWBRpinstoGND.Forovervoltageprotectionatthe
GATE pin, but without latch off or a crowbar SCR such as
Q3 in Figure 1, tie CRWBR to GND.
12V
V
OUT
2.5A
+
R6
127k
1%
16
15
C
LOAD
R3
V
SENSE
CC
100Ω
9
OV
14
GATE
R5
12.4k
1%
t
1
t
t
t
t
t
t
7
t
R4
330Ω
C2
D1
1N4705
18V
2
3
4
5
6
8
IN
20V/DIV
2V/DIV
LTC1642A
0.047µF
OV
Q2
2N2222
4
ON
Q3
MCR12DC
GATE
50V/DIV
6
1
FAULT
CRWBR
OUT
CRWBR
RST TMR
ON
20V/DIV
1V/DIV
2V/DIV
20V/DIV
RST TMR
3
GND
8
C1
0.33µF
* ADD 220Ω RESISTOR IF
USING A SENSITIVE-GATE SCR
C5
0.01µF
ALL RESISTORS ±5% UNLESS NOTED
FAULT
20V/DIV
OV COMPARATOR TRIPS AT V = 13.85V
IN
RESET TIME = 200ms
CROWBAR DELAY TIME = 90µs
100ms/DIV
1642a F09
1642a F08
Figure 9. Overvoltage Timing (Input Side)
Figure 8. Overvoltage Protection Circuitry
1642af
12
LTC1642A
U
W
U U
APPLICATIO S I FOR ATIO
Automatic Restart
The pull-up voltage on the RESET and FAULT pins follows
VCC until the shunt regulator turns on. When the regulator
is on the pull-up voltage is 14.4V.
If there is an overvoltage, and the resistor divider feeding
OV is connected to the output of the N-Channel pass
transistor, the LTC1642A will automatically restart even if
FAULT is not tied to ON. If the divider is connected to the
input side, the LTC1642A will restart itself only if FAULT is
tied to ON, and only after the overvoltage clears.
Undervoltage Monitor
The LTC1642A will assert RESET if a monitored voltage
falls below an adjustable minimum. When the monitored
voltage has exceeded its minimum for at least one system
timing cycle, RESET goes high. The monitoring circuitry
comprises an internal 1.22V bandgap reference, an inter-
nal precision voltage comparator and an external resistive
divider to monitor the output supply voltage.
The OV and FB Comparators
The propagation delay through the OV and FB compara-
tors on low to high transitions depends strongly on the
differential input voltage. The relationship is shown in
Figure 11. The minimum propagation delay for large
overdrives is about 20µs. In addition the comparators
have 3mV of hysteresis.
The circuit is shown in Figure 12, and typical waveforms
in Figure 13. When the voltage at the FB pin rises above its
reset threshold (1.22V), the comparator output goes low
and a timing cycle starts (times 1 and 5). Following the
cycle RESET is pulled high. At time 2 the voltage at FB
drops below the comparator’s threshold and RESET is
pulled low. If the FB pin rises above the reset threshold for
less than a timing cycle the RESET output will remain low
(time 3 to time 4). The 15µA pull-up current source to VCC
onRESEThasaseriesdiodesothepincanbepulledabove
VCC by an external pull-up resistor without forcing current
back into the supply.
Internal Voltage Clamp Protection
The LTC1642A includes a shunt regulator to protect itself
from VCC and SENSE pin voltages up to 33V. The regulator
turns on when VCC exceeds 16.5V and limits most of the
chip’s circuitry to 15V. When it is on the chip functions
normally with one exception: if the charge pump is on, the
GATE voltage is usually near ground but this is not
guaranteed.UsetheOVpintoensurethatGATEisgrounded.
70
60
50
40
30
20
10
0
IN
20V/DIV
2V/DIV
OV
GATE
OUT
20V/DIV
20V/DIV
CRWBR
2V/DIV
2V/DIV
RST TMR
0
40
80
120
160
200
240
FAULT
20V/DIV
OV OVERDRIVE (mV)
100ms/DIV
1642a F10
1642a F11
Figure 10. Overvoltage Timing (Output Side)
Figure 11. OV Comparator Propagation Delay vs
Overdrive Voltage
1642af
13
LTC1642A
U
W
U U
APPLICATIO S I FOR ATIO
The undervoltage monitor behaves differently if FB is
above its threshold when the GATE begins ramping:
RESET goes high as soon as the GATE ramp begins.
Reference
The LTC1642A’s internal voltage reference is buffered and
brought out to the REF pin. The buffer amplifier should be
compensated with a capacitor connected between REF
and ground. If no DC current is drawn from REF, 0.1µF
ensures an adequate phase margin, but the minimum
compensation increases if REF sources a substantial DC
current, as shown in Figure 14.
RESET goes low immediately if VCC falls below the chip’s
2.5V internal undervoltage lockout threshold.
To disable the undervoltage monitor, tie FB to REF and
ground RESET.
R2
Q1
V
IN
0.015Ω
FDS6630A
12V
V
OUT
2.5A
+
16
15
C
LOAD
R3
V
SENSE
CC
100Ω
4
14
ON
GATE
D1
1N4705
18V
R4
t
t
t
3
t
t
5
1
2
4
330Ω
LTC1642A
C2
0.047µF
VIN
20V/DIV
R9
95.3k
1%
7
5
FB
R8
12.4k
1%
VRSTTMR
1V/DIV
RESET
RST TMR GND
VRESET
10V/DIV
3
8
C1
0.33µF
1642a F12
ALL RESISTORS ±5% UNLESS NOTED.
FB COMPARATOR TRIPS AT V = 10.7V
250ms/DIV
1642a F13
OUT
Figure 12. Undervoltage Monitoring Circuitry
Figure 13. Supply Monitor Waveforms
10.0
4.0
2.0
1.0
0.4
0.2
0.1
100µA
1mA
REFERENCE CURRENT
10mA
1642a F14
Figure 14. Minimum REF Compensation vs REF Current
1642af
14
LTC1642A
U
W
U U
APPLICATIO S I FOR ATIO
Uncommitted Comparator
Layout Considerations
The uncommitted comparator has an open drain output.
The comparator has 3mV of hysteresis: the output goes
high when the differential input voltage exceeds 1.5mV
and goes low when the differential input is less than
–1.5mV.
One ounce copper exhibits a sheet resistance of 530µΩ
per square. To minimize self-heating, traces should be
at least 0.02" wide per ampere of current and 0.03" is
recommended.
In high current applications, the voltage drop along traces
can be appreciable. Connect the LTC1642A’s VCC and
SENSE pins directly across sense resistor R2 to prevent
the power trace’s resistance from adding to R2. It is also
a good practice to keep the resistor divider to the ON pin
close to the chip and the divider’s connections to the VCC
and GND pins short. Figure 15 shows an example layout.
The comparator’s input transistors are MOSFETs so the
input bias and offset currents are very small: typically
picoamps at 25°C, increasing to nanoamps at 90°C. If the
auxilliary comparator is unused, the COMP+, COMP– and
COMPOUT pins may be left floating.
R2
I
LOAD
SENSE
RESISTOR, R2
TO SHORT
V
PIN
LT1642A
CC
R6
R5
I
LOAD
1642a F15
Figure 15. Recommended Layout for R1, R2 and R5
1642af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1642A
U
TYPICAL APPLICATIO
12V Hot Swap Circuit for InfiniBand Modules
InfiniBand
BACKPLANE
LONG
InfiniBand
MODULE
R2
Q1
DC/DC
VB_In
CONVERTER
INPUT
R4
330Ω
5%
R3
100Ω
R12
84.5k
1%
R6
127k
1%
R9
681k
1%
D2
1N4705
18V
C2
0.047µF
16
15
SENSE
14
GATE
10
5
R5
UV
V
COMPOUT
RESET
FB
CC
SHORT
10.2k 1%
9
TO CONVERTER'S
RUN/SS
VBxEn_L
OV
11
7
+
COMP
LTC1642A
6
FAULT
ON
4
R11
12.4k
1%
–
REF
COMP CRWBR RST TMR BRK TMR GND
D1*
C7
0.01µF
13
12
1
3
2
8
C5
0.01µF
1N4148
R8
100k
1%
C1*
0.033µF
30k
C6
0.1µF
C4
LONG
0.033µF
TO DC/DC RETURN
VB_Ret
10k
LOCAL POWER
ENABLE
MODULE POWER
R2
Q1
†
†
25W
50W
0.015Ω,5% FDS6612
0.007Ω,5% FDS6680
*INSTALL D1 FOR AUTOMATIC RESTART
IF USING D1, INCREASE C1
START-UP DELAY IS 20ms TYPICAL
CIRCUIT-BREAKER DELAY IS 1ms TYPICAL
1642a TA02
†
FAIRCHILD
(408) 822-2126
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.009
(0.229)
REF
.015 ± .004
(0.38 ± 0.10)
.045 ±.005
16 15 14 13 12 11 10 9
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
0° – 8°
.007 – .0098
(0.178 – 0.249)
TYP
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
.254 MIN
.150 – .165
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
3. DRAWING NOT TO SCALE
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
GN16 (SSOP) 0204
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Hot Swap Controller
Two Supplies from 3V to 12V and –12V
Single Supply from 2.5V to 16.5V, MSOP Package
–48V Supplies, Active Current Limit
LTC4211
Hot Swap Controller with Multifunction Current Control
Negative Voltage Hot Swap Controller in SO-8
PCI-Bus Hot Swap Controller
LT4250
LTC1643
3.3V, 5V, ±12V Supplies for PCI Bus, Active Current Limit
1642af
LT/TP 0605 500 • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1999
相关型号：
LTC1642AIGN#PBF
LTC1642A - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LTC1642AIGN#TR
LTC1642A - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LTC1642CGN#TR
LTC1642 - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
Linear
LTC1642CGN#TRPBF
LTC1642 - Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C
Linear
©2020 ICPDF网 联系我们和版权申明