LTC1609ISW [Linear]
16-Bit, 200ksps, Serial ADC with Multiple Input Ranges; 16位， 200ksps的，具有多种输入范围的串行ADC
| 型号： | LTC1609ISW |
| 厂家： | 
Linear |
| 描述： | 16-Bit, 200ksps, Serial ADC with Multiple Input Ranges |
| 文件： | 总24页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1609
16-Bit, 200ksps, Serial ADC
with Multiple Input Ranges
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FEATURES
DESCRIPTIO
The LTC®1609 is a 200ksps, serial sampling 16-bit A/D
converterthatdrawsonly65mW(typical)fromasingle5V
supply. This easy-to-use device includes a sample-and-
hold, a precision reference, a switched capacitor succes-
sive approximation A/D and trimmed internal clock.
■
Sample Rate: 200ksps
Input Ranges
■
Unipolar: 0V to 10V, 0V to 5V and 0V to 4V
Bipolar: ±10V, ±5V and ±3.3V
■
Guaranteed No Missing Codes
■
Serial I/O
Single 5V Supply
Power Dissipation: 65mW Typ
Power Down Mode: 50µW
SNR: 87dB Typ
The input range is specified for bipolar inputs of ±10V,
±5V and ±3.3V and unipolar inputs of 0V to 10V, 0V to 5V
and 0V to 4V. Maximum DC specs include ±2LSB INL and
16-bit no missing codes over temperature. It has a typical
signal-to-noise ratio of 87dB.
■
■
■
■
■
Operates with Internal or External Reference
■
■
The ADC has a high speed serial interface. The serial
output data can be clocked out using either the internal
serial shift clock or be clocked out by an external shift
clock.Aseparateconvertstartinput(R/C)andadataready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
28-Pin SSOP and 20-Pin SO Packages
Improved 2nd Source to ADS7809 and AD977A
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APPLICATIO S
■
Industrial Process Control
■
Multiplexed Data Acquisition Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
High Speed Data Acquisition for PCs
Digital Signal Processing
■
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TYPICAL APPLICATIO
200kHz, 16-Bit Serial Sampling ADC Configured for ±10V Inputs
200Ω
100Ω
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ANALOG INPUT
–10V TO 10V
R1
V
5V
IN
DIG
+
Nonaveraged 4096 Point FFT Plot
AGND1
V
ANA
0.1µF
10µF
3
0
–20
–40
–60
–80
–100
R2
R3
PWRD
BUSY
CS
IN
f
f
= 200kHz
33.2k
SAMPLE
IN
4
= 1kHz
IN
SINAD = 87.2dB
THD = –100.1dB
5
NC
2.5V
LTC1609
6
CAP
REF
NC
NC
+
2.5V
7
2.2µF
+
8
2.2µF
NC
R/C
NC
9
AGND2
NC
10
11
12
13
14
TAG
NC
SERIAL INTERFACE
NC
SB/BTC
DATA
–120
–130
EXT/INT DATACLK
DGND
SYNC
25
50
FREQUENCY (kHz)
100
0
75
1609 G06
1609 TA01
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LTC1609
ABSOLUTE MAXIMUM RATINGS
W W
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(Notes 1, 2)
VANA .......................................................................... 7V
DIG to VANA ........................................................... 0.3V
VDIG ........................................................................... 7V
Ground Voltage Difference
Digital Input Voltage (Note 4) ........ DGND – 0.3V to 10V
Digital Output Voltage........ DGND – 0.3V to VDIG + 0.3V
Power Dissipation.............................................. 500mW
Operating Ambient Temperature Range
V
DGND, AGND1 and AGND2 .............................. ±0.3V
Analog Inputs (Note 3)
LTC1609AC/LTC1609C............................ 0°C to 70°C
LTC1609AI/LTC1609I ......................... – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
R1IN, R2IN, R3IN ................................................ ±25V
CAP ............................ VANA + 0.3V to AGND2 – 0.3V
REF....................................Indefinite Short to AGND2
Momentary Short to VANA
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PACKAGE/ORDER INFORMATION
ORDER PART
ORDER PART
NUMBER
TOP VIEW
NUMBER
1
2
V
V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R1
DIG
IN
TOP VIEW
AGND1
ANA
LTC1609CG
LTC1609IG
LTC1609CSW
R1
1
2
3
4
5
6
7
8
9
20
19
V
V
IN
DIG
3
PWRD
BUSY
CS
R2
IN
LTC1609ISW
LTC1609ACSW
LTC1609AISW
AGND1
ANA
4
R3
IN
R2
IN
18 PWRD
17 BUSY
16 CS
5
NC
CAP
R3
IN
6
NC
CAP
REF
7
NC
REF
15 R/C
8
R/C
NC
AGND2
SB/BTC
EXT/INT
14 TAG
9
NC
AGND2
NC
13 DATA
12 DATACLK
11 SYNC
10
11
12
13
14
TAG
NC
NC
DGND 10
DATA
DATACLK
SYNC
SB/BTC
EXT/INT
DGND
SW PACKAGE
20-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 130°C/W
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
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CONVERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6).
LTC1609
TYP
LTC1609A
TYP
PARAMETER
CONDITIONS
MIN
16
MAX
MIN
16
MAX
UNITS
Bits
Resolution
●
●
No Missing Codes
Transition Noise
Integral Linearity Error
Differential Linearity Error
Bipolar Zero Error
15
16
Bits
0.9
0.9
LSB
RMS
(Note 7)
●
●
●
±3
3
±2
LSB
–2
–1
1.75
±10
LSB
mV
External Reference = 2.5V (Note 8), Bipolar Ranges
±10
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LTC1609
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CONVERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With external reference (Notes 5, 6).
LTC1609
TYP
LTC1609A
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
ppm/°C
mV
Bipolar Zero Error Drift
Unipolar Zero Error
Unipolar Zero Error Drift
Full-Scale Error Drift
Full-Scale Error
Bipolar Ranges
±2
±2
External Reference = 2.5V, Unipolar Ranges
Unipolar Ranges
●
●
±10
±10
±2
±7
±2
±7
ppm/°C
ppm/°C
%
External Reference = 2.5V (Notes 12, 13)
External Reference = 2.5V
±0.50
±8
±0.25
±8
Full-Scale Error Drift
Power Supply Sensitivity
±2
±2
ppm/°C
V
= V = V
V = 5V ±5% (Note 9)
DD
LSB
ANA
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DIG
DD
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
LTC1609/LTC1609A
SYMBOL PARAMETER
CONDITIONS
4.75V ≤ V
MIN
TYP
MAX
UNITS
V
Analog Input Range (Note 9)
≤ 5.25V, 4.75V ≤ V ≤ 5.25V,
●
±10, 0V to 5V, etc.
(See Tables 1a and 1b)
V
IN
ANA
DIG
C
Analog Input Capacitance
10
pF
IN
R
See Tables 1a and 1b
kΩ
U AnaloW g Input Impedance
IN
DY A IC ACCURACY
(Notes 5, 14)
LTC1609
TYP
LTC1609A
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
S/(N + D) Signal-to-(Noise
+ Distortion) Ratio
1kHz Input Signal (Note 14)
10kHz Input Signal
20kHz, –60dB Input Signal
87.5
87
30
85
87.5
87
30
dB
dB
dB
THD
Total Harmonic
Distortion
1kHz Input Signal, First 5 Harmonics
10kHz Input Signal, First 5 Harmonics
– 100
–94
– 100 –96
–94
dB
dB
Peak Harmonic or
Spurious Noise
1kHz Input Signal
10kHz Input Signal
–102
–94
–102
–94
dB
dB
Full-Power Bandwidth (Note 15)
–3dB Input Bandwidth
Aperture Delay
275
1
275
1
kHz
MHz
ns
40
40
Aperture Jitter
Sufficient to Meet AC Specs Sufficient to Meet AC Specs
Transient Response
Full-Scale Step (Note 9)
2
2
µs
Overvoltage Recovery
150
150
ns
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(UNote 16)
INTERNAL REFERENCE CHARACTERISTICS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1609/LTC1609A
PARAMETER CONDITIONS
MIN
TYP
2.500
±5
MAX
UNITS
V
V
Output Voltage
Output Tempco
I
I
= 0
= 0
●
●
2.470
2.520
V
ppm/°C
µA
REF
REF
OUT
OUT
Internal Reference Source Current
External Reference Voltage for Specified Linearity
External Reference Current Drain
CAP Output Voltage
1
(Notes 9, 10)
2.30
2.50
2.70
100
V
External Reference = 2.5V (Note 9)
µA
I
= 0
2.50
V
1609fa
OUT
3
LTC1609
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1609/LTC1609A
SYMBOL PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
DD
= 4.75V
DD
= 0V to V
IN
●
●
●
2.4
IH
IL
0.8
V
I
±10
µA
pF
V
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
V
= 4.75V
= 4.75V
I = –10µA
4.5
OH
DD
DD
O
I = –200µA
O
●
●
4.0
V
V
Low Level Output Voltage
I = 160µA
O
0.05
0.10
–10
10
V
OL
I = 1.6mA
O
0.4
V
I
I
Output Source Current
Output Sink Current
V
V
= 0V
mA
mA
SOURCE
SINK
OUT
OUT
= V
DD
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TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1609/LTC1609A
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
ns
ns
µs
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns
t
t
t
t
t
t
t
Convert Pulse Width
(Note 11)
●
●
●
40
1
2
3
4
5
6
7
R/C, CS to BUSY Delay
C = 25pF
L
80
3
BUSY Low Time
BUSY Delay After End of Conversion
Aperture Delay
100
5
Conversion Time
●
●
●
3
5
Acquisition Time
2
t + t
6
Throughput Time
7
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
R/C Low to DATACLK Delay
DATACLK Period
260
150
8
9
DATA Valid Setup Time
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
15
40
50
20
20
15
10
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DATA Valid Hold Time
External DATACLK Period
External DATACLK High
External DATACLK Low
R/C, CS to External DATACLK Setup Time
R/C to CS Setup Time
t
12
External DATACLK to SYNC Delay
External DATACLK to DATA Valid Delay
CS to External DATACLK Rising Edge Delay
Previous DATA Valid After CS, R/C Low
BUSY to External DATACLK Setup Time
BUSY Falling Edge to Final External DATACLK
TAG Valid Setup Time
50
50
10
10
2.2
5
(Note 9)
(Note 9)
(Notes 10, 17)
1.2
0
TAG Valid Hold Time
15
1609fa
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LTC1609
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POWER REQUIREMENTS
otherwise specifications are at TA = 25°C. (Note 5)
The ● indicates specifications which apply over the full operating temperature range,
LTC1609/LTC1609A
SYMBOL
PARAMETER
CONDITIONS
(Notes 9, 10)
PWRD = Low
MIN
TYP
MAX
5.25
20
UNITS
V
V
Positive Supply Voltage
Positive Supply Current
Power Dissipation
4.75
DD
I
●
13
mA
DD
P
PWRD = Low
PWRD = High
65
50
100
mW
µW
DIS
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together (unless otherwise noted).
Note 11: With CS low the falling R/C edge starts a conversion. If R/C
returns high at a critical point during the conversion it can create small
errors. For best results ensure that R/C returns high within 1.2µs after the
start of the conversion.
Note 3: When these pin voltages are taken below ground or above V
=
ANA
V
= V , they will be clamped by internal diodes. This product can
DIG
DD
handle input currents of greater than 100mA below ground or above V
without latch-up.
Note 12: As measured with fixed 1% resistors shown in Figures 3a and
3b. Adjustable to zero with external potentiometer.
DD
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents of
90mA below ground without latchup. These pins are not clamped to V
Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of
offset error. For unipolar input ranges full-scale error is the deviation of
the last code transition from ideal divided by the transiton voltage and
includes the effect of offset error.
.
DD
Note 5: V = 5V, f
= 200kHz, t = t = 5ns unless otherwise
r f
DD
SAMPLE
specified.
Note 6: Linearity, offset and full-scale specifications apply for a V input
IN
Note 14: All specifications in dB are referred to a full-scale ±5V input.
with respect to ground.
Note 15: Full-power bandwidth is defined as full-scale input frequency at
which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of
accuracy.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 16: Recovers to specified performance after (2• FS) input
overvoltage.
Note 17: When data is shifted out during a conversion, with an external
data clock, complete the process within 1.2µs from the start of the
conversion (BUSY falling). This will help keep any external disturbances
from causing an error in the conversion result.
Note 8: Bipolar zero error is the offset voltage measured from –0.5 LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Unipolar zero error is the offset voltage measured from
0.5LSB when the output codes flickers between 0000. . .0000 and 0000. .
.0001.
1609fa
5
LTC1609
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TYPICAL PERFOR A CE CHARACTERISTICS
Change in CAP Voltage
vs Load Current
Power Supply Rejection
vs Ripple Frequency
Supply Current vs Supply Voltage
0.05
0.04
0
–10
–20
–30
–40
–50
–60
–70
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
f
= 200kHz
f
= 200kHz
SAMPLE
SAMPLE
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–14 –12 –10 –8 –6 –4 –2
LOAD CURRENT (mA)
0
2
4
5.0
4.75
SUPPLY VOLTAGE (V)
4.5
5.25
5.5
1
10
100
1k
10k 100k 1M
RIPPLE FREQUENCY (Hz)
1609 G03
1609 G02
1609 G01
Nonaveraged 4096 Point FFT Plot
Typical INL Curve
Typical DNL Curve
0
–20
–40
–60
–80
–100
2.0
1.5
2.0
1.5
f
f
= 200kHz
SAMPLE
IN
= 1kHz
SINAD = 87.2dB
THD = –100.1dB
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
–120
–130
32768
CODE
32768
CODE
25
50
100
0
16384
49152
65535
0
16384
49152
65535
0
75
FREQUENCY (kHz)
1609 G04
1609 G05
1609 G06
SINAD vs Input Frequency
THD vs Input Frequency
95
90
85
80
75
70
65
60
–40
–50
–60
–70
–80
–90
–100
–110
1
100
1
100
10
10
FREQUENCY (kHz)
FREQUENCY (kHz)
1609 G07
1609 G08
1609fa
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LTC1609
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(20-Pin SO/28-Pin SSOP)
PIN FUNCTIONS
R1IN (Pin 1/Pin 1): Analog Input. See Table 1 and Figure 1
for input range connections.
low, 16 clock pulses are output during each conversion.
The pin will stay low between conversions.
AGND1(Pin2/Pin2):AnalogGround.Tietoanalogground
DATA (Pin 13/Pin 17): Serial Data Output. The output data
is synchronized to the DATACLK and the format is deter-
minedbySB/BTC.Intheexternalshiftclockmode,after16
bits of data have been shifted out and CS is low and R/C is
high, the level in the TAG pin will be outputted. This can be
used to daisy-chain the serial data output from several
LTC1609s. If EXT/INT is low, the output data is valid on
both the rising and falling edge of the internal shift clock
which is outputted on DATACLK. In between conversions,
DATA will stay at the level of the TAG input when the
conversion was started.
plane.
R2IN (Pin 3/Pin 3): Analog Input. See Table 1 and Figure 1
for input range connections.
R3IN (Pin 4/Pin 4): Analog Input. See Table 1 and Figure 1
for input range connections.
NC (28-Pin SSOP Only—Pins 5, 8, 10, 11, 18, 20, 22,
23): No Connect.
CAP (Pin 5/Pin 6): Reference Buffer Output. Bypass with
2.2µF tantalum capacitor.
TAG(Pin14/Pin19):Taginputisusedintheexternalclock
mode. If EXT/INT is high, digital inputs applied to TAG will
be shifted out on DATA delayed 16 DATACLK pulses as
long as CS is low and R/C is high.
REF (Pin 6/Pin 7): 2.5V Reference Output. Bypass with
2.2µF tantalum capacitor. Can be driven with an external
reference.
AGND2 (Pin 7/Pin 9): Analog Ground. Tie to analog
R/C (Pin 15/Pin 21): Read/Convert Input. With CS low, a
falling edge on R/C puts the internal sample-and-hold into
the hold state and starts a conversion. With CS low, a
rising edge on R/C enables the serial output data.
ground plane.
SB/BTC (Pin 8/Pin 12): Select straight binary or two’s
complement data output format. Tie pin high for straight
binary or tie low for two’s complement format.
CS (Pin 16/Pin 24): Chip Select. Internally OR’d with R/C.
WithR/Clow,afallingedgeonCSwillinitiateaconversion.
With R/C high, a falling edge on CS will enable the serial
output data.
EXT/INT (Pin 9/Pin 13): Select external or internal clock
for shifting out the output data. Tie the pin high to
synchronize the output data to the clock that is applied to
theDATACLKpin.Ifthepinistiedlow,aconvertcommand
will start transmitting the output data from the previous
conversion synchronized to 16 clock pulses that are
outputted on the DATACLK pin.
BUSY (Pin 17/Pin 25): Output Shows Converter Status. It
is low when a conversion is in progress. Data valid on the
rising edge of BUSY. CS or R/C must be high when BUSY
rises or another conversion will start without time for
signal acquisition.
DGND (Pin 10/Pin 14): Digital Ground.
PWRD(Pin18/Pin26):PowerDownInput.Ifthepinistied
high, conversionsareinhibitedandpowerconsumptionis
reduced(10µAtyp). Resultsfromthepreviousconversion
are maintained in the output shift register.
SYNC (Pin 11/Pin 15): Sync Output. If EXT/INT is high,
either a rising edge on R/C with CS low or a falling edge on
CS with R/C high will output a pulse on SYNC synchro-
nized to the external clock applied on the DATACLK pin.
V
ANA(Pin19/Pin27):5VAnalogSupply.Bypasstoground
DATACLK (Pin 12/Pin 16): Either an input or an output
depending on the level set on EXT/INT. The output data is
synchronized to this clock. When EXT/INT is high an
externalshiftclockisappliedtothispin.IfEXT/INTistaken
with a 0.1µF ceramic and a 10µF tantalum capacitor.
VDIG (Pin 20/Pin 28): 5V Digital Supply. Connect directly
to VANA
.
1609fa
7
LTC1609
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FUNCTIONAL BLOCK DIAGRA
C
C
SAMPLE
SAMPLE
20k
R1
R2
R3
IN
IN
IN
10k
5k
V
V
ANA
DIG
20k
ZEROING SWITCHES
4k
REF
2.5V REF
+
REF BUF
COMP
16-BIT CAPACITIVE DAC
–
CAP
(2.5V)
DATA
SUCCESSIVE APPROXIMATION
REGISTER
DATACLK
SYNC
SERIAL INTERFACE
AGND1
AGND2
DGND
INTERNAL
CLOCK
CONTROL LOGIC
1609 BD
CS
R/C
PWRD BUSY
SB/BTC EXT/INT
TAG
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APPLICATIO S I FOR ATIO
the analog signal. During the convert phase, the autozero
switches open, putting the comparator into the compare
mode. The input switch switches CSAMPLE to ground,
injecting the analog input charge onto the summing junc-
tion. This input charge is successively compared with the
binary-weighted charges supplied by the capacitive DAC.
Bit decisions are made by the high speed comparator. At
Conversion Details
The LTC1609 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analogsignaltoa16-bitserialoutput.TheADCiscomplete
with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs. (Please refer to the Digital Interface section for
timing information.)
SAMPLE
Conversion start is controlled by the CS and R/C inputs. At
the start of conversion the successive approximation
register(SAR)isreset. Onceaconversioncyclehasbegun
it cannot be restarted.
SI
C
SAMPLE
R
SAMPLE
HOLD
IN1
V
IN
–
+
R
IN2
C
V
DAC
COMPARATOR
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider to
the sample-and-hold capacitor during the acquire phase
andthecomparatoroffsetisnulledbytheautozeroswitches.
In this acquire phase, a minimum delay of 2µs will provide
enough time for the sample-and-hold capacitor to acquire
DAC
DAC
S
A
R
16-BIT
SHIFT REGISTER
1609 F01
Figure 1. LTC1609 Simplified Equivalent Circuit
1609fa
8
LTC1609
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APPLICATIO S I FOR ATIO
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the end of a conversion, the DAC output balances the VIN
input charge. The SAR contents (a 16-bit data word) that
represents the VIN are loaded into the 16-bit output shift
register.
LT1363 - 50MHz voltage feedback amplifier. 6.3mA sup-
ply current. Good AC/DC specs.
LT1364/LT1365 - Dual and quad 50MHz voltage feedback
amplifiers. 6.3mA supply current per amplifier. Good
AC/DC specs.
Driving the Analog Inputs
LT1468 - 90MHz, 22V/µs 16-bit accurate amplifier
The LTC1609 analog input ranges, along with the nominal
input impedances, are shown in Tables 1a and 1b. The
inputs are overvoltage protected to ±25V. The input im-
pedance can get as low as 10kΩ, therefore, it should be
driven with a low impedance source. Wideband noise
coupling into the input can be minimized by placing a
1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If an
amplifier is to be used to drive the input, care should be
takentoselectanamplifierwithadequateaccuracy,linear-
ity and noise for the application. The following list is a
summary of the op amps that are suitable for driving the
LTC1609. More detailed information is available in the
LinearTechnologydatabooksandLinearViewTM CD-ROM.
LT1469 - Dual LT1468
Offset and Gain Adjustments
The LTC1609 is specified to operate with three unipolar
and three bipolar input ranges. Pins R1IN, R2IN and R3IN
are connected as shown in Tables 1a and 1b for the
different input ranges. The tables also list the nominal
input impedance for each range. Table 1c shows the
output codes for the ideal input voltages of each of the six
input ranges.
TheLTC1609offsetandfull-scaleerrorshavebeentrimmed
at the factory with the external resistors shown in Figures
3aand3b.Thisallowsforexternaladjustmentofoffsetand
full scale in applications where absolute accuracy is im-
portant. The offset and gain adjustment circuits for the six
input ranges are also shown in Figures 3a and 3b. To
adjust the offset for a bipolar input range, apply an input
voltage equal to –0.5LSB where 1LSB = (+FS – –FS)/
65536 and change the offset resistor so the output code is
changing between 1111 1111 1111 1111 and 0000 0000
0000 0000. The gain is trimmed by applying an input
voltage of +FS – 1.5LSB and adjusting the gain trim resis-
tor until the output code is changing between 0111 1111
1111 1110 and 0111 1111 1111 1111. In both cases the
data is in two’s complement format (SB/BTC = LOW)
200Ω
A
IN1
A
IN2
A
IN3
R1
IN
1000pF
1000pF
1000pF
LTC1609
100Ω
R2
IN
IN
R3
1609 F02
Figure 2. Analog Input Filtering
LT1007 - Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
To adjust the offset for a unipolar input range, apply an
input voltage equal to +0.5LSB where 1LSB = +FS/65536.
Then adjust the offset trim resistor until the output code
changes between 0000 0000 0000 0000 and 0000 0000
00000001.Toadjustthegain,applyaninputvoltageequal
to +FS – 1.5LSB and vary the gain trimming resistor until
theoutputcodeischangingbetween1111111111111110
and 1111 1111 1111 1111. In the unipolar case, the data
is in straight binary format (SB/BTC = HIGH). Figures 4a
and 4b show the transfer characteristics of the LTC1609.
LT1097 - Low cost, low power precision amplifier. 300µA
supply current. ±5V to ±15V supplies. Gain bandwidth
product 0.7MHz. DC applications.
LT1227-140MHzvideocurrentfeedbackamplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1360 - 37MHz voltage feedback amplifier. 3.8mA sup-
ply current. ±5V to ±15V supplies. Good AC/DC specs.
LinearView is a trademark of Linear Technology Corporation.
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APPLICATIO S I FOR ATIO
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WITH TRIM
INPUT RANGE
WITHOUT TRIM
(ADJUST OFFSET FIRST AT 0V, THEN ADJUST GAIN)
LTC1609
R1
LTC1609
R1
IN
IN
200Ω
200Ω
AGND1
AGND1
100Ω
100Ω
V
33.2k V
IN
R2
IN
R2
IN
IN
5V
OFFSET
TRIM
R3
IN
R3
IN
0V TO 10V
50k
33.2k
+
+
2.2µF
576k
CAP
CAP
5V
GAIN
TRIM
REF
REF
50k
+
+
2.2µF 2.2µF
2.2µF
AGND2
AGND2
LTC1609
R1
LTC1609
R1
IN
IN
200Ω
200Ω
AGND1
AGND1
100Ω
100Ω
5V
33.2k
R2
IN
R3
IN
R2
R3
IN
IN
OFFSET
TRIM
50k
V
V
0V TO 5V
IN
IN
33.2k
CAP
CAP
5V
576k
+
GAIN
TRIM
REF
REF
2.2µF
50k
+
+
+
2.2µF 2.2µF
2.2µF
AGND2
AGND2
LTC1609
R1
LTC1609
R1
200Ω
200Ω
V
IN
V
IN
IN
IN
AGND1
AGND1
100Ω
100Ω
R2
IN
R3
IN
R2
R3
IN
IN
0V TO 4V
33.2k
33.2k
+
CAP
CAP
5V
5V
2.2µF
576k
GAIN
TRIM
OFFSET
TRIM
REF
REF
50k
50k
+
+
+
2.2µF 2.2µF
2.2µF
AGND2
AGND2
1609 F03a
Figure 3a. Offset/Gain Circuits for Unipolar Input Ranges
Table 1a. Analog Input Range Connections for Figure 3a
ANALOG INPUT
RANGE
CONNECT R1
CONNECT R2
CONNECT R3
TO
INPUT
IMPEDANCE
IN
IN
IN
VIA 200Ω TO
VIA 100Ω TO
0V to 10V
0V to 5V
0V to 4V
AGND
V
AGND
13.3kΩ
IN
AGND
AGND
AGND
V
IN
V
IN
10kΩ
V
IN
10.7kΩ
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WITH TRIM
INPUT RANGE
WITHOUT TRIM
(ADJUST OFFSET FIRST AT 0V, THEN ADJUST GAIN)
LTC1609
LTC1609
200Ω
200Ω
V
IN
R1
R1
IN
V
IN
IN
AGND1
AGND1
R2
R3
R2
R3
IN
IN
IN
IN
100Ω
100Ω
±10V
33.2k
+
33.2k
2.2µF
5V
CAP
CAP
5V
576k
OFFSET
GAIN
TRIM
REF
REF
50k
50k
+
+
TRIM
+
+
+
2.2µF 2.2µF
2.2µF
AGND2
AGND2
LTC1609
R1
LTC1609
R1
IN
IN
200Ω
200Ω
AGND1
AGND1
33.2k
V
100Ω
100Ω
V
R2
IN
R2
IN
IN
IN
5V
OFFSET
TRIM
R3
IN
R3
IN
50k
±5V
+
33.2k
2.2µF
5V
CAP
CAP
576k
GAIN
TRIM
REF
REF
50k
+
+
2.2µF 2.2µF
2.2µF
AGND2
AGND2
LTC1609
R1
LTC1609
R1
200Ω
200Ω
V
V
IN
IN
IN
IN
100Ω
AGND1
AGND1
100Ω
R2
R3
R2
R3
IN
IN
IN
IN
33.2k
+
±3.3V
33.2k
2.2µF
5V
CAP
CAP
5V
576k
GAIN
TRIM
OFFSET
TRIM
REF
REF
50k
50k
+
+
2.2µF 2.2µF
2.2µF
AGND2
AGND2
1609 F03b
Figure 3b. Offset/Gain Circuits for Bipolar Input Ranges
Table 1b. Analog Input Range Connections for Figure 3b
ANALOG INPUT
RANGE
CONNECT R1
CONNECT R2
CONNECT R3
TO
INPUT
IMPEDANCE
IN
IN
IN
VIA 200Ω TO
VIA 100Ω TO
±10V
±5V
V
AGND
CAP
CAP
CAP
22.9kΩ
IN
AGND
V
V
13.3kΩ
IN
IN
±3.3V
V
10.7kΩ
IN
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Table 1c. LTC1609 Output Codes for Ideal Input Voltages
TWO’S COMPLEMENT
(SB/BTC LOW)
STRAIGHT BINARY
(SB/BTC HIGH)
DESCRIPTION
ANALOG INPUT
Full-Scale Range
Least Significant Bit
±10V
±5V
±3.34
102µV
0V to 10V
0V to 5V
0V to 4V
61µV
305µV
153µV
153µV
76µV
+Full Scale (FS – 1LSB) 9.999695V 4.999847V 3.339898V 9.999847V 4.999924V 3.999939V 0111 1111 1111 1111 1111 1111 1111 1111
Midscale
0V
0V
–153µV
–5V
0V
5V
2.5V
2V
0000 0000 0000 0000 1000 0000 0000 0000
1LSB Below Midscale
–Full Scale
–305µV
–10V
–102µV
4.999847V 2.499924V 1.999939V 1111 1111 1111 1111 0111 1111 1111 1111
–3.340000V
0V
0V
0V
1000 0000 0000 0000 0000 0000 0000 0000
011...111
011...110
111...111
BIPOLAR
ZERO
111...110
000...001
000...000
111...111
111...110
100...001
100...000
011...111
011...110
100...001
100...000
000...001
000...000
FSR = +FS – –FS
1LSB = FSR/65536
1LSB = FS/65536
FS – 1LSB
–1 0V
LSB
1
LSB
–FSR/2
FSR/2 – 1LSB
0V
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1609 F04a
1609 F04b
Figure 4a. LTC1609 Bipolar Transfer Characteristics
Figure 4b. LTC1609 Unipolar Transfer Characteristics
2000
Theideal±FSvalueforthe±3.3Vrangeis3.340000V–1LSB
and–3.340000V, respectively. Theexternal33.2kresistor
that is connected between the CAP pin and the R2IN pin,
slightly attenuates the input signal applied to R2IN. With-
out the 33.2k resistor the ±FS value would be 3.333333V
– 1LSB and –3.333333V (zero volt offset), respectively.
1500
1000
500
DC Performance
Onewayofmeasuringthetransitionnoiseassociatedwith
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conver-
sions. For example in Figure 5 the distribution of output
code is shown for a DC input that has been digitized 4096
times. The distribution is Gaussian and the RMS code
transition is about 0.9LSB.
0
–3
–2
–1
0
1
2
3
CODE
1609 F05
Figure 5. Histogram for 4096 Conversions
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Dynamic Performance
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through Nth harmonics.
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 6 shows
a typical LTC1609 FFT plot which yields a SINAD of
87.2dB and THD of –100dB.
Internal Voltage Reference
The LTC1609 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.50V. The full-scale range of the ADC scales
with VREF. The output of the reference is connected to the
input of a unity-gain buffer through a 4k resistor (see
Figure 7). The input to the buffer or the output of the
reference is available at REF. The internal reference can be
overdriven with an external reference if more accuracy is
needed. The buffer output drives the internal DAC and is
available at CAP. The CAP pin can be used to drive a steady
DC load of less than 2mA. Driving an AC load is not
recommended because it can cause the performance of
the converter to degrade.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 6 shows a typical SINAD of 87.2dB with
a 200kHz sampling rate and a 1kHz input.
For minimum code transition noise the REF pin and the
CAP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer
(2.2µF tantalum).
0
f
f
= 200kHz
SAMPLE
IN
= 1kHz
–20
–40
SINAD = 87.2dB
THD = –100.1dB
–60
4k
7
REF
(2.5V)
BANDGAP
REFERENCE
–80
S
V
ANA
2.2µF
–100
+
–
–120
–130
25
50
FREQUENCY (kHz)
100
0
75
6
CAP
(2.5V)
S
1609 F06
INTERNAL
CAPACITOR
DAC
2.2µF
Figure 6. LTC1609 Nonaveraged 4096 Point FFT Plot
1609 F07
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
Figure 7. Internal or External Reference Source
2
2
V22 + V32 + V4 ... + VN
THD = 20log
V1
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Power Shutdown
the sample-and-hold into the hold mode bring CS and
R/C low for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
statusisindicatedbytheBUSYoutputandthisislowwhile
the conversion is in progress.
When the PWRD pin is tied high, power consumption
drops to a typical value of 50µW from a specified maxi-
mum of 100mW. In the power shutdown mode, the result
from the previous conversion is still available in the
internal shift register, assuming the data had not been
clocked out before going into power shutdown.
The conversion result is clocked out serially on the DATA
pin. Itcanbesynchronizedbyusingtheinternaldataclock
or by using an external clock provided by the user. Tying
the EXT/INT pin high puts the LTC1609 in the external
clock mode and the DATACLK pin is a digital input. Tying
theEXT/INTpinlowputsthepartintheinternalclockmode
and the DATACLK pin becomes a digital output.
The internal reference buffer and the reference are shut
down, so the power-up recovery time will be dependent
upon how fast the bypass capacitors on these pins can be
charged. If the internal reference is used, the 4k resistor in
series with the output and the external bypass capacitor,
typically 2.2µF, will be the main time constant for the
power-up recovery time. If an external reference is used,
the reference buffer output will be able to ramp from 0V to
2.5V in 1ms, while charging a typical bypass capacitor of
2.2µF. The recovery time will be less if the bypass capaci-
tor has not completely discharged.
Internal Clock Mode
With the EXT/INT pin tied low, the LTC1609 provides the
data clock on the DATACLK pin. The timing diagram is
shown in Figure 8. Typically, CS is tied low and the R/C
pin is used to start a conversion. During the conversion
a 16-bit word will be shifted out MSB-first on the DATA
pin. This word represents the result from the previous
conversion. The DATACLK pin outputs 16 clock pulses
used to synchronize the data. The output data is valid on
both the rising and falling edges of the clock. After the
LSB bit has been clocked out, the DATA pin will take on
the state of the TAG pin at the start of the conversion. The
DATACLK pin goes low until the next conversion is
requested. The data clock is derived from the internal
conversion clock. To avoid errors from occurring during
the current conversion, minimize the loading on the
DATACLK pin and the DATA pin. For the best conversion
results the external clock mode is recommended.
DIGITAL INTERFACE
Internal Conversion Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 2.7µs. No external adjust-
mentsarerequiredand, withthetypicalacquisitiontimeof
1.5µs, throughput performance of 200ksps is assured.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
t
8
R/C
t
9
t
1
DATACLK
1
2
3
14
B2
15
B1
16
B0
t
11
t
10
B15
(MSB)
DATA
BUSY
B14
B13
t
2
t
3
1609 F08
Figure 8. Serial Data Timing Using Internal Clock (CS, EXT/INT and TAG Tied Low)
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External Clock Mode
pulse on the SYNC pin will be generated on the rising edge
of DATACLK #0. The SYNC output can be captured on the
falling edge of DATACLK #0 or on the rising edge of
DATACLK #1. After the rising edge of DATACLK #1, the
SYNC output will go low and the MSB will be clocked out
ontheDATApin. Thisbitcanbelatchedonthefallingedge
of DATACLK #1 or on the rising edge of DATACLK #2. The
LSBwillbevalidonthefallingedgeofDATACLK#16orthe
rising edge of DATACLK #17. After the rising edge of
DATACLK #17 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #1.
A minimum of 17 clock pulses are required if the data is
captured on falling clock edges.
With the EXT/INT pin tied high, the DATACLK pin becomes
a digital input and the LTC1609 can accept an externally
supplied data clock. There are several ways in which the
conversion results can be clocked out. The data can be
clocked out during or after a conversion with a continuous
or discontinuous data clock. Figures 9 to 12 show the
timing diagram for each of these methods.
External Discontinuous Data Clock Data Read
After the Conversion
Figure 9 shows how the result from the current conver-
sion can be read out after the conversion has been
completed. The externally supplied data clock is running
discontinuously. R/C is used to initiate a conversion with
CS tied low. The conversion starts on the falling edge of
R/C. R/C should be returned high within 1.2µs to prevent
the transition from disturbing the conversion. After the
conversion has been completed (BUSY returning high), a
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will
not degrade the 200kHz throughput. This method mini-
mizes the possible external disturbances that can occur
while a conversion is in progress and will yield the best
performance.
t
12
t
14
t
13
0
1
2
3
15
16
17
EXTERNAL
DATACLK
t
1
R/C
t
t
21
2
t
3
BUSY
t
17
SYNC
DATA
t
12
t
18
B15
(MSB)
B14
B13
B1
B0
TAG0
TAG1
TAG2
t
24
t
23
TAG
TAG0
TAG1
TAG2
TAG3
TAG15
TAG16
TAG17
TAG18
TAG19
1606 F09
Figure 9. Conversion and Read Timing Using an External Discontinuous Data Clock
(EXT/INT Tied High, CS Tied Low). Read Conversion Result After the Conversion
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External Data Clock Data Read After the Conversion
Using the highest frequency permitted for DATACLK
(20MHz), shifting the data out after the conversion will not
degrade the 200kHz throughput.
Figure 10 shows how the result from the current conver-
sion can be read out after the conversion has been com-
pleted. The externally supplied data clock is running
continuously. CS and R/C are first used together to initiate
a conversion and then CS is used to read the result. The
conversion starts on the falling edge of CS with R/C low.
Both CS and R/C should be returned high within 1.2µs to
prevent the transition from disturbing the conversion.
After the conversion has been completed (BUSY returning
high), a pulse on the SYNC pin will be generated after the
first rising edge of DATACLK #1 that occurs after CS goes
low (R/C high). The SYNC output can be captured on the
falling edge of DATACLK #1 or on the rising edge of
DATACLK #2. After the rising edge of DATACLK #2, the
SYNC output will go low and the MSB will be clocked out
on the DATA pin. This bit can be latched on the falling edge
of DATACLK #2 or on the rising edge of DATACLK #3. The
LSBwillbevalidonthefallingedgeofDATACLK#17orthe
rising edge of DATACLK #18. After the rising edge of
DATACLK #18 the DATA pin will take on the value of the
TAG pin that occurred at the rising edge of DATACLK #2.
External Discontinuous Data Clock Data Read
During the Conversion
Figure 11 shows how the result from the previous conver-
sion can be read out during the current conversion. The
externally supplied data clock is running discontinuously.
R/C is used to initiate a conversion with CS tied low. The
conversion starts on the falling edge of R/C. R/C should be
returned high within 1.2µs to prevent the transition from
disturbing the conversion. A pulse on the SYNC pin will be
generated on rising edge of DATACLK #0. The SYNC
output can be captured on the falling edge of DATACLK #0
or on the rising edge of DATACLK #1. After the rising edge
of DATACLK #1, the SYNC output will go low and the MSB
will be clocked out on the DATA pin. This bit can be latched
on the falling edge of DATACLK #1 or on the rising edge of
DATACLK #2. The LSB will be valid on the falling edge of
DATACLK #16. Another clock pulse would be needed if the
LSB is captured on a rising edge. A minimum of 17 clock
pulses are required if the data is captured on falling clock
edges.
t
12
t
14
t
13
0
1
2
3
4
17
18
EXTERNAL
DATACLK
t
19
t
t
1
15
CS
t
t
16
16
R/C
t
t
3
2
BUSY
t
17
SYNC
DATA
t
12
t
18
B15
(MSB)
B14
B1
B0
TAG0
TAG1
t
24
t
23
TAG
TAG0
TAG1
TAG2
TAG15
TAG16
TAG17
TAG18
TAG19
1606 F10
Figure 10. Conversion and Read Timing with External Clock (EXT/INT Tied High). Read After Conversion
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t
12
t
14
t
13
0
1
2
15
16
EXTERNAL
DATACLK
t
15
t
1
R/C
t
2
t
3
t
21
BUSY
t
22
t
17
SYNC
DATA
t
18
B15
(MSB)
B14
B1
B0
1606 F11
Figure 11. Conversion and Read Timing Using a Discontinuous Data Clock (EXT/INT Tied High, CS Tied Low).
Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2µs
To minimize the possible external disturbances that can
occur while a conversion is in progress, the data needs to
be shifted out within 1.2µs from the start of the conver-
sion. Using the maximum data clock frequency of 20MHz
will ensure this condition is met.
To minimize the possible external disturbances that can
occur while a conversion is in progress, the data needs to
be shifted out within 1.2µs from the start of the conver-
sion. Using the maximum data clock frequency of 20MHz
willensurethisconditionismet.Sincethereisnothrough-
put penalty for clocking the data out after the conversion,
clocking the data out during the conversion is not recom-
mended.
External Data Clock Data Read During the Conversion
Figure 12 shows how the result from the previous conver-
sion can be read out during the current conversion. The
externally supplied data clock is running continuously. CS
and R/C are used to initiate a conversion and read the data
from the previous conversion. The conversion starts on
the falling edge of CS after R/C is low. A pulse on the SYNC
pin will be generated on the first rising edge of DATACLK
#1 after R/C has returned high. The SYNC output can be
captured on the falling edge of DATACLK #1 or on the
rising edge of DATACLK #2. After the rising edge of
DATACLK#2theSYNCoutputwillgolowandtheMSBwill
be clocked out on the DATA pin. This bit can be latched on
the falling edge of DATACLK #2 or on the rising edge of
DATACLK #3. The LSB will be valid on the falling edge of
DATACLK #17 or the rising edge of DATACLK #18. After
the rising edge of DATACLK #18 the DATA pin will take on
the value of the TAG pin that occurred at the rising edge of
DATACLK #2.
Use of the TAG Input
The TAG input pin is used to daisy-chain multiple convert-
ers. This is useful for applications where hardware con-
straints may limit the number of lines needed to interface
to a large number of converters. This mode of operation
works only using the external clock method of shifting out
the data.
Figure13showshowthisfeaturecanbeused. R/C, CSand
the DATACLK are tied together on both LTC1609s. CS can
begroundedifadiscontinuousdataclockisused. Afalling
edge on R/C will allow both LTC1609s to capture their
respective analog input signals simultaneously. Once the
conversion has been completed the external data clock
DCLKisstarted. TheMSBfromdevice#1willbevalidafter
the rising edge of DCLK #1. Once the LSB from device #1
has been shifted out on the rising edge of DCLK #16, a null
1609fa
17
LTC1609
APPLICATIO S I FOR ATIO
W U U
U
t
12
t
14
t
t
19
13
0
1
2
3
4
16
17
18
EXTERNAL
DATACLK
CS
R/C
t
t
15
16
t
2
t
3
BUSY
t
17
SYNC
DATA
t
12
t
18
B15
(MSB)
B14
B13
B1
B0
TAG0
TAG1
t
24
t
23
TAG
TAG0
TAG1
TAG2
TAG3
TAG15
TAG16
TAG17
TAG18
TAG19
1606 F12
Figure 12. Conversion and Read Timing Using an External Data Clock (EXT/INT Tied High).
Read Previous Conversion Result During the Conversion. For Best Performance, Complete Read in Less Than 1.2µs
bit will be shifted out on the following clock pulse before
LTC1609
#2
LTC1609
#1
the MSB from device #2 becomes available (Figure 14).
The reason for this is the MSB from device #2 will not be
valid soon enough to meet the minimum setup time of
device #1’s TAG input. A minimum of 34 clock pulses are
needed to shift out the results from both LTC1609s
assuming the data is captured on the falling clock edge.
Using the highest frequency permitted for DATACLK
(20MHz), a 200kHz throughput can still be achieved.
TAG
DATA
TAG
DATA
DATA OUT
CS
R/C
CS
R/C
DCLK
DCLK
DCLK IN
R/C IN
CS IN
1609 F13
Figure 13. Two LTC1609s Cascaded
Together Using the TAG Input
1609fa
18
LTC1609
W U U
APPLICATIO S I FOR ATIO
U
R/C
BUSY
DCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
• • •
• • •
NULL
BIT
DATA
OUT
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B15 B14 B13 B12 B11 B10
1609 F14
DEVICE DATA #1
DEVICE DATA #2
Figure 14. Data Output from Cascading Two (CS = Low, TAG (#2) = Low) LTC1609s Together
Output Data Format
Pay particular attention to the design of the analog and
digital ground planes. Placing the bypass capacitor as
close as possible to the VDIG and VANA pins, the REF pin
and reference buffer output is very important. Low imped-
ance common returns for these bypass capacitors are
essential to low noise operation of the ADC, and the foil
width for these tracks should be as wide as possible. Also,
since any potential difference in grounds between the
signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedance as much as pos-
sible. The digital output latches and the onboard sampling
clock have been placed on the digital ground plane. The
two ground planes are tied together at the power supply
ground connection.
The SB/BTC pin controls the format of the serial digital
output word. With the pin tied high the format is straight
binary. With the pin tied low the data format is two’s
complement. See Table 1c.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1609, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
A “postage stamp” (1.6in × 1.5in) evaluation board is
availableandallowsfastin-situevaluationoftheLTC1609.
See Figures 15a through 15d, inclusive.
1609fa
19
LTC1609
W U U
U
APPLICATIO S I FOR ATIO
C6
2.2µF
E14
GND
C4
1000pF
C5
2.2µF
C2
1000pF
C3
1000pF
E8
5V
C1
C7
R4
10µF
0.1µF
200Ω
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
E15
R1
V
DIG
IN
R4
E13
R5
100Ω
AGND1
V
ANA
PWRD
R1 10k
R2 10k
3
E16
R5
R2
R3
PWRD
BUSY
CS
IN
IN
E12
CS
4
E1
IN
E3
BUSY
R3
5
R6
33k
NC
LTC1609
6
E17
R6
CAP
REF
NC
NC
7
8
E4
RC
NC
R/C
NC
E11
TAG
9
AGND2
NC
R3 10k
10
11
12
13
14
TAG
NC
5V
NC
E5
DATA
JP1
SB/BTC
DATA
E6
DATACLK
EXT/INT DATACLK
DGND
SYNC
E7
JP2
SYNC
E10
GND
1609 F15a
E2
GND
Figure 15a. LTC1609 “Postage Stamp” Evaluation Circuit Schematic
1609fa
20
LTC1609
W U U
APPLICATIO S I FOR ATIO
U
Figure 15b. LTC1609 “Postage Stamp” Evaluation Board
Silkscreen (2× Actual Size)
Figure 15c. LTC1609 “Postage Stamp” Evaluation Board
Top Metal Layer (2× Actual Size)
Figure 15d. LTC1609 “Postage Stamp” Evaluation Board
Bottom Metal Layer (2× Actual Size)
1609fa
21
LTC1609
W U U
U
APPLICATIO S I FOR ATIO
LTC1609
LTC1609
200Ω
R1
IN
R1
V
IN
IN
200Ω
AGND1
AGND1
33.2k
0V TO 10V
±10V
100Ω
V
R2
IN
R2
IN
IN
100Ω
33.2k
OFFSET
R3
IN
R3
IN
LTC1662
OFFSET
TRIM
LTC1662
+
TRIM
2.2µF
CS/LD
SCK
SDI
CS/LD
SCK
SDI
V
CS/LD
SCK
SDI
CS/LD
SCK
SDI
V
OUTA
GND
V
OUTA
GND
V
CAP
CAP
GAIN
TRIM
GAIN
TRIM
CC
787k
CC
787k
5V
REF
V
REF
5V
REF
REF
V
OUTB
OUTB
+
+
+
+
+
2.2µF
2.2µF
2.2µF
AGND2
AGND2
0.1µF
0.1µF
LTC1609
R1
LTC1609
R1
IN
IN
200Ω
200Ω
AGND1
AGND1
33.2k
0V TO 5V
±5V
100Ω
100Ω
33.2k
V
R2
IN
R2
IN
IN
OFFSET
TRIM
V
R3
IN
OFFSET
TRIM
R3
IN
LTC1662
LTC1662
IN
+
2.2µF
CS/LD
SCK
SDI
CS/LD
V
CS/LD
SCK
SDI
CS/LD
SCK
SDI
V
OUTA
GND
V
OUTA
GND
V
CAP
CAP
SCK
SDI
REF
GAIN
TRIM
GAIN
TRIM
CC
787k
CC
787k
5V
V
REF
5V
REF
V
REF
OUTB
OUTB
+
+
2.2µF
2.2µF
2.2µF
AGND2
AGND2
0.1µF
0.1µF
LTC1609
R1
LTC1609
R1
200Ω
200Ω
V
IN
V
IN
IN
IN
AGND1
AGND1
100Ω
0V TO 4V
±3.3V
100Ω
R2
IN
R2
IN
33.2k
33.2k
787k
OFFSET
TRIM
R3
IN
LTC1662
OFFSET
TRIM
R3
IN
+
LTC1662
2.2µF
CS/LD
SCK
SDI
CS/LD
V
CS/LD
SCK
SDI
CS/LD
SCK
SDI
V
OUTA
GND
OUTA
GND
V
+
+
CAP
CAP
SCK
SDI
REF
2.2µF
2.2µF
GAIN
TRIM
GAIN
TRIM
V
CC
CC
787k
2.2µF
5V
V
REF
5V
REF
V
REF
OUTB
OUTB
AGND2
AGND2
0.1µF
0.1µF
1609 F16
OFFSET/GAIN CIRCUITS FOR UNIPOLAR INPUT RANGES
OFFSET/GAIN CIRCUITS FOR BIPOLAR INPUT RANGES
Figure 16. Digitally-Controlled Offset and Full-Scale Adjust Circuits Using
the LTC1662 Dual 10-Bit VOUT DAC (Adjust Offset First at 0V, Then Adjust Gain)
1609fa
22
LTC1609
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
10.07 – 10.33*
(.397 – .407)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
7.65 – 7.90
(.301 – .311)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
5.20 – 5.38**
(.205 – .212)
1.73 – 1.99
(.068 – .078)
0° – 8°
.65
(.0256)
BSC
.13 – .22
.55 – .95
(.005 – .009)
(.022 – .037)
.05 – .21
.25 – .38
(.010 – .015)
(.002 – .008)
NOTE:
G28 SSOP 0501
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1609fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
23
LTC1609
U
PACKAGE DESCRIPTIO
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
0.496 – 0.512*
(12.598 – 13.005)
19 18
16 14 13 12 11
20
17
15
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
BSC
0.004 – 0.012
0.009 – 0.013
(0.102 – 0.305)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
(0.229 – 0.330)
0.014 – 0.019
S20 (WIDE) 1098
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1417
Low Power 400ksps 14-Bit ADC
Low Power 200ksps 14-Bit ADC
16-Bit Mulitplying DACs
20mW, Single 5V or ±5V, Serial I/O
LTC1418
15mW, Single 5V or ±5V, Serial/Parallel I/O
Low Glitch, Serial I/O, SO-8/S16 Packages
4-Quadrant Resistors On-Chip, Low Glitch, Parallel I/O
±2.5V Input, 90dB SINAD, 100dB THD, Parallel I/O
Single 5V, ±10V Input
LTC1595/LTC1596
LTC1597
16-Bit Mulitplying DAC
LTC1604
16-Bit 333ksps Sampling ADC
Low Power 100ksps 16-Bit ADC
Low Power 100ksps 16-Bit ADC
Low Power 100ksps 16-Bit ADC
Low Power 250ksps 16-Bit ADC
16-Bit 500ksps Sampling ADC
16-Bit ±5V Voltage Output DAC
16-Bit Single 5V/3V Voltage Output DACs
LTC1605
LTC1605-1
LTC1605-2
LTC1606
Single 5V, 0V to 4V Input
Single 5V, ±4V Input
Single 5V, ±10V Input, Parallel I/O
LTC1608
±2.5V Input, Pin Compatible with LTC1604
Low Glitch, 4µs Settling Time, Serial I/O
SO-8 Package, Micropower, Serial I/O
LTC1650
LTC1655/LTC1655L
1609fa
LT/TP 0302 1.5K REV A • PRINTED IN THE USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2000
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