LTC1553LCG#PBF [Linear]
LTC1553L - 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® II Processor; Package: SSOP; Pins: 20; Temperature Range: 0°C to 70°C;
| 型号： | LTC1553LCG#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1553L - 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® II Processor; Package: SSOP; Pins: 20; Temperature Range: 0°C to 70°C 开关 控制器 |
| 文件： | 总24页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1553
5-Bit Programmable
Synchronous Switching
Regulator Controller for
Pentium® II Processor
U
FEATURES
DESCRIPTION
The LTC®1553 is a high power, high efficiency switching
regulator controller optimized for 5V or 12V input to 1.8V-
3.5Voutputapplications.Itfeaturesadigitallyprogrammable
output voltage, a precision internal reference and an internal
feedback system that provides output accuracy of ±1.5% at
roomtemperatureandtypically±2%over-temperature, load
current and line voltage shifts. The LTC1553 uses a synchro-
nous switching architecture with two external N-channel
output devices, providing high efficiency and eliminating the
need for a high power, high cost P-channel device. Addition-
ally, it senses the output current across the on-resistance of
the upper N-channel FET, providing an adjustable current
limit without an external low value sense resistor.
■
5-Bit Digitally Programmable 1.8V to 3.5V Fixed
Output Voltage
■
Provides All Features Required by the Intel
Pentium® II Processor VRM 8.2 DC/DC
Converter Specification
Flags for Power Good, Over-Temperature and
Overvoltage Fault
■
■
19A Output Current Capability from a 5V or 12V Supply
■
Dual N-Channel MOSFET Synchronous Driver
■
Initial Output Accuracy: ±1.5%
■
Excellent Output Accuracy: ±2% Typ Over Line,
Load and Temperature Variations
High Efficiency: Over 95% Possible
■
■
Adjustable Current Limit Without External Sense
The LTC1553 free-runs at 300kHz and can be synchronized
to a faster external clock if desired. It includes all the inputs
and outputs required to implement a power supply conform-
ing to the Intel Pentium® II Processor VRM 8.2 DC/DC
Converter Specification.
Resistors
Fast Transient Response
■
■
Available in 20-Lead SSOP and SW Packages
U
APPLICATIONS
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
■
Power Supply for Pentium II, SPARC, ALPHA and
PA-RISC Microprocessors
■
High Power 5V or 12V to 1.8V-3.5V Regulators
U
PV
CC
12V
V
IN
5V
TYPICAL APPLICATION
+
0.1µF
10µF
+
+
C
**
IN
2.7k
0.1µF
10µF
1200µF
× 4
5.6k
5.6k
5.6k
V
CC
I
MAX
PV
CC
PWRGD
FAULT
†
L
O
Q1*
Q2*
G1
2µH
18A
PENTIUM® II
SYSTEM
V
OUT
20Ω
OT
1.8V TO
3.5V
14A
5
LTC1553
I
FB
VID0 TO VID4
OUTEN
††
C
+
OUT
330µF
× 7
G2
COMP
SS
SGND
GND
SENSE
R
C
8.2k
C1
150pF
C
SS
0.1µF
C
*
SILICONIX SUD50N03-10
C
0.1µF
0.01µF
** SANYO 10MV1200GX
†
COILTRONICS CTX02-13198 OR
PANASONIC 12TS-2R5SP
††
AVX TPSE337M006R0100
1553 F01
Figure 1. 5V to 1.8V-3.5V Supply Application
1
LTC1553
W W U W
U
W U
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW
ORDER PART
NUMBER
Supply Voltage
1
2
G1
20
19
18
17
16
15
14
13
12
11
G2
V
CC ........................................................................ 9V
OUTEN
VID0
VID1
VID2
VID3
VID4
PWRGD
FAULT
OT
PV
CC
PVCC ................................................................... 20V
Input Voltage
3
GND
LTC1553CG
LTC1553CSW
4
SGND
IFB (Note 2)............................................ PVCC + 0.3V
5
V
CC
IMAX ...................................................... –0.3V to 13V
All Other Inputs ......................... –0.3V to VCC + 0.3V
Digital Output Voltage............................... –0.3V to 13V
6
SENSE
7
I
MAX
8
I
FB
9
SS
I
FB Input Current (Notes 2, 3) .......................... –100mA
10
COMP
Operating Temperature Range ..................... 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
G PACKAGE
SW PACKAGE
20-LEAD PLASTIC SSOP 20-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 100°C/ W (G)
TJMAX = 125°C, θJA = 100°C/ W (SW)
Consult factory for Industrial and Military grade parts.
VCC = 5V, PVCC = 12V, TA = 25°C, unless otherwise noted. (Note 3)
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
8
UNITS
V
Supply Voltage
●
●
4.5
V
V
V
CC
PV
Supply Voltage for G1, G2
Internal Feedback Voltage
18
CC
V
V
(Note 4)
1.265
FB
OUT
1.8V Initial Output Voltage
2.8V Initial Output Voltage
3.5V Initial Output Voltage
1.8V Initial Output Voltage
2.8V Initial Output Voltage
3.5V Initial Output Voltage
With Respect to Rated Output Voltage (Figure 2)
– 27 (–1.5%)
– 42 (–1.5%)
– 52 (–1.5%)
– 36 (–2%)
– 56 (–2%)
– 70 (–2%)
27 (+1.5%)
42 (+ 1.5%)
52 (+1.5%)
36 (+2%)
56 (+2%)
70 (+2%)
mV
mV
mV
mV
mV
mV
●
●
●
∆V
OUT
Output Load Regulation
Output Line Regulation
I
V
= 0 to 14A (Note 4) (Figure 2)
OUT
–5
±1
mV
mV
= 4.75V to 5.25V, I
= 0 (Note 4)(Figure 2)
IN
OUT
V
Positive Power Good Trip Point
Negative Power Good Trip Point
% Above Output Voltage (Figure 2)
% Below Output Voltage (Figure 2)
●
●
5
–5
7
%
%
PWRGD
–7
12
V
FAULT Trip Point
% Above Output Voltage (Figure 2)
●
15
20
%
FAULT
I
I
f
Operating Supply Current
Shutdown Supply Current
OUTEN = V = 5V (Note 5) (Figure 3)
OUTEN = 0, VID0 to VID4 Floating (Figure 3)
●
●
800
130
1200
250
µA
µA
CC
CC
Supply Current
PV = 12V, OUTEN = V (Note 6) (Figure 3)
15
1
mA
µA
PVCC
OSC
CC
CC
PV = 12V, OUTEN = 0, VID0 to VID4 Floating
CC
Internal Oscillator Frequency
(Figure 4)
(Note 4)
(Note 4)
●
250
300
1.8
2.8
53
350
2.3
kHz
V
V
V
V
at Minimum Duty Cycle
at Maximum Duty Cycle
V
V
SAWL
SAWH
COMP
COMP
G
Error Amplifier Open-Loop DC Gain (Note 7)
●
●
40
dB
ERR
g
Error Amplifier Transconductance
Error Amplifier –3dB Bandwidth
(Note 7)
0.9
1.6
400
millimho
kHz
mERR
BW
COMP = Open (Note 4)
ERR
2
LTC1553
VCC = 5V, PVCC = 12V, TA = 25°C, unless otherwise noted. (Note 3)
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
150
–13
30
TYP
180
–10
60
MAX
220
–7
UNITS
µA
I
I
I
I
Sink Current
V
V
V
= V
CC
●
●
●
IMAX
SS
MAX
IMAX
Soft Start Source Current
= 0V, V
= 0V, V = V
CC
µA
SS
IMAX
IFB
Maximum Soft Start Sink Current
Under Current Limit
= V , V
= V , V = 0V
150
µA
SSIL
SENSE
OUT IMAX
CC IFB
(Notes 8, 9), V = V
SS
CC
I
Soft Start Sink Current Under Hard
Current Limit
V
= 0V, V
= V , V = 0V
●
20
45
mA
SSHIL
SENSE
IMAX
CC IFB
t
t
t
t
t
Hard Current Limit Hold Time
Power Good Response Time↑
Power Good Response Time↓
FAULT Response Time
V
V
V
V
= 0V, V
= 4V, V ↓ from 5V (Note 4)
500
1
µs
ms
µs
µs
µs
V
SSHIL
PWRGD
PWRBAD
FAULT
OT
SENSE
SENSE
SENSE
SENSE
IMAX
IFB
↑ from 0V to Rated V
●
●
●
●
●
●
●
●
●
●
●
●
●
0.5
200
200
15
2
OUT
↓ from Rated V
↑ from Rated V
to 0V
500
500
40
1000
1000
60
OUT
OUT
to V
CC
OT Response Time
OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3)
OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3)
OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3)
OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3)
(Figure 4)
V
V
V
Over-Temperature Trip Point
Over-Temperature Driver Disable
Shutdown
1.9
1.6
2
2.12
1.8
OT
1.7
V
OTDD
SHDN
0.8
V
t , t
Driver Rise and Fall Time
Driver Nonoverlap Time
90
100
84
150
ns
ns
%
V
r
f
t
(Figure 4)
30
77
2
NOL
DC
Maximum G1 Duty Cycle
VID0 to VID4 Input High Voltage
VID0 to VID4 Input Low Voltage
(Figure 4)
88
MAX
V
V
IH
IL
0.8
V
R
VID0 to VID4 Internal Pull-Up
Resistance
10
10
20
kΩ
IN
I
Digital Output Sink Current
●
mA
SINK
The
● denotes specifications which apply over the full operating
Note 6: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC1553 operating frequency, supply voltage and the external FETs
used.
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 7: The open-loop DC gain and transconductance from the SENSE pin to
Note 2: When I is taken below GND, it will be clamped by an internal
FB
COMP pin will be (G )(1.265/3.3) and (g )(1.265/3.3) respectively.
diode. This pin can handle input currents greater than 100mA below GND
without latchup. In the positive direction, it is not clamped to V or PV
ERR
mERR
.
CC
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be zero.
Note 9: Under typical soft current limit, the net soft start discharge current
CC
Note 3: All currents into device pins are positive; all currents out of the
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
will be 60µA (I ) + [–10µA(I )] = 50µA. The soft start sink-to-source
SSIL
SS
current ratio is designed to be 6:1.
Note 4: This parameter is guaranteed by correlation and is not tested
directly.
Note 10: When VID0 to VID4 are all HIGH, the LTC1553 will be forced to
shut down internally. The OUTEN trip voltages are guaranteed by design for
all other input codes.
Note 5: The LTC1553 goes into the shutdown mode if VID0 to VID4 are
floating. Due to the internal pull-up resistors, there will be an additional
0.25mA/pin if any of the VID0 to VID4 pins are pulled low.
3
LTC1553
TYPICAL PERFORMANCE CHARACTERISTICS
U W
Typical 2.8V VOUT Distribution
Efficiency vs Load Current
Load Regulation
100
90
80
70
60
50
40
30
20
10
0
2.825
2.820
2.815
2.810
2.805
2.800
2.795
2.790
2.785
2.780
2.775
140
120
REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
TOTAL SAMPLE SIZE = 1500
A
B
V
= 5V, PV = 12V, T = 25°C
IN
CC
A
100
REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
80
60
40
20
V
C
= 5V, PV = 12V, V
= 2.8V,
IN
OUT
CC
OUT
= 330µF ×7, L = 2µH
25°C
100°C
O
A: Q1 = 1 × SUD50N03-10
Q2 = 1 × SUD50N03-10
B: Q1 = 2 × SUD50N03-10
Q2 = 1 × SUD50N03-10
NO FAN
2
Q1 IS MOUNTED ON 1IN COPPER AREA
0
0
2
4
6
8
10
12
14
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
2.775
2.815
2.825
2.785
2.795
2.805
OUTPUT VOLTAGE (V)
0.3
LOAD CURRENT (A)
OUTPUT CURRENT (A)
1533 G02
1533 G03
1553 G01
Over-Temperature Trip Point
vs Temperature
Line Regulation
Output Temperature Drift
2.12
2.10
2.08
2.06
2.04
2.02
2.00
1.98
1.96
1.94
1.92
1.90
2.860
2.850
2.840
2.830
2.820
2.810
2.800
2.790
2.780
2.770
2.660
2.750
2.740
2.825
2.820
2.815
2.810
2.805
2.800
2.795
2.790
2.785
2.780
2.775
REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
OUTPUT = NO LOAD
T
A
= 25°C
–50
–25
0
25
50
75 100 125
0
25
50
75
125
4.75
4.85
4.95
INPUT VOLTAGE (V)
5.05
5.15
5.25
–50
100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
1553 G06
1553 G04
1553 G05
Error Amplifier Transconductance
vs Temperature
Error Amplifier Open-Loop
DC Gain vs Temperature
Over-Temperature Driver Disable
vs Temperature
1.80
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
2.3
2.1
60
55
50
45
1.9
1.7
1.5
1.3
1.1
0.9
40
–50
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
–25
–50 –25
0
25
75
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
1553 G07
1553 G08
1553 G09
4
LTC1553
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Soft Start Source Current
vs Temperature
IMAX Sink Current
vs Temperature
350
340
330
320
310
300
290
280
270
260
250
220
210
200
190
180
170
160
150
–7
–8
–9
–10
–11
–12
–13
–50
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
–25
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
1553 G10
1553 G11
1553 G12
Maximum G1 Duty Cycle
vs Temperature
VCC Operating Supply Current
vs Temperature
VCC Shutdown Supply Current
vs Temperature
92
1.2
1.1
250
OSCILLATOR FREQUENCY = 300kHz
V
= 5V
= 300kHz
CC
90
88
86
225
200
f
OSC
1.0
0.9
0.8
0.7
0.6
G1, G2 CAPACITANCE = 1100pF
175
150
125
100
75
2200pF
3300pF
84
82
5500pF
7700pF
80
78
0.5
50
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
1553 G13
1553 G14
1553 G15
PVCC Supply Current
vs Gate Capacitance
Output Over Current Protection
Transient Response
70
60
3.0
2.5
PV = 12V
CC
= 25°C
T
A
Q1 CASE = 90°C, V
Q1 = 2 × MTD20N03HDL
Q2 = 1 × MTD20N03HDL
= 2.8V
OUT
50
50mV/DIV
5A/DIV
2.0
R
= 2.7k, R = 20Ω,
IMAX
IFB
SS CAP = 0.01µF
40
30
20
10
1.5
1.0
SHORT-CIRCUIT
CURRENT
1553 G18
0.5
0
100µs/DIV
0
2000
4000
8000
0
6000
0
2
4
6
8
10 12 14 16 18
GATE CAPACITANCE (pF)
OUTPUT CURRENT (A)
1553 G16
1553 G17
5
LTC1553
U
U
U
PIN FUNCTIONS
G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET,
Q2. ThisoutputwillswingfromPVCC toGND. Itwillalways
be low when G1 is high or when the output is disabled. To
preventundershootduringasoftstartcycle,G2isheldlow
until G1 first goes high.
IMAX (Pin 7): Current Limit Threshold. Current limit is set
by the voltage drop across an external resistor connected
betweenthedrainofQ1andIMAX.Thereisa180µAinternal
pull-down at IMAX
.
IFB (Pin 8): Current Limit Sense Pin. Connect to the
switching node between the source of Q1 and the drain of
Q2. If IFB drops below IMAX when G1 is on, the LTC1553
will go into current limit. The current limit circuit can be
disabled by floating IMAX and shorting IFB to VCC through
an external 10k resistor. For VIN = 12V, a 15V Zener diode
from IFB to GND is recommended to prevent the voltage
spike at IFB from exceeding the maximum voltage rating.
PVCC (Pin 2): Power Supply for G1 and G2. PVCC must be
connected to a potential of at least VIN + VGS(ON)Q1. If
VIN = 5V, PVCC can be generated using a simple charge
pump connected to the switching node between Q1 and
Q2(seeFigure7),oritcanbeconnectedtoanauxiliary12V
supply if one exists. For applications where VIN = 12V,
PVCC can be generated using a 17V charge pump (see
Figure 9).
SS (Pin 9): Soft Start. Connect to an external capacitor to
implementasoftstartfunction. Duringmoderateoverload
conditions, the soft start capacitor will be discharged
slowly in order to reduce the duty cycle. In hard current
limit, the soft start capacitor will be forced low immedi-
ately and the LTC1553 will rerun a complete soft start
cycle. CSS mustbeselectedsuchthatduringpower-upthe
current through Q1 will not exceed the current limit value.
GND (Pin 3): Power Ground. GND should be connected to
a low impedance ground plane in close proximity to the
source of Q2.
SGND (Pin 4): Signal Ground. SGND is connected to the
low power internal circuitry and should be connected to
the negative terminal of the output capacitor where it
returns to the ground plane. GND and SGND should be
shorted right at the LTC1553.
COMP (Pin 10): External Compensation. The COMP pin is
connected directly to the output of the error amplifier and
the input of the PWM comparator. An RC+C network is
used at this node to compensate the feedback loop to
provide optimum transient response.
VCC (Pin 5): Power Supply. Power for the internal low
power circuity. VCC should be wired separately from the
drain of Q1 if they share the same supply. A 10µF bypass
capacitor is recommended from this pin to SGND.
OT (Pin 11): Over-Temperature Fault. OT is an open-drain
output and will be pulled low if OUTEN is less than 2V. If
OUTEN = 0, OT pulls low.
SENSE(Pin6):OutputVoltagePin.Connecttothepositive
terminal of the output capacitor. There is an internal 120k
resistor connected from this pin to SGND. SENSE is a very
sensitivepin;foroptimumperformance,connectanexter-
nal 0.1µF capacitor from this pin to SGND. By connecting
a small external resistor between the output capacitor and
the SENSE pin, the initial output voltage can be raised
slightly. Since the internal divider has a nominal imped-
ance of 120kΩ, a 1200Ω series resistor will raise the
nominal output voltage by 1%. If an external resistor is
used, the value of the 0.1µF capacitor on the SENSE pin
must be greatly reduced or loop phase margin will suffer.
Set a time constant for the RC combination of approxi-
mately 0.1µs. So, for example, with a 1200Ω resistor, set
C = 83pF. Use a standard 100pF capacitor.
FAULT (Pin 12): Overvoltage Fault. FAULT is an open-
drain output. If VOUT reaches 15% above the nominal
output voltage, FAULT will go low and G1 and G2 will be
disabled. Once triggered, the LTC1553 will remain in this
state until the power supply is recycled or the OUTEN pin
is toggled. If OUTEN = 0, FAULT floats or is pulled high by
an external resistor.
PWRGD (Pin 13): Power Good. This is an open-drain
signal to indicate validity of output voltage. A high indi-
cates that the output has settled to within ±5% of the rated
outputformorethan1ms.PWRGDwillgolowiftheoutput
is out of regulation for more than 500µs. If OUTEN = 0,
PWRGD pulls low.
6
LTC1553
U
U
U
PIN FUNCTIONS
OT trips. As OUTEN drops below 1.7V, the drivers are
internally disabled to prevent the MOSFETs from heating
further. If OUTEN is less than 1.2V for longer than 30µs,
the LTC1553 will enter shutdown mode. The internal
oscillator can be synchronized to a faster external clock by
applying the external clocking signal to the OUTEN pin.
VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14):
Digital Voltage Select. TTL inputs used to set the regulated
output voltage required by the processor (Table 3). There
is an internal 20kΩ pull-up at each pin. When all five VIDn
pins are high or floating, the chip will shut down.
OUTEN (Pin 19): Output Enable. TTL input which enables
the output voltage. The external MOSFET temperature can
be monitored with an external thermistor as shown in
Figure13. WhentheOUTENinputvoltagedropsbelow2V,
G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET,
Q1. ThisoutputwillswingfromPVCC toGND. Itwillalways
be low when G2 is high or the output is disabled.
W
BLOCK DIAGRAM
115% V
+
REF
FC
12 FAULT
11 OT
DELAY
13
2
PWRGD
–
DISDR
LOGIC
OUTEN 19
SYSTEM
POWER
DOWN
PV
CC
–
R
S
20 G1
PWM
+
COMP 10
I
SS
G2
1
Q
SS
SS
9
BG
ERR
MIN
MAX
6
SENSE
+
–
+
–
+
–
FB
18 VID0
17 VID1
16 VID2
15 VID3
V
V
REF
– 5%
V
REF
+ 5%
REF
8
–
+
I
FB
CC
14
VID4
V
I
7
REF
MAX
I
MAX
DAC
0.5V
0.7V
/
REF
REF
+
–
MHCL
HCL MONO
LVC
1553 BD
7
LTC1553
TEST CIRCUITS
V
CC
5V
PV
CC
12V
V
IN
5V
C
**
+
+
+
IN
1200µF
× 4
0.1µF
0.1µF
3k
3k
3k
10µF
10µF
10k
V
CC
I
FB
PV
100pF
100pF
CC
OUTEN
†
L
O
Q1*
Q2*
PWRGD
FAULT
OT
G1
2µH
15A
V
OUT
LTC1553
NC
I
MAX
G2
††
+
C
OUT
330µF
VID0 TO VID4
VID0 TO VID4
100pF
× 7
COMP
SS
SGND
GND
SENSE
R
C
8.2k
C1
150pF
0.1µF
*
SILICONIX SUD50N03-10
C
C
0.1µF
** SANYO 10MV1200GX
0.01µF
†
COILTRONICS CTX02-13198 OR
PANASONIC 12TS-2R5SP
††
1553 F02
AVX TPSE337M006R0100
Figure 2
V
CC
VID0 VID1 VID2 VID3 VID4
V
CC
+
10k
10µF
0.1µF
V
CC
VID0 VID1 VID2 VID3 VID4
I
FB
PV
CC
OUTEN
PV
CC
+
NC
PWRGD
LTC1553
FAULT
G1
NC
NC
NC
0.1µF
10µF
NC
NC
NC
I
MAX
G2
OT
COMP
SS
NC
SGND
GND
SENSE
1553 F03
Figure 3
V
5V
PV
12V
CC
CC
t
r
t
f
+
+
90%
50%
10%
90%
50%
0.1µF
10k
0.1µF
10µF
10µF
PV
V
CC
CC
10%
G1
G1 RISE/FALL
I
FB
5000pF
LTC1553
t
t
NOL
NOL
G2
SENSE
SGND
G2 RISE/FALL
5000pF
GND
50%
50%
1553 F04
Figure 4
8
LTC1553
U
U
FU CTIO TABLES
Table 1. OT Logic
Table 3. Rated Output Voltage (cont)
INPUT PIN
OUTEN (V)
< 2
OT*
0
RATED OUTPUT
VOLTAGE (V)
V
V
V
V
V
ID4
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ID3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
ID2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
ID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
ID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
> 2
1
1.80
1.85
1.90
1.95
2.00
2.05
SHDN
2.1
Table 2. PWRGD and FAULT Logic
INPUT
OUTPUT*
OUTEN
V
**
OT
0
FAULT
PWRGD
SENSE
0
1
1
X
1
1
1
0
0
1
< 95%
> 95%
1
1
< 105%
>105%
> 115%
2.2
1
1
1
1
1
0
0
0
2.3
2.4
2.5
Table 3. Rated Output Voltage
INPUT PIN
2.6
RATED OUTPUT
VOLTAGE (V)
2.7
V
V
V
V
V
ID0
ID4
ID3
ID2
ID1
2.8
†
0
1
1
1
1
Disabled (1.30)
2.9
†
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Disabled (1.35)
3.0
†
Disabled (1.40)
3.1
†
Disabled (1.45)
3.2
†
Disabled (1.50)
3.3
†
Disabled (1.55)
3.4
†
Disabled (1.60)
3.5
†
Disabled (1.65)
* With external pull-up resistor
†
Disabled (1.70)
** With respect to the output voltage selected in Table 3 as required by
Intel Specification VRM 8.2
†
Disabled (1.75)
†
These code selections are disabled in LTC1553
X Don’t care
9
LTC1553
U
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APPLICATIONS INFORMATION
OVERVIEW
Output regulation can be monitored with the PWRGD pin
which in turn monitors the internal MIN and MAX com-
parators. If the output is ±5% beyond the selected value
for more than 500µs, the PWRGD output will be pulled
low. Once the output has settled within ±5% of the
selected value for more than 1ms, PWRGD will return
high.
The LTC1553 is a voltage feedback, synchronous switch-
ing regulator controller (see Block Diagram) designed for
use in high power, low voltage step-down (buck) convert-
ers. It is designed to satisfy the requirements of the Intel
Pentium II power supply specification. It includes an
on-chip DAC to control the output voltage, a PWM genera-
tor,aprecisionreferencetrimmedto±1%,twohighpower
MOSFET gate drivers and all the necessary feedback and
control circuitry to form a complete switching regulator
circuit.
THEORY OF OPERATION
Primary Feedback Loop
The regulator output voltage at the SENSE pin is divided
down internally by a resistor divider with a total resistance
of approximately 120kΩ. This divided down voltage is
subtracted from a reference voltage supplied by the DAC
output. Theresultingerrorvoltageisamplifiedbytheerror
amplifierandtheoutputiscomparedtotheoscillatorramp
waveform by the PWM comparator. This PWM signal
controls the external MOSFETs through G1 and G2. The
resulting chopped waveform is filtered by LO and COUT
closingtheloop.Loopfrequencycompensationisachieved
with an external RC + C network at the COMP pin, which is
connected to the output node of the transconductance
amplifier.
The LTC1553 includes a current limit sensing circuit that
uses the upper external power MOSFET as a current
sensing element, eliminating the need for an external
sense resistor. Once the current comparator, CC, detects
an overcurrent condition, the duty cycle is reduced by
discharging the soft start capacitor through a voltage-
controlled current source. Under severe overloads or
output short circuit conditions, the chip will be repeatedly
forcedintosoftstartuntiltheshortisremoved, preventing
the external components from being damaged. Under
outputovervoltageconditions, theMOSFETdriverswillbe
disabled permanently until the chip power supply is
recycled or the OUTEN pin is toggled.
OUTEN can optionally be connected to an external nega-
tive temperature coefficient (NTC) thermistor placed near
theexternalMOSFETsorthemicroprocessor.Threethresh-
old levels are provided internally. When OUTEN drops to
2V, OT will trip, issuing a warning to the external CPU. If
the temperature continues to rise and the OUTEN input
drops to 1.7V, the G1 and G2 pins will be forced low. If
OUTEN is pulled below 1.2V, the LTC1553 will go into
shutdownmode, cuttingthesupplycurrenttoaminimum.
If thermal shutdown is not required, OUTEN can be con-
nected to a conventional TTL enable signal. The free-
running 300kHz PWM frequency can be synchronized to
a faster external clock connected to OUTEN. Adjusting the
oscillator frequency can add flexibility in the external
component selection. See the Clock Synchronization
section.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the ERR
amplifiermaynotrespondquicklyenough. MINcompares
the feedback signal FB to a voltage 60mV (5%) below the
internal reference. If FB is lower than the threshold of this
comparator, the MIN comparator overrides the ERR
amplifier and forces the loop to full duty cycle which is set
by the internal oscillator typically to 84%. Similarly, the
MAX comparator forces the output to 0% duty cycle if FB
is more than 5% above the internal reference. To prevent
these two comparators from triggering due to noise, the
MIN and MAX comparators’ response times are deliber-
ately controlled so that they take two to three microsec-
onds to respond. These two comparators help prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.
10
LTC1553
U
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APPLICATIONS INFORMATION
By using the RDS(ON) of Q1 to measure the output current,
the current limiting circuit eliminates an expensive dis-
cretesenseresistorthatwouldotherwiseberequired.This
helps minimize the number of components in the high
current path. Due to switching noise and variation of
Soft Start and Current Limit
The LTC1553 includes a soft start circuit which is used for
initial start-up and during current limit operation. The SS
pin requires an external capacitor to GND with the value
determined by the required soft start time. An internal
10µA current source is included to charge the external SS
capacitor. During start-up, the COMP pin is clamped to a
diode drop above the voltage at the SS pin. This prevents
the error amplifier, ERR, from forcing the loop to maxi-
mum duty cycle. The LTC1553 will begin to operate at low
R
DS(ON), the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuitbeginstotakeeffectwillvaryfromunittounitasthe
RDS(ON) of Q1 varies.
duty cycle as the SS pin rises above about 1.2V (VCOMP
≈
For a given current limit level, the external resistor from
IMAX to VIN can be determined by:
1.8V). As SS continues to rise, QSS turns off and the error
amplifier begins to regulatetheoutput. The MIN compara-
tor is disabled when soft start is active to prevent it from
overriding the soft start function.
I
R
)(
(
)
LMAX
DS(ON)Q1
R
=
IMAX
I
IMAX
The LTC1553 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
MOSFET, Q1, at the IFB pin. Note that when VIN = 12V, the
IFB pin requires an external Zener to GND to prevent
voltage transients at the switching node between Q1 and
Q2 from damaging internal structures. CC compares the
voltage at IFB to the voltage at the IMAX pin. As the peak
current rises, the measured voltage across Q1 increases
duetothedropacrosstheRDS(ON) ofQ1.Whenthevoltage
at IFB drops below IMAX, indicating that Q1’s drain current
has exceeded the maximum level, CC starts to pull current
out of the external soft start capacitor, cutting the duty
cycle and controlling the output current level. The CC
comparator pulls current out of the SS pin in proportion to
the voltage difference between IFB and IMAX. Under minor
overload conditions, the SS pin will fall gradually, creating
a time delay before current limit takes effect. Very short,
mild overloads may not affect the output voltage at all.
More significant overload conditions will allow the SS pin
to reach a steady state, and the output will remain at a
reduced voltage until the overload is removed. Serious
overloads will generate a large overdrive at CC, allowing it
to pull SS down quickly and preventing damage to the
output components.
where,
I
RIPPLE
I
= I
+
LOAD
LMAX
2
ILOAD = Maximum load current
IRIPPLE = Inductor ripple current
V − V
V
(
)(
)
IN
OUT OUT
=
f
(
L
V
IN
)( )(
)
OSC
O
fOSC = LTC1553 oscillator frequency = 300kHz
LO = Inductor value
RDS(ON)Q1 = Hot on-resistance of Q1 at ILMAX
IIMAX = Internal 180µA sink current at IMAX
V
IN
+
+
LTC1553
R
C
IMAX
IN
I
MAX
7
+
–
180µA
Q1
G1
20Ω
CC
I
FB
8
L
O
V
OUT
G2
Q2
C
OUT
1553 F05
Figure 5. Current Limit Setting
11
LTC1553
U
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APPLICATIONS INFORMATION
Table 4. Recommended Minimum RIMAX Resistor (kΩ) vs Maximum Operating Load Current and External MOSFET Q1
MAXIMUM OPERATING
LOAD CURRENT (A)
SUD50N03-10
(TWO IN PARALLEL)
MTD20N03HDL
(TWO IN PARALLEL)
SUD50N03-10
MTD20N03HDL
12
14
16
18
20
2.4
2.7
3.0
3.6
3.9
1.2
1.3
1.5
1.8
2.0
4.3
5.1
6.2
6.8
7.5
2.2
2.7
3.0
3.3
3.6
V
CC
V
IN
OUTEN and Thermistor Input
5.6k
The LTC1553 includes a low power shutdown mode,
controlled by the logic at the OUTEN pin. A high at OUTEN
allows the part to operate normally. A low level at OUTEN
stops all internal switching, pulls COMP and SS to ground
internally and turns Q1 and Q2 off. OT and PWRGD are
pulled low, and FAULT is left floating. In shutdown, the
LTC1553 quiescent current will drop to about 130µA. The
remaining current is used to keep the thermistor sensing
circuit at OUTEN alive. Note that the leakage current of
the external MOSFETs may add to the total shutdown
current consumed by the circuit, especially at elevated
temperature.
PENTIUM II
SYSTEM
OT
G1
G2
Q1
V
L
O
CC
LTC1553
V
OUT
R1
+
Q2
C
OUT
OUTEN
R2
NTC THERMISTOR
MOUNT IN CLOSE
THERMAL PROXIMITY
TO Q1
1553 F06
Figure 6. OUTEN Pin as a Thermistor Input
OUTENislessthan1.2V, theLTC1553willentershutdown
mode. To activate any of these three modes, the OUTEN
voltage must drop below the respective threshold for
longer than 30µs.
OUTEN is designed with multiple thresholds to allow it to
alsobeutilizedforover-temperatureprotection.Thepower
MOSFET operating temperature can be monitored with an
externalnegativetemperaturecoefficient(NTC)thermistor
mounted next to the external MOSFET which is expected
to run the hottest––often the high-side device, Q1. Elec-
trically, the thermistor should form a voltage divider with
another resistor, R1, connected to VCC. Their midpoint
should be connected to OUTEN (see Figure 6). As the
temperature increases, the OUTEN pin voltage is reduced.
Undernormaloperatingconditions,theOUTENpinshould
stay above 2V. All circuits will function normally, and the
OT pin will remain in a high state. If the temperature gets
abnormally high, the OUTEN pin voltage will eventually
drop below 2V. OT will switch to a logic low, providing an
over-temperaturewarningtothesystem.AsOUTENdrops
below 1.7V, the LTC1553 disables both FET drivers. If
Clock Synchronization
The internal oscillator can be synchronized to an external
clock by applying the external clocking signal to the
OUTEN pin. The synchronizing range extends from the
initial operating frequency up to 500kHz. If the external
frequency is much higher than the natural free-running
frequency, the peak-to-peak sawtooth amplitude within
theLTC1553willdecrease. Sincetheloopgainisinversely
proportional to the amplitude of the sawtooth, the com-
pensation network may need to be adjusted slightly. Note
that the temperature sensing circuitry does not operate
when external synchronization is used.
12
LTC1553
U
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APPLICATIONS INFORMATION
MOSFET Gate Drive
V
IN
1N5817
OPTIONAL FOR V > 5V
IN
+
Power for the internal MOSFET drivers is supplied by
PVCC. This supply must be above the input supply voltage
by at least one power MOSFET VGS(ON) for efficient opera-
tion. This higher voltage can be supplied with a separate
supply, or it can be generated using a simple charge pump
as shown in Figure 7. The 84% typical maximum duty
cycle ensures sufficient off-time to refresh the charge
pump during each cycle. Figure 8 shows a tripling charge
pump, which provides additional VGS overdrive to the
external MOSFETs. This circuit can be useful for standard
threshold MOSFETs which demand a higher turn-on volt-
age. An18VZenerdiode(1N5248B)isrecommendedwith
tripler charge pump designs to ensure that PVCC never
exceeds the LTC1553’s 20V absolute maximum PVCC
voltage. This becomes more critical as VIN rises. With VIN
= 12V, the doubler circuit of Figure 7 will also exceed the
20V limit. Figure 9 shows an alternate 17V charge pump
derived from both the 5V and 12V supplies.
1N5248B
2
C
PV
IN
CC
18V
0.1µF
LTC1553
G1
20
Q1
L
O
V
OUT
G2
1
+
C
OUT
Q2
1553 F07
Figure 7. Doubling Charge Pump
V
IN
1N5817 1N5817 1N5817
+
+
1N5248B
18V
2
PV
CC
C
IN
0.1µF
10µF
0.1µF
+
LTC1553
G1
20
Q1
L
O
If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As VCC and PVCC
power up from a 0V condition, an internal undervoltage
lockup circuit prevents G1 and G2 from going high until
VCC reaches about 3.5V. If VCC powers up while PVCC is at
ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
is held low until G1 first goes high.
V
OUT
G2
1
Q2
C
OUT
1553 F08
Figure 8. Tripling Charge Pump
V
IN
12V
1N5817
V
CC
5V
+
1N5248B
18V
Power MOSFETs
C
IN
10Ω
0.1µF
Two N-channel power MOSFETs are required for most
LTC1553 circuits. They should be selected based prima-
rily on threshold and on-resistance considerations. The
required MOSFET threshold should be determined based
on the available power supply voltages and/or the com-
plexity of the gate driver charge pump scheme. In 5V input
designs where a 12V supply is used to power PVCC,
standard MOSFETs with RDS(ON) specified at VGS = 5V or
6V can be used with good results. However, logic level
devices will improve efficiency. The current drawn from
the 12V supply varies with the MOSFETs used and the
LTC1553 operating frequency, but is generally less than
50mA.
PV
2
5
V
CC
CC
C
VCC
LTC1553
G1
20
Q1
L
O
V
OUT
G2
1
+
C
OUT
Q2
1553 F09
Figure 9. 17V Charge Pump for VIN = 12V
13
LTC1553
U
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APPLICATIONS INFORMATION
The LTC1553 designs that use a 5V VIN voltage and a
doubler charge pump to generate PVCC will not provide
enough drive voltage to fully enhance standard power
MOSFETs. Under this condition, the effective MOSFET
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for Pentium II with a 5V input
and a 2.8V, 11.2A output might allow no more than 4%
efficiency loss at full load for each MOSFET. Assuming
roughly 90% efficiency at this current level, this gives a
RDS(ON) may be quite high, raising the dissipation in the
FETs and reducing efficiency. Logic level FETs are a better
choice for 5V-only systems as shown in Figure 7 or 12V
input systems using the 17V charge pump of Figure 9.
They can be fully enhanced with the generated charge
pump voltage and will operate at maximum efficiency.
Note that doubler charge pump designs running from
supplies higher than 5V, and all tripler charge pump
designs, should include a Zener clamp diode at PVCC to
prevent transients from exceeding the absolute maximum
rating at that pin. See the MOSFET Gate Drive section for
more charge pump information.
P
MAX value of:
[(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET
and a required RDS(ON) of:
5V 1.39W
( )(
)
)
R
=
=
= 0.019Ω
DS ON Q1
(
)
2
2.8V 11.2A
(
)(
5V 1.39W
( )(
)
R
= 0.025Ω
DS ON Q2
(
)
2
Once the threshold voltage has been selected, RDS(ON)
should be chosen based on input and output voltage,
allowable power dissipation and maximum required out-
put current. In a typical LTC1553 buck converter circuit
the average inductor current is equal to the output load
current. This current is always flowing through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
5V − 2.8V 11.2A
(
)(
)
Note also that while the required RDS(ON) values suggest
large MOSFETs, the dissipation numbers are only 1.39W
per device or less––large TO-220 packages and heat sinks
are not necessarily required in high efficiency applica-
tions.SiliconixSi4410DYorInternationalRectifierIRF7413
(both in SO-8) or Siliconix SUD50N03 or Motorola
MTD20N03HDL (both in D PAK) are small footprint sur-
facemountdeviceswithRDS(ON) valuesbelow0.03Ωat5V
of gate drive that work well in LTC1553 circuits. With
higher output voltages, the RDS(ON) of Q1 may need to be
significantly lower than that for Q2. These conditions can
often be met by paralleling two MOSFETs for Q1 and using
a single device for Q2. Note that using a higher PMAX value
intheRDS(ON) calculationswillgenerallydecreaseMOSFET
cost and circuit efficiency while increasing MOSFET heat
sink requirements.
V
V
OUT
DC Q1 =
( )
IN
V − V
(
)
IN
OUT
V
V
OUT
DC Q2 = 1−
=
( )
V
IN
IN
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
V
P
P
(
)
IN MAX Q1
MAX Q1
( )
( )
R
=
=
=
DS ON Q1
(
)
2
)
2
)
DC Q1 I
V
I
( ) (
]
(
)(
MAX
OUT MAX
[
V
P
P
(
)
IN MAX Q2
MAX Q2
(
)
(
)
R
=
DS ON Q2
(
)
2
)
2
)
DC Q2 I
V − V
I
( ) (
(
)(
MAX
IN
OUT MAX
[
]
14
LTC1553
U
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APPLICATIONS INFORMATION
Table 5. Recommended MOSFETs for LTC1553 Applications
TYPICAL INPUT
CAPACITANCE
R
DS(ON)
PARTS
AT 25°C (mΩ)
RATED CURRENT (A)
C
ISS
(pF)
θ
(°C/W)
T
JMAX
(°C)
JC
Siliconix SUD50N03-10
TO-252
19
15 at 25°C
10 at 75°C
3200
2700
880
1.8
175
Siliconix Si4410DY
SO-8
20
35
23
7.5
14
28
37
10 at 25°C
8 at 75°C
—
150
150
175
150
175
175
150
Motorola MTD20N03HDL
D PAK
20 at 25°C
16 at 100°C
1.67
2.5
SGS-Thomson STD20N03L
D PAK
20 at 25°C
14 at 100°C
2300
4025
1600
3300
1750
Motorola MTB75N03HDL
DD PAK
75 at 25°C
59 at 100°C
1.0
IRF IRL3103S
DD PAK
56 at 25°C
40 at 100°C
1.8
IRF IRLZ44
TO-220
50 at 25°C
36 at 100°C
1.0
Fuji 2SK1388
TO-220
35 at 25°C
2.08
Note: Please refer to the manufacturer’s data sheet for testing conditions
and detail information.
this5.5µs,thedifferencebetweentheinductorcurrentand
the output current must be made up by the output capaci-
tor, causing a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1µH to 5µH range for most typical 5V input LTC1553
circuits. To optimize performance, different combinations
of input and output voltages and expected loads may
require different inductor values.
Inductor Selection
TheinductorisoftenthelargestcomponentintheLTC1553
design andshould bechosencarefully. Inductorvalueand
type should be chosen based on output slew rate require-
ments, output ripple requirements and expected peak
current. Inductor value is primarily controlled by the
required current slew rate. The maximum rate of rise of
current in the inductor is set by its value, the input-to-
output voltage differential and the maximum duty cycle of
the LTC1553. In a typical 5V input, 2.8V output applica-
tion, the maximum current slew rate will be:
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
V − V
(
)
IN
OUT
1.83
L
A
µs
DC
=
MAX
L
where L is the inductor value in µH. With proper frequency
compensation,thecombinationoftheinductorandoutput
capacitor will determine the transient recovery time. In
general, a smaller value inductor will improve transient
responseattheexpenseofincreasedoutputripplevoltage
and inductor core saturation rating. A 2µH inductor would
have a 0.9A/µs rise time in this application, resulting in a
5.5µsdelayinrespondingtoa5Aloadcurrentstep.During
V − V
V
(
)(
)
IN
OUT OUT
I
=
RIPPLE
f
(
L
V
IN
)( )(
)
OSC
O
fOSC = LTC1553 oscillator frequency = 300kHz
LO = Inductor value
15
LTC1553
U
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APPLICATIONS INFORMATION
Solving this equation with our typical 5V to 2.8V applica-
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s speci-
fication is recommended to extend the useful life of the
circuit. Lower operating temperature will have the largest
effect on capacitor longevity.
tion with a 2µH inductor, we get:
2.2 0.56
(
)(
)
= 2A
P-P
300kHz 2µH
(
)(
)
The output capacitor in a buck converter sees much less
ripplecurrentundersteady-stateconditionsthantheinput
capacitor. Peak-to-peak current is equal to that in the
inductor, usually 10% to 40% of the total load current.
Output capacitor duty places a premium not on power
dissipation but on ESR. During an output load transient,
the output capacitor must supply all of the additional load
current demanded by the load until the LTC1553 can
adjust the inductor current to the new value. Output
capacitor ESR results in a step in the output voltage equal
to the ESR value multiplied by the change in load current.
An 11A load step with a 0.05Ω ESR output capacitor will
result in a 550mV output voltage shift; this is 19.6% of the
output voltage for a 2.8V supply! Because of the strong
relationship between output capacitor ESR and output
load transient response, the output capacitor is usually
chosenforESR,notforcapacitancevalue;acapacitorwith
suitable ESR will usually have a larger capacitance value
than is needed for energy storage.
Peak inductor current at 11.2A load:
2A
2
11.2A +
= 12.2A
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductorswithgradualsaturationcharacteristicsareoften
the best choice.
Input and Output Capacitors
A typical LTC1553 design puts significant demands on
both the input and the output capacitors. During constant
load operation, a buck converter like the LTC1553 draws
square waves of current from the input supply at the
switchingfrequency. Thepeakcurrentvalueisequaltothe
output load current plus 1/2 peak-to-peak ripple current,
and the minimum value is zero. Most of this current is
suppliedbytheinputbypasscapacitor. TheresultingRMS
current flow in the input capacitor will heat it up, causing
premature capacitor failure in extreme cases. Maximum
RMS current occurs with 50% PWM duty cycle, giving an
RMS current value equal to IOUT/2. A low ESR input
capacitor with an adequate ripple current rating must be
used to ensure reliable operation.
Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC1553 applications. OS-CON
electrolytic capacitors from SANYO and other manufac-
turers give excellent performance and have a very high
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. AVX TPS series surface mount
devices are popular surge tested tantalum capacitors that
work well in LTC1553 applications.
Note that capacitor manufacturers’ ripple current ratings
are often based on only 2000 hours (three months)
A common way to lower ESR and raise ripple current
capabilityistoparallelseveralcapacitors.AtypicalLTC1553
16
LTC1553
U
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APPLICATIONS INFORMATION
application might exhibit 5A input ripple current. SANYO Figure 10b shows the Bode plot of the overall transfer
OS-CON part number 10SA220M (220µF/10V) capacitors function.
feature 2.3A allowable ripple current at 85°C; three in
The compensation value used in this design is based on
parallel at the input (to withstand the input ripple current)
the following criteria: fSW = 12fCO, fZ = fLC and fP = 5fCO. At
will meet the above requirements. Similarly, AVX
the closed-loop frequency fCO, the attenuation due the LC
TPSE337M006R0100 (330µF/6V) have a rated maximum
filter and the input resistor divider is compensated by the
ESR of 0.1Ω; seven in parallel will lower the net output
gain of the PWM modulator and the gain of the error
capacitorESRto0.014Ω.Forlowcostapplication,SANYO
amplifier(gmERR)(RC).Althoughamathematicalapproach
MV-GX series of capacitors can be used with acceptable
to frequency compensation can be used, the added
performance.
6
SENSE
Feedback Loop Compensation
LTC1553
TheLTC1553voltagefeedbackloopiscompensatedatthe
COMP pin, attached to the output node of the internal gm
error amplifier. The feedback loop can generally be com-
pensated properly with an RC + C network from COMP to
GND as shown in Figure 10a.
–
+
COMP
10
ERR
R
C
C1
Loop stability is affected by the values of the inductor,
output capacitor, output capacitor ESR, error amplifier
transconductance and error amplifier compensation net-
work. The inductor and the output capacitor creates a
double pole at the frequency:
DAC
C
C
1553 F10
Figure 10a. Compensation Pin Hook-Up
1
O
f
LC
=
2π√(L )(C
)
OUT
f
f
= LTC1553 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
SW
CO
The ESR of the output capacitor forms a zero at the
frequency:
f
Z
1
f
=
ESR
2π(ESR)(C
)
OUT
–20dB/DECADE
The compensation network at the error amplifier output is
to provide enough phase margin at the 0dB crossover
frequency for the overall closed-loop transfer function.
The zero and pole from the compensation network are:
f
P
f
LC
f
FREQUENCY
ESR
f
CO
1
C
1
C
f =
Z
f =
P
1553 F10b
and
respectively.
2π(R )(C )
2π(R )(C1)
C
Figure 10b. Bode Plot of the LTC1553 Overall Transfer Function
17
LTC1553
U
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APPLICATIONS INFORMATION
complication of input and/or output filters, unknown
capacitor ESR, and gross operating point changes with
input voltage, load current variations, all suggest a more
practical empirical method. This can be done by injecting
atransientcurrentattheloadandusinganRCnetworkbox
to iterate toward the final compensation values, or by
obtaining the optimum loop response using a network
analyzer to find the actual loop poles and zeros.
the suggested values slightly because of board layout and
operating condition differences.
An alternate output capacitor is the Sanyo MV-GX series.
Using multiple parallel 1500µF Sanyo MV-GX capacitors
for the output capacitor, Table 8 shows the suggested
compensation component value for a 5V input application
based on the inductor and output capacitor values.
Table 8. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 1500µF SANYO MV-GX
Output Capacitors
Table 6. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 330µF AVX TPS Output
Capacitors
L (
µ
H)
C (
µ
F)
R (k
Ω)
C (
µ
F)
C1 (pF)
270
220
150
100
82
O
O
C
C
L
(
µ
H)
C
(
µ
F)
R (k
Ω)
C (
µ
F)
C1 (pF)
680
330
120
220
120
47
O
O
C
C
1
4500
6000
9000
4500
6000
9000
4500
6000
9000
4.3
5.6
8.2
11
15
22
24
30
47
0.022
0.0047
0.01
1
1
1
990
1.8
3.6
9.1
5.1
10
0.022
0.01
1
1
1980
4950
990
0.01
2.7
2.7
2.7
5.6
5.6
5.6
0.01
2.7
2.7
2.7
5.6
5.6
5.6
0.01
0.01
1980
4950
990
0.01
0.01
56
24
0.0047
0.01
0.01
56
10
120
56
0.0047
0.0047
39
1980
4950
20
0.0047
0.0036
27
51
22
Table 7. Suggested Compensation Network for 12V Input
Application Using Multiple Paralleled 330µF AVX TPS Output
Capacitors
VID0 to VID4, PWRGD and FAULT
Thedigitalinputs(VID0toVID4)programtheinternalDAC
which in turn controls the output voltage. These digital
input controls are intended to be static and are not
designed for high speed switching. Forcing VOUT to step
from a high to a low voltage by changing the VIDn pins
quickly can cause FAULT to trip.
L
(
µ
H)
C
(
µ
F)
R (k
Ω)
C (
µ
F)
C1 (pF)
1500
820
330
560
270
120
270
150
56
O
O
C
C
1
1
1
990
0.82
1.5
3.9
2.2
4.3
10
0.047
0.033
0.022
0.033
0.022
0.01
1980
4950
990
2.7
2.7
2.7
5.6
5.6
5.6
1980
4950
990
Figure 11 shows the relationship between the VOUT volt-
age, PWRGD and FAULT. To prevent PWRGD from inter-
rupting the CPU unnecessarily, the LTC1553 has a built-in
tPWRBAD delay to prevent noise at the SENSE pin from
toggling PWRGD. The internal time delay is designed to
take about 500µs for PWRGD to go low and 1ms for it to
recover. Once PWRGD goes low, the internal circuitry
watchesfortheoutputvoltagetoexceed115%oftherated
voltage. If this happens, FAULT will be triggered. Once
FAULT is triggered, G1 and G2 will be forced low immedi-
ately and the LTC1553 will remain in this state until VCC
power supply is recycled or OUTEN is toggled.
4.3
8.2
22
0.022
0.010
0.010
1980
4950
Tables 6 and 7 show the suggested compensation com-
ponents for 5V and 12V input applications based on the
inductor and output capacitor values. The values were
calculatedusing multipleparalleled330µF AVX TPS series
surface mount tantalum capacitors as the output capaci-
tor. The optimum component values might deviate from
18
LTC1553
U
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APPLICATIONS INFORMATION
15%
disturbances in the LTC1553 and prevents differences
in ground potential from disrupting internal circuit
operation. This connection should then tie into the
groundplaneatasinglepoint,preferablyatafairlyquiet
point in the circuit such as close to the output capaci-
tors. This is not always practical, however, due to
physical constraints. Another reasonably good point to
make this connection is between the output capacitors
and the source connection of the low side FET Q2. Do
not tie this single point ground in the trace run between
the low side FET source and the input capacitor ground,
as this area of the ground plane will be very noisy.
V
OUT
5%
RATED V
OUT
–5%
t
t
FAULT
PWRBAD
t
PWRGD
PWRGD
FAULT
1553 F11
Figure 11. PWRGD and FAULT
3. The small signal resistors and capacitors for frequency
compensation and soft start should be located very
close to their respective pins and the ground ends
connected to the signal ground pin through a separate
trace. Do not connect these parts to the ground plane!
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1553. These items are also illustrated graphically in
the layout diagram of Figure 12. The thicker lines show the
high current paths. Note that at 10A current levels or
above, current density in the PC board itself is a serious
concern. Traces carrying high current should be as wide
aspossible.Forexample,aPCBfabricatedwith2ozcopper
4. The VCC and PVCC decoupling capacitors should be as
close to the LTC1553 as possible. The 10µF bypass
capacitors shown at VCC and PVCC will help provide
optimum regulation performance.
5. The (+) plate of CIN should be connected as close as
possible to the drain of the upper MOSFET. An addi-
tional 1µF ceramic capacitor between VIN and power
ground is recommended.
requires a minimum trace width of 0.15
carry 10A.
" to
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so
that a clean power flow path is achieved. Conductor
widths should be maximized and lengths minimized.
After you are satisfied with the power path, the control
circuitry should be laid out. It is much easier to find
routes for the relatively small traces in the control
circuits than it is to find circuitous routes for high
current paths.
6. The SENSE pin is very sensitive to pickup from the
switching node. Care should be taken to isolate SENSE
frompossiblecapacitivecouplingtotheinductorswitch-
ing signal. A 0.1µF is required between the SENSE pin
and the SGND pin next to the LTC1553.
7. OUTEN is a high impedance input and should be
externally pulled up to a logic HIGH for normal
operation.
2. The GND and SGND pins should be shorted right at the
LTC1553. This helps to minimize internal ground
8. Kelvin sense IMAX and IFB at Q1 drain and source pins.
19
LTC1553
APPLICATIONS INFORMATION
U
W U U
V
IN
+
C
IN
Q1
L
O
1
20
19
18
17
16
15
14
13
12
11
LTC1553
G2
PV
G1
V
OUT
PV
CC
2
3
4
OUTEN
VID0
CC
+
0.1µF
0.1µF
10µF
10µF
VID0
VID1
VID2
VID3
VID4
+
+
GND
C
Q2
OUT
VID1
SGND
5.6k
VID2
5
6
5.6k
V
CC
VID3
SENSE
5.6k
VID4
R
IMAX
7
8
I
I
MAX
R
IFB
PWRGD
FAULT
OT
FB
9
SS
10
COMP
C
SS
1153 F12
R
C
BOLD LINES INDICATE
HIGH CURRENT PATHS
C1
0.1µF
C
C
Figure 12. LTC1553 Layout Diagram
20
LTC1553
U
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APPLICATIONS INFORMATION
V
IN
5V
+
C
**
+
IN
1200µF
× 4
0.1µF
10µF
1N5817
2.7k
5.6k
5.6k
5.6k
V
I
PV
CC
CC
MAX
0.1µF
20Ω
PWRGD
FAULT
OT
†
L
O
Q1*
Q2*
G1
2µH
18A
PENTIUM II
SYSTEM
5
v
LTC1553
OUT
I
FB
VID0 TO VID4
OUTEN
††
C
+
OUT
5V
G2
330µF
× 7
1.8k
DALE
COMP
SS
SGND
GND SENSE
R
8.2k
C
C1
150pF
NTHS-1206N02
MOUNT THERMISTER
IN CLOSE THERMAL
PROXIMITY TO Q1
C
C
SS
0.01µF 0.1µF
C
*
SILICONIX SUD50N03-10
0.1µF
** SANYO 10MV1200GX
†
COILTRONICS CTX02-13198 OR
PANASONIC 12TS-2R5SP
††
AVX TPSE337M006R0100
1553 F13
Figure 13. Single Supply LTC1553 5V to 1.8V-3.5V Application with Thermal Monitor
21
LTC1553
U
PACKAGE DESCRIPTION Dimension in inches (millimeters) unless otherwise noted.
G Package
20-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.278 – 0.289*
(7.07 – 7.33)
20 19 18 17 16 15 14 13 12 11
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G20 SSOP 0595
22
LTC1553
U
PACKAGE DESCRIPTION Dimension in inches (millimeters) unless otherwise noted.
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.496 – 0.512*
(12.598 – 13.005)
19 18
16
14 13 12 11
20
17
15
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
0.009 – 0.013
(0.102 – 0.305)
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.016 – 0.050
(0.406 – 1.270)
S20 (WIDE) 0396
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1553
U
TYPICAL APPLICATION
V
CC
5V
V
IN
12V
1N5817
10Ω
+
1N5248B
18V
C
**
+
IN
10µF
0.1µF
1000µF
× 4
0.1µF
20Ω
5.6k
5.6k
5.1k
V
PV
CC
CC
I
MAX
G1
PWRGD
†
L
O
Q1*
FAULT
OT
4µH
18A
PENTIUM II
SYSTEM
NC
I
FB
5
v
LTC1553
OUT
VID0 TO VID4
OUTEN
††
C
330µF
× 6
1N5245B
15V
+
OUT
Q2*
G2
COMP
SS
SGND
GND SENSE
R
C
C1
180pF
6.2k
C
SS
0.1µF
C
C
0.022µF
*
MOTOROLA MTD20N03HDL
0.1µF
** SANYO 16MV1000GX
†
COILTRONICS CTX02-13199
††AVX TPSE337M006R0100
1553 F14
Figure 14. External Clock Synchronized 12V to 1.8V-3.5V Application
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC1142
LTC1148
LTC1149
LTC1159
LTC1266
LTC1430
LTC1435
Current Mode Dual Step-Down Switching Regulator Controller Dual Version of LTC1148
Current Mode Step-Down Switching Regulator Controller
Current Mode Step-Down Switching Regulator Controller
Current Mode Step-Down Switching Regulator Controller
Current Mode Step-Up/Down Switching Regulator Controller
High Power Step-Down Switching Regulator Controller
Synchronous, V ≤ 20V
IN
Synchronous, V ≤ 48V, for Standard Threshold FETs
IN
Synchronous, V ≤ 40V, for Logic Threshold FETs
IN
Synchronous N- or P-Channel FETs, Comparator/Low-Battery Detector
Synchronous N-Channel FETs, Voltage Mode
High Efficiency Low Noise Synchronous Step-Down
Switching Regulator
Drive Synchronous N-Channel, V ≤ 36V
IN
LTC1438
Dual High Efficiency Low Noise Synchronous Step-Down
Switching Regulator
Dual LTC1435 with Power-On Reset
1553f LT/TP 0198 4K • PRINTED IN USA
Linear Technology Corporation
●
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
24
●
●
FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1997
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