LTC1407CMSE-1#PBF_技术文档

LTC1407-1/LTC1407A-1

Serial 12-Bit/14-Bit, 3Msps

Simultaneous Sampling

ADCs with Shutdown

DESCRIPTION

FEATURES

The LTC^®1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps

ADCs with two 1.5Msps simultaneously sampled differ-

ential inputs. The devices draw only 4.7mA from a single

3V supply and come in a tiny 10-lead MS package. A sleep

shutdown feature lowers power consumption to 10μW.

The combination of speed, low power and tiny package

makestheLTC1407-1/LTC1407A-1suitableforhighspeed,

portable applications.

n

3Msps Sampling ADC with Two Simultaneous

Differential Inputs

n

1.5Msps Throughput per Channel

n

Low Power Dissipation: 14mW (Typ)

n

3V Single Supply Operation

n

1.25V Differential ꢀnput ꢁange

n

Pin Compatible 0V to 2.5V ꢀnput ꢁange Version

(LTC1407/LTC1407A)

n

2.5V ꢀnternal Bandgap ꢁeference with External

The LTC1407-1/LTC1407A-1 contain two separate differ-

entialinputsthataresampledsimultaneouslyontherising

edge of the CONV signal. These two sampled inputs are

then converted at a rate of 1.5Msps per channel.

Overdrive

3-Wire Serial ꢀnterface

Sleep (10μW) Shutdown Mode

Nap (3mW) Shutdown Mode

n

The80dBcommonmoderejectionallowsuserstoeliminate

ground loops and common mode noise by measuring

signals differentially from the source.

80dB Common Mode ꢁejection at 100kHz

n

Tiny 10-Lead MS Package

The devices convert –1.25V to 1.25V bipolar inputs differ-

APPLICATIONS

+

–

+

entially. The absolute voltage swing for CH0 , CH0 , CH1

n

–

Telecommunications

and CH1 extends from ground to the supply voltage.

n

Data Acquisition Systems

Theserialinterfacesendsoutthetwoconversionresultsin32

clocks for compatibility with standard serial interfaces.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6084440, 6522187.

n

Uninterrupted Power Supplies

n

Multiphase Motor Control

ꢀ & Q Demodulation

n

ꢀndustrial ꢁadio

BLOCK DIAGRAM

10μF 3V

THD, 2nd and 3rd vs Input Frequency

for Differential Input Signals

–44

–50

–56

–62

7

V

DD

LTC1407A-1

+

CH0

1

2

+

–

S & H

–

THꢁEE-

STATE

SEꢁꢀAL

OUTPUT

POꢁT

3Msps

14-BꢀT ADC

MUX

8

SDO

–68

–74

+

–

CH1

4

5

3

+

THD

3ꢁD

–80

–86

S & H

CH1

–

10

9

CONV

SCK

–92

TꢀMꢀNG

LOGꢀC

V

–98

ꢁEF

2ND

–104

10μF

GND

0.1

1

10 20

2.5V

ꢁEFEꢁENCE

6

FꢁEQUENCY (MHz)

14071 TA01b

EXPOSED PAD

11

1407A1 BD

14071fb

1

LTC1407-1/LTC1407A-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

TOP VꢀEW

+

CH0

ꢁEF

CH1

1

2

3

4

5

10 CONV

Supply Voltage (V ) .................................................4V

DD

–

9

8

7

6

SCK

SDO

DD

GND

Analog ꢀnput Voltage (Note 3) ..... –0.3V to (V + 0.3V)

V

11

DD

+

–

V

Digital ꢀnput Voltage .................... –0.3V to (V + 0.3V)

DD

Digital Output Voltage ................. –0.3V to (V + 0.3V)

MSE PACKAGE

10-LEAD PLASTꢀC MSOP

DD

Power Dissipation...............................................100mW

T

= 125°C, θ = 40°C/W

JA

JMAX

Operation Temperature ꢁange

EXPOSED PAD ꢀS GND (PꢀN 11), MUST BE SOLDEꢁED TO PCB

LTC1407C-1/LTC1407AC-1 ...................... 0°C to 70°C

LTC1407ꢀ-1/LTC1407Aꢀ-1.....................–40°C to 85°C

Storage Temperature ꢁange...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

LTBGT

PACKAGE DESCRIPTION

10-Lead Plastic MSOP

TEMPERATURE RANGE

LTC1407CMSE-1#PBF

LTC1407ꢀMSE-1#PBF

LTC1407ACMSE-1#PBF

LTC1407AꢀMSE-1#PBF

LTC1407CMSE-1#TꢁPBF

LTC1407ꢀMSE-1#TꢁPBF

LTC1407ACMSE-1#TꢁPBF

LTC1407AꢀMSE-1#TꢁPBF

0°C to 70°C

LTBGV

–40°C to 85°C

0°C to 70°C

LTBGW

LTBGX

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

The l denotes the speciﬁcations which apply over the full operating

CONVERTER CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. With internal reference, V_DD= 3V.

LTC1407-1

LTC1407A-1

TYP

PARAMETER

CONDITIONS

MIN

12

TYP

MAX

MIN

14

MAX

l

ꢁesolution (No Missing Codes)

ꢀntegral Linearity Error

Offset Error

Bits

LSB

(Notes 5, 17)

(Notes 4, 17)

(Note 17)

–2

0.25

1

2

10

5

–4

0.5

2

4

–10

–5

–20

–10

–60

–10

20

10

60

10

Offset Match from CH0 to CH1

Gain Error

0.5

5

1

l

(Notes 4, 17)

(Note 17)

–30

–5

30

5

10

2

Gain Match from CH0 to CH1

Gain Tempco

1

ꢀnternal ꢁeference (Note 4)

External ꢁeference

15

1

15

1

ppm/°C

14071fb

2

LTC1407-1/LTC1407A-1

ANALOG INPUT

The l denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. With internal reference, V_DD= 3V.

SYMBOL PARAMETER CONDITIONS

MIN

TYP

MAX

UNITS

V

Analog Differential ꢀnput ꢁange (Notes 3, 8, 9)

2.7V ≤ V ≤ 3.3V

–1.25 to 1.25

V

ꢀN

DD

Analog Common Mode + Differential

ꢀnput ꢁange (Note 10)

0 to V

CM

DD

l

ꢀ

Analog ꢀnput Leakage Current

1

μA

pF

ns

ps

ꢀN

C

Analog ꢀnput Capacitance

(Note 18)

(Note 6)

13

ꢀN

t

Sample-and-Hold Acquisition Time

Sample-and-Hold Aperture Delay Time

Sample-and-Hold Aperture Delay Time Jitter

Sample-and-Hold Aperture Skew from CH0 to CH1

Analog ꢀnput Common Mode ꢁejection ꢁatio

39

ACQ

AP

1

0.3

JꢀTTEꢁ

SK

200

CMꢁꢁ

f

ꢀN

f

ꢀN

= 1MHz, V = 0V to 3V

–60

–15

dB

ꢀN

= 100MHz, V = 0V to 3V

ꢀN

DYNAMIC ACCURACY ^Thel denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°C. With internal reference, V_DD= 3V. Single-ended signal drive CH0⁺/CH1⁺with

CHO^–/CH1^–= 1.5V DC. Differential signals drive both inputs of each channel with V_CM= 1.5V DC.

LTC1407-1

LTC1407A-1

TYP MAX

SYMBOL PARAMETER

CONDITIONS

MIN

TYP MAX MIN

UNITS

SꢀNAD

Signal-to-Noise Plus 100kHz ꢀnput Signal (Note 19)

70.5

72.0

73.5

76.3

dB

l

Distortion ꢁatio

750kHz ꢀnput Signal (Note 19)

100kHz ꢀnput Signal, External V = 3.3V,

68

70

ꢁEF

V

≥ 3.3V (Note 19)

DD

750kHz ꢀnput Signal, External V = 3.3V,

72.0

76.3

dB

ꢁEF

V

≥ 3.3V (Note 19)

DD

THD

SFDꢁ

ꢀMD

Total Harmonic

Distortion

100kHz First 5 Harmonics (Note 19)

750kHz First 5 Harmonics (Note 19)

–87

–83

–90

–86

dB

l

–77

–80

Spurious Free

Dynamic ꢁange

100kHz ꢀnput Signal (Note 19)

750kHz ꢀnput Signal (Note 19)

87

83

90

86

dB

ꢀntermodulation

Distortion

0.625V 1.4MHz Summed with 0.625V , 1.56MHz

–82

dB

P-P

+

–

into CH0 and ꢀnverted into CHO . Also Applicable

+

–

to CH1 and CH1

Code-to-Code

Transition Noise

V

ꢁEF

= 2.5V (Note 17)

0.25

1

LSB

ꢁMS

Full Power Bandwidth

V

= 2.5V , SDO = 11585LSB (–3dBFS) (Note 15)

50

5

50

5

MHz

ꢀN

P-P

Full Linear Bandwidth S/(N + D) ≥ 68dB

14071fb

3

LTC1407-1/LTC1407A-1

T_A= 25°C. V_DD= 3V.

INTERNAL REFERENCE CHARACTERISTICS

PARAMETER

CONDITIONS

ꢀ = 0

OUT

MIN

TYP

2.5

15

MAX

UNITS

V

ꢁEF

V

ꢁEF

V

ꢁEF

V

ꢁEF

V

ꢁEF

Output Voltage

Output Tempco

Line ꢁegulation

Output ꢁesistance

Setting Time

ppm/°C

μV/V

Ω

V

= 2.7V to 3.6V, V = 2.5V

600

0.2

2

DD

ꢁEF

Load Current = 0.5mA

ms

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 3V.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

High Level ꢀnput Voltage

Low Level ꢀnput Voltage

Digital ꢀnput Current

V

= 3.3V

= 2.7V

2.4

V

ꢀH

ꢀL

DD

ꢀN

0.6

10

ꢀ

= 0V to V

μA

pF

V

ꢀN

DD

C

V

Digital ꢀnput Capacitance

High Level Output Voltage

Low Level Output Voltage

5

ꢀN

l

V

DD

= 3V, ꢀ = –200μA

OUT

2.5

2.9

OH

OL

V

DD

V

DD

= 2.7V, ꢀ

= 160μA

= 1.6mA

0.05

0.10

V

OUT

l

0.4

10

ꢀ

OZ

Hi-Z Output Leakage D

V

= 0V to V

DD

μA

pF

OUT

C

Hi-Z Output Capacitance D

1

OZ

OUT

ꢀ

Output Short-Circuit Source Current

Output Short-Circuit Sink Current

V

= 0V, V = 3V

20

15

mA

SOUꢁCE

SꢀNK

OUT

DD

ꢀ

= V = 3V

OUT

DD

POWER REQUIREMENTS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. With internal reference, V_DD= 3V.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply Voltage

Supply Current

2.7

3.6

V

DD

l

ꢀ

Active Mode, f

= 1.5Msps

SAMPLE

4.7

1.1

2.0

7.0

1.5

15

mA

μA

DD

l

Nap Mode

Sleep Mode (LTC1407)

Sleep Mode (LTC1407A)

10

μA

PD

Power Dissipation

Active Mode with SCK in Fixed State (Hi or Lo)

12

mW

14071fb

4

LTC1407-1/LTC1407A-1

TIMING CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 3V.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

f

Maximum Sampling Frequency per Channel

(Conversion ꢁate)

1.5

MHz

SAMPLE(MAX)

l

t

Minimum Sampling Period (Conversion + Acquisition Period)

Clock Period

667

ns

THꢁOUGHPUT

(Note 16)

19.6

32

2

10000

ns

SCK

Conversion Time

(Note 6)

34

SCLK cycles

CONV

Minimum Positive or Negative SCLK Pulse Width

CONV to SCK Setup Time

(Note 6)

ns

ms

1

(Notes 6, 10)

(Note 6)

3

10000

2

SCK Before CONV

0

3

Minimum Positive or Negative CONV Pulse Width

SCK to Sample Mode

(Note 6)

4

(Note 6)

4

5

CONV to Hold Mode

(Notes 6, 11)

(Notes 6, 7, 13)

(Notes 6, 12)

(Notes 6, 14)

1.2

45

8

6

32nd SCK↑ to CONV↑ ꢀnterval (Affects Acquisition Period)

Minimum Delay from SCK to Valid Bits 0 Through 11

SCK to Hi-Z at SDO

7

8

6

9

Previous SDO Bit ꢁemains Valid After SCK

2

10

12

V

ꢁEF

Settling Time After Sleep-to-Wake Transition

2

Note 1: Stresses beyond those listed under Absolute Maximum ꢁatings

may cause permanent damage to the device. Exposure to any Absolute

Maximum ꢁating condition for extended periods may affect device

reliability and lifetime.

Note 10: ꢀf less than 3ns is allowed, the output data will appear one

clock cycle later. ꢀt is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay (1ns) is the

difference between the 2.2ns delay through the sample-and-hold and the

1.2ns CONV to hold mode delay.

Note 2: All voltage values are with respect to ground GND.

Note 3: When these pins are taken below GND or above V , they will be

DD

clamped by internal diodes. This product can handle input currents greater

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the

32nd rising clock and it is ended by the rising edge of CONV.

than 100mA below GND or greater than V without latchup.

DD

+

Note 4: Offset and range speciﬁcations apply for a single-ended CH0

+

–

or CH1 input with CH0 or CH1 grounded and using the internal 2.5V

reference.

Note 14: The internal reference settles in 2ms after it wakes up from sleep

Note 5: ꢀntegral linearity is tested with an external 2.55V reference and is

deﬁned as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 6: Guaranteed by design, not subject to test.

Note 7: ꢁecommended operating conditions.

mode with one or more cycles at SCK and a 10μF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

swing drops by 3dB with a 2.5V input sine wave.

P-P

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read with an arbitrarily long clock period.

Note 17: The LTC1407A-1 is measured and speciﬁed with 14-bit

ꢁesolution (1LSB = 152μV) and the LTC1407-1 is measured and speciﬁed

with 12-bit ꢁesolution (1LSB = 610μV).

Note 18: The sampling capacitor at each input accounts for 4.1pF of the

input capacitance.

Note 19: Full-scale sinewaves are fed into the noninverting inputs while

the inverting inputs are kept at 1.5V DC.

Note 8: The analog input range is deﬁned for the voltage difference

+

–

+

–

between CH0 and CH0 or CH1 and CH1 . Performance is speciﬁed

–

+

–

with CHO = 1.5V DC while driving CHO and with CH1 = 1.5V DC while

driving CH1 .

Note 9: The absolute voltage at CH0 , CH0 , CH1 and CH1 must be

+

–

+

–

within this range.

14071fb

5

LTC1407-1/LTC1407A-1

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3V, T_A= 25°C. Single-ended signals drive

+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with V_CM= 1.5V DC (LTC1407A-1)

ENOBs and SINAD

THD, 2nd and 3rd

vs Input Frequency

vs Input Sinewave Frequency

SFDR vs Input Frequency

–44

–50

–56

–62

104

98

92

86

80

74

68

62

56

50

44

12.0

11.5

11.0

10.5

10.0

9.5

74

71

68

65

62

59

56

53

50

–68

–74

THD

2ND

3ꢁD

–80

–86

9.0

–92

8.5

–98

–104

8.0

0.1

1

10

100

0.1

1

10

100

0.1

1

10

100

FꢁEQUENCY (MHz)

14071 G02

14071 G03

14071 G01

ENOBs and SINAD

vs Input Sinewave Frequency

for Differential Input Signals

THD, 2nd and 3rd

vs Input Frequency for

SNR vs Input Frequency

Differential Input Signals

–44

–50

–56

–62

12.0

11.5

11.0

10.5

10.0

9.5

74

71

68

65

62

59

56

53

50

74

71

68

65

62

59

56

53

50

–68

–74

THD

3ꢁD

2ND

–80

–86

9.0

–92

8.5

–98

8.0

0.1

–104

1

10

100

0.1

1

10 20

0.1

1

10

100

FꢁEQUENCY (MHz)

14071 G05

14071 G06

14071 G04

748kHz Sine Wave 4096 Point

FFT Plot

SFDR vs Input Frequency for

Differential Input Signals

98kHz Sine Wave 4096 Point

FFT Plot

104

98

92

86

80

74

68

62

56

50

44

0

–10

0

–10

–20

–30

–40

–50

–30

–40

–50

–60

–70

–80

–90

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0

100 200 300 400 500 600 700

0.1

1

10

100

0

100 200 300 400 500 600 700

FꢁEQUENCY (kHz)

FꢁEQUENCY (MHz)

FꢁEQUENCY (kHz)

14071 G07

14071 G08

14071 G09

14071fb

6

LTC1407-1/LTC1407A-1

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3V, T_A= 25°C. Single-ended signals drive

+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with V_CM= 1.5V DC (LTC1407A-1)

1403kHz Input Summed with

1563kHz Input IMD 4096 Point FFT

Plot for Differential Input Signals

10.7MHz Sine Wave 4096 Point

FFT Plot for Differential Input

Signals

748kHz Sine Wave 4096 Point FFT

Plot for Differential Input Signals

0

–10

0

–10

–20

0

–10

–20

–30

–40

–50

–30

–40

–50

–30

–40

–50

–60

–70

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

185k

371k

556k

741k

0

185k

371k

556k

741k

0

100 200 300 400 500 600 700

FꢁEQUENCY (Hz)

FꢁEQUENCY (kHz)

14071 G11

14071 G12

14071 G10

Integral Linearity End Point Fit for

CH0 with Internal 2.5V Reference

for Differential Input Signals

Differential Linearity for CH0 with

Internal 2.5V Reference

Integral Linearity End Point Fit for

CH0 with Internal 2.5V Reference

1.0

0.8

4.0

3.2

4.0

3.2

0.6

2.4

0.4

1.6

0.2

0.8

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.8

–1.6

–2.4

–3.2

–4.0

–0.8

–1.6

–2.4

–3.2

–4.0

0

8192

12288

4096

16384

0

8192

12288

4096

16384

0

8192

12288

4096

16384

OUTPUT CODE

14071 G13

14071 G14

14071 G15

Integral Linearity End Point Fit for

CH1 with Internal 2.5V Reference

for Differential Input Signals

Differential Linearity for CH1 with

Internal 2.5V Reference

Integral Linearity End Point Fit for

CH1 with Internal 2.5V Reference

4.0

3.2

1.0

0.8

4.0

3.2

2.4

0.6

2.4

1.6

0.4

1.6

0.8

0.2

0.8

0

–0.8

–1.6

–2.4

–3.2

–4.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.8

–1.6

–2.4

–3.2

–4.0

0

8192

12288

4096

16384

0

8192

12288

0

8192

12288

4096

16384

4096

16384

OUTPUT CODE

14071 G17

14071 G16

14071 G18

14071fb

7

LTC1407-1/LTC1407A-1

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3V, T_A= 25°C. Single ended signals drive

+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with V_CM= 1.5V DC (LTC1407A-1)

Differential and Integral Linearity

vs Conversion Rate

SINAD vs Conversion Rate

78

77

76

75

74

73

72

71

70

69

68

8

7

6

5

4

3

MAX ꢀNL

2

1

MAX DNL

0

MꢀN DNL

MꢀN ꢀNL

–1

–2

–3

–4

EXTEꢁNAL V

ꢀNTEꢁNAL V

= 3.3V, f ~ fS/3

ꢀN

ꢁEF

= 3.3V, f ~ fS/40

ꢀN

= 2.5V, f ~ fS/3

ꢀN

= 2.5V, f ~ fS/40

ꢀN

ꢀNTEꢁNAL V

2

2.5

3

3.5

4

3

3.25

3.5 3.75

2

2.25 2.5 2.75

4

CONVEꢁSꢀON ꢁATE (Msps)

CONVEꢁSꢀON ꢁATE (MSPS)

14071 G20

14071 G19

V_DD= 3V, T_A= 25°C (LTC1407-1/LTC1407A-1)

Full-Scale Signal Frequency

Response

CMRR vs Frequency

Crosstalk vs Frequency

0

12

–20

–30

–40

–50

–60

–70

–80

–90

6

0

–20

–40

–6

–12

–18

–60

–80

CH0

CH1

CH1 TO CH0

CH0 TO CH1

–24

–30

–36

–100

–120

1M

10M

100M

1G

100

1k

10k 100k

1M

10M 100M

100

1k

10k

100k

1M

10M

FꢁEQUENCY (Hz)

14071 G22

14071 G21

14071 G23

Output Match with Simultaneous

Input Steps at CH0 and CH1

from 25Ω

PSSR vs Frequency

–25

16384

14336

12288

10240

CH0 AND CH1

ꢁꢀSꢀNG

–30

–35

–40

–45

–50

–55

–60

–65

–70

CH0

CH1

8192

6144

4096

2048

0

CH0 AND CH1

FALLꢀNG

1

10

100

1k

10k 100k

1M

0

5

15

–5

20

25

10

FꢁEQUENCY (Hz)

TꢀME (ns)

14071 G25

14071 G24

14071fb

8

LTC1407-1/LTC1407A-1

TYPICAL PERFORMANCE CHARACTERISTICS

V_DD= 3V, T_A= 25°C (LTC1407-1/LTC1407A-1)

Reference Voltage

vs Load Current

Reference Voltage vs V_DD

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

LOAD CUꢁꢁENT (mA)

2.6

2.8

3.0

3.2

(V)

3.4

3.6

V

DD

14071 G27

14071 G26

PIN FUNCTIONS

+

CH0 (Pin 1): Noninverting Channel 0. CH0 operates

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

ﬂow through these connections.

–

fully differentially with respect to CH0 , with a –1.25V to

–

1.25V differential swing with respect to CH0 and a 0 to

V

absolute input range.

DD

V

(Pin 7): 3V Positive Supply. This single power pin

DD

–

CH0 (Pin 2): ꢀnverting Channel 0. CH0 operates fully

supplies 3V to the entire chip. Bypass to GND pin and

solid analog ground plane with a 10μF ceramic capacitor

(or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in

mindthatinternalanalogcurrentsanddigitaloutputsignal

currents ﬂow through this pin. Care should be taken to

place the 0.1μF bypass capacitor as close to Pins 6 and 7

as possible.

+

differentially with respect to CH0 , with a 1.25V to –1.25V

+

differential swing with respect to CH0 and a 0 to V

absolute input range.

DD

V

(Pin 3): 2.5V ꢀnternal ꢁeference. Bypass to GND and

REF

a solid analog ground plane with a 10μF ceramic capacitor

(or 10μF tantalum in parallel with 0.1μF ceramic). Can be

overdriven by an external reference voltage ≥2.55V and

SDO (Pin 8): Three-State Serial Data Output. Each pair of

outputdatawordsrepresentthetwoanaloginputchannels

at the start of the previous conversion. The output format

is 2’s complement.

≤V .

DD

+

CH1 (Pin 4): Noninverting Channel 1. CH1 operates

–

fully differentially with respect to CH1 , with a –1.25V to

–

1.25V differential swing with respect to CH1 and a 0 to

SCK (Pin 9): External Clock ꢀnput. Advances the conver-

sion process and sequences the output data on the rising

edge. One or more pulses wake from sleep.

V

absolute input range.

DD

–

CH1 (Pin 5): ꢀnverting Channel 1. CH1 operates fully

+

differentially with respect to CH1 , with a 1.25V to –1.25V

CONV (Pin 10): Convert Start. Holds the two analog input

signals and starts the conversion on the rising edge. Two

pulses with SCK in ﬁxed high or ﬁxed low state starts nap

mode. Four or more pulses with SCK in ﬁxed high or ﬁxed

low state starts sleep mode.

+

differential swing with respect to CH1 and a 0 to V

absolute input range.

DD

GND (Pins 6, 11): Ground and Exposed Pad. This single

ground pin and the Exposed Pad must be tied directly to

14071fb

9

LTC1407-1/LTC1407A-1

BLOCK DIAGRAM

10μF 3V

7

V

DD

LTC1407A-1

+

CH0

1

2

+

–

S & H

–

CH0

THꢁEE-

STATE

SEꢁꢀAL

OUTPUT

POꢁT

3Msps

14-BꢀT ADC

MUX

8

SDO

+

–

CH1

4

5

3

+

S & H

CH1

–

10

9

CONV

SCK

TꢀMꢀNG

LOGꢀC

V

ꢁEF

10μF

GND

2.5V

ꢁEFEꢁENCE

6

EXPOSED PAD

11

1407A1 BD

14071fb

10

LTC1407-1/LTC1407A-1

TIMING DIAGRAMS

14071fb

11

LTC1407-1/LTC1407A-1

TIMING DIAGRAMS

Nap Mode Waveforms

SCK

t

1

CONV

NAP

Sleep Mode Waveforms

SCK

t

1

CONV

NAP

SLEEP

t

12

V

1407 TD02

ꢁEF

NOTE: NAP AND SLEEP AꢁE ꢀNTEꢁNAL SꢀGNALS

SCK to SDO Delay

SCK

V

ꢀH

t

10

8

t

9

V

90%

10%

OH

OL

SDO

14071 TD03

14071fb

12

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

DRIVING THE ANALOG INPUT

the time between conversions. The best choice for an op

amp to drive the LTC1407-1/LTC1407A-1 depends on the

application.Generally,applicationsfallintotwocategories:

AC applications where dynamic speciﬁcations are most

critical and time domain applications where DC accuracy

and settling time are most critical. The following list is a

summary of the op amps that are suitable for driving the

LTC1407-1/LTC1407A-1.

ThedifferentialanaloginputsoftheLTC1407-1/LTC1407A-1

are easy to drive. The inputs may be driven differentially or

–

asasingle-endedinput(i.e.,theCH0 inputisACgrounded

at V /2). All four analog inputs of both differential analog

CC

+

–

+

–

input pairs, CH0 with CH0 and CH1 with CH1 , are

sampled at the same instant. Any unwanted signal that is

commontobothinputsofeachinputpairwillbereducedby

thecommonmoderejectionofthesample-and-holdcircuit.

Theinputsdrawonlyonesmallcurrentspikewhilecharging

the sample-and-hold capacitors at the end of conversion.

During conversion, the analog inputs draw only a small

leakage current. ꢀf the source impedance of the driving

circuit is low, then the LTC1407-1/LTC1407A-1 inputs can

be driven directly. As source impedance increases, so will

acquisition time. For minimum acquisition time with high

source impedance, a buffer ampliﬁer must be used. The

main requirement is that the ampliﬁer driving the analog

input(s) must settle after the small current spike before

the next conversion starts (settling time must be 39ns for

full throughput rate). Also keep in mind, while choosing

an input ampliﬁer, the amount of noise and harmonic

distortion added by the ampliﬁer.

LTC1566-1: Low Noise 2.3MHz Continuous Time Low-

pass Filter.

LT^®1630: Dual 30MHz ꢁail-to-ꢁail Voltage FB Ampliﬁer.

2.7V to 15V supplies. Very high A , 500μV offset and

VOL

520ns settling to 0.5LSB for a 4V swing. THD and noise

are –93dB to 40kHz and below 1LSB to 320kHz (A = 1,

V

2V into 1kꢂ, V = 5V), making the part excellent for

P-P

S

AC applications (to 1/3 Nyquist) where rail-to-rail perfor-

mance is desired. Quad version is available as LT1631.

LT1632: Dual 45MHz ꢁail-to-ꢁail Voltage FB Ampliﬁer.

2.7V to 15V supplies. Very high A , 1.5mV offset and

VOL

400ns settling to 0.5LSB for a 4V swing. ꢀt is suitable for

applications with a single 5V supply. THD and noise are

–93dB to 40kHz and below 1LSB to 800kHz (A = 1,

V

2V into 1kꢂ, V = 5V), making the part excellent for

P-P

S

ACapplicationswhererail-to-railperformanceisdesired.

Quad version is available as LT1633.

CHOOSING AN INPUT AMPLIFIER

Choosing an input ampliﬁer is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the ampliﬁer from charging

the sampling capacitor, choose an ampliﬁer that has a low

output impedance (<100ꢂ) at the closed-loop bandwidth

frequency. For example, if an ampliﬁer is used in a gain

of 1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz must be less than 100ꢂ. The

secondrequirementisthattheclosed-loopbandwidthmust

be greater than 40MHz to ensure adequate small-signal

settling for full throughput rate. ꢀf slower op amps are

used, more time for settling can be provided by increasing

LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/ampli-

ﬁer, 8.5nV/√Hz.

LT1806/LT1807: 325MHz GBWP, –80dBc distortion at

5MHz, unity-gain stable, rail-to-rail in and out, 10mA/am-

pliﬁer, 3.5nV/√Hz

.

LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,

unity-gain stable, rail-to-rail in and out, 15mA/ampliﬁer,

16nV/√Hz.

LinearView is a trademark of Linear Technology Corporation.

14071fb

13

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

LT1818/LT1819: 400MHz, 2500V/μs, 9mA, Single/Dual

Voltage Mode Operational Ampliﬁer.

components can add distortion. NPO and silvermica type

dielectriccapacitorshaveexcellentlinearity.Carbonsurface

mount resistors can generate distortion from self heating

and from damage that may occur during soldering. Metal

ﬁlm surface mount resistors are much less susceptible to

both problems. When high amplitude unwanted signals

are close in frequency to the desired signal frequency a

multiple pole ﬁlter is required.

LT6200: 165MHz GBWP, –85dBc distortion at 1MHz,

unity-gain stable, rail-to-rail in and out, 15mA/ampliﬁer,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc distortion at 1MHz,

unity-gain stable, rail-to-rail in and out, 3mA/ampliﬁer,

1.9nV/√Hz.

High external source resistance, combined with 13pF

of input capacitance, will reduce the rated 50MHz input

bandwidth and increase acquisition time beyond 39ns.

LT6600: Ampliﬁer/Filter Differential ꢀn/Out with 10MHz

Cutoff.

INPUT FILTERING AND SOURCE IMPEDANCE

INPUT RANGE

The noise and the distortion of the input ampliﬁer and

other circuitry must be considered since they will add

to the LTC1407-1/LTC1407A-1 noise and distortion. The

small-signal bandwidth of the sample-and-hold circuit is

50MHz. Any noise or distortion products that are pres-

ent at the analog inputs will be summed over this entire

bandwidth. Noisy input circuitry should be ﬁltered prior

to the analog inputs to minimize noise. A simple 1-pole

ꢁC ﬁlter is sufﬁcient for many applications. For example,

The analog inputs of the LTC1407-1/LTC1407A-1 may be

driven fully differentially with a single supply. Either input

may swing up to 3V, provided the differential swing is no

greater than 1.25V. ꢀn the valid input range, each input of

each channel is always up to 1.25V away from the other

input of each channel. The –1.25V to 1.25V range is also

ideally suited for AC-coupled signals in single supply

applications. Figure 2 shows how to AC-couple signals

in a single supply system without needing a mid-supply

1.5V DC external reference. The DC common mode level

is supplied by the previous stage that is already bounded

by single supply voltage of the system. The common

+

Figure 1 shows a 47pF capacitor from CHO to ground

and a 51ꢂ source resistor to limit the net input bandwidth

to 30MHz. The 47pF capacitor also acts as a charge

reservoir for the input sample-and-hold and isolates the

ADC input from sampling-glitch sensitive circuitry. High

qualitycapacitorsandresistorsshouldbeusedsincethese

mode range of the inputs extends from ground to the

+

supply voltage V . ꢀf the difference between the CH0

DD

–

+

–

and CH0 inputs or the CH1 and CH1 inputs exceeds

1.25V, the output code will stay ﬁxed at zero and all ones,

and if this difference goes below –1.25V, the output code

will stay ﬁxed at one and all zeros.

51ꢂ*

1

ANALOG

ꢀNPUT

+

CH0

47pF*

2

V

–

CM

1.5V DC

LTC1407-1/

LTC1407A-1

C2

1μF

3

V

ꢁEF

10μF

LTC1407-1/

ꢁ2

11

LTC1407A-1

GND

1.6k

1

ꢁ3

+

CHO

V

51Ω*

51Ω

ANALOG

ꢀNPUT

4

2

+

–

CH1

V

ꢀN

4.09V 3

47pF*

ꢁ1

1.6k

ꢁEF

C4

10μF

C3

56pF

C1

1μF

+

5

14071 F02

V

–

CM

1.5V DC

C1, C2: FꢀLM TYPE

C3: COG TYPE

C4: CEꢁAMꢀC BYPASS

14071 F01

*TꢀGHT TOLEꢁANCE ꢁEQUꢀꢁED TO AVOꢀD

APEꢁTUꢁE SKEW DEGꢁADATꢀON

Figure 1. RC Input Filter

Figure 2. AC Coupling of AC Signals with 1kHz Low Cut

14071fb

14

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

INTERNAL REFERENCE

errors (DNL) are largely independent of the common

mode voltage. However, the offset error will vary. CMꢁꢁ

is typically better than 60dB.

TheLTC1407-1/LTC1407A-1haveanon-chip,temperature

compensated, bandgap reference that is factory trimmed

near 2.5V to obtain a precise 1.25V input span. The ref-

erence ampliﬁer output V_ꢁEF, (Pin 3) must be bypassed

with a capacitor to ground. The reference amplifier is

stable with capacitors of 1μF or greater. For the best noise

performance, a 10μF ceramic or a 10μF tantalum in paral-

lel with a 0.1μF ceramic is recommended. The V_ꢁEFpin

can be overdriven with an external reference as shown

in Figure 3. The voltage of the external reference must be

higher than the 2.5V of the open-drain P-channel output

of the internal reference. The recommended range for an

external reference is 2.55V to V_DD. An external reference

at 2.55V will see a DC quiescent load of 0.75mA and as

much as 3mA during conversion.

Figure 5 shows the ideal input/output characteristics for

the LTC1407-1/LTC1407A-1. The code transitions occur

midway between successive integer LSB values (i.e.,

0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code

is 2’s complement with 1LSB = 2.5V/16384 = 153μV for

the LTC1407A-1 and 1LSB = 2.5V/4096 = 610μV for the

LTC1407-1. The LTC1407A-1 has 1LSB ꢁMS of Gaussian

white noise. Figure 6a shows the LTC1819 converting a

single-ended input signal to differential input signals for

optimum THD and SFDꢁ performance as shown in the

FFT plot (Figure 6b).

0

–20

–40

3

3V ꢁEF

V

ꢁEF

LTC1407-1/

LTC1407A-1

GND

10μF

–60

11

CH0

CH1

–80

14071 F02

–100

–120

Figure 3

100

1k

10k 100k

1M

10M 100M

INPUT SPAN VERSUS REFERENCE VOLTAGE

FꢁEQUENCY (Hz)

14071 F04

Thedifferentialinputrangehasaunipolarvoltagespanthat

equals the difference between the voltage at the reference

Figure 4. CMRR vs Frequency

buffer output V (Pin 3) and the voltage at the Exposed

ꢁEF

Pad ground. The differential input range of ADC is –1.25V

to 1.25V when using the internal reference. The internal

ADC is referenced to these two nodes. This relationship

also holds true with an external reference.

011...111

011...110

011...101

DIFFERENTIAL INPUTS

TheADCwillalwaysconvertthebipolardifferenceofCH0⁺

minusCH0^–orthebipolardifferenceofCH1⁺minusCH1^–,

independent of the common mode voltage at either set

of inputs. The common mode rejection holds up at high

frequencies (see Figure 4). The only requirement is that

both inputs not go below ground or exceed V_DD. ꢀntegral

nonlinearity errors (ꢀNL) and differential nonlinearity

100...010

100...001

100...000

–FS

FS – 1LSB

ꢀNPUT VOLTAGE (V)

14071 F05

Figure 5. LTC1407-1/LTC1407A-1 Transfer Characteristic

14071fb

15

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

5V

0

–10

–20

C5

0.1μF

–30

–40

–50

C3

–

ꢁ1

1μF

–60

–70

51ꢂ

U1

+CH0 Oꢁ

+CH1

1/2 LT1819

V

P-P

MAX

ꢀN

+

C1

–80

1.25V

C6

0.1μF

47pF

–90

ꢁ5

1k

–100

–110

–120

ꢁ4

499ꢂ

ꢁ3

499ꢂ

1.5V

CM

LTC1407A-1

–5V

ꢁ6

1k

0

185k

371k

FꢁEQUENCY (Hz)

556k

741k

C4

1μF

–

ꢁ2

51ꢂ

14031 F06b

U2

–CH0 Oꢁ

–CH1

1/2 LT1819

+

Figure 6b. LTC1407-1 6MHz Sine Wave 4096 Point FFT Plot

with the LT1819 Driving the Inputs Differentially

C2

47pF

1407A F06a

Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1407-1/LTC1407A-1, a printed

circuit board with ground plane is required. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. ꢀn

particular, care should be taken not to run any digital track

alongside an analog signal track. ꢀf optimum phase match

between the inputs is desired, the length of the four input

wires of the two input channels should be kept matched.

But each pair of input wires to the two input channels

should be kept separated by a ground trace to avoid high

frequency crosstalk between channels.

High quality tantalum and ceramic bypass capacitors

should be used at the V and V pins as shown in the

DD

ꢁEF

Block Diagram on the ﬁrst page of this data sheet. For

optimum performance, a 10μF surface mount tantalum

capacitorwitha0.1μFceramicisrecommendedfortheV

DD

1407-1 F07

and V pins. Alternatively, 10μF ceramic chip capacitors

ꢁEF

Figure 7. Recommended Layout

such as X5ꢁ or X7ꢁ may be used. The capacitors must be

located as close to the pins as possible. The traces con-

necting the pins and the bypass capacitors must be kept

Care should be taken to place the 0.1μF V bypass ca-

DD

pacitor as close to Pins 6 and 7 as possible.

short and should be made as wide as possible. The V

DD

Figure7showstherecommendedsystemgroundconnec-

tions. All analog circuitry grounds should be terminated

14071fb

bypass capacitor returns to GND (Pin 6) and the V by-

ꢁEF

passcapacitorreturnstotheExposedPadground(Pin11).

16

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

at the LTC1407-1/LTC1407A-1 Exposed Pad. The ground

returnfromtheLTC1407-1/LTC1407A-1Pin6tothepower

supply should be low impedance for noise-free operation.

The Exposed Pad of the 10-lead MSE package is also tied

toPin 6andtheLTC1407-1/LTC1407A-1GND.TheExposed

Pad should be soldered on the PC board to reduce ground

connection inductance. Digital circuitry grounds must be

connected to the digital supply common.

compatible, if the logic swing does not exceed V . A de-

DD

tailed description of the three serial port signals follows:

Conversion Start Input (CONV)

The rising edge of CONV starts a conversion, but subse-

quent rising edges at CONV are ignored by the LTC1407-1/

LTC1407A-1 until the following 32 SCK rising edges have

occurred. ThedutycycleofCONVcanbearbitrarilychosen

to be used as a frame sync signal for the processor serial

port.AsimpleapproachtogenerateCONVistocreateapulse

that is one SCK wide to drive the LTC1407-1/LTC1407A-1

and then buffer this signal to drive the frame sync input

of the processor serial port. ꢀt is good practice to drive the

LTC1407-1/LTC1407A-1 CONV input ﬁrst to avoid digital

noise interference during the sample-to-hold transition

triggeredbyCONVatthestartofconversion.ꢀtisalsogood

practice to keep the width of the low portion of the CONV

signal greater than 15ns to avoid introducing glitches in

the front end of the ADC just before the sample-and-hold

goes into hold mode at the rising edge of CONV.

POWER-DOWN MODES

Uponpower-up,theLTC1407-1/LTC1407A-1areinitialized

to the active state and are ready for conversion. The nap

and sleep mode waveforms show the power-down modes

fortheLTC1407-1/LTC1407A-1.TheSCKandCONVinputs

controlthepower-downmodes(seeTimingDiagrams).Two

risingedgesatCONV, withoutanyinterveningrisingedges

at SCK, put the LTC1407-1/LTC1407A-1 in nap mode and

the power drain drops from 14mW to 6mW. The internal

reference remains powered in nap mode. One or more

rising edges at SCK wake up the LTC1407-1/LTC1407A-1

for service very quickly and CONV can start an accurate

conversion within a clock cycle.

Minimizing Jitter on the CONV Input

ꢀnhighspeedapplicationswherehighamplitudesinewaves

above 100kHz are sampled, the CONV signal must have

as little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

thisrequirementeasily.ThechallengeistogenerateaCONV

signalfromthiscrystalclockwithoutjittercorruptionfrom

other digital circuits in the system. A clock divider and

any gates in the signal path from the crystal clock to the

CONV input should not share the same integrated circuit

with other parts of the system. As shown in the interface

circuit examples, the SCK and CONV inputs should be

drivenﬁrst, withdigitalbuffersusedtodrivetheserialport

interface. Also note that the master clock in the DSP may

already be corrupted with jitter, even if it comes directly

from the DSP crystal. Another problem with high speed

processor clocks is that they often use a low cost, low

speed crystal (i.e., 10MHz) to generate a fast, but jittery,

phase-locked-loop system clock (i.e., 40MHz). The jitter

in these PLL-generated high speed clocks can be several

nanoseconds. Note that if you choose to use the frame

sync signal generated by the DSP port, this signal will

have the same jitter of the DSP’s master clock.

Four rising edges at CONV, without any intervening rising

edgesatSCK,puttheLTC1407-1/LTC1407A-1insleepmode

andthepowerdraindropsfrom14mWto10μW.Tobringthe

partoutofsleepmoderequiresoneormorerisingSCKedges

followed by a nap request. Then one or more rising edges

at SCK wake up the LTC1407-1/LTC1407A-1 for operation.

When nap mode is entered after sleep mode, the reference

that was shut down in sleep mode is reactivated.

The internal reference (V ) takes 2ms to slew and settle

ꢁEF

with a 10μF load. Using sleep mode more frequently com-

promises the settled accuracy of the internal reference.

Note that for slower conversion rates, the nap and sleep

modes can be used for substantial reductions in power

consumption.

DIGITAL INTERFACE

The LTC1407-1/LTC1407A-1 have a 3-wire SPꢀ (serial

protocol interface) interface. The SCK and CONV inputs

and SDO output implement this interface. The SCK and

CONV inputs accept swings from 3V logic and are TTL

14071fb

17

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

Serial Clock Input (SCK)

be valid by the next rising edge of SCK. The 32-bit output

data stream is compatible with the 16-bit or 32-bit serial

port of most processors.

The rising edge of SCK advances the conversion process

and also updates each bit in the SDO data stream. After

CONV rises, the third rising edge of SCK sends out two

sets of 12/14 data bits, with the MSB sent ﬁrst. A simple

approach is to generate SCK to drive the LTC1407-1/

LTC1407A-1 ﬁrst and then buffer this signal with the

appropriate number of inverters to drive the serial clock

input of the processor serial port. Use the falling edge of

the clock to latch data from the serial data output (SDO)

into your processor serial port. The 14-bit serial data will

be received right justiﬁed, in two 16-bit words with 32 or

more clocks per frame sync. ꢀt is good practice to drive

the LTC1407-1/LTC1407A-1 SCK input ﬁrst to avoid digi-

tal noise interference during the internal bit comparison

decision by the internal high speed comparator. Unlike the

CONVinput, theSCKinputisnotsensitivetojitterbecause

the input signal is already sampled and held constant.

HARDWARE INTERFACE TO TMS320C54x

The LTC1407-1/LTC1407A-1 are serial output ADCs

whose interface has been designed for high speed buff-

ered serial ports in fast digital signal processors (DSPs).

Figure 8 shows an example of this interface using a

TMS320C54X.

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial

data can be collected in two alternating 1kB segments,

in real time, at the full 3Msps conversion rate of the

LTC1407-1/LTC1407A-1. The DSP assembly code sets

frame sync mode at the BFSꢁ pin to accept an external

positive going pulse and the serial clock at the BCLKꢁ

pin to accept an external positive edge clock. Buffers near

the LTC1407-1/LTC1407A-1 may be added to drive long

tracks to the DSP to prevent corruption of the signal to

LTC1407-1/LTC1407A-1. This conﬁguration is adequate

to traverse a typical system board, but source resistors

at the buffer outputs and termination resistors at the DSP,

may be needed to match the characteristic impedance

of very long transmission lines. ꢀf you need to terminate

the SDO transmission line, buffer it ﬁrst with one or two

74ACxx gates. The TTL threshold inputs of the DSP port

respondproperlytothe3VswingusedwiththeLTC1407-1/

LTC1407A-1.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to

the high impedance state. The SDO output remains in high

impedance until a new conversion is started. SDO sends

out two sets of 12/14 bits in 2’s complement format in the

output data stream after the third rising edge of SCK after

the start of conversion with the rising edge of CONV. The

two 12-/14-bit words are separated by two clock cycles in

high impedance mode. Please note the delay speciﬁcation

from SCK to a valid SDO. SDO is always guaranteed to

3V

5V

7

V

CC

DD

10

9

CONV

LTC1407-1/

LTC1407A-1

SCK

BFSꢁ

TMS320C54x

BCLKꢁ

B13 B12

8

6

SDO

GND

BDꢁ

CONV

CLK

3-WꢀꢁE SEꢁꢀAL

ꢀNTEꢁFACELꢀNK

14071 F08

0V TO 3V LOGꢀC SWꢀNG

Figure 8. DSP Serial Interface to TMS320C54x

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18

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

; 12-03-03 ******************************************************************

; Files: 014SIAB.ASM ->

1407A Sine wave collection with Serial Port interface

both channels collected in sequence in the same 2k record.

Buffered mode 2k buffer size.

;

bvectors.asm

s2k14ini.asm

; First element at 1024, last element at 1023, two middles at 2047 and 0000

; bipolar mode

; Works 16 or 64 clock frames.

; negative edge BCLKR

; negative BFSR pulse

; -0 data shifted

; ***************************************************************************

.width

160

.length 110

.title “sineb0 BSP in auto buffer mode”

.mmregs

.setsect “.text”,

0x500,0

;Set address of executable

.setsect “vectors”, 0x180,0

.setsect “buffer”, 0x800,0

.setsect “result”, 0x1800,0

.text

;Set address of incoming 1403 data

;Set address of BSP buffer for clearing

;Set address of result for clearing

;.text marks start of code

start:

;this label seems necessary

;Make sure /PWRDWN is low at J1-9

;to turn off AC01 adc

tim=#0fh

prd=#0fh

tcr = #10h

tspc = #0h

pmst = #01a0h

sp = #0700h

dp = #0

; stop timer

; stop TDM serial port to AC01

; set up iptr. Processor Mode STatus register

; init stack pointer.

; data page

ar2 = #1800h

ar3 = #0800h

ar4 = #0h

; pointer to computed receive buffer.

; pointer to Buffered Serial Port receive buffer

; reset record counter

call sineinit

; Double clutch the initialization to insure a proper

sinepeek:

call sineinit

; reset. The external frame sync must occur 2.5 clocks

; or more after the port comes out of reset.

wait

goto wait

;

———————— Buffered Receive Interrupt Routine —————————

breceive:

ifr = #10h

TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer

; clear interrupt ﬂags

; if this still the ﬁrst half get next half

if (NTC) goto bufull

bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))

return_enable

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19

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

;

——————— mask and shift input data ——————————————

bufull:

b = *ar3+ << -0

b = #07FFFh & b

b = b ^ #2000h

; load acc b with BSP buffer and shift right -0

; mask out the TRISTATE bits with #03FFFh

; invert the MSB for bipolar operation

;

*ar2+ = data(#0bh)

; store B to out buffer and advance AR2 pointer

TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h

if (TC) goto start

goto bufull

; restart if out buffer is at 1fffh

;

————————— dummy bsend return ————————————

return_enable ;this is also a dummy return to deﬁne bsend

;in vector table ﬁle BVECTORS.ASM

bsend

;

——————————— end ISR ——————————————

.copy “c:\dskplus\1403\s2k14ini.asm”

;initialize buffered serial port

.space 16*32

;clear a chunk at the end to mark the end

;======================================================================

;

VECTORS

;======================================================================

.sect “vectors”

;The vectors start here

;get BSP vectors

.copy “c:\dskplus\1403\bvectors.asm”

.sect “buffer”

.space 16*0x800

.sect “result”

.space 16*0x800

;Set address of BSP buffer for clearing

;Set address of result for clearing

.end

; ***************************************************************************

; File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus

10.Jul.96

;

BSP vectors and Debugger vectors

TDM vectors just return

; ***************************************************************************

; The vectors in this table can be conﬁgured for processing external and

; internal software interrupts. The DSKplus debugger uses four interrupt

; vectors. These are RESET, TRAP2, INT2, and HPIINT.

;

*

DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER

*

; All other vector locations are free to use. When programming always be sure

; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and

; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the

; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.

;

14071fb

20

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

.title “Vector Table”

.mmregs

reset

nmi

goto #80h

;00; RESET * DO NOT MODIFY IF USING DEBUGGER *

nop

return_enable

;04; non-maskable external interrupt

nop

trap2

int0

goto #88h

;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *

nop

.space 52*16

;0C-3F: vectors for software interrupts 18-30

;40; external interrupt int0

return_enable

nop

int1

return_enable

;44; external interrupt int1

;48; external interrupt int2

;4C; internal timer interrupt

;50; BSP receive interrupt

;54; BSP transmit interrupt

;58; TDM receive interrupt

nop

int2

return_enable

nop

tint

return_enable

nop

brint

bxint

trint

goto breceive

nop

goto bsend

nop

return_enable

nop

txint

int3

return_enable

;5C; TDM transmit interrupt

;60; external interrupt int3

nop

return_enable

nop

hpiint

dgoto #0e4h

;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *

nop

14071fb

21

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

.space 24*16

;68-7F; reserved area

**********************************************************************

*

**********************************************************************

*

* File: s2k14ini.ASM BSP initialization code for the ‘C54x DSKplus

*

for use with 1407 in buffered mode

BSPC and SPC are the same in the ‘C542

BSPCE and SPCE seem the same in the ‘C542

**********************************************************************

.title “Buffered Serial Port Initialization Routine”

ON

.set 1

OFF

.set !ON

.set 1

YES

NO

.set !YES

.set 2

BIT_8

BIT_10

BIT_12

BIT_16

GO

.set 1

.set 3

.set 0

.set 0x80

**********************************************************************

* This is an example of how to initialize the Buffered Serial Port (BSP).

* The BSP is initialized to require an external CLK and FSX for

* operation. The data format is 16-bits, burst mode, with autobuffering

* enabled.

*

*******************************************************************************************

*LTC1407 timing from board with 10MHz crystal.

*

*10MHz, divided from 40MHz, forced to CLKIN by 1407 board.

*

*Horizontal scale is 25ns/chr or 100ns period at BCLKR

*

*Timing measured at DSP pins. Jxx pin labels for jumper cable.

*

*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/

~~~~~~~~~~~*

*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/

~\_/~\_/~*

*BDR

B12*

Pin J1-26 _—_—_—<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—<B13-

*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/

~~~~~~~\_______/~~~~~*

*C542 read

0

B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

0

B13 B12*

*

* negative edge BCLKR

* negative BFSR pulse

* no data shifted

* 1’ cable from counter to CONV at DUT

14071fb

22

LTC1407-1/LTC1407A-1

APPLICATIONS INFORMATION

* 2’ cable from counter to CLK at DUT

*No right shift is needed to right justify the input data in the main program

*

*the two msbs should also be masked

*

*******************************************************************************************

*

Loopback

Format

.set

NO

;(digital looback mode?)

;(Data format? 16,12,10,8)

DLB bit

FO bit

BIT_16

NO

IntSync

;(internal Frame syncs generated?) TXM bit

IntCLK

BurstMode

CLKDIV

NO

;(internal clks generated?)

MCM bit

YES

3

;(if BurstMode=NO, then Continuous) FSM bit

;(3=default value, 1/4 CLOCKOUT)

;(Turn on PCM mode?)

PCM_Mode

FS_polarity

CLK_polarity

Frame_ignore

XMTautobuf

RCVautobuf

XMThalt

NO

YES

NO

;(change polarity)YES=^^^\_/^^^, NO=___/^\___

;(change polarity)for BCLKR YES=_/^, NO=~\_

;(inverted !YES -ignores frame)

;(transmit autobuffering)

!YES

NO

YES

NO

;(receive autobuffering)

;(transmit buff halt if XMT buff is full)

;(receive buff halt if RCV buff is full)

;(address of transmit buffer)

RCVhalt

XMTbufAddr

XMTbufSize

RCVbufAddr

RCVbufSize

*

0x800

0x000

0x800

;(length of transmit buffer)

;(address of receive buffer)

;(length of receive buffer)works up to 800

* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up

* valid buffer start and length values. Page 9-44

*

**********************************************************************

.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync

<<5)) ,SPCval

.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format &

1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval

.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)),

SPCEval

sineinit:

bspc = #SPCval

ifr = #10h

; places buffered serial port in reset

; clear interrupt ﬂags

imr = #210h

intm = 0

; Enable HPINT,enable BRINT0

; all unmasked interrupts are enabled.

; programs BSPCE and ABU

bspce = #SPCEval

axr = #XMTbufAddr

bkx = #XMTbufSize

arr = #RCVbufAddr

bkr = #RCVbufSize

bspc = #(SPCval | GO)

return

; initializes transmit buffer start address

; initializes transmit buffer size

; initializes receive buffer start address

; initializes receive buffer size

; bring buffered serial port out of reset

;for transmit and receive because GO=0xC0

14071fb

23

LTC1407-1/LTC1407A-1

PACKAGE DESCRIPTION

MSE Package

10-Lead Plastic MSOP

(ꢁeference LTC DWG # 05-08-1664 ꢁev C)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.06 p 0.102

2.794 p 0.102

(.110 p .004)

0.889 p 0.127

(.035 p .005)

(.081 p .004)

1

0.29

ꢁEF

1.83 p 0.102

(.072 p .004)

0.05 ꢁEF

5.23

(.206)

MIN

2.083 p 0.102 3.20 – 3.45

(.082 p .004) (.126 – .136)

DETAꢀL “B”

COꢁNEꢁ TAꢀL ꢀS PAꢁT OF

THE LEADFꢁAME FEATUꢁE.

FOꢁ ꢁEFEꢁENCE ONLY

NO MEASUREMENT PURPOSE

DETAꢀL “B”

10

0.50

(.0197)

BSC

0.305 p 0.038

(.0120 p .0015)

TYP

3.00 p 0.102

(.118 p .004)

(NOTE 3)

0.497 p 0.076

(.0196 p .003)

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

REF

3.00 p 0.102

(.118 p .004)

(NOTE 4)

4.90 p 0.152

(.193 p .006)

DETAIL “A”

0.254

(.010)

0o – 6o TYP

1

2

3

4 5

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 p 0.0508

(.004 p .002)

0.50

(.0197)

BSC

MSOP (MSE) 0908 REV C

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

14071fb

24

LTC1407-1/LTC1407A-1

REVISION HISTORY ^{(Revision history begins at Rev B)}

REV

DATE

DESCRIPTION

PAGE NUMBER

B

12/09 Update Pin Conﬁguration

2

14071fb

ꢀnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

LTC1407-1/LTC1407A-1

TYPICAL APPLICATION

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC1608

16-Bit, 500ksps Parallel ADC

16-Bit, 250ksps Serial ADC

5V Supply, 2.5V Span, 90dB SꢀNAD

5V Conﬁgurable Bipolar/Unipolar ꢀnputs

3V, 15mW, Unipolar ꢀnputs, MSOP Package

3V, 15mW, Bipolar ꢀnputs, MSOP Package

3V, 14mW, 2-Channel Unipolar ꢀnput ꢁange

5V, Selectable Spans, 80dB SꢀNAD

LTC1609

LTC1403/LTC1403A

LTC1403-1/LTC1403A-1

LTC1407/LTC1407A

LTC1411

12-/14-Bit, 2.8Msps Serial ADC

12-/14-Bit, 3Msps Simultaneous Sampling ADC

14-Bit, 2.5Msps Parallel ADC

12-Bit, 10Msps Parallel ADC

LTC1420

5V, Selectable Spans, 72dB SꢀNAD

LTC1405

12-Bit, 5Msps Parallel ADC

5V, Selectable Spans, 115mW

LTC1412

12-Bit, 3Msps Parallel ADC

5V Supply, 2.5V Span, 72dB SꢀNAD

5V or 5V Supply, 4.096V or 2.5V Span

5V or 3V (L-Version), Micropower, MSOP Package

LTC1402

12-Bit, 2.2Msps Serial ADC

LTC1864/LTC1865

LTC1864L/LTC1865L

16-Bit, 250ksps 1-/2-Channel Serial ADCs

DACs

LTC1666/LTC1667

LTC1668

12-/14-/16-Bit, 50Msps DAC

87dB SFDꢁ, 20ns Settling Time

LTC1592

16-Bit, Serial SoftSpan™ ꢀ

DAC

1LSB ꢀNL/DNL, Software Selectable Spans

OUT

References

LT1790-2.5

LT1461-2.5

LT1460-2.5

Micropower Series ꢁeference in SOT-23

Precision Voltage ꢁeference

0.05% ꢀnitial Accuracy, 10ppm Drift

0.04% ꢀnitial Accuracy, 3ppm Drift

0.10% ꢀnitial Accuracy, 10ppm Drift

Micropower Series Voltage ꢁeference

SoftSpan is a trademark of Linear Technology Corporation.

14071fb

LT 0110 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

26

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1407CMSE-1#PBF
厂家：	Linear
描述：	LTC1407-1 - Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总26页 (文件大小：504K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1407CMSE-1#PBF [Linear]

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LTC1408

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