LTC1163CN8 [Linear]

Triple 1.8V to 6V High-Side MOSFET Drivers; 三重1.8V至6V的高边MOSFET驱动器
LTC1163CN8
型号: LTC1163CN8
厂家: Linear    Linear
描述:

Triple 1.8V to 6V High-Side MOSFET Drivers
三重1.8V至6V的高边MOSFET驱动器

驱动器
文件: 总8页 (文件大小:233K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
LTC1163/LTC1165  
Triple 1.8V to 6V High-Side  
MOSFET Drivers  
U
DESCRIPTIO  
EATURE  
S
F
Operates from 1.8V to 6V  
The LTC1163/LTC1165 triple low voltage MOSFET drivers  
make it possible to switch supply or ground referenced  
loadsthroughinexpensive,lowRDS(ON) N-channelswitches  
from as little as a 1.8V supply. The LTC1165 has inverting  
inputs and makes it possible to directly replace P-channel  
MOSFET switches while maintaining system drive polar-  
ity. The LTC1163 has noninverting inputs.  
0.01µA Standby Current  
95µA Operating Current per Channel at 3.3V  
Fully Enhances N-Channel Switches  
No External Charge Pump Components  
Built-In Gate Voltage Clamps  
Easily Protected Against Supply Transients  
Controlled Switching ON and OFF Times  
Compatible with 5V, 3V and Sub-3V Logic Families  
Available in 8-Pin SOIC  
Micropower operation, with 0.01µA standby current and  
95µA operating current, coupled with a power supply  
range of 1.8V to 6V, make the LTC1163/LTC1165 ideally  
suited for 2- to 4-cell battery-powered applications. The  
LTC1163/LTC1165 are also well suited for sub-3V, 3.3V  
and 5V nominal supply applications.  
O U  
PPLICATI  
A
S
PCMCIA Card 3.3V/5V Switch  
2-Cell High-Side Load Switching  
Boost Regulator Shutdown to Zero Standby Current  
Replacing P-Channel Switches  
Notebook Computer Power Management  
Palmtop Computer Power Management  
Portable Medical Equipment  
The LTC1163/LTC1165 internal charge pumps boost the  
gatevoltage8Vabovea3.3Vrail, fullyenhancing inexpen-  
sive N-channels for high- or low-side switch applications.  
The LTC1163/LTC1165 are available in both an 8-pin DIP  
and an 8-pin SOIC.  
Mixed 3.3V and 5V Supply Switching  
U
O
TYPICAL APPLICATI  
2-Cell Triple High-Side Switch  
MOSFET Switch Gate Voltage  
(1.8V TO 3V)  
18  
16  
14  
+
+
2-CELL  
BATTERY  
PACK  
10µF  
RFD14N05LSM RFD14N05LSM RFD14N05LSM  
12  
10  
8
V
S
IN1  
IN2  
IN3  
OUT1  
OUT2  
OUT3  
CONTROL  
LTC1163  
LTC1165  
LOGIC  
OR µP  
GND  
6
2-CELL  
LOAD  
2-CELL  
LOAD  
2-CELL  
LOAD  
4
LTC1163 HAS NONINVERTING INPUTS  
LTC1165 HAS INVERTING INPUTS  
2
0
LTC1163/65 • TA01  
0
1
2
5
6
3
4
SUPPLY VOLTAGE (V)  
LTC1163/65 • TA02  
1
LTC1163/LTC1165  
W W W  
U
ABSOLUTE AXI U RATI GS  
Supply Voltage ......................................................... 7V  
Any Input Voltage .......................... 7V to (GND – 0.3V)  
Any Output Voltage....................... 20V to (GND – 0.3V)  
Current (Any Pin)................................................. 50mA  
Operating Temperature Range  
LTC1163C/LTC1165C ........................... 0°C to 70°C  
Storage Temperature Range ................ 65°C to 150°C  
Lead Temperature (Soldering, 10 sec)................. 300°C  
W
U
/O  
PACKAGE RDER I FOR ATIO  
ORDER PART  
ORDER PART  
TOP VIEW  
TOP VIEW  
NUMBER  
NUMBER  
IN1  
IN2  
1
2
3
4
8
7
6
5
V
S
IN1  
IN2  
1
2
3
4
V
S
8
7
6
5
LTC1163CS8  
LTC1165CS8  
OUT1  
OUT2  
OUT3  
OUT1  
OUT2  
OUT3  
LTC1163CN8  
LTC1165CN8  
IN3  
IN3  
GND  
GND  
S8 PART MARKING  
N8 PACKAGE  
8-LEAD PLASTIC DIP  
S8 PACKAGE  
8-LEAD PLASTIC SOIC  
1163  
1165  
TJMAX = 100°C, θJA = 150°C/W  
TJMAX = 100°C, θJA = 130°C/W  
VS = 1.8V to 6V, TA = 25°C, unless otherwise noted.  
ELECTRICAL CHARACTERISTICS  
LTC1163C/LTC1165C  
SYMBOL  
PARAMETER  
CONDITIONS  
V = 1.8V, V = V = V = V (Note 1,2)  
MIN  
TYP  
MAX  
UNITS  
I
Quiescent Current OFF  
0.01  
0.01  
0.01  
1
1
1
µA  
µA  
µA  
Q
S
IN1  
IN2  
IN3  
OFF  
V = 3.3V, V = V = V = V (Note 1,2)  
S
IN1  
IN2  
IN3  
OFF  
V = 5V, V = V = V = V (Note 1,2)  
S
IN1  
IN2  
IN3  
OFF  
Quiescent Current ON  
Input High Voltage  
V = 1.8V, V = V (Note 2,3)  
60  
95  
180  
120  
200  
400  
µA  
µA  
µA  
S
IN  
ON  
V = 3.3V, V = V (Note 2,3)  
S
IN  
ON  
V = 5V, V = V (Note 2,3)  
S
IN  
ON  
V
V
1.8V < V < 2.7V  
80% × V  
70% × V  
V
V
INH  
S
S
S
2.7V < V < 6V  
S
Input Low Voltage  
Input Current  
1.8V < V < 6V  
15% × V  
±1  
V
µA  
pF  
INL  
S
S
I
0V V V  
IN S  
IN  
C
V
Input Capacitance  
Gate Voltage Above Supply  
5
IN  
– V  
V = 1.8V, V = V (Note 2)  
3.5  
4.0  
4.5  
6.0  
5.0  
4.1  
4.6  
5.2  
8.0  
9.0  
6.0  
7.0  
8.0  
9.5  
13.0  
V
V
V
V
V
GATE  
S
S
IN  
ON  
V = 2V, V = V (Note 2)  
S
IN  
ON  
V = 2.2V, V = V (Note 2)  
S
IN  
ON  
V = 3.3V, V = V (Note 2)  
S
IN  
ON  
V = 5V, V = V (Note 2)  
S
IN  
ON  
t
Turn-ON Time  
V = 3.3V, C  
Time for V  
Time for V  
= 1000pF  
ON  
S
GATE  
GATE  
GATE  
> V + 1V  
40  
60  
120  
180  
400  
600  
µs  
µs  
S
> V + 2V  
S
V = 5V, C  
Time for V  
Time for V  
= 1000pF  
S
GATE  
> V + 1V  
30  
40  
95  
130  
300  
400  
µs  
µs  
GATE  
GATE  
S
> V + 2V  
S
2
LTC1163/LTC1165  
ELECTRICAL CHARACTERISTICS VS = 1.8V to 6V, TA = 25°C, unless otherwise noted.  
LTC1163C/LTC1165C  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
t
Turn-OFF Time  
V = 3.3V, C  
Time for V  
= 1000pF  
< 0.5V  
OFF  
S
GATE  
GATE  
20  
15  
65  
200  
150  
µs  
V = 5V, C  
= 1000pF  
< 0.5V  
S
GATE  
Time for V  
45  
µs  
GATE  
The  
denotes specifications which apply over the full operating  
Note 2: LTC1163: V = 0V, V = V . LTC1165: V = V , V = 0V  
OFF ON S OFF S ON  
temperature range.  
Note 3: Quiescent current ON is per driver and is measured independently.  
Note 1: Quiescent current OFF is for all channels in OFF condition.  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Standby Supply Current  
Supply Current per Driver ON  
Gate Voltage Above Supply  
5
4
600  
500  
400  
300  
200  
100  
0
12  
10  
8
T
= 25°C  
T
= 25°C  
A
T
= 25°C  
A
A
ALL THREE INPUTS = OFF  
ONE INPUT = ON  
OTHER INPUTS = OFF  
3
2
6
1
4
0
2
–1  
0
0
2
3
4
5
6
1
0
2
3
4
5
6
0
2
3
4
5
6
1
1
SUPPLY VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
LTC1163/65 • TPC01  
LTC1163/65 • TPC02  
LTC1163/65 • TPC03  
Turn-OFF Time  
Input Threshold Voltage  
Turn-ON Time  
6
5
4
3
2
1
0
600  
500  
400  
300  
200  
100  
0
300  
250  
200  
150  
100  
50  
C
= 1000pF  
T
= 25°C  
C
= 1000pF  
GATE  
TIME FOR V  
A
GATE  
< 0.5V  
GATE  
V
HI  
V
= 2V  
GS  
V
LO  
V
= 1V  
GS  
4
0
0
2
3
4
5
6
0
2
3
5
6
0
2
3
4
5
6
1
1
1
SUPPLY VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
LTC1163/65 • TPC04  
LTC1163/65 • TPC05  
LTC1163/65 • TA06  
3
LTC1163/LTC1165  
TYPICAL PERFOR A CE CHARACTERISTICS  
U W  
Standby Supply Current  
Supply Current per Driver ON  
MOSFET Gate Drive Current  
5
4
1000  
100  
10  
300  
250  
200  
150  
100  
50  
T
A
= 25°C  
3
V
= 5V  
S
V
S
= 5V  
2
V
S
= 3.3V  
V
= 3.3V  
= 1.8V  
S
S
1
1
V
0
V
= 1.8V  
V = 2.2V  
S
S
–1  
0
0.1  
0
10  
20  
30  
40  
50  
60  
70  
0
10  
20  
30  
40  
50  
60  
70  
0
2
4
6
8
10  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
GATE VOLTAGE ABOVE SUPPLY (V)  
LTC1163/65 • TPC07  
LTC1163/65 • TPC08  
LTC1163/65 • TPC09  
U U  
U
PI FU CTIO S  
Input Pins  
Output Pins  
The LTC1163 is noninverting; i.e., the MOSFET gate is  
driven above the supply when the input pin is held high.  
TheLTC1165isinvertinganddrivestheMOSFETgatehigh  
when the input pin is held low. The inverting inputs of the  
LTC1165 allow P-channel switches to be replaced by  
lower resistance/cost N-channel switches while maintain-  
ing system drive polarity.  
The output pin is either driven to ground when the switch  
is turned OFF or driven above the supply rail when the  
switch is turned ON. The output is clamped to about 14V  
above ground by a built-in Zener clamp. This pin has a  
relatively high impedance when driven above the rail (the  
equivalent of a few hundred k). Care should be taken to  
minimize any loading of this pin by parasitic resistance to  
ground or supply.  
The LTC1163/LTC1165 logic inputs are high impedance  
CMOS gates with ESD protection diodes to ground and  
therefore should not be forced below ground. The inputs  
can however, be driven above the power supply rail as  
therearenoclampingdiodesconnectedbetweentheinput  
pins and supply pin. This facilitates operation in mixed  
5V/3V systems.  
Supply Pin  
A 150resistor should be inserted in series with the  
ground pin or supply pin if negative supply voltage tran-  
sients are anticipated. This will limit the current flowing  
from the power source into the LTC1163/LTC1165 to tens  
of milliamps during reverse battery conditions.  
U
OPERATIO  
The input threshold voltage is set at roughly 50% of the  
supply voltage and approximately 200mV of input hyster-  
esis is provided to ensure clean switching.  
The LTC1163/LTC1165 are triple micropower MOSFET  
drivers designed for operation over the 1.8V to 6V supply  
range and include the following functional blocks:  
The input enables all of the following circuit blocks: the  
bias generator, the high frequency oscillator and gate  
charge pump. Therefore, when the input is turned off, the  
entire circuit powers down and the supply current drops  
below 1µA.  
3V Logic Compatible Inputs  
The LTC1163/LTC1165 inputs have been designed to  
accommodate a wide range of 3V and 5V logic families.  
4
LTC1163/LTC1165  
U
OPERATIO  
Gate Charge Pump  
Controlled Gate Rise and Fall Times  
Gate drive for the power MOSFET is produced by an  
internal charge pump circuit which generates a gate volt-  
age substantially higher than the power supply voltage.  
The charge pump capacitors are included on chip and  
thereforenoexternalcomponentsarerequiredtogenerate  
gate drive.  
When the input is switched ON and OFF, the gate is  
charged by the internal charge pump and discharged in a  
controlled manner. The charge and discharge rates have  
been set to minimize RFI and EMI emissions.  
W
BLOCK DIAGRA  
(One Channel)  
LTC1165  
LTC1163  
HIGH  
FREQUENCY  
OSCILLATOR  
CHARGE  
GATE  
PUMP  
GATE  
DISCHARGE  
BIAS  
GENERATOR  
INPUT  
LOGIC  
14V  
LTC1163/65 • BD  
U U  
W
U
APPLICATIO S I FOR ATIO  
Logic-Level MOSFET Switches  
For example, if a 100µF capacitor is powered through a  
switchwithaslewrateof0.1V/µs, thecurrentduringstart-  
up is:  
The LTC1163/LTC1165 are designed to operate with  
logic-level N-channel MOSFET switches. Although there  
is some variation among manufacturers, logic-level  
MOSFET switches are typically rated with VGS = 4V with  
a maximum continuous VGS rating of ±10V. RDS(ON) and  
maximum VDS ratings are similar to standard MOSFETs  
and there is generally little price differential. Logic-level  
MOSFETs are frequently designated by an “L” and are  
usually available in surface mount packaging. Some  
logic-level MOSFETs are rated with VGS up to ±15V and  
can be used in applications which require operation over  
the entire 1.8V to 6V range.  
ISTART = C(V/t)  
= (100 × 106)(1 × 105)  
= 10A  
Obviously, this is too much current for the regulator (or  
output capacitor) to supply and the output will glitch by as  
much as a few volts.  
The startup current can be substantially reduced by limit-  
ing the slew rate at the gate of an N-channel as shown in  
Figure 1. The gate drive output of the LTC1163/LTC1165  
is passed through a simple RC network, R1 and C1, which  
substantially slows the slew rate of the MOSFET gate to  
approximately 1.5 × 104V/µs. Since the MOSFET is  
operating as a source follower, the slew rate at the source  
is essentially the same as that at the gate, reducing the  
startup current to approximately 15mA which is easily  
Powering Large Capacitive Loads  
Electrical subsystems in portable battery-powered equip-  
ment are typically bypassed with large filter capacitors to  
reduce supply transients and supply induced glitching. If  
not properly powered however, these capacitors may  
themselves become the source of supply glitching.  
5
LTC1163/LTC1165  
U U  
W
U
APPLICATIO S I FOR ATIO  
3.3V  
on a 3.3V supply which is compatible with 5V TTL and  
CMOS logic. (The LTC1163/LTC1165 cannot however, be  
driven by 3V logic when powered from a 5V supply  
because the threshold is approximately 2.5V.)  
LT1129-3.3  
V
IN  
+
3.3µF  
R1  
100k  
R2  
1k  
V
S
OUT1  
MTD3055EL  
3.3V  
C1  
0.1µF  
1/3 LTC1163  
GND  
+
ON/OFF  
IN1  
C
L
100µF  
V
3.3V  
LOAD  
S
5V  
OUT1  
MTD3055EL  
1/3 LTC1163  
LTC1163/65 • F01  
IN1  
3.3V  
LOAD  
GND  
Figure 1. Powering a Large Capacitive Load  
LTC1163/65 • F01  
managed by the system regulator. R2 is required to  
eliminate the possibility of parasitic MOSFET oscillations  
duringswitchtransitions.Itisagoodpracticetoisolatethe  
gates of paralleled MOSFETs with 1k resistors to decrease  
the possibility of interaction between switches.  
Figure 2. Direct Interface to 5V Logic  
Reverse Battery Protection  
The LTC1163/LTC1165 can be protected against reverse  
battery conditions by connecting a 150resistor in series  
with the ground pin or supply pin. The resistor limits the  
supply current to less than 24mA with –3.6V applied.  
Because the LTC1163/LTC1165 draw very little current  
while in normal operation, the drop across the resistor is  
minimal.The3.3VµP(orcontrollogic)canbeprotectedby  
adding 10k resistors in series with the input pins.  
Mixed 5V/3V Systems  
BecausetheinputESDprotectiondiodesarereferencedto  
ground instead of the supply pin, it is possible to drive the  
LTC1163/LTC1165 inputs from 5V CMOS or TTL logic  
even though the LTC1163/LTC1165 are powered from a  
3.3V supply as shown in Figure 2. The input threshold  
voltageisapproximately50%ofthesupplyvoltageor1.6V  
U
TYPICAL APPLICATIO S  
PCMCIA Card 3.3V/5V VCC Switch  
5V  
+
10µF  
PCMCIA  
CONTROLLER  
1/2 MMDF3N02HD  
V
V
CC  
S
V
5V  
3V  
IN1  
OUT1  
OUT2  
OUT3  
CC  
CC  
+
LTC1165  
PC  
1µF  
V
IN2  
IN3  
CARD  
SOCKET  
MMDF3N02HD  
GND  
LTC1163/65 • TA03  
3.3V  
NOTE: USE LTC1163 WITH NONINVERTING PCMCIA CONTROLLERS  
6
LTC1163/LTC1165  
U
TYPICAL APPLICATIO S  
2-Cell to 3.3V, 5V and 12V High-Side Switch/Converter  
with 0.01µA Standby Current  
+
+
2-CELL  
BATTERY  
PACK  
100µF  
6.3V  
V
S
IN1  
IN2  
IN3  
OUT1  
OUT2  
OUT3  
RFD14N05LSM  
CONTROL  
LOGIC  
OR µP  
LTC1163  
LTC1165  
RFD14N05LSM  
RFD14N05LSM  
GND  
MBRS120T3  
100µH  
3.3V  
22µH  
MBRS120T3  
22µH  
47Ω  
MBRS120T3  
12V  
5V  
1
3
1
3
1
2
3
39k  
7
8
7
8
8
LT1109CS8-12  
4
LT1109CS8-5  
4
LT1173CS8  
+
+
+
10µF  
20V  
22µF  
16V  
220µF  
6.3V  
24k  
4
5
LTC1163/65 • TA04  
PCMCIA Card Socket VPP Switch/Reglator  
MMDF3N02HD  
MURS120T3  
1
3
33µH  
7,8  
V
= 3.3V  
OR 5V  
V
= 0V, 3.3V,  
CC  
PP  
5V, 12V, OR HI-Z  
+
3
1M  
100µF  
6.3V  
1/4 74HC02  
1
8
LT1109ACS8-12  
1N4148  
EN0  
1N4148  
2
4
5,6  
EN0  
EN1 OUTPUT  
7
+
0
1
0
1
0
0
1
1
0V  
47µF  
16V  
12V  
4
V
CC  
V
S
HI-Z  
1/4 74HC02  
IN1  
OUT1  
OUT2  
OUT3  
LTC1163  
1/4 74HC02  
IN2  
IN3  
2N7002  
EN1  
GND  
LTC1163/65 • TA05  
Ultra-Low Drop Triple 3.3V High-Side Switch  
3.3V  
+
MTD  
3055EL  
MTD  
3055EL  
MTD  
3055EL  
10µF  
V
S
(11V)  
(11V)  
(11V)  
IN1  
IN2  
IN3  
OUT1  
OUT2  
OUT3  
3.3V  
LOGIC  
OR µP  
LTC1163  
LTC1165  
GND  
3.3V  
LOAD  
3.3V  
LOAD  
3.3V  
LOAD  
LTC1163/65 • TA06  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-  
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.  
7
LTC1163/LTC1165  
U
O
TYPICAL APPLICATI S  
Mixed Voltage High- and Low-Side Switches  
3.3V  
12V  
5V  
+
+
+
Si9956DY  
10µF  
10µF  
10µF  
V
S
12V  
IN1  
IN2  
IN3  
OUT1  
OUT2  
OUT3  
LOAD  
5V  
LOGIC  
OR µP  
LTC1163  
LTC1165  
IRFR024  
GND  
5V  
LOAD  
3.3V  
LOAD  
LTC1163/65 • TA07  
3-Cell to 3.3V Ultra-Low Drop Regulator with 2 Ramped Switches  
+
+
3-CELL  
BATTERY  
PACK  
10µF  
MTD3055EL  
3.3V  
OUTPUT  
MTD3055EL  
1k  
MTD3055EL  
1k  
1
3
V
S
+
220µF  
6.3V  
IN1  
IN2  
IN3  
OUT1  
OUT2  
OUT3  
510pF  
3.3k  
10k  
CONTROL  
LTC1163  
LTC1165  
LOGIC  
LT1431  
5
OR µP  
8
GND  
3.3V  
3.3V  
LOAD  
6
100k 100k  
LOAD  
680Ω  
0.1µF  
0.1µF  
LTC1163/65 • TA08  
U
Dimensions in inches (millimeters) unless otherwise noted.  
PACKAGE DESCRIPTIO  
0.400  
(10.160)  
MAX  
0.130 ± 0.005  
0.045 – 0.065  
0.300 – 0.320  
(7.620 – 8.128)  
(3.302 ± 0.127)  
(1.143 – 1.651)  
N8 Package  
8
7
6
5
4
8-Lead  
0.065  
(1.651)  
TYP  
Plastic DIP  
0.250 ± 0.010  
(6.350 ± 0.254)  
0.009 – 0.015  
(0.229 – 0.381)  
0.125  
(3.175)  
MIN  
0.020  
(0.508)  
MIN  
+0.025  
–0.015  
0.045 ± 0.015  
(1.143 ± 0.381)  
1
8
2
0.325  
3
+0.635  
8.255  
(
)
–0.381  
0.100 ± 0.010  
(2.540 ± 0.254)  
0.018 ± 0.003  
(0.457 ± 0.076)  
0.189 – 0.197  
(4.801 – 5.004)  
7
5
6
0.010 – 0.020  
(0.254 – 0.508)  
× 45°  
0.053 – 0.069  
(1.346 – 1.752)  
S8 Package  
8-Lead  
Plastic SOIC  
0.004 – 0.010  
(0.101 – 0.254) 0.228 – 0.244  
(5.791 – 6.197)  
0.008 – 0.010  
(0.203 – 0.254)  
0.150 – 0.157  
(3.810 – 3.988)  
0°– 8° TYP  
0.016 – 0.050  
0.406 – 1.270  
0.050  
0.014 – 0.019  
(0.355 – 0.483)  
(1.270)  
BSC  
1
2
3
4
LT/GP 1093 10K REV 0 • PRINTED IN USA  
LINEAR TECHNOLOGY CORPORATION 1993  
Linear Technology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7487  
8
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977  

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