LT4356CDE-1 [Linear]
Overvoltage Protection Regulator and Inrush Limiter; 过压保护稳压器和浪涌限制器
| 型号： | LT4356CDE-1 |
| 厂家： | 
Linear |
| 描述： | Overvoltage Protection Regulator and Inrush Limiter |
| 文件： | 总20页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4356-1
Overvoltage Protection
Regulator and Inrush Limiter
FEATURES
DESCRIPTION
The LT®4356-1 surge stopper protects loads from high
voltage transients. It regulates the output during an
overvoltage event, such as load dump in automobiles,
by controlling the gate of an external N-Channel MOSFET.
The output is limited to a safe value thereby allowing the
loadstocontinuefunctioning.TheLT4356-1alsomonitors
n
Stops High Voltage Surges
n
Adjustable Output Clamp Voltage
n
Overcurrent Protection
n
Wide Operation Range: 4V to 80V
n
Reverse Input Protection to –60V
n
Low 7μA Shutdown Current
n
Adjustable Fault Timer
the voltage drop between the V and SNS pins to protect
CC
n
Controls N-Channel MOSFET
against overcurrent faults. An internal amplifier limits the
current sense voltage to 50mV. In either fault condition, a
timer is started inversely proportional to MOSFET stress.
If the timer expires, the FLT pin pulls low to warn of an
impending power down. If the condition persists, the
MOSFET is turned off.
n
Shutdown Pin Withstands –60V to 100V
n
Fault Output Indication
n
Spare Amplifier for Level Detection Comparator or
Linear Regulator Controller
n
Available in (4mm × 3mm) 12-Pin DFN or 10-Pin
MSOP Packages
The spare amplifier may be used as a voltage detection
comparator or as a linear regulator controller driving an
external PNP pass transistor.
APPLICATIONS
n
Back-to-back FETs can be used in lieu of a Schottky diode
for reverse input protection, reducing voltage drop and
powerloss. Ashutdownpinreducesthequiescentcurrent
to less than 7μA during shutdown.
Automotive/Avionic Surge Protection
n
Hot Swap/Live Insertion
n
High Side Switch for Battery Powered Systems
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
4A, 12V Overvoltage Output Regulator
Overvoltage Protector Regulates
Output at 27V During Transient
10mΩ
IRLR2908
V
OUT
V
IN
12V
80V INPUT SURGE
10Ω
102k
V
IN
V
SNS GATE OUT
FB
20V/DIV
CC
383k
V
CC
SHDN
12V
12V
4.99k
27V CLAMP
DC-DC
+
IN
LT4356DE-1
V
OUT
CONVERTER
20V/DIV
100k
EN
SHDN
GND
UNDERVOLTAGE
A
FLT
FAULT
43561 TA01b
OUT
GND
TMR
100ms/DIV
43561 TA01
0.1μF
43561fd
1
LT4356-1
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
V , SHDN................................................–60V to 100V
Operating Temperature Range
CC
SNS..............................V –30V or –60V to V + 0.3V
LT4356C-1 ............................................... 0°C to 70°C
LT4356I-1 ............................................–40°C to 85°C
LT4356H-1.........................................–40°C to 125°C
Storage Temperature Range
CC
CC
OUT, A , FLT, EN.....................................–0.3V to 80V
OUT
GATE (Note 3)................................ –0.3V to V
+ 10V
OUT
+
FB, TMR, IN ................................................–0.3V to 6V
A
, EN, FLT .........................................................–3mA
DE12..................................................–65°C to 125°C
MS.....................................................–65°C to 150°C
Lead Temperature (Soldering, 10 sec, MS10)....... 300°C
OUT
PIN CONFIGURATION
TOP VIEW
+
TMR
FB
1
2
3
4
5
6
12 IN
TOP VIEW
11
A
OUT
FB
OUT
1
2
3
4
5
10 TMR
OUT
GATE
SNS
10 GND
9
8
7
6
GND
EN
13
GATE
SNS
9
8
7
EN
FLT
V
CC
SHDN
FLT
MS PACKAGE
10-LEAD PLASTIC MSOP
= 125°C, θ = 120°C/W
V
SHDN
CC
T
JMAX
JA
DE PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W
JMAX
JA
EXPOSED PAD (PIN 13) PCB GND CONNECTION OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
LT4356CDE-1#PBF
LT4356IDE-1#PBF
LT4356HDE-1#PBF
LT4356CMS-1#PBF
LT4356IMS-1#PBF
LT4356HMS-1#PBF
LEAD BASED FINISH
LT4356CDE-1
TAPE AND REEL
PART MARKING*
43561
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LT4356CDE-1#TRPBF
LT4356IDE-1#TRPBF
LT4356HDE-1#TRPBF
LT4356CMS-1#TRPBF
LT4356IMS-1#TRPBF
LT4356HMS-1#TRPBF
TAPE AND REEL
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
43561
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
43561
LTCNS
LTCNS
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 125°C
TEMPERATURE RANGE
0°C to 70°C
LTCNS
10-Lead Plastic MSOP
PART MARKING*
43561
PACKAGE DESCRIPTION
LT4356CDE-1#TR
LT4356IDE-1#TR
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LT4356IDE-1
43561
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LT4356HDE-1
LT4356HDE-1#TR
LT4356CMS-1#TR
LT4356IMS-1#TR
LT4356HMS-1#TR
43561
LT4356CMS-1
LTCNS
LT4356IMS-1
LTCNS
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 125°C
LT4356HMS-1
LTCNS
10-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
43561fd
2
LT4356-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
MIN
TYP
MAX
80
UNITS
V
V
I
Operating Voltage Range
Supply Current
4
l
CC
V
V
V
= FLOAT
= 0V
1
1.5
mA
l
CC
CC
SHDN
7
7
7
25
30
40
μA
μA
μA
SHDN
LT4356I-1, LT4356C-1
LT4356H-1
l
l
I
R
Reverse Input Current
V
V
= V = –30V, SHDN Open
0.3
0.8
1
2
mA
mA
l
l
SNS
SNS
CC
= V = V
= –30V
CC
SHDN
ΔV
I
GATE Pin Output High Voltage
GATE Pin Pull-Up Current
GATE Pin Pull-Down Current
V
= 4V; (V
– V
GATE
)
4.5
10
8
V
V
l
l
GATE
CC
GATE
OUT
48V ≥ V ≥ 8V; (V
– V
)
18
CC
OUT
V
GATE
V
GATE
= 12V; V = 12V
= 48V; V = 48V
–4
–4.5
–23
–30
–36
–50
μA
μA
l
l
GATE,UP
GATE,DN
CC
CC
I
Overvoltage, V = 1.4V, V
= 12V
75
5
1.5
150
10
5
mA
mA
mA
l
l
l
FB
CC
GATE
Overcurrent, V – V
= 120mV, V
= 0V, V
= 12V
GATE
= 12V
SNS
SHDN
Shutdown Mode, V
GATE
V
I
FB Pin Servo Voltage
V
V
= 12V; V
= 12V; V
= 12V, LT4356I-1, LT4356C-1
= 12V, LT4356H-1
1.225
1.215
1.25
1.25
1.275
1.275
V
V
l
l
FB
GATE
GATE
OUT
OUT
FB Pin Input Current
V
= 1.25V
FB
0.3
1
μA
l
FB
ΔV
Overcurrent Fault Threshold
ΔV
SNS
ΔV
SNS
ΔV
SNS
ΔV
SNS
= (V – V ), V = 12V, LT4356I-1, LT4356C-1
45
42.5
46
50
50
51
51
55
55
56
56
mV
mV
mV
mV
l
l
l
l
SNS
CC
SNS
CC
= (V – V ), V = 12V, LT4356H-1
CC
SNS
CC
= (V – V ), V = 48V, LT4356I-1, LT4356C-1
CC
SNS
CC
= (V – V ), V = 48V, LT4356H-1
43
CC
SNS
CC
I
SNS Pin Input Current
V
= V = 12V to 48V
5
10
22
μA
l
l
SNS
SNS
CC
I
FLT, EN Pins Leakage Current
FLT, EN = 80V
2.5
4.5
μA
μA
LEAK
A
Pin Leakage Current
A = 80V
OUT
OUT
I
TMR Pin Pull-up Current
V
TMR
= 1V, V = 1.5V, (V – V ) = 0.5V
–1.5
–44
–3.5
–2.5
–195
–2.5
–50
–5.5
–4.5
–260
–4
–55
–8
–6.5
–315
μA
μA
μA
μA
μA
l
l
l
l
l
TMR
TMR
FB
CC
OUT
V
= 1V, V = 1.5V, (V – V ) = 75V
FB
CC
OUT
V
= 1.3V, V = 1.5V
TMR
FB
V
= 1V, ΔV
= 1V, ΔV
= 60mV, (V – V ) = 0.5V
TMR
SNS
SNS
CC
CC
OUT
OUT
V
TMR
= 60mV, (V – V ) = 80V
TMR Pin Pull-down Current
TMR Pin Thresholds
V
= 1V, V = 1V, ΔV = 0V
SNS
1.7
2.2
2.7
μA
l
TMR
FB
V
TMR
FLT From High to Low, V = 5V to 80V
1.22
0.48
1.25
0.5
1.28
0.52
V
V
l
l
CC
V
GATE
From Low to High, V = 5V to 80V
CC
ΔV
Early Warning Period
From FLT going Low to GATE going Low, V = 5V to 80V
80
100
1.25
0.3
120
1.28
1
mV
V
l
l
l
TMR
+
CC
+
V
I
IN Pin Threshold
1.22
IN
+
+
+
IN Pin Input Current
V
I
= 1.25V
μA
IN
IN
V
FLT, EN, A
Pins Output Low
= 2mA
= 0.1mA
2
300
8
800
V
mV
l
l
OL
OUT
SINK
SINK
I
I
OUT Pin Input Current
V
OUT
V
OUT
= V = 12V
200
6
300
12
μA
mA
l
l
OUT
CC
= V = 12V, V
= 0V
CC
SHDN
ΔV
OUT Pin High Threshold
ΔV
= V – V ; EN From Low to High
0.25
0.5
1.4
0.7
V
l
OUT
OUT
CC
OUT
V
SHDN
SHDN Pin Threshold
V
CC
= 12V to 48V
0.6
0.4
1.7
2.1
V
V
l
l
l
l
l
V
I
SHDN Pin Float Voltage
V
V
= 12V to 48V
= 0V
1.7
–4
2.2
–8
4
V
μA
μs
μs
SHDN(FLT)
CC
SHDN Pin Current
–1
SHDN
SHDN
t
t
)
Overcurrent Turn Off Delay Time
Overvoltage Turn Off Delay Time
2
GATE From High to Low, ΔV
= 0 → 120mV
OFF(OC
SNS
0.25
1
GATE From High to Low, V = 0 → 1.5V
OFF(OV)
FB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
the OUT pin. Driving this pin to voltages beyond the clamp may damage
Note 2: All currents into device pins are positive; all currents out of device
the device.
43561fd
3
LT4356-1
TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at VCC = 12V, TA = 25°C
unless otherwise noted.
ICC (Shutdown) vs VCC
ICC vs VCC
ICC (Shutdown) vs Temperature
60
50
40
30
20
10
0
1000
800
600
400
200
0
35
30
25
20
15
10
5
0
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
(V)
–50 –25
0
25
50
75 100 125
V
(V)
V
TEMPERATURE (°C)
CC
CC
43561 G01
43561 G02
43561 G19
Reverse Current vs Reverse
Voltage
SHDN Current vs Temperature
GATE Pull-Up Current vs VCC
–20
–15
–10
–5
6
5
4
3
2
1
0
40
35
30
25
20
15
10
5
V
= 0V
V
= SNS
SHDN
CC
0
0
–40
V
–50 –25
0
25
50
75 100 125
0
10 20 30 40 50 60 70 80
(V)
0
–20
–60
–80
TEMPERATURE (°C)
V
(V)
CC
CC
43561 G04
43561 G05
43561 G03
GATE Pull-Up Current
vs Temperature
GATE Pull-Down Current
vs Temperature
GATE Pull-Down Current
vs Temperature
35
30
25
20
15
10
5
220
200
180
160
140
120
100
12
10
8
V
= V
= 12V
OUT
OVERVOLTAGE CONDITION
= 1.5V
OVERCURRENT CONDITION
ΔV = 120mV
GATE
V
FB
SNS
6
4
2
0
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
43561 G06
43561 G07
43561 G08
43561fd
4
LT4356-1
Specifications are at VCC = 12V, TA = 25°C
TYPICAL PERFORMANCE CHARACTERISTICS
unless otherwise noted.
ΔVGATE vs IGATE
ΔVGATE vs Temperature
ΔVGATE vs VCC
14
12
10
8
14
12
10
8
14
12
10
8
V
= 12V
I
= –1μA
OUT
GATE
T
A
T
A
= 25°C
V
= 8V
CC
T
= 0°C
A
= –40°C
6
6
6
V
= 4V
CC
4
4
4
2
2
2
I
= –1μA
CC
GATE
OUT
V
= V
0
0
0
0
2
4
6
8
10 12 14 16
(μA)
–50 –25
0
25
50
75 100 125
0
10 20 30 40 50 60 70 80
(V)
I
TEMPERATURE (°C)
V
GATE
CC
43561 G09
4356 G10
43561 G11
Warning Period TMR Current
vs VCC
Overcurrent TMR Current
vs (VCC – VOUT
Overvoltage TMR Current
vs (VCC – VOUT
)
)
280
240
200
160
120
80
48
40
32
24
16
8
14
12
10
8
OVERCURRENT CONDITION
OVERVOLTAGE CONDITION
OVERVOLTAGE, EARLY
WARNING PERIOD
V
V
= 0V
= 1V
V
V
= 5V
= 1V
OUT
TMR
OUT
TMR
V
FB
V
TMR
= 1.5V
= 1.3V
6
4
40
2
0
0
0
0
10 20 30 40 50 60 70 80
– V (V)
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
V
V
– V
(V)
V
(V)
CC
CC
OUT
CC
OUT
43561 G13
43561 G12
43561 G14
TMR Pull-Down Current
vs Temperature
Output Low Voltage vs Current
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 1V
TMR
A
OUT
FLT
EN
–50 –25
0
25
50
75 100 125
0
0.5
1.0
1.5
2.0
2.5
3.0
TEMPERATURE (°C)
CURRENT (mA)
43561 G15
43561 G16
43561fd
5
LT4356-1
TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at VCC = 12V, TA = 25°C
unless otherwise noted.
Overvoltage Turn-Off Time
vs Temperature
Overcurrent Turn-Off Time
vs Temperature
500
400
300
200
100
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
OVERVOLTAGE CONDITION
= 1.5V
OVERCURRENT CONDITION
ΔV = 120mV
V
FB
SNS
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
43561 G17
43561 G18
PIN FUNCTIONS (DE/MS)
A
(Pin 11 DE Only): Amplifier Output. Open collector
condition (current fault). The internal NPN is capable of
sinking up to 3mA of current from 80V to drive an LED or
opto-coupler.
OUT
output of the auxiliary amplifier. It is capable of sinking
up to 2mA from 80V. The negative input of the amplifier
is internally connected to a 1.25V reference.
GATE(Pin4/Pin3):N-ChannelMOSFETGateDriveOutput.
The GATE pin is pulled up by an internal charge pump
current source and clamped to 14V above the OUT pin.
Both voltage and current amplifiers control the GATE pin
toregulatetheoutputvoltageandlimitthecurrentthrough
the MOSFET.
EN (Pin 9/Pin 8): Open-Collector Enable Output. The EN
pin goes high impedance when the voltage at the OUT pin
is above (V – 0.7V), indicating the external MOSFET is
CC
fully on. The state of the pin is latched until the OUT pin
voltage resets at below 0.5V and goes back up above 2V.
The internal NPN is capable of sinking up to 3mA of cur-
rent from 80V to drive an LED or opto-coupler.
GND (Pin 10/Pin 9): Device Ground.
+
IN (Pin 12 DE Only): Positive Input of the Auxiliary
Exposed Pad (Pin 13 DE Only): Exposed pad may be left
open or connected to device ground (GND).
Amplifier. This amplifier can be used as a level detection
comparator with external hysteresis or linear regulator
controllinganexternalPNPtransistor. Thispinisclamped
internally to 7V. Connect to ground if unused.
FB (Pin 2/Pin 1): Voltage Regulator Feedback Input. Con-
nectthispintothecentertapoftheoutputresistivedivider
connected between the OUT pin and ground. During an
overvoltage condition, the GATE pin is servoed to main-
tain a 1.25V threshold at the FB pin. This pin is clamped
internally to 7V. Tie to GND to disable the OV clamp.
OUT (Pin 3/Pin 2): Output Voltage Sense Input. This pin
senses the voltage at the source of the N-channel MOSFET
and sets the fault timer current. When the OUT pin volt-
age reaches 0.7V away from V , the EN pin goes high
CC
FLT (Pin 8/Pin 7): Open-Collector Fault Output. This pin
pulls low after the voltage at the TMR pin has reached
the fault threshold of 1.25V. It indicates the pass transis-
tor is about to turn off because either the supply voltage
has stayed at an elevated level for an extended period
of time (voltage fault) or the device is in an overcurrent
impedance.
SHDN(Pin7/Pin6):ShutdownControlInput.TheLT4356-1
can be shutdown to a low current mode by pulling the
SHDN pin below the shutdown threshold of 0.6V. Pull
this pin above 1.7V or disconnect it and allow the inter-
43561fd
6
LT4356-1
nal current source to turn the part back on. The leakage
current to ground at the pin should be limited to no more
than 1μA if no pull up device is used to turn the part on.
The SHDN pin can be pulled up to 100V or below GND by
60V without damage.
charging up this pin during fault conditions depends on
the voltage difference between the V and OUT pins.
CC
When V
reaches 1.25V, the FLT pin pulls low to in-
TMR
dicate the detection of a fault condition. If the condition
persists, the pass transistor turns off when V reaches
TMR
the threshold of 1.35V. The pull up current stops and
a 2μA current source starts to pull the TMR pin down
SNS (Pin 5/Pin 4): Current Sense Input. Connect this pin
to the output of the current sense resistor. The current
limitcircuitcontrolstheGATEpintolimitthesensevoltage
as soon as the fault condition disappears. When V
TMR
reaches the retry threshold of 0.5V, the GATE pin pulls
between V and SNS pins to 50mV. At the same time the
CC
high turning back on the pass transistor.
sense amplifier also starts a current source to charge up
the TMR pin. This pin can be pulled below GND by up to
V
(Pin 6/Pin 5): Positive Supply Voltage Input. The
CC
60V, though the voltage difference with the V pin must
positive supply input ranges from 4V to 80V for normal
operation. It can also be pulled below ground potential
by up to 60V during a reverse battery condition, without
damaging the part. The supply current is reduced to 7μA
with all the functional blocks off.
CC
be limited to less than 30V. Connect to V if unused.
CC
TMR (Pin 1/Pin 10): Fault Timer Input. Connect a ca-
pacitor between this pin and ground to set the times for
early warning, fault and cool down periods. The current
BLOCK DIAGRAM
V
CC
SNS
GATE
OUT
14V
+
–
50mV
CHARGE
PUMP
FB
+
–
+
–
VA
IA
1.25V
SHDN
FLT
A
OUT
OC
SHDN
OUT
OV
–
1.25V
EN
CONTROL
LOGIC
AUXILLARY
AMPLIFIER
+
RESTART
GATEOFF FLT
+
IN
1.35V
–
+
V
CC
+
–
0.5V
I
TMR
+
–
2μA
1.25V
TMR
GND
43561 BD
43561fd
7
LT4356-1
OPERATION
Some power systems must cope with high voltage surges
of short duration such as those in automobiles. Load
circuitry must be protected from these transients, yet
high availability systems must continue operating during
these events.
The potential at the TMR pin starts decreasing as soon as
the overvoltage condition disappears. When the voltage
at the TMR pin reaches 0.5V the GATE pin begins rising,
turning on the MOSFET. The FLT pin will then go to a high
impedance state.
The LT4356-1 is an overvoltage protection regulator that
drives an external N-channel MOSFET as the pass transis-
tor. It operates from a wide supply voltage range of 4V to
80V. It can also be pulled below ground potential by up
to 60V without damage. The low power supply require-
ment of 4V allows it to operate even during cold cranking
conditionsinautomotiveapplications. Theinternalcharge
pump turns on the N-channel MOSFET to supply current
to the loads with very little power loss. Two MOSFETs can
be connected back to back to replace an inline Schottky
diode for reverse input protection. This improves the ef-
ficiency and increases the available supply voltage level
to the load circuitry during cold crank.
The fault timer allows the loads to continue functioning
duringshorttransienteventswhileprotectingtheMOSFET
frombeingdamagedbyalongperiodofsupplyovervoltage,
such as a load dump in automobiles. The timer period var-
ies with the voltage across the MOSFET. A higher voltage
corresponds to a shorter fault timer period, ensuring the
MOSFET operates within its safe operating area (SOA).
TheLT4356-1sensesanovercurrentconditionbymonitor-
ing the voltage across an optional sense resistor placed
between the V and SNS pins. An active current limit
CC
circuit (IA) controls the GATE pin to limit the sense volt-
age to 50mV. A current is also generated to start charging
up the TMR pin. This current is about 5 times the current
generated during an overvoltage event. The FLT pin pulls
low when the voltage at the TMR pin reaches 1.25V and
the MOSFET is turned off when it reaches 1.35V.
Normally, the pass transistor is fully on, powering the
loads with very little voltage drop. When the supply volt-
age surges too high, the voltage amplifier (VA) controls
the gate of the MOSFET and regulates the voltage at the
source pin to a level that is set by the external resistor
divider from the OUT pin to ground and the internal 1.25V
reference. A current source starts charging up the capaci-
tor connected at the TMR pin to ground. If the voltage at
A spare amplifier (SA) is provided with the negative input
connected to an internal 1.25V reference. The output pull
down device is capable of sinking up to 2mA of current
allowing it to drive an LED or opto coupler. This amplifier
can be configured as a linear regulator controller driving
an external PNP transistor or a comparator function to
monitor voltages.
the TMR pin, V , reaches 1.25V, the FLT pin pulls low
TMR
to indicate impending turn-off due to the overvoltage
condition. The pass transistor stays on until the TMR
pin reaches 1.35V, at which point the GATE pin pulls low
turning off the MOSFET.
A shutdown pin turns off the pass transistor and reduces
the supply current to less than 7μA.
43561fd
8
LT4356-1
APPLICATIONS INFORMATION
The LT4356-1 can limit the voltage and current to the load
circuitry during supply transients or overcurrent events.
The total fault timer period should be set to ride through
short overvoltage transients while not causing damage
to the pass transistor. The selection of this N-channel
MOSFET pass transistor is critical for this application.
It must stay on and provide a low impedance path from
the input supply to the load during normal operation and
then dissipate power during overvoltage or overcurrent
conditions.
Anovercurrentfaultoccurswhenthecurrentlimitcircuitry
has been engaged for longer than the time-out delay set
by the timer capacitor. The GATE pin is then immediately
pulled low by a 10mA current to GND turning off the
MOSFET. After the fault condition has disappeared and a
cool down period has transpired, the GATE pin is allowed
to pull back up and turn on the pass transistor.
Fault Timer
The LT4356-1 includes an adjustable fault timer pin. Con-
necting a capacitor from the TMR pin to ground sets the
delay timer period before the MOSFET is turned off. The
same capacitor also sets the cool down period before the
MOSFETisallowedtoturnbackonafterthefaultcondition
has disappeared.
The following sections describe the overcurrent and the
overvoltage faults, and the selection of the timer capacitor
value based on the required warning time. The selection
of the N-channel MOSFET pass transistor is discussed
next. Auxiliary amplifier, reverse input, and the shutdown
functionsarecoveredaftertheMOSFETselection.External
component selection is discussed in detail in the Design
Example section.
Once a fault condition, either overvoltage or overcurrent,
is detected, a current source charges up the TMR pin.
The current level varies depending on the voltage drop
across the drain and source terminals of the power
Overvoltage Fault
MOSFET(V ), which is typically from the V pin to the
DS
CC
OUT pin. This scheme takes better advantage of the avail-
ableSafeOperatingArea(SOA)oftheMOSFETthanwould
a fixed timer current. The timer function operates down to
The LTC4356-1 limits the voltage at the OUT pin during an
overvoltage situation. An internal voltage amplifier regu-
lates the GATE pin voltage to maintain a 1.25V threshold at
the FB pin. During this period of time, the power MOSFET
is still on and continues to supply current to the load. This
allows uninterrupted operation during short overvoltage
transient events.
V
= 5V across the whole temperature range.
CC
Fault Timer Current
The timer current starts at around 2μA with 0.5V or less
of V , increasing linearly to 50μA with 75V of V dur-
DS
DS
When the voltage regulation loop is engaged for longer
than the time-out period, set by the timer capacitor con-
nectedfromtheTMRpintoground, anovervoltagefaultis
detected. The GATE pin is pulled down to the OUT pin by a
150mA current. After the fault condition has disappeared
andacooldownperiodhastranspired, theGATEpinstarts
to pull high again. This prevents the power MOSFET from
being damaged during a long period of overvoltage, such
as during load dump in automobiles.
ing an overvoltage fault (Figure 1). During an overcurrent
fault, it starts at 4μA with 0.5V or less of V but increases
DS
to 260μA with 80V across the MOSFET (Figure 2). This
arrangement allows the pass transistor to turn off faster
duringanovercurrentevent,sincemorepowerisdissipated
during this condition. Refer to the Typical Performance
Characteristics section for the timer current at different
V
DS
in both overvoltage and overcurrent events.
When the voltage at the TMR pin, V
, reaches the 1.25V
TMR
Overcurrent Fault
threshold, the FLT pin pulls low to indicate the detection
of a fault condition and provide warning to the load of
the impending power loss. In the case of an overvoltage
fault, the timer current then switches to a fixed 5μA.
The LT4356-1 features an adjustable current limit that
protects against short circuits or excessive load current.
During an overcurrent event, the GATE pin is regulated to
limit the current sense voltage across the V and SNS
CC
pins to 50mV.
43561fd
9
LT4356-1
APPLICATIONS INFORMATION
V
TMR(V)
MOSFET. The TMR pin is then actively regulated to 0.5V
until the next fault condition appears. The total cool down
timer period is given by:
I
= 5μA
I
= 5μA
TMR
TMR
1.35
1.25
V
TMR
= 75V
= 50μA)
DS
(I
CTMR • 0.85V
V
TMR
= 10V
= 8μA)
DS
tCOOL
=
(I
2µA
MOSFET Selection
0.50
TIME
t
t
WARNING
FLT
= 15ms/μF
TheLT4356-1drivesanN-channelMOSFETtoconductthe
load current. The important features of the MOSFET are
= 20ms/μF
t
= 93.75ms/μF
t
FLT
WARNING
= 20ms/μF
on-resistanceR
,themaximumdrain-sourcevoltage
DS(ON)
TOTAL FAULT TIMER = t + t
FLT WARNING
43561 F01
V
, the threshold voltage, and the SOA.
(BR)DSS
Figure 1. Overvoltage Fault Timer Current
The maximum allowable drain-source voltage must be
higher than the supply voltage. If the output is shorted
to ground or during an overvoltage event, the full supply
voltage will appear across the MOSFET.
V
TMR(V)
1.35
1.25
V
TMR
= 80V
DS
V
TMR
= 10V
(I
= 260μA)
The gate drive for the MOSFET is guaranteed to be more
DS
(I
= 35μA)
than10Vandlessthan18VforthoseapplicationswithV
CC
higher than 8V. This allows the use of standard threshold
voltage N-channel MOSFETs. For systems with V less
CC
0.50
TIME
than 8V, a logic level MOSFET is required since the gate
drive can be as low as 4.5V.
t
WARNING
= 0.38ms/μF
t
FLT
= 2.88ms/μF
t
= 21.43ms/μF
FLT
t
WARNING
= 2.86ms/μF
The SOA of the MOSFET must encompass all fault condi-
tions. In normal operation the pass transistor is fully on,
dissipating very little power. But during either overvoltage
or overcurrent faults, the GATE pin is servoed to regu-
late either the output voltage or the current through the
MOSFET. Large current and high voltage drop across the
MOSFET can coexist in these cases. The SOA curves of
the MOSFET must be considered carefully along with the
selection of the fault timer capacitor.
43561 F02
TOTAL FAULT TIMER = t + t
FLT WARNING
Figure 2. Overcurrent Fault Timer Current
The interval between FLT asserting low and the MOSFET
turning off is given by:
CTMR • 100mV
tWARNING
=
5µA
This fixed early warning period allows the systems to per-
formnecessarybackuporhousekeepingfunctionsbefore
the power supply is cut off. After V
threshold, the pass transistor turns off immediately. Note
that during an overcurrent event, the timer current is not
reduced to 5μA after V
Transient Stress in the MOSFET
crosses the 1.35V
TMR
During an overvoltage event, the LT4356-1 drives a series
passMOSFETtoregulatetheoutputvoltageatanacceptable
level.Theloadcircuitrymaycontinueoperatingthroughout
this interval, but only at the expense of dissipation in the
MOSFET pass device. MOSFET dissipation or stress is a
function of the input voltage waveform, regulation voltage
and load current. The MOSFET must be sized to survive
this stress.
has reached 1.25V threshold,
TMR
since it would lengthen the overall fault timer period and
cause more stress on the power MOSFET.
As soon as the fault condition has disappeared, a 2μA
current starts to discharge the timer capacitor to ground.
WhenV
reachesthe0.5Vthreshold,theinternalcharge
TMR
Most transient event specifications use the model shown
pump starts to pull the GATE pin high, turning on the
in Figure 3. The idealized waveform comprises a linear
43561fd
10
LT4356-1
APPLICATIONS INFORMATION
V
V
PK
PK
T
T
V
REG
V
V
IN
IN
t
r
t
r
43561 F04
43561 F03
Figure 4. Safe Operating Area Required to Survive Prototypical
Transient Waveform
Figure 3. Prototypical Transient Waveform
ramp of rise time t , reaching a peak voltage of V and
r
PK
Let
exponentially decaying back to V with a time constant
IN
of t. A common automotive transient specification has
a = V
b = V – V
(V = Nominal Input Voltage)
– V
IN
IN
REG
PK
constants of t = 10μs, V = 80V and τ = 1ms. A surge
r
PK
condition known as “load dump” has constants of
IN
t = 5ms, V = 60V and τ = 200ms.
r
PK
Then
MOSFET stress is the result of power dissipated within the
device. For long duration surges of 100ms or more, stress
is increasingly dominated by heat transfer; this is a matter
of device packaging and mounting, and heatsink thermal
mass. For short duration transients of less than 100ms,
MOSFETsurvivalisincreasinglyamatterofsafeoperating
area (SOA), an intrinsic property of the MOSFET.
3
ꢈ
ꢊ
ꢊ
ꢊ
ꢊ
ꢉ
ꢋ
ꢍ
ꢍ
ꢍ
ꢍ
ꢌ
b– a
b
1
3
1
2
(
)
tr
+
2
P2t = ILOAD
b
ꢂ
ꢅ
ꢆ
ꢀ 2a2 ln + 3a2 +b2 ꢁ 4ab
ꢄ
ꢇ
ꢃ
a
Typically V
≈ V and τ >> t simplyfying the above to
IN r
REG
SOA quantifies the time required at any given condition
of V and I to raise the junction temperature of the
1
2
P2t = ILOAD V – V
2 τ
(W2s)
2
(
)
DS
D
PK
REG
MOSFETtoitsratedmaximum.MOSFETSOAisexpressed
2
in units of watt-squared-seconds (P t). This figure is es-
For the transient conditions of V = 80V, V = 12V,
PK
IN
sentially constant for intervals of less than 100ms for any
given device type, and rises to infinity under DC operating
conditions. Destruction mechanisms other than bulk die
temperature distort the lines of an accurately drawn SOA
V
= 16V, t = 10μs and τ = 1ms, and a load current
REG
r
2
2
of 3A, P t is 16.7W s—easily handled by a MOSFET in
a D-pak package. The P t of other transient waveshapes
is evaluated by integrating the square of MOSFET power
versus time.
2
2
graph so that P t is not the same for all combinations of
2
I and V . In particular P t tends to degrade as V ap-
D
DS
DS
proaches the maximum rating, rendering some devices
useless for absorbing energy above a certain voltage.
Calculating Short Circuit Stress
SOA stress must also be calculated for short circuit condi-
tions. Short circuit P t is given by:
2
Calculating Transient Stress
P2t = (V • ΔVSNS /RSNS)2 • tTMR (W2s)
To select a MOSFET suitable for any given application, the
SOA stress must be calculated for each input transient
whichshallnotinterruptoperation.Itisthenasimplemat-
ter to chose a device which has adequate SOA to survive
IN
where, ΔV
is the SENSE pin threshold, and t
is the
SNS
TMR
overcurrent timer interval.
For V = 14.7V, V
= 50mV, R
= 12mΩ and C
SNS TMR
2
IN
SNS
the maximum calculated stress. P t for a prototypical
2
2
= 100nF, P t is 6.6W s—less than the transient SOA
calculated in the previous example. Nevertheless, to ac-
43561fd
transient waveform is calculated as follows (Figure 4).
11
LT4356-1
APPLICATIONS INFORMATION
count for circuit tolerances this figure should be doubled
The amplifier can also be configured as a low dropout
linearregulatorcontroller. WithanexternalPNPtransistor,
such as 2N2905A, it can supply up to 100mA of current
with only a few hundred mV of dropout voltage. Current
limit can be easily included by adding two diodes and one
resistor (Figure 6).
2
to 13.2W s.
Limiting Inrush Current and GATE Pin Compensation
The LT4356-1 limits the inrush current to any load capaci-
tance by controlling the GATE pin voltage slew rate. An
external capacitor can be connected from GATE to ground
to slow down the inrush current further at the expense of
slower turn-off time.
2N2905A OR
BCP53
*4.7Ω
INPUT
OUTPUT
TheLTC4356-1doesnotneedextracompensationcompo-
nents at the GATE pin for stability during an overvoltage or
overcurrentevent.However,withfast,highvoltagetransient
stepsattheinput,agatecapacitor,C1,togroundisneeded
to prevent turn-on of the N-Channel MOSFET.
*OPTIONAL FOR
CURRENT LIMIT
R6
100k
D1*
BAV99
11
A
OUT
LT4356DE-1
43561 F06
The extra gate capacitance slows down the turn off time
during fault conditions and may allow excessive current
duringanoutputshortevent.Anextraresistor,R1,inseries
with the gate capacitor can improve the turn off time. A
diode, D1, should be placed across R1 with the cathode
connected to C1 as shown in Figure 5.
Figure 6. Auxiliary LDO Output with Optional Current Limit
Reverse Input Protection
A blocking diode is commonly employed when reverse
input potential is possible, such as in automotive applica-
tions. This diode causes extra power loss, generates heat,
and reduces the available supply voltage range. During
cold crank, the extra voltage drop across the diode is
particularly undesirable.
Auxiliary Amplifier
An uncommitted amplifier is included in the LT4356-1 to
provide flexibility in the system design. With the negative
input connected internally to the 1.25V reference, the am-
plifier can be connected as a level detect comparator with
The LT4356-1 is designed to withstand reverse voltage
without damage to itself or the load. The V , SNS, and
CC
external hysteresis. The open collector output pin, A
,
SHDN pins can withstand up to 60V of DC voltage below
the GND potential. Back-to-back MOSFETs must be used
to eliminate the current path through their body diodes
(Figure 7). Figure 8 shows the approach with a P-Channel
MOSFET in place of Q2.
OUT
is capable of driving an opto or LED. It can also interface
with the system via a pull-up resistor to a supply voltage
up to 80V.
Q1
Shutdown
D1
The LT4356-1 can be shut down to a low current mode
whenthevoltageattheSHDNpingoesbelowtheshutdown
threshold of 0.6V. The quiescent current drops to 7μA.
IN4148W
R3
R1
The SHDN pin can be pulled up to V or below GND by
C1
CC
GATE
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn on
the part while clamping the pin to 2.5V. The leakage cur-
rent at the pin should be limited to no more than 1μA if
no pull up device is used to help turn it on.
LT4356-1
43561 F05
Figure 5
43561fd
12
LT4356-1
APPLICATIONS INFORMATION
R
Q2
Q1
SNS
10mΩ
power trace parasitic inductance should be minimized by
using wide traces. A snubber circuit dampens the ringing
associatedwithvoltagespikes.A10Ωresistorinserieswith
IRLR2908
IRLR2908
V
V
OUT
IN
12V
12V, 3A
CLAMPED
AT 16V
D2*
SMAJ58CA
R4
R3
R5
Q3
10Ω
10Ω
1M
2N3904
a 0.1μF capacitor between V and GND is effective with
CC
R1
up to 1μH feed point inductance. A surge suppressor, D2,
in Figure 9, at the input will clamp the voltage spikes.
59k
D1
1N4148
R7
10k
5
SNS
4
3
A 1μF ceramic capacitor, C , is needed at the OUT pin to
L
GATE OUT
FB
6
2
V
CC
clamp the voltage spike if the input voltage rise time is
C2
0.1μF
R6
10Ω
R2
4.99k
R
LT4356DE-1
Q1
SNS
10mΩ
IRLR2908
7
11
12
V
IN
SHDN
C2
0.1μF
100V
D2
8
9
A
OUT
FLT
SMAJ58A
R6
+
10Ω
IN
EN
43561 F07
GND
10
TMR
1
R3
10Ω
R1
59k
C
L
1μF
C
TMR
0.1μF
5
4
3
*DIODES INC.
CERAMIC
SNS GATE OUT
6
V
CC
2
FB
Figure 7. Overvoltage Regulator with N-Channel MOSFET
Reverse Input Protection
R4
383k
7
V
CC
SHDN
R2
4.99k
12
DC-DC
CONVERTER
+
IN
LT4356DE-1
R5
9
8
R
100k
Q2
Q1
SNS
EN
SHDN
GND
10mΩ
Si4435
IRLR2908
V
IN
12V
V
OUT
11
12V, 3A
UNDERVOLTAGE
A
OUT
FLT
FAULT
D1
1N5245
15V
GND
10
TMR
CLAMPED AT 16V
D2*
SMAJ58CA
43561 F09
1
C
TMR
47nF
R3
10Ω
R6
10k
R1
59k
5
SNS
4
3
Figure 9. Overvoltage Regulator with Low Battery Detection
GATE OUT
6
2
V
CC
FB
C2
0.1μF
faster than 10μs. A total bulk capacitance in the range of
R2
4.99k
22μF is also required close to the V pin of the DC/DC
CC
LT4356DE-1
7
11
12
converter, if not already provided by the converter.
SHDN
8
9
A
OUT
FLT
Layout Considerations
+
IN
EN
GND
10
TMR
1
To achieve accurate current sensing, Kelvin connection
43561 F08
C
TMR
0.1μF
to the current sense resistor (R
in Figure 9) is recom-
SNS
*DIODES INC.
mended. The minimum trace width for 1oz copper foil is
0.02" per amp to ensure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530μΩ/square.Smallresistancescancauselargeerrorsin
highcurrentapplications.Noiseimmunitywillbeimproved
significantly by locating resistive dividers close to the pins
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
Supply Transient Protection
The LT4356-1 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. Neverthe-
less, voltagetransientsabove100Vmaycausepermanent
damage.Duringashort-circuitcondition,thelargechange
incurrentflowingthroughpowersupplytracesandassoci-
ated wiring can cause inductive voltage transients which
couldexceed100V. Tominimizethevoltagetransients, the
with short V and GND traces.
CC
43561fd
13
LT4356-1
APPLICATIONS INFORMATION
Design Example
C
TMR
is then chosen for 1ms of early warning time:
As a design example, take an application with the follow-
1ms • 5µA
CTMR
=
= 50nF
ing specifications: V = 8V to 14V DC with transient up
CC
100mV
The closest standard value for C
to 80V, V
≤ 16V, current limit (I ) at 5A, low battery
OUT
LIM
is 47nF.
detection at 6V, and 1ms of overvoltage early warning
(Figure 9).
TMR
Finally,calculateR4andR5forthe6Vlowbatterythreshold
detection:
First, calculate the resistive divider value to limit V
16V during an overvoltage event:
to
OUT
1.25V • R4 + R5
(
)
6V =
1.25V • R1 + R2
(
)
R5
VREG
=
=16V
R2
Choose 100kΩ for R5.
Set the current through R1 and R2 during the overvoltage
condition to 250μA.
6V – 1.25V • R5
(
)
R4 =
= 380kꢀ
1.25V
1.25V
R2 =
= 5kꢀ
Select 383kΩ for R4.
250µA
Choose 4.99kΩ for R2.
16V – 1.25V • R2
The pass transistor, Q1, should be chosen to withstand
the output short condition with V = 14V.
CC
(
)
The total overcurrent fault time is:
R1 =
= 58.88kꢀ
1.25V
47nF • 0.85V
tOC
=
= 0.878ms
The closest standard value for R1 is 59kΩ.
45.5μA
Next calculate the sense resistor, R , value:
SNS
The power dissipation on Q1 equals to:
50mV 50mV
14V • 50mV
RSNS
=
=
= 10mꢀ
P =
= 70W
ILIM
5A
10mꢀ
These conditions are well within the Safe Operating Area
of IRLR2908.
43561fd
14
LT4356-1
TYPICAL APPLICATIONS
24V Overvoltage Regulator Withstands 150V at VIN
Q1
IRF640
V
V
OUT
IN
24V
CLAMPED AT 32V
R9
1k
1W
R3
10Ω
R1
118k
5
4
3
SNS
GATE
OUT
6
2
V
FB
CC
D2*
SMAT70A
R2
4.99k
LT4356DE-1
7
8
9
SHDN
FLT
EN
GND
10
TMR
1
43561 TA05
C
TMR
*DIODES INC.
0.1μF
43561fd
15
LT4356-1
TYPICAL APPLICATIONS
Overvoltage Regulator with Low Battery Detection and Output Keep Alive During Shutdown
1k
0.5W
R
SNS
Q1
IRLR2908
10mΩ
V
V
OUT
IN
12V
12V, 4A
C2
10μF
CLAMPED AT 16V
D2*
SMAJ58A
R3
D1
10Ω
Q2
1N4746A
18V
R4
VN2222
402k
1W
5
SNS
4
3
OUT
R1
GATE
294k
6
V
2
CC
FB
C2
0.1μF
R2
24.9k
V
DD
R6
10Ω
R6
47k
LT4356DE-1
12
7
11
8
+
IN
A
LBO
OUT
R5
105k
SHDN
FLT
9
EN
GND
10
TMR
1
43561 TA03
*DIODES INC.
C
TMR
0.1μF
43561fd
16
LT4356-1
TYPICAL APPLICATIONS
2.5A, 48V Hot Swap with Overvoltage Output Regulation at 72V and UV Shutdown at 35V
R
Q1
FDB3632
SNS
15mΩ
V
V
OUT
IN
48V
48V
R
S
R4
140k
R6
27k
2.5A
D2*
SMAT70A
100Ω
R3
10Ω
C
S
0.01μF
C
L
300μF
C1
6.8nF
6
5
4
3
OUT
D1
1N4714
V
SNS GATE
R7
CC
BV = 33V
1M
12
2
+
IN
7
SHDN
R5
4.02k
R8
47k
R1
226k
LT4356DE-1
FB
R2
4.02k
8
9
FLT
11
EN
A
PWRGD
OUT
GND
10
TMR
1
43561 TA06
C
TMR
0.1μF
*DIODES INC.
2.5A, 28V Hot Swap with Overvoltage Output Regulation at 36V and UV Shutdown at 15V
R
Q1
FDB3632
SNS
15mΩ
V
V
OUT
IN
28V
28V
R
S
R4
113k
R6
27k
2.5A
D2*
SMAT70A
100Ω
R3
10Ω
C
C
S
L
0.01μF
300μF
C1
6.8nF
6
5
4
3
OUT
D1
1N4700
V
SNS GATE
R7
CC
BV = 13V
1M
12
2
+
IN
7
SHDN
R5
4.02k
R8
47k
R1
110k
LT4356DE-1
FB
R2
4.02k
8
9
FLT
11
EN
A
PWRGD
OUT
GND
10
TMR
1
43561 TA07
C
TMR
0.1μF
*DIODES INC.
43561fd
17
LT4356-1
PACKAGE DESCRIPTION
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev C)
0.70 0.05
3.60 0.05
2.20 0.05 (2 SIDES)
1.70 0.05
PACKAGE OUTLINE
0.25 0.05
0.50
BSC
3.30 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.40 0.10
4.00 0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.05
TYP
3.00 0.10 1.70 0.05
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0905 REV C
6
0.25 0.05
1
0.75 0.05
0.200 REF
0.50
BSC
3.30 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
43561fd
18
LT4356-1
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127
(.035 .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 0.102
(.118 .004)
(NOTE 3)
(.0197)
0.497 0.076
(.0196 .003)
REF
0.50
0.305 0.038
(.0120 .0015)
TYP
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
1
2
3
4 5
0.53 0.152
(.021 .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 0.0508
(.004 .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
43561fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT4356-1
TYPICAL APPLICATION
Overvoltage Regulator with Linear Regulator Up to 100mA
Q2
2N2905A
2.5V, 100mA
C5
10μF
R
Q1
IRLR2908
SNS
10mΩ
V
IN
12V
V
OUT
12V, 3A
CLAMPED AT 16V
D2*
SMAJ58A
R3
R1
10Ω
59k
5
4
3
6
SNS
GATE
OUT
R6
100k
V
A
CC
2
C2
FB
0.1μF
R2
R6
10Ω
4.99k
R4
249k
C3
47nF
LT4356DE-1
11
7
12
8
+
IN
OUT
R5
249k
SHDN
FLT
9
EN
GND
10
TMR
43561 TA04
1
C
*DIODES INC.
TMR
0.1μF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1641-1/LT1641-2 Positive High Voltage Hot Swap™ Controllers
Active Current Limiting, Supplies From 9V to 80V
ThinSOT™ Package, 2.7V to 28V
LTC1696
LTC1735
Overvoltage Protection Controller
High Efficiency Synchronous Step-Down
Switching Regulator
Output Fault Protection, 16-Pin SSOP
LTC1778
No R
™ Wide Input Range Synchronous
Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
≤ (0.9)(V ),
OUT IN
SENSE
IN
Step-Down Controller
I
Up to 20A
OUT
LTC2909
Triple/Dual Inputs UV/OV Negative Monitor
Single/Dual UV/OV Voltage Monitor
Quad UV/OV Monitor
Pin Selectable Input Polarity Allows Negative and OV Monitoring
Ads UV and OV Trip Values, 1.5% Threshold Accuracy
For Positive and Negative Supplies
LTC2912/LTC2913
LTC2914
LTC3727/LTC3727-1 2-Phase, Dual, Synchronous Controller
LTC3827/LTC3827-1 Low I , Dual, Synchronous Controller
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 14V
IN
OUT
OUT
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V, 80μA Quiescent Current
Q
IN
LTC3835/LTC3835-1 Low I , Synchronous Step-Down Controller
Single Channel LTC3827/LTC3827-1
4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, 120μA Quiescent Current
Q
LT3845
LT3850
Low I , Synchronous Step-Down Controller
Q
IN
OUT
Dual, 550kHz, 2-Phase Sychronous Step-Down
Controller
Dual 180° Phased Controllers, V 4V to 24V, 97% Duty Cycle, 4mm × 4mm
IN
QFN-28, SSOP-28 Packages
LT4256
Positive 48V Hot Swap Controller with
Open-Circuit Detect
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to
80V Supply
LTC4260
Positive High Voltage Hot Swap Controller with
Wide Operating Range 8.5V to 80V
2
ADC and I C
LT4351
Ideal MOSFET ORing Diode
External N-channel MOSFETs Replace ORing Diodes, 1.2V to 20V
Controls Two N-Channel MOSFETs, 1μs Turn-Off, 80V Operation
Controls Two N-Channel MOSFETs, 0.5μs Turn-Off, 80V Operation
LTC4354
Negative Voltage Diode-OR Controller
Positive Voltage Diode-OR Controller
LTC4355
Hot Swap, No R
and ThinSOT are trademarks of Linear Technology Corporation.
SENSE
43561fd
LT 0808 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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