LT4220IGN#TRPBF [Linear]
LT4220 - Dual Supply Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LT4220IGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT4220 - Dual Supply Hot Swap Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 输入元件 光电二极管 |
| 文件： | 总16页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4220
Dual Supply
Hot Swap Controller
U
FEATURES
DESCRIPTIO
Hot SwapTM Controller for Positive
The LT®4220 16-pin dual voltage Hot Swap controller
allows a board to be safely inserted and removed from a
live backplane. The device operates with any combination
of 2.7V to 16.5V and –2.7V to –16.5V supplies. Using two
external N-channel pass transistors, the board supply
voltages can be ramped up at an adjustable rate. A select-
able tracking mode allows dual supply tracking control for
ramping the positive and negative supplies together.
■
and Negative Supplies
■
Supply Tracking Mode
■
±2.7V to ±16.5V Operation
■
Analog Current Limit with Foldback
■
Allows Safe Board Insertion and Removal
from a Live Backplane
■
Open-Collector Power Good Comparators
■
Automatic Retry or Latchoff After a Current Fault
The LT4220 features foldback current limit and latches off
both gates if either supply remains in current limit longer
than an adjustable time period. The IC can be configured
for automatic restart after a delay set by the same timer.
■
Dual Undervoltage Lockout Comparator Inputs
■
Current Fault IndUication
APPLICATIO S
A power good signal indicates when the output voltages
monitoredby thetwoFBcomparatorsarewithintolerance,
and the gate drive signals are at their full on voltage.
■
Live Board Insertion
■
RAID Systems
■
–5.2V ECL Supplies
The LT4220 is available in a 16-lead narrow SSOP
package.
■
Industrial Controls
■
Split Supply Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
±12V 10A Hot Swap Controller
+
R
Q1
S
+
0.005Ω
SUB85N03-04
V
12V
CC
IN
12V
OUT
+
V
V
R13
10Ω
C1
10nF
+
Z1*
R5
10Ω
R6
1k
C4
100nF
CL1
7
16
15
SENSE
14
GATE
+
+
R15
20k
12V
IN
R1
V
TRACK
D1
CC
R9
10
13
V
+
36.5k
IN4001
PWRGD
12
36.5k
+
ON
R16, 20k
+
FB
11
8
R2
4.99k
FAULT
TIMER
12V
+
R10
4.99k
C7
V
OUT
10nF
C6
1µF
LT4220
9
6
R12
4.99k
GND
–12V
5
R4
4.99k
C8
10nF
–
V
–
IN
FB
R11
36.5k
–
ON
D2
IN4001
–
–
–12V
V
EE
SENSEK SENSE
GATE
R3
36.5k
C2
10nF
V
–
OUT
1
2
3
4
R8
1k
C5
1µF
TIME (10ms/DIV)
C3
100nF
+
R7
CL2
10Ω
Z2*
R14
10Ω
–
R
S
–
0.005Ω
V
IN
–12V
–12V
–
V
OUT
V
Q2
SUB85N03-04
EE
* 1SMA13AT3 TRANSIENT
VOLTAGE SUPPRESSOR
4220 TA01
4220f
1
LT4220
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
VCC to GND ............................................................. 22V
VEE to GND ........................................................... –22V
TRACK, TIMER .............................. – 0.3V to VCC + 0.3V
ON+, FB+ ................................. VEE – 0.3V to VCC + 0.3V
ON–, FB–.................................. VEE – 0.3V to VCC + 0.3V
GATE+ ................................................ –0.3V to VCC + 8V
GATE–.............................. –16.5V with VEE = –22V to 0V
SENSE+ ............................................. –0.3V to VCC + 5V
SENSE–, SENSEK ....................... VEE – 0.3V to VEE + 3V
PWRGD, FAULT ................................. –0.3V to VCC + 5V
Operating Temperature Range
ORDER PART
TOP VIEW
NUMBER
V
1
2
3
4
5
6
7
8
16
15
14
13
V
CC
EE
+
SENSEK
SENSE
LT4220CGN
LT4220IGN
–
+
SENSE
GATE
–
+
GATE
FB
–
+
FB
12 ON
–
ON
11
10
9
FAULT
GN PART MARKING
TRACK
TIMER
PWRGD
GND
4220
4220I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
LT4220C........................................... 0°C ≤ TA ≤ 70°C
LT4220I ....................................... –40°C ≤ TA ≤ 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
16.5
4
UNITS
V
V
V
V
V
V
V
V
Operating Range
Supply Current
●
●
●
2.7
CC
EE
CC
CC
EE
EE
CC
EE
I
2.7
mA
V
CC
V
Operating Range
Supply Current
–2.7
–16.5
–2.4
2.55
–2.5
1.26
70
I
–1.6
2.45
–2.45
1.24
50
mA
V
EE
V
Undervoltage Lockout
Undervoltage Lockout
●
●
●
●
●
●
●
●
●
●
●
●
●
●
2.35
–2.4
1.22
25
PLKO
MLKO
V
V
+
+
V
+
ON ON Threshold
ON Rising
V
ON H
+
V
+
ON Hysteresis
mV
mV/V
mV/V
mV
V
ON HYS
+
+
∆V
∆V
ON ON Threshold Line Regulation
V
V
= 2.7V, V = –2.7V to V = 16.5V, V = –16.5V
0.02
0.05
50
0.15
1
ON
H
H
CC
CC
EE
CC
EE
–
–
ON ON Threshold Line Regulation
= 2.7V, V = –2.7V to V = 16.5V, V = –16.5V
EE CC EE
ON
–
–
V
V
ON Hysteresis
25
70
ON HYS
–
–
–
ON ON Voltage Threshold
ON Falling
–1.22
–1.24
0.01
0.01
1.24
50
–1.26
±1
ON
H
+
+
+
I
I
ON Input Current
V
V
= 2V
µA
µA
V
ON
ON
ON
–
–
–
+
ON Input Current
= GND
±1
ON
+
+
V
V
V
V
FB PWRGD Voltage Threshold
FB Rising
Gate = 5V
1.22
25
1.26
70
FB H
+
+
FB Hysteresis
mV
V
FB HYS
–
–
–
FB PWRGD Voltage Threshold
FB Falling
–1.22
25
–1.24
50
–1.26
70
FB
H
–
–
FB Hysteresis
Gate = 3V
mV
FB HYS
4220f
2
LT4220
DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
0.09
0.08
0.015
0.05
MAX
±1
UNITS
µA
+
+
I
I
+
–
FB Input Current
FB = 3V
●
●
●
●
●
INFB
INFB
–
–
FB Input Current
FB = –3V
±1
µA
+
∆V
+
FB PWRGD Threshold Line Regulation
V
V
= 2.7V, V = –2.7V to V = 16.5V, V = –16.5V
0.15
0.5
mV/V
mV/V
FB H
CC
CC
EE
CC
EE
–
∆
–
FB PWRGD Threshold Line Regulation
= 2.7V, V = –2.7V to V = 16.5V, V = –16.5V
EE CC EE
VFB H
+
+
+
+
)
+
V
SENSE Trip Voltage (V – V
V
V
= 0V, GATE – 0.5V
= 1V, GATE – 0.5V
6
36
15
48
22
60
mV
mV
SENSE
CC
SENSE
FB
FB
+
+
–
–
V
–
SENSE Trip Voltage (V
– V
–
)
V
–
–
= 0V, GATE – 0.5V
●
–10
–43
–15
–52
–22
–61
mV
mV
SENSE
SENSEK
SENSE
FB
–
V
FB
= –1V, GATE – 0.5V
+
+
–
+
I
I
I
I
GATE Pull-Up Current
Charge Pump On, V
= 7V
●
●
●
●
●
–9
–6
20
30
–13
–10
40
–17
–14
60
µA
µA
GATEUP
GATEUP
GATEDN
GATEDN
GATE
–
GATE Pull-Up Current
V
– = –3V
GATE
+
+
–
+
GATE Pull-Down Current
Any Fault Condition, V
Any Fault Condition, V
+
–
= 1V
mA
mA
GATE
–
GATE Pull-Down Current
= V + 4V
70
130
GATE
EE
+
∆V
External N-Channel GATE Drive
V
V
+
– V , V = 2.7V, V = –2.7V
= 5V to 16.5V, V = –5V to –16.5V
3.5
5
4
6.5
6
8
V
V
GATE
GATE
CC CC
EE
CC
EE
–
–
–
– V , V = 2.7V, V = –2.7V
∆V
GATE
External N-Channel GATE Drive
V
V
●
3.5
7.5
5.2
8.5
6
9
V
V
GATE
EE CC
EE
= 5V to 16.5V, V = –5V to –16.5V
CC
EE
V
V
TIMER High Threshold, Sets FAULT
TIMER Low Threshold, Allows Restart
TIMER Pull-Up Current
●
●
●
●
1.22
0.4
–40
2
1.24
0.5
–65
3.3
5
1.26
0.6
–85
4.5
7
V
V
TIMERH
TIMERL
I
I
I
TIMER = 0V
TIMER = 1V
µA
µA
%
TIMERUP
TIMERDN
TIMER(R)
TIMER Pull-Down Current
TIMER Current Ratio
I
/I
TIMERDN TIMERUP
V
PWRGD Output Low Voltage
I
= 2mA
O
O
●
0.3
0.5
V
V
OL
I = 5mA
I
PWRGD Leakage Current
FAULT Output Low Voltage
V
= 16.5V
PWRGD
●
●
0.1
2
µA
OH
V
I = 2mA
0.3
0.5
V
V
FOL
O
I = 5mA
O
I
FAULT Leakage Current
TRACK Input Threshold
TRACK Input Current
V
= 16.5V
●
●
●
●
●
0.06
0.8
0.05
40
2
1.1
2
µA
V
FPH
FAULT
V
0.3
TRKTHR
I
TRACK = 16.5V
µA
mV
mV
TRK
+
+
–
+
V
V
TRACK Mode FB Threshold
I
I
= 0µA, TRACK = V (Note 3)
70
80
TRKFB
GATE
GATE
CC
–
–
TRACK Mode FB Threshold
= 0µA, TRACK = V (Note 3)
40
TRKFB
CC
4220f
3
LT4220
AC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
0.6
0.6
0.5
0.6
0.6
1
TYP
0.8
1.5
0.8
1.25
1
MAX
1.2
3
UNITS
µs
+
+
+
+
+
t
t
t
t
t
t
t
t
t
t
ON Low to GATE Low
5k Pull-Up to GATE , 1nF Load Capacitor
●
●
●
●
●
●
●
●
●
●
PHLON
PLHON
+
+
+
ON High to GATE High
5k Pull-Up to GATE , 1nF Load Capacitor
µs
+
+
FB Low to PWRGD Low
5k Pull-Up to PWRGD
5k Pull-Up to PWRGD
1.2
3
µs
PHLFB
PLHFB
PHLON
PLHON
+
+
FB High to PWRGD High
µs
–
–
–
–
–
ON Low to GATE Low
5k Pull-Up to GATE , 1nF Load Capacitor
1.5
3.5
1.5
2
µs
–
–
–
ON High to GATE High
5k Pull-Up to GATE , 1nF Load Capacitor
2.1
1
µs
–
–
FB Low to PWRGD Low
5k Pull-Up to PWRGD
0.6
0.8
1
µs
PHLFB
PLHFB
SENSE
SENSE
–
–
FB High to PWRGD High
5k Pull-Up to PWRGD
1.25
4
µs
+
+
+
+
–
SENSE to GATE Low
1nF On GATE , 100mV Step, 5k Pull-Up
6
µs
–
–
–
SENSE to GATE Low
1nF On GATE , 100mV Step, 5k Pull-Up
1
4
6
µs
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages referenced to ground (GND) unless
specified.
+
–
Note 3: The absolute voltage difference between FB and FB required to
+
–
force either the GATE or GATE current to 0µA.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Positive Circuit Breaker Sense
Negative Circuit Breaker Sense
Voltage vs FB– Voltage
Voltage vs FB+ Voltage
Supply Current vs Supply Voltage
4
3
2
1
0
50
40
30
20
10
0
60
50
40
30
20
10
0
T
= 25°C
V
V
= 5V
V
V
= 5V
A
CC
EE
CC
EE
= –5V
= –5V
+
I
+
CC
ON = 2V
ON = 2V
–
–
ON = –2V
ON = –2V
T
= 25°C
T
= 25°C
A
A
I
EE
10
15
–1.5
–0.5
FB VOLTAGE (V)
0
0.5
1.0
1.5
–1.5
–0.5
FB VOLTAGE (V)
0
0.5
1.0
1.5
0
20
–1.0
–1.0
5
+
–
SUPPLY VOLTAGE (V)
4220 G02
4220 G03
4220 G01
4220f
4
LT4220
U W
TYPICAL PERFOR A CE CHARACTERISTICS
GATE+ Pull-Up Current vs
GATE+ Voltage
GATE+ Drive vs VCC
GATE– Drive vs VEE
8
7
6
5
4
10
16
14
12
10
8
T
= 25°C
T = 25°C
A
A
9
V
= 5V
CC
V
= –5V
EE
8
7
V
= 2.7V
CC
6
V
= –2.7V
EE
6
V
V
V
V
= 5V
CC
EE
= –5V
4
+ = V
– = V
SENSE
SENSE
CC
EE
5
2
T
= 25°C
A
0
4
0
3
6
9
12
15
18
14
10
0
3
6
9
12
15
18
1
2
3
4
5
7
0
6
+
+
V
(V)
V
(V)
EE
GATE VOLTAGE (V
– V ) (V)
CC
CC
GATE
4220 G04
4220 G05
4220 G06
GATE+ Pull-Down Current vs
GATE+ Voltage
GATE– Pull-Down Current vs
GATE– Voltage
GATE– Pull-Up Current vs
GATE– Voltage
60
50
40
30
20
10
0
12
10
8
70
60
50
40
30
20
10
0
V
CC
V
EE
= 5V
= –5V
–
–
ON = 0V
FB = –2V
T
A
= 25°C
6
4
V
= 5V
V
V
= 5V
CC
CC
EE
V
= –5V
= –5V
EE
+
+
ON = 0V
SENSE = V
2
CC
EE
+
–
FB = 2V
SENSE = V
T
A
= 25°C
T
= 25°C
A
0
2
4
6
+
8
10
2
4
6
8
10
2
–
3
4
5
6
8
0
12
0
0
7
1
–
GATE VOLTAGE (V)
GATE VOLTAGE (V
– – V ) (V)
GATE VOLTAGE (V
– – V ) (V)
GATE
EE
GATE EE
4220 G07
4220 G08
4220 G09
ON+, ON– and FB+, FB–
Hysteresis vs Temperature
PWRGD and FAULT VOL vs
Sink Current
TIMER Pull-Up Current vs VCC
75
70
65
60
55
50
900
800
700
600
500
400
300
200
100
0
45.0
44.5
44.0
43.5
43.0
42.5
42.0
41.5
41.0
T
= 25°C
A
V
V
T
= 5V
CC
EE
= –5V
= 25°C
A
FAULT
PWRGD
0
3
6
9
12
15
18
4
40
0
TEMPERATURE (°C)
80
0
2
6
8
–40 –20
20
60
V
(V)
SINK CURRENT (mA)
CC
4220 G11
4220 G10
4220 G12
4220f
5
LT4220
U W
TYPICAL PERFOR A CE CHARACTERISTICS
FB+ and ON+ Threshold Voltage vs
Temperature
FB– and ON– Threshold Voltage vs
Temperature
TIMER Pull-Up Current vs
Temperature
1.241
1.240
1.239
1.238
1.237
1.236
1.235
–1.241
–1.240
–1.239
–1.238
–1.237
–1.236
–1.235
70
69
68
67
66
65
64
40
TEMPERATURE (°C)
80
40
TEMPERATURE (°C)
80
40
TEMPERATURE (°C)
80
–40 –20
0
20
60
–40 –20
0
20
60
–40 –20
0
20
60
4220 G13
4220 G14
4220 G15
GATE+, GATE– Pull-Up Current vs
Temperature
15
14
13
12
11
10
+
GATE
–
GATE
40
TEMPERATURE (°C)
80
–40 –20
0
20
60
4220 G16
4220f
6
LT4220
U
U
U
PI FU CTIO S
VEE (Pin 1): Negative Supply. The negative supply input
ranges from –2.7V to –16.5V for normal operation. IEE is
typically –1.6mA. An internal undervoltage lockout circuit
disablesthedeviceforinputsgreaterthan–2.45V. A10Ω,
1µFRCbypassnetworkfromVIN–totheVEE pindecouples
transients from the device.
FB– also controls the negative supply current limit sense
amplifierinputoffsettoprovidefoldbackcurrentlimit. The
FB– pin linearly reduces the negative supply sense ampli-
fier offset from –52mV to –15mV for FB– in the range
–0.75V < FB– < 0V. To disable VEE PWRGD and foldback
current limit, the FB– pin should be set to a voltage in the
range: –1.3V > FB– > VEE + 0.5V but should never be more
negative then –5.8V for normal operation.
SENSEK (Pin 2): Negative Supply Current Limit Kelvin
Sense Pin. Connect to VIN–.
ON– (Pin6):TheNegativeSupplyGoodComparatorInput.
This pin monitors the negative input voltage (VEE) with an
external resistive divider for undervoltage lockout. When
the voltage at the ON– pin is below the VON–H high-to-low
threshold (–1.24V), the negative supply is considered
good. If the ON– pin rises above –1.185V, both GATE– and
GATE+ are pulled low. If ON– is not used, the ON– pin
should be set to –1.3V > ON– > VEE + 0.5V.
SENSE– (Pin3): NegativeSupplyCurrentLimitSensePin.
A sense resistor is placed in the supply path between
SENSEKandSENSE–.Thecurrentlimitcircuitwillregulate
the voltage across the sense resistor to
–50mV (SENSEK – SENSE–) when the FB– voltage is less
–
than –0.7V. If VFB goes above –0.7V, the voltage across
the sense resistor decreases linearly and stops at –15mV
–
when VFB is 0V. If current limit is not used, connect to
SENSEK.
TRACK(Pin7):SupplyTrackingModeControl.IftheTRACK
pin is pulled high, the internal supply tracking circuit will
be enabled during start-up. The TRACK circuit monitors
the FB+ and the FB– pins to keep their magnitude within a
small voltage range by controlling the GATE+ and GATE–
charge currents. The tracking is disabled when either FB
comparator indicates the output is good. Tracking is re-
enabledifON+ ispulledbelow1.185V, ON– ispulledabove
–1.185Voreithersupplyisbelowtheinternalundervoltage
lockout. Typically, the TRACK pin is tied to GND or to VCC.
If left floating, tracking is enabled.
GATE– (Pin4):GateDrivefortheExternalNegativeSupply
N-ChannelFET. Aninternal10µAcurrentsourcedrivesthe
pin. An external capacitor connected from the GATE– pin
to VOUT– will control the rising slope of the VOUT– signal.
The voltage is clamped to 9V above VEE.
When the current limit is reached, the GATE– pin voltage
will be adjusted to maintain a constant voltage across the
RS– resistor while the timer capacitor starts to charge. If
theTIMERpinvoltageexceeds1.24V,thefaultlatchwillbe
set and both GATE– and GATE+ pins will be pulled low.
The GATE– pin is pulled to VEE whenever the ON+ pin is
below1.24V,theON– pinisabove–1.24V,oreithersupply
is in the undervoltage lockout voltage range, or the fault
latch is set by the TIMER pin rising above 1.24V.
FB– (Pin 5): Negative Power Good Comparator Input. This
pin monitors the negative output voltage (VOUT–) with an
external resistive divider. When the voltage on FB– is
below –1.24V and the initial GATE– drive voltage has
reached a maximum (indicated by setting the internal
GATE– good latch) and the FB+ release conditions are met,
thePWRGDpinisreleased.PWRGDispulledlowwhenthe
FB– pin is above –1.185V. Note the PWRGD pin is wire-
ORed with the FB+ pin conditions.
TIMER (Pin 8): Fault Time Out Control. An external timing
capacitor at this pin programs the maximum time the part
is allowed to remain in current limit before issuing a fault
and turning off the external FETs. Additionally, for
autorestart,thispincontrolsthetimebeforeanautorestart
is initiated.
When the part goes into current limit, a 65µA pull-up
currentsourcestartstochargethetimingcapacitor. When
the voltage reaches VTIMERH (1.24V), the internal fault
latchisset, FAULTpullslowandbothGATEpinsarepulled
low;thepull-upcurrentwillbeturnedoffandthecapacitor
is discharged by a 3.3µA pull-down current. When the
TIMER pin falls below 0.5V, the part is allowed to restart
if the ON+ pin is pulsed below 1.185V, thereby resetting
internal fault latch—typically done by connecting the
4220f
7
LT4220
U
U
U
PI FU CTIO S
FAULT pin to the ON+ pin, otherwise the part remains released. PWRGD is pulled low when the FB+ pin is below
latched off.
1.185V. The PWRGD pin is wire-ORed with the FB– pin
conditions.
To disable the timeout circuit breaker, connect the TIMER
pin to GND.
FB+ also controls the positive current limit sense amplifier
input offset to provide foldback current limit. The FB+ pin
linearly reduces the positive sense amplifier offset from
48mV to 15mV for FB+ in the range 0.85V > FB+ > 0V. If
PWRGD and foldback current limit are not used, the FB+
pin should be set to a voltage in the range of 1.3V < FB+ <
VCC + 0.3V.
GATE+ (Pin 14): High Side Gate Drive for the External
Positive Supply N-Channel FET. An internal charge pump
guarantees at least 3.5V above VCC, for supply voltages at
±2.7Vincreasingtoaminimumof5VaboveVCC forsupply
voltages greater than ±5V. A 10µA pull-up current source
drives the pin. An external capacitor connected from the
GATE+ pintoGNDwillcontroltherisingslopeoftheGATE+
signal. The voltage is clamped to 7V above VCC.
When the current limit is reached, the GATE+ pin voltage
will be adjusted to maintain a constant voltage across the
RS+ resistor while the timer capacitor starts to charge. If
the TIMER pin voltage exceeds 1.24V, the GATE+ pin will
be pulled low.
The GATE+ pin is pulled to GND whenever the ON+ pin is
below 1.24V, the ON– pin is above –1.24V, either supply is
in the undervoltage lockout voltage range, or the TIMER
pin rises above 1.24V.
GND (Pin 9): Supply Ground Pin.
PWRGD(Pin10):Open-CollectorOutputtoGND. PWRGD
goes to high impedance after the initial GATE– and final
GATE+ pins havereachedtheirmaximumvoltageandafter
the FB+ pin goes above 1.24V low-to-high threshold and
after the FB– pin falls below –1.24V high-to-low threshold.
An external pull-up resistor can pull the pin to a voltage
higher or lower than VCC. If not used, PWRGD can be left
floating or tied to GND.
FAULT (Pin 11): Open-Collector Output to GND. The
FAULT pin is pulled low whenever the TIMER pin rises
above VTIMERH (1.24V) threshold, thereby setting the
internalfaultlatch.Itgoestohighimpedancewheneverthe
internal fault latch is reset. The fault latch is reset with
either internal undervoltage lockout conditions, or by the
ON comparators if the TIMER pin is also below 0.5V. If not
used, the FAULT pin can be left floating or tied to GND.
ON+ (Pin 12): Positive Supply Good Comparator Input. It
monitors the positive input voltage (VCC) with an external
resistive divider for undervoltage lockout. When the volt-
age on ON+ is above the VON+H high-to-low threshold
(1.24V) the positive supply is considered good. If ON+
drops below 1.185V, both GATE– and GATE+ are pulled
low.
If ON+ is pulled low after a current limit fault and when the
TIMER pin is below 0.5V, the fault latch is reset allowing
the part to turn back on. Typically the FAULT pin is tied
back to the ON+ pin for autorestart. If not used, the ON+ pin
should be set to a voltage in the range of 1.3V < ON+ < VCC
+0.3V.TheON+ pinrequiresabypasscapacitorconnected
to ground.
SENSE+ (Pin15):PositiveSupplyCurrentLimitSensePin.
A sense resistor must be placed in the supply path be-
tween VCC and SENSE+. The current limit circuit will
regulate the voltage across the sense resistor to 50mV
(VCC – SENSE+) when the FB+ voltage is greater than
+
0.85V. If VFB goes below 0.85V, the voltage across the
senseresistordecreaseslinearlyandstopsat 15mVwhen
+
VFB is 0V.
VCC (Pin 16): Positive Supply. The positive supply input
ranges from 2.7V to 16.5V for normal operation. ICC is
typically 2.7mA. An internal undervoltage lockout circuit
disables the chip for inputs less than 2.45V. Place a 0.1µF
bypass capacitor next to the VCC pin.
FB+ (Pin13):PositivePowerGoodComparatorInput.This
pin monitors the positive output voltage (VOUT+) with an
external resistor divider. When the voltage on FB+ is above
the VFB+H low-to-high threshold (1.24V) and the GATE+
drive voltage has reached a maximum, the PWRGD is
4220f
8
LT4220
W
BLOCK DIAGRA
V
CC
CURRENT LIMIT
60µA
3µA
FROM SENSE AMPS
TIMER AND LOGIC
+
I
LIM
FAULT
S Q
R
R Q
TIMER
8
1.24V
–
FAULT
11
FAULT
LATCH
+
–
0.5V
1.24V
+
+
ON
ON
PUMP
12
–
10µA
–
ON
+
GATE
14
15
V
CC
+
–
6
+
GATE ON
+
UVLO
AND
–1.24V
FB
–
V
EE
CC
V
GOOD
+
+
SENSE
–
53mV
1.24V
+
+
+
–
FB
13
TRACK
EN
–
PWRGD
10
P GATE
GOOD
S Q
V
CC
–
FB
Q
R
ON
10µA
5
+
–
GATE GOOD
LATCHES
–
GATE
4
2
+
–
–1.24V
N GATE
GOOD
S Q
R Q
S Q
R Q
SENSEK
+
–
52mV
TOFF
–
SENSE
3
WEAK DIODES
TRACK OFF
LATCH
V
V
CC
GND
1
9
16
EE
TRACK
7
4220 BD
V
CC
SUBSTRATE
4220f
9
LT4220
W U
W
TI I G DIAGRA S
+
+
1V
FB
1V
1V
1V
ON
100mV
t
100mV
t
0V
0V
+
+
+
+
t
t
PLHFB
PLHON
PHLON
PHLFB
PWRGD
0V
+
2.5V
10V
0.5V
2.5V
GATE
0V
4220 F01
4220 F02
Figure 1. ON+-to-GATE+ Timing
Figure 2. FB+-to-PWRGD Timing
0V
0V
–
–
ON
–1V
–1V
FB
–1V
–1V
–
–
–
–
t
t
t
t
PLHON
PHLON
PLHFB
PHLFB
V
EE
+ 3.5V
–
GATE
PWRGD
0V
2.5V
2.5V
V
EE
+ 1.2V
V
EE
4220 F03
4220 F04
Figure 3. ON–-to-GATE– Timing
Figure 4. FB–-to-PWRGD Timing
100mV
0V
+
–
50mV
–50mV
V
CC
– SENSE
V
EE
– SENSE
0V
–100mV
+
–
t
t
SENSE
SENSE
10V
+
–
GATE
GATE
–2V
0V
V
EE
4220 F05
4220 F06
Figure 5. SENSE+-to-GATE+ Timing
Figure 6. SENSE–-to-GATE– Timing
W U U
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APPLICATIO S I FOR ATIO
Hot Circuit Insertion
The dual power supply on the circuit board is controlled
with two external N-channel pass transistors Q1 and Q2 in
When circuit boards are inserted into a live backplane, the
circuit board bypass capacitors can draw large peak
currents from the backplane power bus as they charge up.
The LT4220 is designed to turn on a board’s ±V dual
supplies in a controlled manner, allowing the circuit board
tobesafelyinsertedorremovedfromalivebackplane.The
part provides supply tracking as well as undervoltage and
overcurrent protection. Power good and fault output sig-
nals indicate, respectively, if both power output voltages
are ready or if an overcurrent time-out fault has occurred.
+
the ±V dual power supply path. The sense resistors RS
and RS– provide current detection while capacitor C1 and
C2 control the VOUT+ and VOUT– slew rate. Optionally, the
TRACK pin can be tied to VCC enabling the dual output
voltages to ramp up together by tracking the voltages at
the FB+ and FB– pins. Resistors R6 and R8 provide current
control loop compensation while R5 and R7 prevent high
frequency oscillations in Q1 and Q2. C3 and R8 on Q2
prevent fast dV/dt transients from turning Q2 on during
4220f
10
LT4220
W U U
APPLICATIO S I FOR ATIO
U
live insertion. Resistive dividers R1, R2 and R3, R4 pro-
vide undervoltage sensing. Resistor dividers R9, R10 and
R11, R12 provide a power good signal and control output
voltage tracking when TRACK is enabled.
Initial Power-Up Sequence
Afterthepowerpinsfirstmakecontact, transistorsQ1and
Q2 remain off. If the voltage at the ON+ and ON– pins
exceed the turn-on threshold voltage, the internal voltage
on the VCC and VEE power pins exceed the undervoltage
lockout threshold, and the timer pin voltage is less than
1.24V, the gate drive to transistors Q1 and Q2 will be
turned on. The voltage on the GATE+ and GATE– pins will
be regulated to control the inrush current if the voltage
Internal Supply Diodes
The LT4220 contains two internal diodes which clamp VEE
and VCC with respect to GND in the event either supply pin
is floating. VEE is clamped one diode above GND and VCC
is clamped one diode below GND. The current through
these diodes are designed to handle 10mA internal device
current and should not be used for high load current
conditions.
+
–
across RS or RS exceeds the sense amplifier current
limitthreshold. Ifsupplytrackingisenabled, eachgatewill
also be regulated to keep the magnitudes at the FB+ and
FB– pins within 50mV of each other.
STAGGERED
BACKPLANE
CONNECTOR
PCB EDGE
CONNECTOR
+
R
S
+
Q1
V
IN
V
CC
V
OUT
+
R13
+
10Ω
C1
10nF
CL1
R5
10Ω
R6
1k
Z1*
C4
100nF
D1
IN4001
7
16
15
SENSE
14
GATE
PWRGD
+
+
R1
R2
CONNECT FOR
AUTO RESTART
V
TRACK
CC
10
13
R9
R16, 20k
12
+
ON
+
FB
11
8
FAULT
TIMER
C7
C8
R10
R12
GND
C6
LT4220
1µF
9
6
ESD
GND
CONTROL
5
–
R4
R3
FB
–
R11
ON
D2
IN4001
–
–
V
EE
SENSEK SENSE
GATE
C2
10nF
1
2
3
4
R8
1k
C5
1µF
C3
100nF
+
R7
10Ω
CL2
Z2*
R14
10Ω
–
–
R
S
V
IN
V
EE
V
–
OUT
Q2
4220 F07
*TRANSIENT VOLTAGE SUPPRESSOR
GND MUST CONNECT FIRST
Figure 7. Hot Swap Controller on Daughter Board with Tracking Disabled
4220f
11
LT4220
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APPLICATIO S I FOR ATIO
Whenever the output voltages reach their final value as
sensedbyR9, R10andR11, R12andbothgatesignalsare
fully on, the PWRGD pin will go high impedance.
parators indicate the output is good, the PWRGD pin
output goes high impedance and is pulled up by an
external pullup resistor.
A typical timing sequence is shown in Figure 8 with
tracking enabled. The sequence is as follows:
Power Supply Ramping
Forlargecapacitiveloads,theinrushcurrentwillbelimited
by the VOUT+ and VOUT– slew rate or by the fold-back
current limit. For a desired inrush current that is less than
the fold-back current limit, the feedback networks R6, C1
and R8, C2 can be used to control the VOUT slew rate. For
thedesiredinrushcurrentandtypicalgatepull-upcurrent,
the feedback network capacitors C1 and C2 can be calcu-
lated as:
1) The power pins make contact and the undervoltage
lockout thresholds are exceeded.
2) The ON comparator thresholds are exceeded and the
GATE pins start ramping up. VOUT+ follows GATE+ by
the N-channel FET threshold voltage.
3) GATE+ is limited by the tracking circuit because VOUT
–
lags behindVOUT+.WhenVOUT–startsramping,GATE–
holds at approximately the threshold voltage of the
N-channel FET due to C2 slew rate control.
C1 = (10µA • CL1)/IINRUSH+ and
(1)
C2 = (10µA • CL2)/IINRUSH
–
(2)
4) When the magnitude of VOUT– catches up with VOUT+,
GATE+ resumes ramping. The slowest VOUT will limit
the faster VOUT slew rate.
5) GATE+ internal gate good signal threshold is reached.
6) GATE– internal gate good signal threshold is reached,
enabling the FB output comparators. If both FB com-
where CL1 and CL2 are the positive and negative output
load capacitance. If the supply-tracking mode is enabled
(TRACK = High), during startup, the output with the
slowest slew rate will also limit the slew rate of the
opposite output (Note: Supply-tracking is also controlled
by the resistive dividers on the FB pins. See Supply
Tracking). Additionally, C1 and C2 should be greater than
5nF to prevent large overshoot in the output voltage for
transient loads with small capacitive loads.
1 2
3
4
5
6
V
CC
+UVLO
–UVLO
Capacitor C3 and resistor R8 prevent Q2 from momen-
tarily turning on when the power pins first make contact.
Without C3, capacitor C2 and CGD(Q2) would hold the gate
of Q2 near ground before the LT4220 could power up and
pull the gate low. The minimum required value of C3 can
be calculated by:
V
EE
+
ON
–
ON
+
GATE
VEE − VTH
V
+
–
OUT
C3 =
(CGD(Q2) + C2) •1.2
(3)
VTH
GATE
V
–
where VTH is the MOSFET’s minimum gate threshold and
VEEMAX is the maximum negative supply input voltage. If
C2 is not used, the minimum value for C3 should be 10nF
to ensure stability. C2 and C3 must be the same type to
ensure tracking over temperature.
OUT
PWRGD
4220 F08
Figure 8. Typical Timing Sequence
4220f
12
LT4220
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APPLICATIO S I FOR ATIO
Current Limit/Electronic Circuit Breaker
faultlatchisset, theLT4220canberestartedbypullingthe
ON+ pin low after the TIMER pin falls below 0.5V. The
LT4220 can also be restarted by cycling either supply
beyond its UVLO. Otherwise the part remains latched off.
The LT4220 features foldback current limit with an elec-
tronic circuit breaker that protects against short-circuits
or excessive supply currents. The current limit is set by
placing sense resistors between VCC (Pin 16) and SENSE+ For autorestart, the FAULT pin can be tied to the ON+ pin.
(Pin15)andbetweenSENSEK(Pin2)andSENSE–(Pin3). The autorestart will occur after the TIMER pin falls below
An adjustable timer will trip an electronic circuit breaker if 0.5V.
the part remains in current limit for too long.
Undervoltage Detection
TheON+andON–pinscanbeusedtodetectanundervoltage
To prevent excessive power dissipation in the pass tran-
sistors and to prevent voltage spikes on the input supply
condition at the power supply inputs. The ON+ and ON–
during overcurrent conditions at the output, the current
pins are connected to analog comparators with 50mV of
hysteresis. If the ON+ pin falls below its threshold voltage
or the ON– pin rises above its threshold voltage, the GATE
pinsarepulledlowandheldlowuntiltheON+ andON– pins
exceed their turn-on thresholds (1.24V and –1.24V). Ex-
ternal capacitance at the ON pins may be required to filter
supply ringing from crossing the ON comparator thresh-
old.
folds back as a function of the output voltage, which is
sensedatthefeedbackpinsFB+andFB– .Whenthevoltage
at the FB+ (or FB–) pin is 0V, the sense amplifier offset is
15mV (–15mV), and limits the current to ILIMIT = 15mV/
+
–
RS (–15mV/RS ). As the output voltage increases, the
sense amplifier offset increases until the FB+ (or FB–)
voltage reaches 0.85V (–0.75V), At which point the cur-
+
rent limit reaches a maximum of ILIMIT = 48mV/RS
–
(–52mV/RS ).
Additionally there is an internal undervoltage lockout on
both supplies of approximately VCC < 2.45V and VEE
>
Timer Function and Autorestart
–2.45V. If either supply is in UVLO, both GATE pins will be
The TIMER pin (Pin 8) provides a method for setting the pulled low and all internal latches will be reset.
maximumtimetheLT4220isallowedtooperateincurrent
ON– Protection
limit. When the current limit circuitry is not active, the
If the ON– pin is driven directly and not connected to the
negative supply through a resistor divider, a 10k resistor
must be connected between the driver and the ON– pin.
TIMER pin is pulled to GND by a 3.3µA current sink.
Whenever the current limit circuit becomes active, by
either a positive or negative sense amplifier operating in
current limit, a 65µA pull-up current source is connected
to the TIMER pin and the voltage rises with a slope equal
to dV/dt = 65µA/CTIMER. The desired current limit time (t)
can be set with a capacitor value of:
Power Good Detection
The LT4220 includes two comparators for monitoring the
output voltages. The FB+ and the FB– pins are compared
against1.24Vand–1.24Vinternalreferencesrespectively.
The comparators exhibit 50mV of hysteresis. The com-
paratoroutputsarewire-ORedtotheopencollectorPWRGD
pin that is enabled once both GATE+ and GATE– pins have
reached their maximum gate drive voltage as indicated by
the internal gate good latches. The PWRGD pin goes high
impedance when both FB+ and FB– inputs exceed VFB+H
and VFB–H thresholds, GATE+ is fully on and Gate– initially
has been fully on.
CTIMER = t • 65µA/1.24V
(4)
If the current limit circuit turns off, the TIMER pin will be
discharged to GND at a rate of:
dV/dt = 3.3µA/CTIMER
(5)
Whenever the TIMER pin ramps up and reaches the 1.24V
threshold, the internal fault latch is set and the FAULT pin
(Pin 11) is pulled low. GATE+ is pulled down to ground,
GATE– is pulled down to VEE, and the TIMER pin starts
ramping back to GND by the 3.3µA current sink. After the
4220f
13
LT4220
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APPLICATIO S I FOR ATIO
Supply Tracking
ON+, ON– Bypass Capacitors
If the TRACK pin (Pin 7) is high the supply power-up
tracking mode is enabled. This feature forces both sup-
plies to reach their final value at the same time, during
power-up and for faults that drive the output supplies to
zero. During this mode the GATE pins are controlled to
keep the differential magnitude of the FB pins to within
50mV. The FB pins are scaled versions of the output
voltages. Therefore, control of the FB pins, via the GATE
pins, will control the output voltages at the same scale.
Bypass capacitors are required from ON+ to ground and
ON– to ground. A typical time constant is:
TC (ON+) = (R1||R2)C7 = 44µs
TC (ON–) = (R3||R4)C8 = 44µs
Supply Ringing
Normal circuit design practice calls for capacitive bypass-
ing of the input supply to active devices. The opposite is
true for Hot Swap circuits that are connected into a
backplane, where capacitive loading would cause tran-
sients during an abrupt connection to the backplane. With
little or no capacitive decoupling on the powered side of
the N-channel FETs, connection transients or load tran-
sients will typically cause ringing on the supply leads due
to parasitic inductance. It is recommended to use a
snubber circuit comprising of a series 10Ω and 0.1µF
capacitor to dampen transient ringing. The supply
decoupling circuit on the VEE pin also provides a snubber
for VIN–.
–
|∆VFB(TRK)| = |VFB+ – VFB
|
(6)
Supply tracking will continue until: either FB pin reaches
the associated PWRGD threshold. If any fault condition
occursthatturnstheGATEpinsoff, supplytrackingwillbe
reenabled. The GATE off conditions include: (1) either ON
pin detects undervoltage, (2) internal undervoltage lock-
out, (3) the fault latch is set by a current limit time-out.
VEE Bypassing
The VEE supply pin should be filtered with an RC network
to reduce high dV/dt slew rates from disturbing internal
circuits. Typical RC bypassing sufficient to prevent circuit
misbehavior is R14 = 10Ω and C5 = 1µF. The GATE–,
SENSEK and SENSE– pins have been designed such that
they can be pulled below or above VEE for short periods of
time while the VEE pin is reaching its steady state voltage.
If desired, a higher R14 • C5 time constant may be used to
prevent short circuit transients from tripping the VEE
undervoltage lockout circuit at –2.45V. R14 should be
sufficient to decouple C5 from causing transients on VIN–
during live insertion.
Additionally, if the supply voltage overshoot can exceed
the ±22V maximum rating on the part, a transient voltage
suppressor is recommended. Voltage transients can oc-
cur during load short-circuit conditions, where parasitic
inductance in the supply leads can build up energy before
the external N-channel FET can be turned off. This is
especially true for the negative side FET where a large C3
value slows the turn off of the N-channel FET. Subsequent
overshoot when the FET is finally turned off can be as
much as 2× the supply voltage even with the snubber
circuit. Additional protection using a transient suppressor
may be needed to prevent exceeding the maximum supply
voltage rating.
Under the condition of a short circuit on VOUT–, parasitic
inductance and resistance in the VIN– path will cause VIN–
to collapse toward 0V causing the VEE pin voltage to also
dischargetoward0VbeforetheexternalFETcanbeturned
off (typically 7µs to 10µs). To prevent a UVLO condition
from occurring, the R14 • C5 time constant should be
sufficient to hold the VEE pin voltage out of the VEE UVLO
voltage range. If the VEE pin reaches its UVLO voltage,
GATE+ will also be pulled low. For the case where C3 is
large, causing an even slower N-channel FET turnoff,
higherRCbypassingmaybenecessarytopreventtripping
the VEE UVLO.
Supply Reversal Protection
A variety of conditions on VOUT+ and VOUT– may result in
supply reversal. To protect devices connected to VOUT
+
and VOUT– protection diodes should be used. 1N4001
diodes can be used for most aplications. Connection of
these diodes (D1, D2) are shown in the front page Typical
Application.
4220f
14
LT4220
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
4220f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
15
LT4220
U
TYPICAL APPLICATIO
STAGGERED
PCB EDGE
CONNECTOR
BACKPLANE
CONNECTOR
Q1
+
POWER GOOD
R
S
SUB85N03-04
V
V
CC
OUT+
R13
RPG
5.1k
C1
10nF
10Ω
Z1*
R5
10Ω
R6
1k
C4
100nF
7
16
15
14
+
CONNECT FOR
R9
R1
+
+
CL1
V
SENSE
GATE
PWRGD
AUTO RESTART
TRACK
CC
10
12
+
ON
13
5
+
FB
11
8
FAULT
TIMER
R2
R4
C7
C8
R10
R12
GND
C6
1µF
LT4220
9
6
ESD
GND
CONTROL
–
FB
–
R11
ON
+
–
–
V
EE
SENSEK SENSE
GATE
CL2
R3
C2
10nF
1
2
3
4
R8
1k
C3
100nF
R7
10Ω
C5
1µF
R14
10Ω
–
R
S
V
V
–
EE
OUT
Q2
SUB85N03-04
4220 F09
Z2*
GND MUST CONNECT FIRST
*TRANSIENT VOLTAGE SUPPRESSOR
Figure 9. Hot Swap Controller on Mainboard with Tracking
RELATED PARTS
PART NUMBER
LTC®1421
LTC1422
DESCRIPTION
COMMENTS
Dual Hot Swap Controller
Single Hot Swap Controller in SO-8
Dual Hot Swap Controller
Dual Hot Swap Controller
Two Circuit Breakers for Supplies from 3V to 12V and Supports –12V
Operates from 3V to 12V
LTC1645
Operates from 1.2V to 12V, Allows Supply Sequencing
Operates from 2.7V to 16.5V, Separate ON Pins
2.5V to 16.5V, Active Inrush Limiting, Fast Comparator
LTC1647
LTC4211
Single Hot Swap Controller with Multifunction
Current Control
LTC4230
Triple Hot Swap Controller with Multifunction
Current Control
1.7V to 16.5V, Active Inrush Limiting, Fast Comparator
4220f
LT/TP 0403 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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