LT3757IMSE [Linear]
Boost, Flyback, SEPIC and Inverting Controller; 升压,反激式, SEPIC和负输出控制器型号: | LT3757IMSE |
厂家: | Linear |
描述: | Boost, Flyback, SEPIC and Inverting Controller |
文件: | 总36页 (文件大小:396K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT3757/LT3757A
Boost, Flyback, SEPIC and
Inverting Controller
FeaTures
DescripTion
The LT®3757/LT3757A are wide input range, current
mode, DC/DC controllers which are capable of generating
either positive or negative output voltages. They can be
configured as either a boost, flyback, SEPIC or inverting
converter. The LT3757/LT3757A drive a low side external
N-channelpowerMOSFETfromaninternalregulated7.2V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.
n
Wide Input Voltage Range: 2.9V to 40V
n
Positive or Negative Output Voltage Programming
with a Single Feedback Pin
n
Current Mode Control Provides Excellent Transient
Response
n
Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
n
Synchronizable to an External Clock
n
Low Shutdown Current < 1µA
n
Internal 7.2V Low Dropout Voltage Regulator
The operating frequency of LT3757/LT3757A can be set
with an external resistor over a 100kHz to 1MHz range,
and can be synchronized to an external clock using the
SYNC pin. A low minimum operating supply voltage of
2.9V, and a low shutdown quiescent current of less than
1µA, make the LT3757/LT3757A ideally suited for battery-
operated systems.
n
Programmable Input Undervoltage Lockout with
Hysteresis
Programmable Soft-Start
n
n
Small 10-Lead DFN (3mm × 3mm) and Thermally
Enhanced 10-Pin MSOP Packages
applicaTions
The LT3757/LT3757A feature soft-start and frequency
foldbackfunctionstolimitinductorcurrentduringstart-up
and output short-circuit. The LT3757A has improved load
transient performance compared to the LT3757.
n
Automotive and Industrial Boost, Flyback, SEPIC and
Inverting Converters
n
Telecom Power Supplies
Portable Electronic Equipment
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and No R
and ThinSOT are trademarks of Linear Technology Corporation. All other
SENSE
trademarks are the property of their respective owners.
Typical applicaTion
High Efficiency Boost Converter
Efficiency
V
IN
100
90
8V TO 16V
10µF
25V
X5R
200k
V
IN
10µH
SHDN/UVLO
V
= 8V
V
24V
2A
IN
OUT
80
43.2k
V
= 16V
LT3757
IN
SYNC
GATE
70
60
50
40
30
226k
SENSE
RT
SS
+
47µF
35V
×2
FBX
GND INTV
V
C
CC
41.2k
300kHz
16.2k
22k
6.8nF
10µF
25V
X5R
4.7µF
10V
X5R
0.1µF
0.01Ω
0.001
0.1
1
10
0.01
OUTPUT CURRENT (A)
3757 TA01b
3757 TA01a
3757afd
1
LT3757/LT3757A
absoluTe MaxiMuM raTings (Note 1)
Operating Temperature Range (Notes 2, 8)
V , SHDN/UVLO (Note 6).........................................40V
IN
LT3757E/LT3757AE............................ –40°C to 125°C
LT3757I/LT3757AI ............................. –40°C to 125°C
LT3757H/LT3757AH........................... –40°C to 150°C
LT3757MP/LT3757AMP ..................... –55°C to 150°C
Storage Temperature Range
INTV ....................................................V + 0.3V, 20V
CC
IN
GATE........................................................ INTV + 0.3V
CC
SYNC ..........................................................................8V
V , SS.........................................................................3V
C
RT............................................................................1.5V
SENSE.................................................................... 0.3V
FBX ................................................................. –6V to 6V
DFN.................................................... –65°C to 125°C
MSOP ................................................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP ...............................................................300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
V
1
2
3
4
5
10
9
V
IN
C
V
FBX
SS
RT
SYNC
1
2
3
4
5
10
9
V
IN
C
FBX
SS
SHDN/UVLO
SHDN/UVLO
11
11
8
INTV
8
INTV
CC
CC
7
6
GATE
RT
7
GATE
SENSE
SYNC
6
SENSE
MSE PACKAGE
10-LEAD PLASTIC MSOP
= 150°C, θ = 40°C/W
JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
DD PACKAGE
T
JMAX
10-LEAD (3mm × 3mm) PLASTIC DFN
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LDYW
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3757EDD#PBF
LT3757EDD#TRPBF
LT3757IDD#TRPBF
LT3757EMSE#TRPBF
LT3757IMSE#TRPBF
LT3757HMSE#TRPBF
LT3757MPMSE#TRPBF
LT3757AEDD#TRPBF
LT3757AIDD#TRPBF
LT3757AEMSE#TRPBF
LT3757AIMSE#TRPBF
LT3757AHMSE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
LT3757IDD#PBF
LDYW
LT3757EMSE#PBF
LT3757IMSE#PBF
LT3757HMSE#PBF
LT3757MPMSE#PBF
LT3757AEDD#PBF
LT3757AIDD#PBF
LT3757AEMSE#PBF
LT3757AIMSE#PBF
LT3757AHMSE#PBF
LT3757AMPMSE#PBF
LTDYX
LTDYX
LTDYX
LTDYX
LGGR
LGGR
LTGGM
LTGGM
LTGGM
LT3757AMPMSE#TRPBF LTGGM
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3757afd
2
LT3757/LT3757A
elecTrical characTerisTics The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Range
2.9
40
V
IN
IN
V
Shutdown I
SHDN/UVLO = 0V
SHDN/UVLO = 1.15V
0.1
1
6
µA
µA
Q
V
V
Operating I
V = 0.3V, R = 41.2k
1.6
280
110
–65
2.2
400
120
mA
µA
IN
Q
C
T
Operating I with Internal LDO Disabled
V = 0.3V, R = 41.2k, INTV = 7.5V
C T CC
IN
Q
l
SENSE Current Limit Threshold
SENSE Input Bias Current
Error Amplifier
100
mV
µA
Current Out of Pin
l
l
FBX Regulation Voltage (V
FBX Overvoltage Lockout
FBX Pin Input Current
)
V
V
> 0V (Note 3)
< 0V (Note 3)
1.569
1.6
1.631
V
V
FBX(REG)
FBX
FBX
–0.816
–0.80
–0.784
V
V
> 0V (Note 4)
< 0V (Note 4)
6
7
8
11
10
14
%
%
FBX
FBX
V
V
= 1.6V (Note 3)
= –0.8V (Note 3)
70
100
10
nA
nA
FBX
FBX
–10
Transconductance g (∆I /∆V
FBX
)
(Note 3)
(Note 3)
230
5
µS
m
VC
V Output Impedance
C
MΩ
V
Line Regulation [∆V /(∆V • V
)]
V
V
> 0V, 2.9V < V < 40V (Notes 3, 7)
0.002
0.0025
0.056
0.05
%/V
%/V
FBX
FBX
IN
FBX(REG)
FBX
FBX
IN
< 0V, 2.9V < V < 40V (Notes 3, 7)
IN
V Current Mode Gain (∆V /∆V
)
5.5
V/V
µA
C
VC
SENSE
V Source Current
C
V
= 0V, V = 1.5V
–15
FBX
C
V Sink Current
C
V
V
= 1.7V
= –0.85V
12
11
µA
µA
FBX
FBX
Oscillator
Switching Frequency
R = 41.2k to GND, V = 1.6V
270
300
100
330
0.4
kHz
kHz
kHz
T
FBX
R = 140k to GND, V = 1.6V
T
FBX
R = 10.5k to GND, V = 1.6V
1000
T
FBX
RT Voltage
V
= 1.6V
1.2
220
220
V
ns
ns
V
FBX
Minimum Off-Time
Minimum On-Time
SYNC Input Low
SYNC Input High
SS Pull-Up Current
Low Dropout Regulator
1.5
V
SS = 0V, Current Out of Pin
–10
7.2
µA
l
INTV Regulation Voltage
7
7.4
2.8
V
CC
INTV Undervoltage Lockout Threshold
Falling INTV
2.6
2.7
0.1
V
V
CC
CC
UVLO Hysteresis
INTV Overvoltage Lockout Threshold
16
30
17.5
V
CC
INTV Current Limit
V
IN
V
IN
= 40V
= 15V
40
95
55
mA
mA
CC
INTV Load Regulation (∆V
/ V
)
0 < I
< 20mA, V = 8V
–0.9
–0.5
0.008
400
%
%/V
mV
µA
CC
INTVCC INTVCC
INTVCC
IN
INTV Line Regulation ∆V
/(V
• ∆V )
8V < V < 40V
0.03
CC
INTVCC
INTVCC
IN
IN
Dropout Voltage (V – V
)
V
IN
= 6V, I
= 20mA
INTVCC
IN
INTVCC
INTV Current in Shutdown
SHDN/UVLO = 0V, INTV = 8V
16
CC
CC
3757afd
3
LT3757/LT3757A
elecTrical characTerisTics The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INTV Voltage to Bypass Internal LDO
7.5
V
CC
Logic Inputs
l
SHDN/UVLO Threshold Voltage Falling
SHDN/UVLO Input Low Voltage
SHDN/UVLO Pin Bias Current Low
SHDN/UVLO Pin Bias Current High
Gate Driver
V
= INTV = 8V
1.17
1.7
1.22
1.27
0.4
V
V
IN
CC
I(V ) Drops Below 1µA
IN
SHDN/UVLO = 1.15V
SHDN/UVLO = 1.30V
2
2.5
µA
nA
10
100
t Gate Driver Output Rise Time
C = 3300pF (Note 5), INTV = 7.5V
22
20
ns
ns
V
r
L
CC
t Gate Driver Output Fall Time
f
C = 3300pF (Note 5), INTV = 7.5V
L CC
Gate V
Gate V
0.05
OL
OH
INTV –0.05
V
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LT3757/LT3757A are tested in a feedback loop which servos
to the reference voltages (1.6V and –0.8V) with the V pin forced
to 1.3V.
V
FBX
C
Note 4: FBX overvoltage lockout is measured at V
relative
FBX(OVERVOLTAGE)
Note 2: The LT3757E/LT3757AE are guaranteed to meet performance
specifications from the 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LT3757I/LT3757AI are guaranteed over the full –40°C to
125°C operating junction temperature range. The LT3757H/LT3757AH are
guaranteed over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes. Operating
lifetime is derated at junction temperatures greater than 125°C. The
LT3757MP/LT3757AMP are 100% tested and guaranteed over the full
–55°C to 150°C operating junction temperature range.
to regulated V
.
FBX(REG)
Note 5: Rise and fall times are measured at 10% and 90% levels.
Note 6: For V below 6V, the SHDN/UVLO pin must not exceed V .
IN
IN
Note 7: SHDN/UVLO = 1.33V when V = 2.9V.
IN
Note 8: The LT3757/LT3757A include overtemperature protection that
is intended to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating junction
temperature when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
Quiescent Current
vs Temperature, VIN
1605
1600
1595
1590
1585
1580
–788
–790
–792
–794
–796
–798
–800
–802
–804
1.8
1.7
1.6
1.5
1.4
V
= 40V
V
= INTV = 2.9V
CC
IN
IN
SHDN/UVLO = 1.33V
V
= 24V
IN
V
= 40V
IN
V
= 24V
IN
V
= 8V
IN
V
= 8V
IN
V = 40V
IN
V
= INTV = 2.9V
IN
CC
SHDN/UVLO = 1.33V
V
IN
= 24V
V
= INTV = 2.9V
CC
IN
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3757 G01
3757 G02
3757 G03
3757afd
4
LT3757/LT3757A
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Dynamic Quiescent Current
Normalized Switching Frequency
vs FBX
vs Switching Frequency
RT vs Switching Frequency
35
30
25
20
15
10
5
1000
120
100
80
60
40
20
0
C
= 3300pF
L
100
0
10
–0.8
0
0.4
FBX VOLTAGE (V)
0.8
1.2
1.6
0
300
400 500 600 700 800 900 1000
0
300 400 500 600 700 800 900 1000
–0.4
100 200
100 200
SWITCHING FREQUENCY (KHz)
SWITCHING FREQUENCY (KHz)
3757 G04
3757 G05
3757 G06
Switching Frequency
vs Temperature
SENSE Current Limit Threshold
vs Temperature
SENSE Current Limit Threshold
vs Duty Cycle
330
320
310
300
290
280
270
120
115
110
105
100
115
110
105
100
95
R
= 41.2K
T
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
DUTY CYCLE (%)
3757 G07
3757 G08
3757 G09
SHDN/UVLO Threshold
vs Temperature
SHDN/UVLO Hysteresis Current
vs Temperature
SHDN/UVLO Current vs Voltage
1.28
1.26
1.24
1.22
1.20
1.18
2.4
2.2
2.0
1.8
1.6
40
30
20
10
0
SHDN/UVLO RISING
SHDN/UVLO FALLING
–75 –50 –25
0
25 50 75 100 125 150
0
10
20
30
40
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
SHDN/UVLO VOLTAGE (V)
TEMPERATURE (°C)
3757 G10
3757 G12
3757 G11
3757afd
5
LT3757/LT3757A
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
INTVCC Minimum Output Current
vs VIN
INTVCC vs Temperature
INTVCC Load Regulation
7.4
7.3
7.2
7.1
7.0
90
80
70
60
50
40
30
20
10
0
7.3
7.2
T = 150°C
J
V
= 8V
IN
7.1
7
INTV = 6V
CC
INTV = 4.5V
CC
6.9
6.8
0
5
10 15 20 25 30 35 40
–75 –50 –25
0
25 50 75 100 125 150
0
20
30
40
50
60
70
10
TEMPERATURE (°C)
V
(V)
INTV LOAD (mA)
IN
CC
3757 G13
3757 G14
3757 G15
INTVCC Dropout Voltage
vs Current, Temperature
Gate Drive Rise
INTVCC Line Regulation
and Fall Time vs CL
700
600
500
400
300
200
100
0
7.30
7.25
7.20
7.15
7.10
90
80
70
60
50
40
30
20
10
0
V
= 6V
IN
150°C
INTV = 7.2V
CC
125°C
75°C
25°C
RISE TIME
FALL TIME
0°C
–55°C
10
15
20
0
5
0
5
10
15
(nF)
20
25
30
25 30
40
0
5
10 15 20
(V)
35
INTV LOAD (mA)
CC
C
V
L
IN
3757 G16
3757 G17
3757 G18
Gate Drive Rise
and Fall Time vs INTVCC
FBX Frequency Foldback
Waveforms During Overcurrent
Typical Start-Up Waveforms
30
25
20
15
10
5
V
= 12V
C
= 3300pF
V = 12V
IN
V
IN
L
OUT
10V/DIV
RISE TIME
V
SW
V
20V/DIV
OUT
FALL TIME
5V/DIV
I
+ I
L1A L1B
I
+ I
5A/DIV
L1A L1B
5A/DIV
3757 G20
3757 G21
2ms/DIV
50µs/DIV
PAGE 31 CIRCUIT
PAGE 31 CIRCUIT
0
9
12
15
3
6
INTV (V)
CC
3757 G19
3757afd
6
LT3757/LT3757A
pin FuncTions
V (Pin 1): Error Amplifier Compensation Pin. Used to
GATE (Pin 7): N-Channel MOSFET Gate Driver Output.
C
stabilize the voltage loop with an external RC network.
Switches between INTV and GND. Driven to GND when
CC
IC is shut down, during thermal lockout or when INTV
CC
FBX(Pin2):PositiveandNegativeFeedbackPin.Receives
the feedback voltage from the external resistor divider
across the output. Also modulates the frequency during
start-up and fault conditions when FBX is close to GND.
is above or below the OV or UV thresholds, respectively.
INTV (Pin 8): Regulated Supply for Internal Loads and
CC
GateDriver. SuppliedfromV andregulatedto7.2V(typi-
IN
cal). INTV must be bypassed with a minimum of 4.7µF
CC
SS(Pin3):Soft-StartPin.Thispinmodulatescompensation
capacitor placed close to pin. INTV can be connected
CC
pin voltage (V ) clamp. The soft-start interval is set with
C
directly to V , if V is less than 17.5V. INTV can also
IN
IN
CC
an external capacitor. The pin has a 10µA (typical) pull-up
current source to an internal 2.5V rail. The soft-start pin
is reset to GND by an undervoltage condition at SHDN/
be connected to a power supply whose voltage is higher
than 7.5V, and lower than V , provided that supply does
IN
not exceed 17.5V.
UVLO, an INTV undervoltage or overvoltage condition
CC
or an internal thermal lockout.
SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
is okayto enable switching. Rising hysteresisis generated
by the external resistor divider and an accurate internal
2µA pull-down current. An undervoltage condition resets
sort-start. Tie to 0.4V, or less, to disable the device and
RT (Pin 4): Switching Frequency Adjustment Pin. Set the
frequency using a resistor to GND. Do not leave this pin
open.
SYNC (Pin 5): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an R resistor should be chosen to
reduce V quiescent current below 1µA.
T
IN
programaswitchingfrequency20%slowerthantheSYNC
pulse frequency. Tie the SYNC pin to GND if this feature
is not used. SYNC is ignored when FBX is close to GND.
V (Pin 10): Input Supply Pin. Must be locally bypassed
IN
with a 0.22µF, or larger, capacitor placed close to the pin.
ExposedPad(Pin11):Ground. Thispinalsoservesasthe
negativeterminalofthecurrentsenseresistor.TheExposed
Pad must be soldered directly to the local ground plane.
SENSE (Pin 6): The Current Sense Input for the Control
Loop. Kelvin connect this pin to the positive terminal of
the switch current sense resistor in the source of the
N-channel MOSFET. The negative terminal of the current
sense resistor should be connected to GND plane close
to the IC.
3757afd
7
LT3757/LT3757A
block DiagraM
C
DC
L1
D1
V
IN
V
OUT
+
R4
R3
C
IN
C
L2
OUT2
R2
R1
+
•
FBX
C
OUT1
9
10
V
IN
SHDN/UVLO
A10
–
+
I
S1
2.5V
2µA
1.22V
2.5V
INTERNAL
REGULATOR
AND UVLO
I
S3
CURRENT
LIMIT
I
S2
17.5V
V
C
10µA
+
–
UVLO
A9
1
7.2V LDO
INTV
Q3
CC
C
VCC
8
7
G4
G3
A8
C
R
C2
C
+
–
2.7V UP
C
A11
A12
C1
1.72V
2.6V DOWN
–
+
TSD
165˚C
DRIVER
G6
SR1
VC –
GATE
–
+
G5
G2
A7
R
O
M1
+
–0.88V
S
Q2
PWM
COMPARATOR
108mV
–
+
1.6V
+
–
A6
A5
A1
SLOPE
RAMP
V
ISENSE
FBX
SENSE
FBX
2
6
+
–
+
–
RAMP
A2
R
SENSE
GND
–0.8V
GENERATOR
1.25V
–
+
11
A3
100kHz-1MHz
OSCILLATOR
G1
1.25V
FREQ
FOLDBACK
+
FREQUENCY
FOLDBACK
+
A4
Q1
–
R5
8k
FREQ
PROG
D3
D2
SS
3
SYNC
RT
5
4
3757 F01
C
R
T
SS
Figure 1. LT3757 Block Diagram Working as a SEPIC Converter
3757afd
8
LT3757/LT3757A
applicaTions inForMaTion
Main Control Loop
comparator A2 performs the noninverting amplification
from FBX to V .
C
The LT3757 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation. Op-
eration can be best understood by referring to the Block
Diagram in Figure 1.
The LT3757 has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
ThestartofeachoscillatorcyclesetstheSRlatch(SR1)and
turns on the external power MOSFET switch M1 through
driver G2. The switch current flows through the external
current sensing resistor R
and generates a voltage
SENSE
proportional to the switch current. This current sense
voltage V (amplified by A5) is added to a stabilizing
ISENSE
slope compensation ramp and the resulting sum (SLOPE)
isfedintothepositiveterminalofthePWM comparatorA7.
When SLOPE exceeds the level at the negative input of A7
(V pin), SR1 is reset, turning off the power switch. The
C
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
Programming Turn-On and Turn-Off Thresholds with
the SHDN/UVLO Pin
The SHDN/UVLO pin controls whether the LT3757 is
enabled or is in shutdown state. A micropower 1.22V
reference, a comparator A10 and a controllable current
sourceI allowtheusertoaccuratelyprogramthesupply
S1
TheLT3757hasaswitchcurrentlimitfunction.Thecurrent
sense voltage is input to the current limit comparator A6.
If the SENSE pin voltage is higher than the sense current
voltage at which the IC turns on and off. The falling value
can be accurately set by the resistor dividers R3 and R4.
When SHDN/UVLO is above 0.7V, and below the 1.22V
limitthresholdV
(110mV, typical), A6willreset
SENSE(MAX)
SR1 and turn off M1 immediately.
threshold, the small pull-down current source I (typical
S1
2µA) is active.
The LT3757 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost, flyback or SEPIC converter to gen-
erate positive output voltage, or as an inverting converter
to generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
The purpose of this current is to allow the user to program
therisinghysteresis.TheBlockDiagramofthecomparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
(R3+ R4)
VVIN,FALLING = 1.22•
R4
VVIN,RISING = 2µA •R3+ VIN,FALLING
age divider (R1 and R2) connected from V
to GND.
OUT
Comparator A2 becomes inactive and comparator A1
performstheinvertingamplificationfromFBXtoV .When
C
For applications where the SHDN/UVLO pin is only used
as a logic input, the SHDN/UVLO pin can be connected
the LT3757 is in an inverting configuration, the FBX pin
is pulled down to –0.8V by a voltage divider connected
directly to the input voltage V for always-on operation.
from V
to GND. Comparator A1 becomes inactive and
IN
OUT
3757afd
9
LT3757/LT3757A
applicaTions inForMaTion
INTV Regulator Bypassing and Operation
The LT3757 uses packages with an Exposed Pad for en-
hanced thermal conduction. With proper soldering to the
Exposed Pad on the underside of the package and a full
copper plane underneath the device, thermal resistance
CC
Aninternal,lowdropout(LDO)voltageregulatorproduces
the 7.2V INTV supply which powers the gate driver,
CC
as shown in Figure 1. If a low input voltage operation is
expected(e.g.,supplyingpowerfromalithium-ionbattery
or a 3.3V logic supply), low threshold MOSFETs should
be used. The LT3757 contains an undervoltage lockout
comparator A8 and an overvoltage lockout comparator
(θ )willbeabout43°C/WfortheDDpackageand40°C/W
JA
fortheMSEpackage. Foranambientboardtemperatureof
T = 70°C and maximum junction temperature of 125°C,
A
the maximum I
be calculated as:
(I
) of the DD package can
DRIVE DRIVE(MAX)
A9 for the INTV supply. The INTV undervoltage (UV)
CC
CC
threshold is 2.7V (typical), with 100mV hysteresis, to
ensurethattheMOSFETshavesufficientgatedrivevoltage
before turning on. The logic circuitry within the LT3757 is
(TJ − TA)
(θJA • VIN)
1.28W
VIN
IDRIVE(MAX)
=
− IQ =
− 1.6mA
The LT3757 has an internal INTV
I
current limit
CC DRIVE
also powered from the internal INTV supply.
CC
function to protect the IC from excessive on-chip power
The INTV overvoltage (OV) threshold is set to be 17.5V
CC
dissipation. The I
current limit decreases as the V
DRIVE
IN
IN
(typical) to protect the gate of the power MOSFET. When
increases(seetheINTV MinimumOutputCurrentvsV
CC
INTV is below the UV threshold, or above the OV thresh-
CC
graphintheTypicalPerformanceCharacteristicssection).
If I reaches the current limit, INTV voltage will fall
old, the GATE pin will be forced to GND and the soft-start
DRIVE
CC
operation will be triggered.
and may trigger the soft-start.
The INTV regulator must be bypassed to ground imme-
CC
BasedontheprecedingequationandtheINTV Minimum
CC
diatelyadjacenttotheICpinswithaminimumof4.7µFcera-
mic capacitor. Good bypassing is necessary to supply the
hightransientcurrentsrequiredbytheMOSFETgatedriver.
Output Current vs V graph, the user can calculate the
IN
maximum MOSFET gate charge the LT3757 can drive at
a given V and switch frequency. A plot of the maximum
IN
Q vs V at different frequencies to guarantee a minimum
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
Theon-chippowerdissipationcanbeasignificantconcern
when a large power MOSFET is being driven at a high fre-
G
IN
4.5V INTV is shown in Figure 2.
CC
AsillustratedinFigure2, atrade-offbetweentheoperating
frequencyandthesizeofthepowerMOSFETmaybeneeded
in order to maintain a reliable IC junction temperature.
quency and the V voltage is high. It is important to limit
IN
the power dissipation through selection of MOSFET and/
or operating frequency so the LT3757 does not exceed its
maximum junction temperature rating. The junction tem-
300
peratureT canbeestimatedusingthefollowingequations:
250
J
300kHz
T = T + P • θ
JA
J
A
IC
200
T = ambient temperature
A
150
θ
= junction-to-ambient thermal resistance
JA
100
P = IC power consumption
1MHz
IC
50
0
= V • (I + I )
DRIVE
IN
Q
I = V operation I = 1.6mA
Q
IN
Q
10 15 20 25 30 35 40
(V)
0
5
V
IN
I
= average gate drive current = f • Q
G
3757 F02
DRIVE
f = switching frequency
Figure 2. Recommended Maximum QG vs VIN at Different
Frequencies to Ensure INTVCC Higher Than 4.5V
Q = power MOSFET total gate charge
G
3757afd
10
LT3757/LT3757A
applicaTions inForMaTion
Prior to lowering the operating frequency, however, be
Operating Frequency and Synchronization
sure to check with power MOSFET manufacturers for their
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
operation improves efficiency by reducing gate drive cur-
rent and MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications for
loopcompensation.TheLT3757usesaconstant-frequency
architecture that can be programmed over a 100kHz to
1000kHz range with a single external resistor from the
RT pin to ground, as shown in Figure 1. The RT pin must
have an external resistor to GND for proper operation of
most recent low Q , low R
devices. Power MOSFET
G
DS(ON)
manufacturingtechnologiesarecontinuallyimproving,with
newer and better performance devices being introduced
almost yearly.
An effective approach to reduce the power consumption
of the internal LDO for gate drive is to tie the INTV pin
CC
to an external voltage source high enough to turn off the
internal LDO regulator.
If the input voltage V does not exceed the absolute
IN
maximum rating of both the power MOSFET gate-source
voltage(V )andtheINTV overvoltagelockoutthreshold
GS
CC
the LT3757. A table for selecting the value of R for a given
operating frequency is shown in Table 1.
T
voltage (17.5V), the INTV pin can be shorted directly
CC
to the V pin. In this condition, the internal LDO will be
IN
turned off and the gate driver will be powered directly
Table 1. Timing Resistor (RT) Value
from the input voltage, V . With the INTV pin shorted to
IN
CC
OSCILLATOR FREQUENCY (kHz)
R (kΩ)
T
V , however, a small current (around 16µA) will load the
IN
100
200
300
400
500
600
700
800
900
1000
140
63.4
41.2
30.9
24.3
19.6
16.5
14
INTV in shutdown mode. For applications that require
CC
the lowest shutdown mode input supply current, do not
connect the INTV pin to V .
CC
IN
In SEPIC or flyback applications, the INTV pin can be
CC
connected to the output voltage V
through a blocking
meets the following
OUT
diode, as shown in Figure 3, if V
conditions:
OUT
1. V
2. V
3. V
< V (pin voltage)
OUT
OUT
OUT
IN
12.1
10.5
< 17.5V
< maximum V rating of power MOSFET
GS
TheoperatingfrequencyoftheLT3757canbesynchronized
to an external clock source. By providing a digital clock
signal into the SYNC pin, the LT3757 will operate at the
A resistor R can be connected, as shown in Figure 3, to
VCC
limit the inrush current from V . Regardless of whether
OUT
or not the INTV pin is connected to an external voltage
CC
SYNCclockfrequency.Ifthisfeatureisused,anR resistor
T
source, it is always necessary to have the driver circuitry
bypassed with a 4.7µF low ESR ceramic capacitor to
should be chosen to program a switching frequency 20%
slowerthanSYNCpulsefrequency.TheSYNCpulseshould
have a minimum pulse width of 200ns. Tie the SYNC pin
to GND if this feature is not used.
ground immediately adjacent to the INTV and GND pins.
CC
LT3757
INTV
D
VCC
R
VCC
V
OUT
CC
C
VCC
4.7µF
GND
3757 F03
Figure 3. Connecting INTVCC to VOUT
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applicaTions inForMaTion
Duty Cycle Consideration
Soft-Start
Switching duty cycle is a key variable defining converter
operation.Assuch,itslimitsmustbeconsidered.Minimum
on-time is the smallest time duration that the LT3757 is
capable of turning on the power MOSFET. This time is
generally about 220ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3757 keeps the power switch off for at least
220ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The LT3757 contains several features to limit peak switch
currents and output voltage (V ) overshoot during
OUT
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since V
is far from its final value,
OUT
the feedback loop is saturated and the regulator tries to
chargetheoutputcapacitorasquicklyaspossible,resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
The LT3757 addresses this mechanism with the SS pin. As
shown in Figure 1, the SS pin reduces the power MOSFET
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
current by pulling down the V pin through Q2. In this
C
way the SS allows the output capacitor to charge gradu-
ally toward its final value while limiting the start-up peak
currents. The typical start-up waveforms are shown in the
Typical Performance Characteristics section. The inductor
Programming the Output Voltage
The output voltage (V ) is set by a resistor divider, as
OUT
shown in Figure 1. The positive and negative V
by the following equations:
are set
OUT
current I slewing rate is limited by the soft-start function.
L
Besides start-up, soft-start can also be triggered by the
following faults:
R2
R1
VOUT,POSITIVE = 1.6V • 1+
1. INTV > 17.5V
CC
R2
R1
VOUT,NEGATIVE = –0.8V • 1+
2. INTV < 2.6V
CC
3. Thermal lockout
The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
Any of these three faults will cause the LT3757 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10µA current source I starts
S2
In the applications where V
is pulled up by an external
OUT
charging the SS pin, initiating a soft-start operation.
positivepowersupply,theFBXpinisalsopulledupthrough
theR2andR1network.MakesuretheFBXdoesnotexceed
its absolute maximum rating (6V). The R5, D2, and D3 in
Figure 1 provide a resistive clamp in the positive direction.
To ensure FBX is lower than 6V, choose sufficiently large
R1 and R2 to meet the following condition:
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
1.25V
10µA
TSS = CSS
•
R2
R1
R2
8kΩ
6V • 1+
+ 3.5V •
> VOUT(MAX)
where V
is the maximum V
that is pulled up
OUT(MAX)
by an external power supply.
OUT
3757afd
12
LT3757/LT3757A
applicaTions inForMaTion
FBX Frequency Foldback
Theoptimumvaluesdependontheconvertertopology,the
componentvaluesandtheoperatingconditions(including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3757/LT3757A, a series resistor-
When V
is very low during start-up or a short-circuit
OUT
fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor current
decayrateisverylowduringswitchofftime.Theminimum
on-timelimitationmaypreventtheswitcherfromattaining
a sufficiently low duty cycle at the programmed switching
frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3757 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normal-
ized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).
capacitor network is usually connected from the V pin to
C
GND.Figure1showsthetypicalV compensationnetwork.
C
Formostapplications, thecapacitorshouldbeintherange
of 470pF to 22nF, and the resistor should be in the range
of 5k to 50k. A small capacitor is often connected in par-
allel with the RC compensation network to attenuate the
V voltage ripple induced from the output voltage ripple
C
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
The typical frequency foldback waveforms are shown
in the Typical Performance Characteristics section. The
frequency foldback function prevents I from exceeding
L
SENSE Pin Programming
the programmed limits because of the minimum on-time.
For control and protection, the LT3757 measures the
During frequency foldback, external clock synchroniza-
tion is disabled to prevent interference with frequency
reducing operation.
powerMOSFETcurrentbyusingasenseresistor(R
)
SENSE
between GND and the MOSFET source. Figure 4 shows a
typical waveform of the sense voltage (V ) across the
SENSE
Thermal Lockout
senseresistor. ItisimportanttouseKelvintracesbetween
the SENSE pin and R , and to place the IC GND as
SENSE
If LT3757 die temperature reaches 165°C (typical), the
part will go into thermal lockout. The power switch will
be turned off. A soft-start operation will be triggered. The
part will be enabled again when the die temperature has
dropped by 5°C (nominal).
close as possible to the GND terminal of the R
for
SENSE
proper operation.
V
SENSE
∆V
V
SENSE = χ • SENSE(MAX)
Loop Compensation
V
V
SENSE(PEAK)
SENSE(MAX)
Loop compensation determines the stability and transient
performance. The LT3757/LT3757A use current mode
control to regulate the output which simplifies loop com-
pensation. The LT3757A improves the no-load to heavy
load transient response, when compared to the LT3757.
New internal circuits ensure that the transient from not
switching to switching at high current can be made in a
few cycles.
t
DT
S
T
S
3757 F04
Figure 4. The Sense Voltage During a Switching Cycle
3757afd
13
LT3757/LT3757A
applicaTions inForMaTion
Due to the current limit function of the SENSE pin, R
APPLICATION CIRCUITS
SENSE
shouldbeselectedtoguaranteethatthepeakcurrentsense
voltageV duringsteadystatenormaloperation
is lower than the SENSE current limit threshold (see the
Electrical Characteristics table). Given a 20% margin,
TheLT3757canbeconfiguredasdifferenttopologies. The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.
SENSE(PEAK)
V
is set to be 80mV. Then, the maximum
SENSE(PEAK)
Boost Converter: Switch Duty Cycle and Frequency
switch ripple current percentage can be calculated using
the following equation:
The LT3757 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
∆VSENSE
c =
80mV − 0.5• ∆VSENSE
c
is used in subsequent design examples to calculate in-
ductor value. ∆V is the ripple voltage across R
.
SENSE
SENSE
TheLT3757switchingcontrollerincorporates100nstiming
interval to blank the ringing on the current sense signal
immediately after M1 is turned on. This ringing is caused
by the parasitic inductance and capacitance of the PCB
trace, the sense resistor, the diode, and the MOSFET. The
100ns timing interval is adequate for most of the LT3757
applications. In the applications that have very large and
long ringing on the current sense signal, a small RC filter
can be added to filter out the excess ringing. Figure 5
shows the RC filter on SENSE pin. It is usually sufficient
The conversion ratio as a function of duty cycle is
VOUT
VIN 1− D
1
=
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
to choose 22Ω for R and 2.2nF to 10nF for C
.
FLT
FLT
voltage (V ) and the input voltage (V ). The maximum
OUT
duty cycle (D
minimum input voltage:
IN
Keep R ’s resistance low. Remember that there is 65µA
FLT
) occurs when the converter has the
MAX
(typical) flowing out of the SENSE pin. Adding R will
FLT
affect the SENSE current limit threshold:
VOUT − VIN(MIN)
DMAX
=
V
= 108mV – 65µA • R
SENSE_ILIM
FLT
VOUT
Discontinuous conduction mode (DCM) provides higher
conversionratiosatagivenfrequencyatthecostofreduced
efficiencies and higher switching currents.
M1
GATE
LT3757
R
FLT
SENSE
GND
C
FLT
R
SENSE
3757 F05
Figure 5. The RC Filter on SENSE Pin
3757afd
14
LT3757/LT3757A
applicaTions inForMaTion
Boost Converter: Inductor and Sense Resistor Selection
Set the sense voltage at I
to be the minimum of the
L(PEAK)
SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
For the boost topology, the maximum average inductor
current is:
80mV
IL(PEAK)
1
RSENSE
=
IL(MAX) = IO(MAX)
•
1− DMAX
Boost Converter: Power MOSFET Selection
Then, the ripple current can be calculated by:
Important parameters for the power MOSFET include the
1
∆IL = c •IL(MAX) = c •IO(MAX)
•
drain-source voltage rating (V ), the threshold voltage
DS
1− DMAX
(V
), the on-resistance (R
), the gate to source
GS(TH)
DS(ON)
c
The constant in the preceding equation represents the
percentage peak-to-peak ripple current in the inductor,
and gate to drain charges (Q and Q ), the maximum
GS GD
drain current (I
resistances (R and R ).
) and the MOSFET’s thermal
D(MAX)
relative to I
.
L(MAX)
θJC θJA
Theinductorripplecurrenthasadirecteffectonthechoice
of the inductor value. Choosing smaller values of ∆I
The power MOSFET will see full output voltage, plus a
diode forward voltage, and any additional ringing across
its drain-to-source during its off-time. It is recommended
L
requires large inductances and reduces the current loop
gain(theconverterwillapproachvoltagemode).Accepting
to choose a MOSFET whose B
is higher than V
by
VDSS
OUT
larger values of ∆I provides fast transient response and
a safety margin (a 10V safety margin is usually sufficient).
L
allowstheuseoflowinductances,butresultsinhigherinput
The power dissipated by the MOSFET in a boost conver-
ter is:
current ripple and greater core losses. It is recommended
c
that fall within the range of 0.2 to 0.6.
2
2
P
=I
RSS
• R
• D
+ 2 • V • I
OUT L(MAX)
FET
• C
L(MAX) DS(ON) MAX
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalueoftheboostconvertercanbedetermined
using the following equation:
• f/1A
The first term in the preceding equation represents the
conduction losses in the device, and the second term, the
switching loss. C
is the reverse transfer capacitance,
RSS
V
L = IN(MIN) •DMAX
∆IL • f
which is usually specified in the MOSFET characteristics.
For maximum efficiency, R and C should be
DS(ON)
RSS
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
The peak and RMS inductor current are:
c
2
IL(PEAK) = IL(MAX) • 1+
T = T + P • θ = T + P • (θ + θ )
J
A
FET
JA
A
FET
JC
CA
c2
12
T must not exceed the MOSFET maximum junction
J
IL(RMS) = IL(MAX) • 1+
temperature rating. It is recommended to measure the
MOSFETtemperatureinsteadystatetoensurethatabsolute
maximum ratings are not exceeded.
Based on these equations, the user should choose the
inductors having sufficient saturation and RMS current
ratings.
3757afd
15
LT3757/LT3757A
applicaTions inForMaTion
Boost Converter: Output Diode Selection
thesethreeparameters(ESR,ESLandbulkC)ontheoutput
voltage ripple waveform for a typical boost converter is
illustrated in Figure 6.
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to:
t
t
OFF
ON
∆V
COUT
V
OUT
(AC)
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
∆V
ESR
c
2
3757 F05
ID(PEAK) = IL(PEAK) = 1+
•I
L(MAX)
Figure 6. The Output Ripple Waveform of a Boost Converter
It is recommended that the peak repetitive reverse voltage
rating V is higher than V by a safety margin (a 10V
RRM
OUT
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
safety margin is usually sufficient).
The power dissipated by the diode is:
between the ESR step ∆V
and the charging/discharg-
ESR
P = I
D
• V
D
O(MAX)
ing ∆V
. For the purpose of simplicity, we will choose
COUT
and the diode junction temperature is:
T = T + P • R
2% for the maximum output ripple, to be divided equally
between ∆V and ∆V . This percentage ripple will
change,dependingontherequirementsoftheapplication,
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
ESR
COUT
J
A
D
θJA
The R to be used in this equation normally includes the
θJA
R
θJC
for the device plus the thermal resistance from the
boardtotheambienttemperatureintheenclosure.T must
notexceedthediodemaximumjunctiontemperaturerating.
J
0.01• VOUT
ID(PEAK)
Boost Converter: Output Capacitor Selection
ESRCOUT
≤
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
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For the bulk C component, which also contributes 1% to
the total ripple:
FLYBACK CONVERTER APPLICATIONS
The LT3757 can be configured as a flyback converter
for the applications where the converters have multiple
outputs, high output voltages or isolated outputs. Figure
7 shows a simplified flyback converter.
IO(MAX)
COUT
≥
0.01• VOUT • f
Theoutputcapacitorinaboostregulatorexperienceshigh
RMSripplecurrents, asshowninFigure6. TheRMSripple
current rating of the output capacitor can be determined
using the following equation:
The flyback converter has a very low parts count for mul-
tipleoutputs, andwithprudentselectionofturnsratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
thehighpeakcurrents,highpeakvoltagesandconsequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.
DMAX
IRMS(COUT) ≥ IO(MAX)
•
1− DMAX
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
therequiredRMScurrentrating.Additionalceramiccapaci-
tors in parallel are commonly used to reduce the effect of
parasiticinductanceintheoutputcapacitor,whichreduces
high frequency switching noise on the converter output.
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency. In the high output voltage
applications, the flyback converters can be designed
to operate in discontinuous mode to avoid using large
transformers.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 10µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
SUGGESTED
D
RCD SNUBBER
N :N
P
S
V
IN
–
SN
+
+
+
+
V
C
I
D
C
R
IN
SN
SN
C
L
L
OUT
P
S
–
D
SN
I
SW
LT3757
GATE
+
V
–
M
R
The RMS input capacitor ripple current for a boost con-
verter is:
DS
SENSE
SENSE
I
= 0.3 • ∆I
L
RMS(CIN)
GND
3757 F06
Figure 7. A Simplified Flyback Converter
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Flyback Converter: Switch Duty Cycle and Turns Ratio
Accordingtotheprecedingequations,theuserhasrelative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select-
ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
The flyback converter conversion ratio in the continuous
mode operation is:
VOUT NS
VIN NP 1− D
D
=
•
where N /N is the second to primary turns ratio.
S
P
Figure 8 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
period T , three subintervals occur: DT , D2T , D3T .
• Lower MOSFET RMS current I
, but higher
SW(RMS)
S
S
S
S
MOSFET V peak voltage
During DT , M is on, and D is reverse-biased. During
DS
S
D2T , M is off, and L is conducting current. Both L and
S
S
P
• Lower diode peak reverse voltage, but higher diode
RMS current I
L currents are zero during D3T .
S
S
D(RMS)
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
• Higher transformer turns ratio (N /N )
P
S
The choice,
VOUT NS
D
=
•
D
1
VIN NP D2
=
D+ D2 3
(for discontinuous mode operation with a given D3) gives
the power MOSFET the lowest power stress (the product
of RMS current and peak voltage). However, in the high
output voltage applications, a higher duty cycle may be
adopted to limit the large peak reverse voltage of the
diode. The choice,
V
DS
I
SW
D
2
=
I
SW(MAX)
D+ D2 3
(for discontinuous mode operation with a given D3) gives
the diode the lowest power stress (the product of RMS
current and peak voltage). An extreme high or low duty
cycleresultsinhighpowerstressontheMOSFETordiode,
and reduces efficiency. It is recommended to choose a
duty cycle, D, between 20% and 80%.
I
D
I
D(MAX)
DT
S
D2T
S
D3T
t
S
T
S
3757 F07
Figure 8. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
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Flyback Converter: Transformer Design for
Discontinuous Mode Operation
According to Figure 8, the primary and secondary peak
currents are:
Thetransformerdesignfordiscontinuousmodeofopera-
tion is chosen as presented here. According to Figure 8,
I
I
= I
= I
= 2 • I
SW(PEAK) LP(MAX)
LP(PEAK)
LS(PEAK)
= 2 • I
D(PEAK)
LS(MAX)
the minimum D3 (D3 ) occurs when the converter
MIN
The primary and second inductor values of the flyback
converter transformer can be determined using the fol-
lowing equations:
has the minimum V and the maximum output power
IN
MIN
(P ). Choose D3
to be equal to or higher than 10%
OUT
to guarantee the converter is always in discontinuous
modeoperation(choosinghigherD3allowstheuseoflow
inductances, but results in a higher switch peak current).
2
2
D
• V
• h
IN(MIN)
MAX
L =
P
2 •P
• f
OUT(MAX)
The user can choose a D
as the start point. Then, the
MAX
2
maximum average primary currents can be calculated by
the following equation:
D2 •(V
+ V )
D
OUT
L =
S
2 •I
• f
OUT(MAX)
POUT(MAX)
ILP(MAX) = ISW(MAX)
=
The primary to second turns ratio is:
DMAX • VIN(MIN) • h
NP
NS
LP
LS
where h is the converter efficiency.
=
If the flyback converter has multiple outputs, P
is the sum of all the output power.
OUT(MAX)
Flyback Converter: Snubber Design
The maximum average secondary current is:
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOS-
FET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
In some cases a snubber circuit will be required to avoid
overvoltagebreakdownattheMOSFET’sdrainnode.There
are different snubber circuits, and Application Note 19 is
a good reference on snubber design. An RCD snubber is
shown in Figure 7.
IOUT(MAX)
ILS(MAX) = ID(MAX)
where:
D2 = 1 – D
=
D2
– D3
MAX
the primary and secondary RMS currents are:
DMAX
ILP(RMS) = 2•ILP(MAX)
ILS(RMS) = 2•ILS(MAX)
•
•
3
The snubber resistor value (R ) can be calculated by the
SN
D2
3
following equation:
NP
NS
V2 − VSN • VOUT
•
SN
RSN = 2 •
I2SW(PEAK) •LLK • f
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where V is the snubber capacitor voltage. A smaller
Flyback Converter: Power MOSFET Selection
SN
V
results in a larger snubber loss. A reasonable V is
2 to 2.5 times of:
SN
SN
Fortheflybackconfiguration, theMOSFETisselectedwith
a V rating high enough to handle the maximum V , the
DC
IN
reflected secondary voltage and the voltage spike due to
VOUT •NP
theleakageinductance.ApproximatetherequiredMOSFET
NS
V
DC
rating using:
L istheleakageinductanceoftheprimarywinding,which
LK
BV
> V
DS(PEAK)
DSS
is usually specified in the transformer characteristics. L
LK
where:
canbeobtainedbymeasuringtheprimaryinductancewith
the secondary windings shorted. The snubber capacitor
VDS(PEAK) = VIN(MAX) + VSN
value(C )canbedeterminedusingthefollowingequation:
CN
The power dissipated by the MOSFET in a flyback con-
verter is:
VSN
∆VSN •RCN • f
CCN
=
2
2
P
RSS
= I
• R
+ 2 • V
• I
•
FET
M(RMS)
DS(ON)
DS(PEAK) L(MAX)
where ∆V is the voltage ripple across C . A reasonable
SN
CN
C
• f/1A
∆V is 5% to 10% of V . The reverse voltage rating of
SN
SN
SN
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
D
should be higher than the sum of V and V
.
SN
IN(MAX)
loss. C
is the reverse transfer capacitance, which is
RSS
Flyback Converter: Sense Resistor Selection
usually specified in the MOSFET characteristics.
In a flyback converter, when the power switch is turned
on, the current flowing through the sense resistor
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
equation:
(I
) is:
SENSE
I
= I
LP
SENSE
T = T + P • θ = T + P • (θ + θ )
J
A
FET
JA
A
FET
JC
CA
Set the sense voltage at I
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
to be the minimum of
LP(PEAK)
T must not exceed the MOSFET maximum junction
J
temperature rating. It is recommended to measure the
MOSFETtemperatureinsteadystatetoensurethatabsolute
maximum ratings are not exceeded.
80mV
ILP(PEAK)
RSENSE
=
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Flyback Converter: Output Diode Selection
Flyback Converter: Input Capacitor Selection
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
discontinuous operation can be determined using the
following equation:
Approximate the required peak repetitive reverse voltage
rating V
using:
RRM
POUT(MAX)
4− (3•DMAX
3•DMAX
)
NS
IRMS(CIN),DISCONTINUOUS
≥
•
VRRM
>
• VIN(MAX) + VOUT
VIN(MIN) • h
NP
The power dissipated by the diode is:
P = I • V
SEPIC CONVERTER APPLICATIONS
D
O(MAX)
D
The LT3757 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
and the diode junction temperature is:
T = T + P • R
J
A
D
θJA
The R to be used in this equation normally includes the
θJA
R
for the device, plus the thermal resistance from the
θJC
VOUT + VD
D
boardtotheambienttemperatureintheenclosure.T must
=
J
VIN
1− D
notexceedthediodemaximumjunctiontemperaturerating.
in continuous conduction mode (CCM).
Flyback Converter: Output Capacitor Selection
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer
totheBoostConverter:OutputCapacitorSelectionsection
for the calculation of C
and ESR
.
OUT
COUT
Compared to the flyback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
The RMS ripple current rating of the output capacitors
in discontinuous operation can be determined using the
following equation:
output diode voltages are clamped by the capacitors (C ,
IN
C
DC
and C ), therefore, there is less voltage ringing
OUT
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the inductor L1 is in series
with the input, and the ripple current flowing through the
input capacitor is continuous.
4− (3•D2)
IRMS(COUT),DISCONTINUOUS ≥ IO(MAX)
•
3•D2
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SEPIC Converter: Switch Duty Cycle and Frequency
In a SEPIC converter, the switch current is equal to I
L2
average switch current is defined as:
+
L1
I
when the power switch is on, therefore, the maximum
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
1
voltage (V ), the input voltage (V ) and the diode
OUT
IN
ISW(MAX) = IL1(MAX) + IL2(MAX) = IO(MAX)
•
forward voltage (V ).
1− DMAX
D
Themaximumdutycycle(D )occurswhentheconverter
MAX
and the peak switch current is:
has the minimum input voltage:
c
2
1
VOUT + VD
VIN(MIN) + VOUT + VD
ISW(PEAK) = 1+
•I
•
O(MAX)
DMAX
=
1− DMAX
c
The constant in the preceding equations represents the
percentage peak-to-peak ripple current in the switch, rela-
SEPIC Converter: Inductor and Sense Resistor Selection
tive to I
, as shown in Figure 9. Then, the switch
As shown in Figure 1, the SEPIC converter contains two
inductors:L1andL2.L1andL2canbeindependent,butcan
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
SW(MAX)
ripple current ∆I can be calculated by:
SW
c
∆I = • I
SW
SW(MAX)
The inductor ripple currents ∆I and ∆I are identical:
L1
L2
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
∆I = ∆I = 0.5 • ∆I
SW
L1
L2
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
∆I requires large inductances and reduces the current
L
D
MAX
I
I
= I
= I
•
loop gain (the converter will approach voltage mode).
L1(MAX) IN(MAX) O(MAX)
1− D
MAX
Accepting larger values of ∆I allows the use of low in-
L
= I
ductances, but results in higher input current ripple and
L2(MAX) O(MAX)
c
greater core losses. It is recommended that falls in the
range of 0.2 to 0.4.
I
SW
∆I
I
SW = χ • SW(MAX)
I
SW(MAX)
t
DT
S
T
S
3757 F08
Figure 9. The Switch Current Waveform of the SEPIC Converter
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Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalue(L1andL2areindependent)oftheSEPIC
convertercanbedeterminedusingthefollowingequation:
Basedontheprecedingequations,theusershouldchoose
the inductors having sufficient saturation and RMS cur-
rent ratings.
In a SEPIC converter, when the power switch is turned on,
the current flowing through the sense resistor (I
the switch current.
) is
SENSE
VIN(MIN)
L1= L2=
•DMAX
0.5• ∆ISW • f
Set the sense voltage at I
to be the minimum
SENSE(PEAK)
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.
of the SENSE current limit threshold with a 20% margin.
The sense resistor value can then be calculated to be:
BymakingL1=L2,andwindingthemonthesamecore,the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
80 mV
ISW(PEAK)
RSENSE
=
VIN(MIN)
SEPIC Converter: Power MOSFET Selection
L =
•DMAX
∆ISW • f
For the SEPIC configuration, choose a MOSFET with a
V
rating higher than the sum of the output voltage and
DC
Thismaintainsthesameripplecurrentandenergystorage
in the inductors. The peak inductor currents are:
input voltage by a safety margin (a 10V safety margin is
usually sufficient).
I
I
= I
= I
+ 0.5 • ∆I
+ 0.5 • ∆I
L1(PEAK)
L2(PEAK)
L1(MAX)
L2(MAX)
L1
L2
The power dissipated by the MOSFET in a SEPIC con-
verter is:
2
P
= I
• R
• D
MAX
The RMS inductor currents are:
FET
SW(MAX)
DS(ON)
2
+ 2 • (V
+ V ) • I
• C
• f/1A
IN(MIN)
OUT
L(MAX)
RSS
c2
12
L1
IL1(RMS) = IL1(MAX) • 1+
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
where:
cL1 =
loss. C
is the reverse transfer capacitance, which is
RSS
usually specified in the MOSFET characteristics.
∆IL1
IL1(MAX)
For maximum efficiency, R and C should be
DS(ON)
RSS
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
c2
12
L2
IL2(RMS) = IL2(MAX) • 1+
T = T + P • θ = T + P • (θ + θ )
J
A
FET
JA
A
FET
JC
CA
where:
cL2 =
T must not exceed the MOSFET maximum junction
J
∆IL2
IL2 (MAX)
temperature rating. It is recommended to measure the
MOSFETtemperatureinsteadystatetoensurethatabsolute
maximum ratings are not exceeded.
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SEPIC Converter: Output Diode Selection
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
DC
IN
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current, and the peak current is equal to:
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
lowing equation:
V
+ V
D
OUT
c
2
1
I
> I
•
RMS(CDC) O(MAX)
ID(PEAK) = 1+
•I
•
O(MAX)
V
IN(MIN)
1− DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
It is recommended that the peak repetitive reverse voltage
rating V is higher than V + V by a safety
well for C .
DC
RRM
OUT
IN(MAX)
margin (a 10V safety margin is usually sufficient).
INVERTING CONVERTER APPLICATIONS
The power dissipated by the diode is:
TheLT3757canbeconfiguredasadual-inductorinverting
P = I
• V
D
D
O(MAX)
topology, as shown in Figure 10. The V
to V ratio is:
OUT
IN
and the diode junction temperature is:
T = T + P • R
VOUT − VD
D
1− D
= −
J
A
D
θJA
VIN
The R used in this equation normally includes the R
θJA
θJC
for the device, plus the thermal resistance from the board,
in continuous conduction mode (CCM).
to the ambient temperature in the enclosure. T must not
J
C
+
exceed the diode maximum junction temperature rating.
DC
L1
L2
C
–
V
IN
–
+
SEPIC Converter: Output and Input Capacitor Selection
C
LT3757
GATE
IN
D1
OUT
M1
+
The selections of the output and input capacitors of the
SEPICconverteraresimilartothoseoftheboostconverter.
Please refer to the Boost Converter, Output Capacitor
Selection and Boost Converter, Input Capacitor Selection
sections.
V
OUT
SENSE
R
SENSE
+
GND
3757 F09
Figure 10. A Simplified Inverting Converter
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (C ,
DC
as shown in Figure 1) should be larger than the maximum
input voltage:
V
> V
IN(MAX)
CDC
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Inverting Converter: Switch Duty Cycle and Frequency
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negativeoutputvoltage(V )andtheinputvoltage(V ).
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
OUT
IN
Themaximumdutycycle(D )occurswhentheconverter
MAX
has the minimum input voltage:
VOUT − VD
VOUT − VD − VIN(MIN)
The RMS ripple current rating of the output capacitor
needs to be greater than:
DMAX
=
I
> 0.3 • ∆I
L2
RMS(COUT)
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
Inverting Converter: Selecting the DC Coupling Capacitor
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an invert-
ing converter are similar to those of the SEPIC converter.
PleaserefertothecorrespondingSEPICconvertersections.
The DC voltage rating of the DC coupling capacitor (C ,
DC
asshowninFigure10)shouldbelargerthanthemaximum
input voltage minus the output voltage (negative voltage):
V
> V
– V
IN(MAX) OUT
CDC
Inverting Converter: Output Capacitor Selection
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
convertersforsimilaroutputripples. Thisisduetothefact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
outputcapacitorsarecontinuous.Theoutputripplevoltage
is produced by the ripple current of L2 flowing through
the ESR and bulk capacitance of the output capacitor:
DC
IN
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
lowing equation:
DMAX
1− DMAX
IRMS(CDC) > IO(MAX)
•
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
1
∆VOUT(P–P) = ∆IL2 • ESRCOUT
+
8 • f •COUT
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Board Layout
should be kept as tight as possible to reduce inductive
ringing:
The high speed operation of the LT3757 demands careful
attention to board layout and component placement. The
Exposed Pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the Exposed Pad and the ground
plane of the board. For the LT3757 to deliver its full output
power, it is imperative that a good thermal path be pro-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
• In boost configuration, the high di/dt loop contains
the output capacitor, the sensing resistor, the power
MOSFET and the Schottky diode.
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
power MOSFET and the sensing resistor. The high di/
dt secondary loop contains the output capacitor, the
secondary winding and the output diode.
• In SEPIC configuration, the high di/dt loop contains
the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies
• In inverting configuration, the high di/dt loop contains
power MOSFET, sense resistor, Schottky diode and the
coupling capacitor.
C
IN
V
IN
C
C
C1
C2
L1
R3
R
C
R1
R2
R
1
2
3
4
5
10
LT3757
9
8
7
6
C
SS
VCC
R
T
1
2
3
4
8
7
6
5
M1
R
S
VIAS TO GROUND
PLANE
D1
C
OUT2
C
OUT1
V
OUT
3757 F10
Figure 11. 8V to 16V Input, 24V/2A Output Boost Converter Suggested Layout
3757afd
26
LT3757/LT3757A
applicaTions inForMaTion
Check the stress on the power MOSFET by measuring its
drain-to-sourcevoltagedirectlyacrossthedeviceterminals
(reference the ground of a single scope probe directly to
the source pad on the PC board). Beware of inductive
ringing, which can exceed the maximum specified voltage
rating of the MOSFET. If this ringing cannot be avoided,
and exceeds the maximum rating of the device, either
choose a higher voltage device or specify an avalanche-
rated power MOSFET.
Table 2. Recommended Component Manufacturers
VENDOR
AVX
COMPONENTS
WEB ADDRESS
avx.com
Capacitors
BH Electronics
Inductors,
Transformers
bhelectronics.com
Coilcraft
Inductors
Inductors
Diodes
coilcraft.com
bussmann.com
Cooper Bussmann
Diodes, Inc
Fairchild
diodes.com
MOSFETs
Diodes
fairchildsemi.com
generalsemiconductor.com
General
Semiconductor
Thesmall-signalcomponentsshouldbeplacedawayfrom
highfrequencyswitchingnodes.Foroptimumloadregula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
thetopoftheoutputcapacitor(Kelvinconnection),staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3757 in order to keep the high impedance
FBX node short.
International Rectifier MOSFETs, Diodes
irf.com
irctt.com
IRC
Sense Resistors
Capacitors
Toroid Cores
Diodes
Kemet
kemet.com
mag-inc.com
microsemi.com
murata.co.jp
Magnetics Inc
Microsemi
Murata-Erie
Inductors,
Capacitors
Nichicon
Capacitors
Diodes
nichicon.com
onsemi.com
Figure 11 shows the suggested layout of the 8V to 16V
Input, 24V/2A Output Boost Converter.
On Semiconductor
Panasonic
Sanyo
Capacitors
Capacitors
Inductors
Capacitors
panasonic.com
sanyo.co.jp
Recommended Component Manufacturers
Sumida
sumida.com
Some of the recommended component manufacturers
are listed in Table 2.
Taiyo Yuden
TDK
t-yuden.com
Capacitors,
Inductors
component.tdk.com
Thermalloy
Tokin
Heat Sinks
Capacitors
Inductors
Capacitors
Resistors
MOSFETs
Capacitors
Inductors
aavidthermalloy.com
nec-tokinamerica.com
tokoam.com
Toko
United Chemi-Con
Vishay/Dale
Vishay/Siliconix
Vishay/Sprague
Würth Elektronik
Zetex
chemi-con.com
vishay.com
vishay.com
vishay.com
we-online.com
zetex.com
Small-Signal
Discretes
3757afd
27
LT3757/LT3757A
Typical applicaTions
3.3V Input, 5V/10A Output Boost Converter
L1
0.5µH
V
IN
Efficiency vs Output Current
3.3V
C
IN
22µF
6.3V
×2
V
100
90
IN
49.9k
34k
C
INTV
VCC
CC
4.7µF
10V
SHDN/UVLO
D1
V
5V
10A
OUT
X5R
80
70
LT3757
SYNC
GATE
M1
34k
1%
60
50
FBX
22Ω
C
OUT1
RT
SS
+
SENSE
150µF
6.3V
40
V
GND
C
×4
41.2k
300kHz
0.004Ω
1W
30
20
C
6.8k
22nF
OUT2
22µF
15.8k
1%
0.1µF
2.2nF
6.3V
0.001
0.1
1
10
0.01
X5R
OUTPUT CURRENT (A)
×4
3757 TA02b
3757 TA02a
C
C
C
: TAIYO YUDEN JMK325BJ226MM
D1: MBRB2515L
L1: VISHAY SILICONIX IHLP-5050FD-01
M1: VISHAY SILICONIX SI4448DY
IN
: PANASONIC EEFUEOJ151R
OUT1
OUT2
: TAIYO YUDEN JMK325BJ226MM
Boost Preregulator for Automotive Stop-Start/Idle
L1
3.3µH
D1
V
9V
2A
OUT
MIN
V
IN
3V TO 36V
10µF
50V
X5R
×2
Transient VIN and VOUT Waveforms
M1
GATE
10µF
50V
X5R
1M
OUTPUT POWER = 10W
SENSE
GND
SHDN/UVLO
8mΩ
698k
LT3757A
SYNC
RT
V
IN
75k
C1
V
+
OUT
SS
FBX
5V/DIV
10µF
50V
V
IN
V
INTV
16.2k
C
CC
×4
5V/DIV
41.2k
300kHz
0V
10ms/DIV
10k
10nF
3757 TA03b
0.1µF
4.7µF
3757 TA03a
L1: COILTRONIX DR127-3R3
M1: VISHAY SILICONIX Si7848BDP
D1: VISHAY SILICONIX 50SQ04FN
C1: KEMET T495X106K050A
3757afd
28
LT3757/LT3757A
Typical applicaTions
8V to 16V Input, 24V/2A Output Boost Converter
V
IN
8V TO 16V
C
IN
R3
200k
L1
10µF
25V
X5R
V
IN
10µH
SHDN/UVLO
D1
V
24V
2A
OUT
R4
43.2k
LT3757
SYNC
GATE
M1
R2
226k
1%
SENSE
C
OUT1
RT
SS
+
47µF
35V
×4
FBX
GND INTV
CC
VC
R
T
R
41.2k
300kHz
S
C
R
C2
C
0.01Ω
1W
C
10µF
25V
X5R
100pF
22k
OUT2
R1
16.2k
1%
C
VCC
C
4.7µF
10V
C
6.8nF
SS
0.1µF
C1
X5R
C
C
, C
OUT1
: MURATA GRM31CR61E106KA12
IN OUT2
3757 TA04a
: KEMET T495X476K035AS
D1: ON SEMI MBRS340T3G
L1: VISHAY SILICONIX IHLP-5050FD-01 10µH
M1: VISHAY SILICONIX Si4840BDP
Efficiency vs Output Current
Load Step Response at VIN = 12V
100
90
V
OUT
500mV/DIV
(AC)
V
= 8V
80
IN
V
= 16V
IN
70
60
50
40
30
1.6A
I
OUT
1A/DIV
0.4A
3757 TA04c
500µs/DIV
0.001
0.1
1
10
0.01
OUTPUT CURRENT (A)
3757 TA04b
3757afd
29
LT3757/LT3757A
Typical applicaTions
High Voltage Flyback Power Supply
DANGER! HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1
1:10
D1
V
350V
OUT
V
IN
5V TO 12V
C
10mA
IN
•
47µF
16V
×4
105k
1.50M
1%
•
SHDN/UVLO
V
IN
22Ω
C
47µF
25V
46.4k
INTV
CC
VCC
1M
1%
220pF
C
68nF
OUT
SYNC
V
SW
LT3757
X5R
×2
1M
1%
GATE
M1
RT
SS
22Ω
SENSE
FBX
V
C
GND
140k
100kHz
10nF
16.2k
1%
6.8k
22nF
0.02Ω
0.1µF
100pF
3757 TA05a
C
C
: MURATA GRM32ER61C476K
IN
: TDK C3225X7R2J683K
OUT
D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
M1: VISHAY SILICONIX Si7850DP
T1: TDK DCT15EFD-U44S003
Start-Up Waveforms
Switching Waveforms
V
OUT
5V/DIV
(AC)
V
SW
20V/DIV
V
OUT
100V/DIV
3757 TA05b
3757 TA05c
2ms/DIV
5µs/DIV
3757afd
30
LT3757/LT3757A
Typical applicaTions
5.5V to 36V Input, 12V/2A Output SEPIC Converter
V
IN
5.5V TO 36V
C
C
IN2
IN1
+
•
C
4.7µF
4.7µF
50V
×2
4.7µF
50V
×2
DC
105k
I
V
L1A
L1A
IN
50V, X5R, ×2
SHDN/UVLO
D1
V
OUT
12V
2A
V
SW
46.4k
LT3757A
SYNC
GATE
M1
L1B
I
L1B
105k
1%
•
SENSE
0.01Ω
1W
C
47µF
OUT1
RT
SS
+
FBX
20V
V
GND INTV
CC
C
×4
41.2k
300kHz
10k
6.8nF
C
10µF
25V
X5R
OUT2
4.7µF
10V
X5R
15.8k
1%
0.1µF
3757 TA06a
C
C
C
C
, C : TAIYO YUDEN UMK316BJ475KL
: KEMET T495X475K050AS
IN1 DC
IN2
: KEMET T495X476K020AS
: TAIYO YUDEN TMK432BJ106MM
OUT1
OUT2
D1: ON SEMI MBRS360T3G
L1A, L1B: COILTRONICS DRQ127-4R7 (*COUPLED INDUCTORS)
M1: VISHAY SILICONIX Si7460DP
Efficiency vs Output Current
Load Step Waveforms
100
90
V
= 12V
IN
V
OUT
2V/DIV
V
= 8V
IN
80
70
AC-COUPLED
V
= 16V
IN
60
50
2A
I
OUT
2A/DIV
0A
40
30
500µs/DIV
3757 TA06c
20
0.001
0.1
1
10
0.01
OUTPUT CURRENT (A)
3757 TA06b
Start-Up Waveforms
Frequency Foldback Waveforms When Output Short-Circuits
V
= 12V
V
= 12V
V
IN
IN
OUT
10V/DIV
V
SW
V
20V/DIV
OUT
5V/DIV
I
+ I
L1A L1B
I
+ I
5A/DIV
L1A L1B
5A/DIV
3757 TA06d
3757 TA06e
2ms/DIV
50µs/DIV
3757afd
31
LT3757/LT3757A
Typical applicaTions
5V to 12V Input, 12V/0.4A Output SEPIC Converter
V
IN
5V TO 12V
C
47µF
16V
C
IN1
IN2
+
•
C
105k
DC1
V
1µF
IN
T1
1,2,3,4
4.7µF
16V, X5R
16V, X5R
SHDN/UVLO
D1
V
OUT1
12V
46.4k
LT3757
0.4A
1.05k
1%
C
M1
C
OUT2
SYNC
GATE
DC2
4.7µF
16V, X5R
×3
4.7µF
16V
5
SENSE
FBX
158Ω
1%
•
X5R
RT
SS
GND
0.02Ω
C
OUT2
D2
4.7µF
16V, X5R
×3
V
C
GND INTV
CC
6
V
–12V
0.4A
OUT2
30.9k
400kHz
22k
6.8nF
3757 TA07
C
VCC
4.7µF
10V
0.1µF
100pF
X5R
D1, D2: MBRS140T3
T1: COILTRONICS VP1-0076 (*PRIMARY = 4 WINDINGS IN PARALLEL)
M1: SILICONIX/VISHAY Si4840BDY
Nonisolated Inverting SLIC Supply
VP5-0155 (PRIMARY = 3 WINDINGS IN PARALLEL)
D1
DFLS160
V
IN
GND
5V TO 16V
C
IN
22µF
C2
C3
R2
•
10µF
50V
X5R
V
IN
22µF
25V
X5R
T1
105k
25V, X5R
×2
4
1,2,3
SHDN/UVLO
•
•
•
R1
46.4k
LT3757
M1
Si7850DP
D2
DFLS160
SYNC
GATE
V
OUT1
–24V
SENSE
FBX
200mA
C4
C
3.3µF
100V
RT
SS
OUT
22µF
25V
X5R
5
V
C
GND INTV
CC
D3
63.4k
200kHz
0.012Ω
0.5W
DFLS160
9.1k
10nF
C
4.7µF
10V, X5R
VCC
0.1µF
C5
22µF
25V
X5R
100pF
6
V
OUT1
15.8k
–72V
464k
200mA
3757 TA08
3757afd
32
LT3757/LT3757A
package DescripTion
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
0.40 ± 0.10
TYP
6
10
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
PIN 1
TOP MARK
(SEE NOTE 6)
CHAMFER
(DD) DFN REV C 0310
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3757afd
33
LT3757/LT3757A
package DescripTion
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev H)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1.88 ±0.102
(.074 ±.004)
0.889 ±0.127
(.035 ±.005)
1
0.29
REF
1.68
(.066)
0.05 REF
5.23
(.206)
MIN
1.68 ±0.102
3.20 – 3.45
DETAIL “B”
(.066 ±.004) (.126 – .136)
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
10
NO MEASUREMENT PURPOSE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ±.0015)
TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.497 ±0.076
(.0196 ±.003)
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
REF
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
1
2
3
4 5
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.50
(.0197)
BSC
MSOP (MSE) 0911 REV H
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
3757afd
34
LT3757/LT3757A
revision hisTory (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
3/10
Deleted Bullet from Features and Last Line of Description
Updated Entire Page to Add H-Grade and Military Grade
1
2
Updated Electrical Characteristics Notes and Typical Performance Characteristics for H-Grade and Military Grade
Revised TA04a and Replaced TA04c in Typical Applications
Updated Related Parts
4 to 6
30
36
C
D
5/11
Revised MP-grade temperature range in Absolute Maximum Ratings and Order Information sections
Revised Note 2
2
4
Revised formula in Applications Information
19
30
Updated Typical Application drawing TA04a values
Revised Typical Application title TA06
32
07/12 Added LT3757A version
Updated Block Diagram
Throughout
8
Updated Programming the Output Voltage section
12
13
28
31
Updated Loop Compensation section
Added an application circuit in the Typical Applications section
Updated the schematic and Load Step Waveforms in the Typical Applications section
3757afd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LT3757/LT3757A
Typical applicaTion
High Efficiency Inverting Power Supply
Efficiency vs Output Current
V
IN
5V TO
15V
C
47µF
16V
R2
105k
IN
C
47µF
25V, X5R
DC
100
•
V
IN
L1
90
80
70
60
50
40
L2
SHDN/UVLO
V
–5V
3A to 5A
X5R
OUT
R1
46.4k
V
= 5V
LT3757
IN
SYNC
GATE
M1
84.5k
V
= 16V
IN
Si7848BDP
SENSE
D1
MBRD835L
0.006Ω
1W
RT
SS
FBX
V
C
GND INTV
CC
41.2k
300kHz
30
20
10
C
9.1k
10nF
VCC
C
16k
OUT
4.7µF
10V
X5R
100µF
0.1µF
6.3V, X5R
×2
0.001
0.1
1
10
0.01
OUTPUT CURRENT (A)
3757 TA09b
3757 TA09a
L1, L2: COILTRONICS DRQ127-3R3 (*COUPLED INDUCTORS)
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LT3758A
Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages
LT3759
LT3957A
LT3958
Boost, SEPIC and Inverting Controller
1.6V ≤ V ≤ 42V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, MSOP-12E Packages
Boost, Flyback, SEPIC and Inverting Controller 3V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation
with 5A, 40V Switch
IN
Frequency, 5mm × 6mm QFN Package
Boost, Flyback, SEPIC and Inverting Controller 5V ≤ V ≤ 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation
with 3.3A, 84V Switch
IN
Frequency, 5mm × 6mm QFN Package
LT3573/LT3574/
LT3575
40V Isolated Flyback Converters
Monolithic No-Opto Flybacks with Integrated 1.25A/0.65A/2.5A Switch
LT3511/LT3512
LT3798
100V Isolated Flyback Converters
Monolithic No-Opto Flybacks with Integrated 240mA/420mA Switch
Offline Isolated No Opto-Coupler Flyback
Controller with Active PFC
V
IN
and V
Limited Only by External Components, MSOP-16 Package
OUT
LT3799/LT3799-1
Offline Isolated Flyback LED Controllers with
Active PFC
V
and V
Limited Only by External Components, MSOP-16 Package
IN
OUT
3757afd
LT 0712 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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