LT3651_技术文档

LTC4000

High Voltage High Current

Controller for Battery Charging

and Power Management

DescripTion

FeaTures

TheLTC^®4000isahighvoltage,highperformancecontroller

that converts many externally compensated DC/DC power

supplies into full-featured battery chargers.

n

Complete High Performance Battery Charger When

Paired with a DC/DC Converter

n

Wide Input and Output Voltage Range: 3V to 60V

Input Ideal Diode for Low Loss Reverse Blocking

and Load Sharing

Output Ideal Diode for Low Loss PowerPath™ and

Load Sharing with the Battery

FeaturesoftheLTC4000’sbatterychargerinclude:accurate

( 0.ꢀ25% programmable float voltage, selectable timer or

current termination, temperature qualified charging using

anNTCthermistor,automaticrecharge,C/10tricklecharge

for deeply discharged cells, bad battery detection and

statusindicatoroutputs.Thebatterychargeralsoincludes

precisioncurrentsensingthatallowslowersensevoltages

for high current applications.

n

Instant-On Operation with Heavily Discharged

Battery

Programmable Input and Charge Current:

1ꢀ Accuracy

0.ꢁ2ꢀ Accurate Programmable Float Voltage

Programmable C/X or Timer Based Charge

Termination

NTC Input for Temperature Qualified Charging

ꢀ8-Lead 4mm × 2mm QFN or SSOP Packages

n

The LTC4000 supports intelligent PowerPath control. An

external PFET provides low loss reverse current protec-

tion. Another external PFET provides low loss charging

or discharging of the battery. This second PFET also

facilitates an instant-on feature that provides immediate

downstream system power even when connected to a

heavily discharged or short faulted battery.

n

applicaTions

n

High Power Battery Charger Systems

The LTC4000 is available in a low profile ꢀ8-lead 4mm ×

2mm QFN and SSOP packages.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

n

High Performance Portable Instruments

n

Industrial Battery Equipped Devices

Notebook/Subnotebook Computers

n

Typical applicaTion

48V to 10.8V at 10A Buck Converter Charger for Three LiFePO₄Cells

Charge Current and V_OUTProfile

vs V_BATDuring a Charge Cycle

Si7135DP

LT3845

IN

OUT

15V TO 60V

12V, 15A

V

SHDN

12

10

8

11

10.5

10

9.5

9

C

5mΩ

100µF

47nF

1.15M

5mΩ

I

CHARGE

V

OUT

14.7k

ITH

CC

IID IGATE CSP

RST

CLN

IN

CSN

V

OUT

BGATE

Si7135DP

6

BAT

OFB

1µF

1.10M

4

127k

VM

LTC4000

FBG

100k

3.0V

ENC

CHRG

FLT

2

8.5

8

I

CHARGE

7

133k

10.8V FLOAT

10A MAX CHARGE

CURRENT

BFB

NTC

0

1.13M

IIMON

6

8

9

(V)

10

11

12

10nF

IBMON

V

BAT

4000 TA01b

10k

10nF

TMR

CL

CX

GND BIAS

3-CELL LiFePO

BATTERY PACK

4

10k

24.9k

22.1k

0.1µF

1µF

4000 TA01a

NTHS0603

N02N1002J

4000f

1

LTC4000

absoluTe MaxiMuM raTings

(Note 1)

IN, CLN, IID, CSP, CSN, BAT....................... –0.3V to 6ꢀV

IN-CLN, CSP-CSN............................................–1V to 1V

OFB, BFB, FBG ........................................... –0.3V to 6ꢀV

FBG............................................................–1mA to ꢀmA

BIAS.............................................–0.3V to Min (6V, V %

IN

IBMON ..................................–0.3V to Min (V

, V

%

BIAS CSP

ITH............................................................... –0.3V to 6V

CHRG, FLT, RST.......................................... –0.3V to 6ꢀV

CHRG, FLT, RST..........................................–1mA to ꢀmA

Operating Junction Temperature Range

(Note ꢀ%................................................................. 1ꢀ2°C

Storage Temperature Range .................. –62°C to 120°C

IGATE...........Max (V , V % – 10V to Max (V , V

%

IID CSP

BAT CSN

BGATE.......Max (V , V % – 10V to Max (V , V

BAT CSN

ENC, CX, NTC, VM ...................................–0.3V to V

BIAS

IL, CL, TMR, IIMON, CC ...........................–0.3V to V

pin conFiguraTion

TOP VIEW

1

2

IL

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ENC

IBMON

CX

IIMON

RST

VM

28 27 26 25 24 23

3

VM

RST

IIMON

IL

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

IGATE

OFB

4

CL

5

GND

IN

TMR

GND

FLT

CSP

6

CSN

BGATE

BAT

29

GND

7

CLN

CC

ENC

IBMON

CX

8

CHRG

BIAS

NTC

9

ITH

BFB

10

11

12

13

14

IID

CL

FBG

IGATE

OFB

CSP

CSN

FBG

9

10 11 12 13 14

UFD PACKAGE

BFB

BAT

BGATE

28-LEAD (4mm × 5mm) PLASTIC QFN

= 1ꢀ2°C, θ = 43°C/W, θ = 4°C/W

T

GN PACKAGE

28-LEAD PLASTIC SSOP

= 1ꢀ2°C, θ = 80°C/W, θ = ꢀ2°C/W

JMAX

JA

JC

EXPOSED PAD (PIN ꢀ9% IS GND, MUST BE SOLDERED TO PCB

T

JMAX

JA

JC

orDer inForMaTion

LEAD FREE FINISH

LTC4000EUFD#PBF

LTC4000IUFD#PBF

LTC4000EGN#PBF

LTC4000IGN#PBF

TAPE AND REEL

PART MARKING*

4000

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 1ꢀ2°C

LTC4000EUFD#TRPBF

LTC4000IUFD#TRPBF

LTC4000EGN#TRPBF

LTC4000IGN#TRPBF

ꢀ8-Lead (4mm × 2mm% Plastic QFN

ꢀ8-Lead Plastic SSOP

4000

LTC4000GN

ꢀ8-Lead Plastic SSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

4000f

2

LTC4000

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= ꢁ2°C. V_IN= V_CLN= 3V to 60V unless otherwise noted (Notes ꢁ, 3).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

Input Supply Operating Range

Input Quiescent Operating Current

Battery Pin Operating Current

Battery Only Quiescent Current

3

60

IN

I

0.4

20

10

mA

µA

IN

BAT

l

V

≥ 3V, V

≥ 0V, V

= V

≥ V

100

ꢀ0

IN

CSN

CSP

BAT

μA

BAT

Shutdown

l

ENC Input Voltage Low

ENC Input Voltage High

ENC Pull-Up Current

0.4

V

1.2

–4

V

= 0V

–ꢀ

–0.2

µA

V

ENC

l

ENC Open Circuit Voltage

= Open

1.2

ꢀ.2

ENC

Voltage Regulation

V

Battery Feedback Voltage

1.133

1.1ꢀ2

1.136

1.139

1.147

V

BFB_REG

l

BFB Input Current

V

= 1.ꢀV

0.1

1.193

0.1

µA

V

BFB

OFB

V

Output Feedback Voltage

1.181

96.9

1.ꢀ04

OFB_REG

OFB Input Current

µA

Ω

5

l

R

Ground Return Feedback Resistance

Rising Recharge Battery Threshold Voltage

100

97.6

0.2

400

FBG

V

5 of V

98.3

RECHRG(RISE%

RECHRG(HYS%

OUT(INST_ON%

LOBAT

BFB_REG

Recharge Battery Threshold Voltage Hysteresis 5 of V

l

Instant-On Battery Voltage Threshold

Falling Low Battery Threshold Voltage

Low Battery Threshold Voltage Hysteresis

5 of V

8ꢀ

62

86

90

71

68

3

LOBAT(HYS%

Current Regulation

l

Ratio of Monitored-Current Voltage to Sense

Voltage

V

= 20mV, V

CSP,CSN

/V

IIMON IN,CLN

19

ꢀ0

ꢀ1

V/V

IN,CLN

= 20mV, V

/V

IBMON CSP,CSN

V

Sense Voltage Offset

V

= 20mV, V

= 60V or

CSP

OS

CSP,CSN

IN,CLN

= 20mV, V = 60V (Note 4%

–300

300

µV

µA

μA

IN

CLN Pin Current

CSP Pin Current

CSN Pin Current

1

90

V

= Open, V = 0V

IID

IGATE

= Open, V = 0V

42

BGATE

BAT

l

I

Pull-Up Current for the Input Current Limit

Programming Pin

–22

–2.2

–20

–42

–4.2

IL

Pull-Up Current for the Charge Current Limit

Programming Pin

–20

μA

CL

Pull-Up Current for the Charge Current Limit

Programming Pin in Trickle Charge Mode

V

< V

–2.0

CL_TRKL

BFB

LOBAT

Input Current Monitor Resistance to GND

Charge Current Monitor Resistance to GND

40

90

0

140

10

kΩ

mV

l

A4, A2 Error Amp Offset for the Current Loops

(See Figure 1%

= 0.8V, V = 0.8V

–10

CL

IL

Maximum Programmable Current Limit

Voltage Range

0.982

1.0

1.012

V

4000f

3

LTC4000

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= ꢁ2°C. V_IN= V_CLN= 3V to 60V unless otherwise noted (Notes ꢁ, 3).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Charge Termination

l

CX Pin Pull-Up Current

V

= 0.1V

–2.2

0.2

–2.0

10

–4.2

ꢀ2

µA

mV

μA

Hz

V

CX

V

CX Comparator Offset Voltage, IBMON Falling

CX Comparator Hysteresis Voltage

TMR Pull-Up Current

CX,IBMON(OS%

CX,IBMON(HYS%

2

V

C

= 0V

–2.0

2.0

200

ꢀ.1

ꢀ.9

4

TMR

TMR Pull-Down Current

= 1.2V

= 0.01μF

TMR Pin Frequency

400

600

ꢀ.2

l

TMR Threshold for CX Termination

Charge Termination Time

t

C

= 0.1μF

ꢀ.3

3.2

h

T

TMR

t /t

T

Ratio of Charge Terminate Time to Bad Battery

Indicator Time

3.92

4.02

h/h

BB

l

V

NTC Cold Threshold

V

Rising, 5 of V

Falling, 5 of V

73

33

72

32

2

77

37

5

NTC(COLD%

NTC(HOT%

NTC(HYS%

NTC(OPEN%

NTC

BIAS

NTC Hot Threshold

BIAS

NTC Thresholds Hysteresis

NTC Open Circuit Voltage

NTC Open Circuit Input Resistance

5 of V

5

BIAS

l

42

20

300

22

5

R

kΩ

NTC(OPEN%

Voltage Monitoring and Open Drain Status Pins

V

VM Input Falling Threshold

VM Input Hysteresis

1.181

1.193

40

1.ꢀ04

V

mV

µA

V

VM(TH%

VM(HYS%

VM Input Current

V

= 1.ꢀV

= 60V

0.1

1

VM

I

Open Drain Status Pins Leakage Current

Open Drain Status Pins Voltage Output Low

RST,CHRG,FLT(LKG%

l

V

I

= 1mA

0.4

RST,CHRG,FLT(VOL%

Input PowerPath Control

Input PowerPath Forward Regulation Voltage

l

V

, 3V ≤ V

≤ 60V

≤ 60V,

0.1

8

ꢀ0

mV

IID,CSP

CSP

Input PowerPath Fast Reverse Turn-Off

Threshold Voltage

V

∆I

, 3V ≤ V

–90

–20

–ꢀ0

IID,CSP

CSP

= V

– ꢀ.2V,

CSP

IGATE

/∆ V

≥ 100μA/mV

IID,CSP

l

Input PowerPath Fast Forward Turn-On

Threshold Voltage

V

, 3V ≤ V

≤ 60V,

40

80

130

mV

IID,CSP

CSP

= V – 1.2V,

IGATE

IID

∆I

/∆ V

≥ 100μA/mV

IGATE

IID,CSP

Input Gate Turn-Off Current

Input Gate Turn-On Current

V

= V , V

= V – 1.2V

CSP

–0.3

0.3

μA

IID

CSP IGATE

V

= V – ꢀ0mV,

IID

= V – 1.2V

CSP

IGATE

IID

I

Input Gate Fast Turn-Off Current

Input Gate Fast Turn-On Current

Input Gate Clamp Voltage

V

= V + 0.1V,

IGATE

–0.2

0.7

13

mA

V

IGATE(FASTOFF%

CSP

IID

= V

– 2V

CSP

V

= V – 0.1V,

IID

IGATE(FASTON%

CSP

= V – 1.2V

IGATE

IID

l

V

I

= ꢀµA, V = 1ꢀV to 60V,

12

IGATE(ON%

IGATE

V

IID

= V – 0.2V, Measure

CSP

IID

IGATE

– V

Input Gate Off Voltage

I

= – ꢀμA, V = 3V to 29.9V,

0.42

0.7

V

IGATE

V

IID

= V + 0.2V, Measure

CSP

IID

IGATE

– V

4000f

4

LTC4000

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= ꢁ2°C. V_IN= V_CLN= 3V to 60V unless otherwise noted (Notes ꢁ, 3).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Battery PowerPath Control

l

Battery Discharge PowerPath Forward

V

, ꢀ.8V ≤ V ≤ 60V

0.1

8

ꢀ0

mV

BAT,CSN

BAT

Regulation Voltage

Battery PowerPath Fast Reverse Turn-Off

Threshold Voltage

, ꢀ.8V ≤ V ≤ 60V, Not

–90

–20

–ꢀ0

BAT,CSN

BAT

Charging, V

= V

– ꢀ.2V,

CSN

BGATE

∆I

/∆V

≥ 100μA/mV

BGATE

BAT,CSN

l

Battery PowerPath Fast Forward Turn-On

Threshold Voltage

V

, ꢀ.8V ≤ V

≤ 60V,

40

80

130

mV

μA

BAT,CSN

CSN

= V – 1.2V,

BGATE

BAT

∆I

BGATE

/∆ V

≥ 100μA/mV

BAT,CSN

Battery Gate Turn-Off Current

V

= V

– 1.2V, V

≥ V ,

BAT

–0.3

BGATE

OFB

CSN

< V

and Charging

OUT(INST_ON%

in Progress, or V

Charging

= V and Not

BAT

CSN

Battery Gate Turn-On Current

V

= V – 1.2V, V

≥ V ,

BAT

0.3

μA

BGATE

OFB

BAT

CSN

> V

and Charging in

OUT(INST_ON%

Progress, or V

= V – ꢀ0mV

BAT

CSN

I

Battery Gate Fast Turn-Off Current

Battery Gate Fast Turn-On Current

Battery Gate Clamp Voltage

V

= V + 0.1V and Not

–0.2

0.7

13

mA

V

BGATE(FASTOFF%

CSN

BAT

Charging, V

= V

– 2V

CSN

BGATE

V

= V – 0.1V,

BAT

BGATE(FASTON%

CSN

= V – 1.2V

BGATE

BAT

l

V

I

= ꢀμA, V = 1ꢀV to 60V,

12

BGATE(ON%

BGATE

V

BAT

= V – 0.2V, Measure

CSN

BAT

BGATE

– V

Battery Gate Off Voltage

I

= – ꢀμA, V = ꢀ.8V to 60V,

0.42

0.7

V

BGATE

BAT

V

= V + 0.2V and not Charging,

CSN

BAT

CSN

Measure V

– V

BGATE

BIAS Regulator Output and Control Pins

l

V

BIAS Output Voltage

No Load

ꢀ.4

ꢀ.9

–0.2

–1ꢀ

0.2

80

3.2

V

5

BIAS

∆V

BIAS Output Voltage Load Regulation

BIAS Output Short-Circuit Current

Transconductance of Error Amp

Open Loop DC Voltage Gain of Error Amp

Pull-Up Current on the ITH Pin

I

= – 0.2mA

= 0V

–10

BIAS

V

mA

mA/V

dB

BIAS

CC = 1V

CC = Open

I

V

= 0V, V = 0V

–6

–2

–4

μA

ITH(PULL_UP%

ITH

CC

l

Pull-Down Current on the ITH Pin

Open Loop DC Voltage Gain of ITH Driver

= 0.4V, CC = Open

0.2

1

mA

dB

ITH(PULL_DOWN%

ITH = Open

60

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors. The junction temperature (T , in °C% is calculated from the ambient

J

temperature (T , in °C% and power dissipation (P , in Watts% according to

A

D

the following formula:

Note ꢁ: The LTC4000 is tested under conditions such that T ≈ T . The

J

A

LTC4000E is guaranteed to meet specifications from 0°C to 82°C junction

temperature. Specifications over the –40°C to 1ꢀ2°C operating junction

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC4000I is guaranteed over the

full –40°C to 1ꢀ2°C operating junction temperature range. Note that the

maximum ambient temperature consistent with these specifications is

T = T + (P • θ %, where θ (in °C/W% is the package thermal

impedance.

Note 3: All currents into pins are positive; all voltages are referenced to

GND unless otherwise noted.

Note 4: These parameters are guaranteed by design and are not 1005

tested.

J A D JA JA

4000f

5

LTC4000

Typical perForMance characTerisTics

Input Quiescent Current and

Battery Float Voltage Feedback, Output

Voltage Regulation Feedback and VM

Falling Threshold Over Temperature

Battery Quiescent Current Over

Temperature

Battery Only Quiescent Current

Over Temperature

1.0

0.1

0

100

10

1.20

1.19

1.18

1.17

1.16

1.15

1.14

1.13

1.12

1.11

1.10

V

= V

CSN

= 15V

BAT

IN

= 15.5V

V

= 60V

= 15V

I

BAT

IN

V

OFB_REG

V

VM(TH)

1

I

BAT

V

= 3V

0.1

BFB_REG

BAT

0.01

0.001

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

4000 G01

4000 G02

4000 G03

Battery Thresholds: Rising Recharge,

Instant-On Regulation and Falling Low

Battery As a Percentage of Battery

Float Feedback Over Temperature

Maximum Programmable Current

Limit Voltage Over Temperature

IL and CL Pull-Up Current Over

Temperature

100

95

90

85

80

75

70

65

60

–45.0

–47.5

–50.0

–52.5

–55.0

1.015

1.010

1.005

1.000

0.995

0.990

0.985

V

RECHRG(RISE)

V

OUT(INST_ON)

V

LOBAT

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

4000 G04

4000 G05

4000 G06

Current Sense Offset Voltage

Over Temperature

CX Comparator Offset Voltage with

V_IBMONFalling Over Temperature

Current Sense Offset Voltage Over

Common Mode Voltage Range

300

200

100

0

300

200

100

0

20

19

18

17

16

15

14

13

12

11

10

9

V

= V

= 15V

MAX(CSP, CSN)

MAX(IN,CLN)

V

OS(CSP, CSN)

V

OS(IN, CSN)

–100

–200

–300

–100

–200

–300

8

7

6

5

4

3

–60 –40 –20

0

20 40 60 80 100 120 140

0

10

20

30

/V

40

50

(V)

60

–60 –40 –20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

V

TEMPERATURE (°C)

MAX(IN, CLN) MAX(CSP, CSN)

4000 G07

4000 G08

4000 G09

4000f

6

LTC4000

Typical perForMance characTerisTics

PowerPath Forward Voltage

Regulation Over Temperature

Charge Termination Time with 0.1µF

Timer Capacitor Over Temperature

NTC Thresholds Over

Temperature

3.5

3.3

3.1

2.9

2.7

2.5

2.3

80

75

70

65

60

55

50

45

40

35

30

V

14

12

10

8

NTC(COLD)

V

= V

= 15V

BAT

IID

V

= V

= 3V

BAT

IID

V

NTC(OPEN)

V

= V

= 60V

BAT

IID

6

4

V

NTC(HOT)

2

0

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

4000 G12

4000 G10

4000 G11

PowerPath Fast Off, Fast On

and Forward Regulation Over

Temperature

PowerPath Turn-On Gate Clamp

Voltage Over Temperature

PowerPath Turn-Off Gate Voltage

Over Temperature

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

600

550

500

450

400

350

300

250

200

V

= V

= 15V

V

IID

= V

= 15V

BAT

V

= V

= 15V

CSN

120

90

IID

BAT

CSP

60

30

0

–30

–60

–90

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

4000 G13

4000 G14

4000 G15

BIAS Voltage at 0.2mA Load Over

Temperature

I

_THPull-Down Current Over

I_THPull-Down Current

vs V_ITH

Temperature

3.2

3.1

3.0

2.9

2.8

2.7

2.6

2.5

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

2.5

2.0

1.5

1.0

0.5

0

V

ITH

= 0.4V

V

= 60V

IN

V

= 15V

IN

V

= 3V

IN

–60 –40 –20

0

20 40 60 80 100 120 140

–60 –40 –20

0

20 40 60 80 100 120 140

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

(V)

4000 G18

1

TEMPERATURE (°C)

V

ITH

4000 G16

4000 G17

4000f

7

LTC4000

pin FuncTions ^(QFN/SSOP)

VM(Pin1/Pinꢁ2):VoltageMonitorInput.Highimpedance

input to an accurate comparator with a 1.193V threshold

(typical%. This pin controls the state of the RST output

ENC (Pin 2/Pin 1): Enable Charging Pin. High impedance

digital input pin. Pull this pin above 1.2V to enable charg-

ing and below 0.2V to disable charging. Leaving this pin

open causes the internal 1µA pull-up current to pull the

pin to ꢀ.2V (typical%.

pin. Connect a resistor divider (R , R % between the

VM1 VMꢀ

monitored voltage and GND, with the center tap point con-

nected to this pin. The falling threshold of the monitored

voltage is calculated as follows:

IBMON (Pin 6/Pin ꢁ): Battery Charge Current Monitor. The

voltage on this pin is ꢀ0 times (typical% the sense voltage

R

_VM1+R_VMꢀ

R_VMꢀ

(V

% across the battery current sense resistor (R %,

CSP,CSN CS

V_{VM_RST}

=

• 1.193V

therefore providing a voltage proportional to the battery

charge current. Connect an appropriate capacitor to this

pin to obtain a voltage representation of the time-average

battery charge current. Short this pin to GND to disable

charge current limit feature.

where R

is the bottom resistor between the VM pin

VMꢀ

and GND. Tie to the BIAS pin if voltage monitoring func-

tion is not used.

RST(Pinꢁ/Pinꢁ6):HighVoltageOpenDrainResetOutput.

WhenthevoltageattheVMpinisbelow1.193V, thisstatus

pin is pulled low. When driven low, this pin can disable a

DC/DC converter when connected to the converter’s en-

able pin. This pin can also drive an LED to provide a visual

status indicator of a monitored voltage. Short this pin to

GND when not used.

CX (Pin 7/Pin 3): Charge Current Termination Pro-

gramming. Connect the charge current termination pro-

gramming resistor (R % to this pin. This pin is a high

CX

impedance input to a comparator and sources 2μA of

current. When the voltage on this pin is greater than the

charge current monitor voltage (V

%, the CHRG pin

IBMON

turns high impedance indicating that the CX threshold is

reached. When this occurs, the charge current is imme-

diately terminated if the TMR pin is shorted to the BIAS

pin, otherwise charging continues until the charge termi-

nationtimerexpires. Thechargecurrentterminationvalue

is determined using the following formula:

IIMON (Pin 3/Pin ꢁ7): Input Current Monitor. The voltage

on this pin is ꢀ0 times (typical% the sense voltage (V

%

IN,CLN

across the input current sense resistor(R %, therefore

IS

providing a voltage proportional to the input current.

Connect an appropriate capacitor to this pin to obtain a

voltage representation of the time-average input current.

Short this pin to GND to disable input current limit feature.

0.ꢀ2µA •R

− 0.2mV

(

=

)

CX

I_C/X

R_CS

IL (Pin 4/Pin ꢁ8): Input Current Limit Programming. Con-

nect the input current programming resistor (R % to this

IL

Where R is the sense resistor connected to the CSP

CS

pin. This pin sources 20µA of current. The regulation loop

and the CSN pins. Note that if R = R ≤ 19.1kΩ, where

CX

CL

compares the voltage on this pin with the input current

R

CL

is the charge current programming resistor, then the

monitor voltage (V

%, and drives the ITH pin accord-

IIMON

chargecurrentterminationvalueisonetenththefullcharge

current, more familiarly known as C/10. Short this pin to

GND to disable CX termination.

ingly to ensure that the programmed input current limit is

not exceeded. The input current limit is determined using

the following formula:

⎛

⎜

⎝

⎞

⎟

⎠

R_IL

I

= ꢀ.2µA •

ILIM

R

IS

where R is the sense resistor connected to the IN and

IS

the CLN pins. Leave the pin open for the maximum input

current limit of 20mV/R .

IS

4000f

8

LTC4000

pin FuncTions ^(QFN/SSOP)

CL(Pin8/Pin4):ChargeCurrentLimitProgramming.Con-

of these pins with an LED in series with a resistor to a

voltage source to provide a visual status indicator. Short

these pins to GND when not used.

nectthechargecurrentprogrammingresistor(R %tothis

CL

pin. This pin sources 20µA of current. The regulation loop

compares the voltage on this pin with the charge current

BIAS (Pin 13/Pin 9): ꢀ.9V Regulator Output. Connect a

capacitor of at least 470nF to bypass this ꢀ.9V regulated

voltage output. Use this pin to bias the resistor divider to

set up the voltage at the NTC pin.

monitor voltage (V

%, and drives the ITH pin accord-

IBMON

ingly to ensure that the programmed charge current limit

is not exceeded. The charge current limit is determined

using the following formula:

NTC (Pin 14/Pin 10): Thermistor Input. Connect a ther-

mistor from NTC to GND, and a corresponding resistor

fromBIAStoNTC. Thevoltagelevelonthispindetermines

if the battery temperature is safe for charging. The charge

current and charge timer are suspended if the thermistor

indicatesatemperaturethatisunsafeforcharging.Oncethe

temperature returns to the safe region, charging resumes.

Leave the pin open or connected to a capacitor to disable

the temperature qualified charging function.

⎛

⎜

⎝

⎞

⎟

⎠

R_CL

I_CLIM= ꢀ.2µA •

R

CS

Where R is the sense resistor connected to the CSP

CS

and the CSN pins. Leave the pin open for the maximum

charge current limit of 20mV/R .

CS

TMR (Pin 9/Pin 2): Charge Timer. Attach 1nF of external

capacitance(C

%toGNDforeach104secondsofcharge

TMR

termination time and ꢀ6 seconds of bad battery indicator

time. Short to GND to prevent bad battery indicator time

and charge termination time from expiring – allowing a

continuous trickle charge and top off float voltage regula-

tion charge. Short to BIAS to disable bad battery detect

and enable C/X charging termination.

FBG (Pin 12/Pin 11): Feedback Ground Pin. This is the

ground return pin for the resistor dividers connected to

the BFB and OFB pins. As soon as the voltage at IN is valid

(>3Vtypical%,thispinhasa100ΩresistancetoGND.When

the voltage at IN is not valid, this pin is disconnected from

GND to ensure that the resistor dividers connected to the

BFB and OFB pins do not continue to drain the battery

when the battery is the only available power source.

GND (Pins 10, ꢁ8, ꢁ9/Pins 6, ꢁ4): Device Ground Pins.

Connect the ground pins to a suitable PCB copper ground

plane for proper electrical operation. The QFN package

exposed pad must be soldered to PCB ground for rated

thermal performance.

BFB (Pin 16/Pin 1ꢁ): Battery Feedback Voltage Pin. This

pin is a high impedanceinputpin used to sensethe battery

voltage level. In regulation, the battery float voltage loop

sets the voltage on this pin to 1.136V (typical%. Connect

this pin to the center node of a resistor divider between

the BAT pin and the FBG pin to set the battery float voltage.

The battery float voltage can then be obtained as follows:

FLT, CHRG (Pin 11, Pin 1ꢁ/Pin 7, Pin 8): Charge Status

Indicator Pins. These pins are high voltage open drain pull

down pins. The FLT pin pulls down when there is an under

or over temperature condition during charging or when

the voltage on the BFB pin stays below the low battery

threshold during charging for a period longer than the bad

battery indicator time. The CHRG pin pulls down during

a charging cycle. Please refer to the application informa-

tion section for details on specific modes indicated by the

combination of the states of these two pins. Pull up each

R

_BFBꢀ+R

V

=

^BFB1• 1.136V

FLOAT

R_BFBꢀ

BAT (Pin 17/Pin 13): Battery Pack Connection. Connect

the battery to this pin. This pin is the anode of the battery

ideal diode driver (the cathode is the CSN pin%.

4000f

9

LTC4000

pin FuncTions ^(QFN/SSOP)

BGATE (Pin 18/Pin 14): External Battery PMOS Gate Drive

Output. When not charging, the BGATE pin drives the

external PMOS to behave as an ideal diode from the BAT

pin (anode% to the CSN pin (cathode%. This allows efficient

delivery of any required additional power from the battery

to the downstream system connected to the CSN pin.

OFB (Pin ꢁ1/Pin 17): Output Feedback Voltage Pin. This

pin is a high impedance input pin used to sense the output

voltagelevel.Inregulation,theoutputvoltageloopsetsthe

voltage on this feedback pin to 1.193V. Connect this pin

to the center node of a resistor divider between the CSP

pin and the FBG pin to set the output voltage when battery

charging is terminated and all the output load current is

provided from the input. The output voltage can then be

obtained as follows:

When charging a heavily discharged battery, the BGATE

pin is regulated to set the output feedback voltage (OFB

pin% to 865 of the battery float voltage (0.974V typical%.

This allows the instant-on feature, providing an immedi-

ate valid voltage level at the output when the LTC4000 is

charging a heavily discharged battery. Once the voltage

on the OFB pin is above the 0.974V typical value, then the

BGATE pin is driven low to ensure an efficient charging

path from the CSN pin to the BAT pin.

R

_OFBꢀ+R

V_OUT

=

^OFB1• 1.193V

R_OFBꢀ

Whenchargingaheavilydischargedbattery(suchthatV

OFB

<V

%, thebatteryPowerPathPMOSconnected

OUT(INST_ON%

to BGATE is regulated to set the voltage on this feedback

pin to 0.974V (approximately 865 of the battery float

voltage%. The instant-on output voltage is then as follows:

CSN(Pin19/Pin12):ChargeCurrentSenseNegativeInput

and Battery Ideal Diode Cathode. Connect a sense resistor

between this pin and the CSP pin. The LTC4000 senses

the voltage across this sense resistor and regulates it to

a voltage equal to 1/ꢀ0th (typical% of the voltage set at the

CL pin. The maximum regulated sense voltage is 20mV.

The CSN pin is also the cathode input of the battery ideal

diode driver (the anode input is the BAT pin%. Tie this pin

to theCSP pin ifnocharge currentlimit isdesired. Referto

the Applications Information section for complete details.

R

_OFBꢀ+R

V_{OUT(INST _ON%}

=

^OFB1• 0.974V

R_OFBꢀ

IGATE(Pinꢁꢁ/Pin18):InputPMOSGateDriveOutput.The

IGATE pin drives the external PMOS to behave as an ideal

diode from the IID pin (anode% to the CSP pin (cathode%.

IID (Pin ꢁ3/Pin 19): Input Ideal Diode Anode. This pin is

the anode of the input ideal diode driver (the cathode is

the CSP pin%.

CSP (Pin ꢁ0/Pin 16): Charge Current Sense Positive Input

and Input Ideal Diode Cathode. Connect a sense resis-

tor between this pin and the CSN pin for charge current

sensing and regulation. This input should be tied to CSN

to disable the charge current regulation function. This

pin is also the cathode of the input ideal diode driver (the

anode is the IID pin%.

ITH (Pin ꢁ4/Pin ꢁ0): High Impedance Control Voltage Pin.

When any of the regulation loops (input current, charge

current,batteryfloatvoltageortheoutputvoltage%indicate

that its limit is reached, the ITH pin will sink current (up to

1mA% to regulate that particular loop at the limit. In many

applications, this ITH pin is connected to the control/com-

pensationnodeofaDC/DCconverter.Withoutanyexternal

pull-up, the operating voltage range on this pin is GND to

ꢀ.2V. With an external pull-up, the voltage on this pin can

be pulled up to 6V. Note that the impedance connected to

this pin affects the overall loop gain. For details, refer to

the Applications Information section.

4000f

10

LTC4000

pin FuncTions ^(QFN/SSOP)

CC(Pinꢁ2/Pinꢁ1):ConverterCompensationPin.Connect

an R-C network from this pin to the ITH pin to provide a

suitable loop compensation for the converter used. Refer

to the Applications Information section for discussion and

procedure on choosing an appropriate R-C network for a

particular DC/DC converter.

IN (Pin ꢁ7/Pin ꢁ3): Input Supply Voltage: 3V to 60V.

Supplies power to the internal circuitry and the BIAS pin.

Connect the power source to the downstream system

and the battery charger to this pin. This pin is also the

positive sense pin for the input current limit. Connect a

sense resistor between this pin and the CLN pin. Tie this

pin to CLN if no input current limit is desired. A local 0.1µF

bypass capacitor to ground is recommended on this pin.

CLN (Pin ꢁ6/Pin ꢁꢁ): Input Current Sense Negative Input.

Connect a sense resistor between this pin and the IN pin.

The LTC4000 senses the voltage across this sense resis-

tor and regulates it to a voltage equal to 1/ꢀ0th (typical%

of the voltage set at the IL pin. Tie this pin to the IN pin if

no input current limit is desired. Refer to the Applications

Information section for complete details.

4000f

11

LTC4000

block DiagraM

R

IS

OUT

DC/DC CONVERTER

IN

SYSTEM

LOAD

C

L

C

CLN

IID

C

IN

C

IBMON

R

C

IN

CLN

RST

ITH

CC

IID

IGATE

IBMON

R

VM1

VM

CSP

CSN

CP1

–

+

–

VM2

R

CS

+

A9

g = 0.33m

m

8mV

1.193V

–

60k

A8

m

A1

g

= 0.33m

LINEAR

A2

GATE

DRIVER

AND

BGATE

–

8mV

+

VOLTAGE

CLAMP

INPUT IDEAL

DIODE DRIVER

A11

g

m

IIMON

ENABLE

CHARGING

0.974V

60k

BATTERY IDEAL DIODE

BIAS

ITH AND CC DRIVER

A5

AND INSTANT-ON DRIVER

A10

50µA

BIAS

R

OFB1

–

A4

g

m

+

–

IL

5µA/

50µA

R

IL

1V

–

g

m

+

CL

g

1V

m

–

R

CL

A7

OFB

BFB

IN

+

–

OFB

g

m

1.193V

1.136V

LDO,

BG,

REF

A6

CP6

REF

0.771V

–

+

–

g

m

R

OFB2

C

BIAS

NTC

+

BFB

R

BFB1

CP5

+

CP4

CP3

+

R

BFB2

–

TOO COLD

1.109V

–

FBG

NTC FAULT

LOGIC

+

–

BAT

CP2

–

+

BIAS

C

BAT

TOO HOT

+

–

5µA

10mV

R

NTC

+

–

BIAS

CX

BATTERY PACK

2µA

C

TMR

R

CX

TMR

OSCILLATOR

GND

ENC

CHRG

FLT

4000 BD

R3

Figure 1. LTC4000 Functional Block Diagram

4000f

12

LTC4000

operaTion

Overview

and the battery float voltage loop is disabled. Charging is

enabled when the ENC pin is left floating or pulled high

(≥1.2V%

The LTC4000 is designed to simplify the conversion of

any externally compensated DC/DC converter into a high

performance battery charger with PowerPath control. It

only requires the DC/DC converter to have a control or

external-compensation pin (usually named VC or ITH%

whose voltage level varies in a positive monotonic way

with its output. The output variable can be either output

voltage or output current. For the following discussion,

refer to the Block Diagram in Figure 1.

The LTC4000 offers several user configurable battery

charge termination schemes. The TMR pin can be config-

uredforeitherC/Xtermination,chargetimerterminationor

no termination. After a particular charge cycle terminates,

the LTC4000 features an automatic recharge cycle if the

battery voltage drops below 97.65 of the programmed

float voltage.

TheLTC4000includesfourdifferentregulationloops:input

current, charge current, battery float voltage and output

voltage (A4-A7%. Whichever loop requires the lowest volt-

age on the ITH pin for its regulation controls the external

DC/DC converter.

Trickle charge mode drops the charge current to one

tenth of the normal charge current (programmed using a

resistor from the CL pin to GND% when charging into an

over discharged or dead battery. When trickle charging,

a capacitor on the TMR pin can be used to program a

time out period. When this bad battery timer expires and

the battery voltage fails to charge above the low battery

The input current regulation loop ensures that the pro-

grammed input current limit (using a resistor at IL% is not

exceeded at steady state. The charge current regulation

loop ensures that the programmed battery charge current

limit(usingaresistoratCL%isnotexceeded. Thefloatvolt-

age regulation loop ensures that the programmed battery

stack voltage (using a resistor divider from BAT to FBG

via BFB% is not exceeded. The output voltage regulation

loop ensures that the programmed system output voltage

(using a resistor divider from CSP to FBG via OFB% is not

exceeded. The LTC4000 also provides monitoring pins

for the input current and charge current at the IIMON and

IBMON pins respectively.

threshold (V

%, the LTC4000 will terminate charging

LOBAT

and indicate a bad battery condition through the status

pins (FLT and CHRG%.

The LTC4000 also includes an NTC pin, which provides

temperaturequalifiedchargingwhenconnectedtoanNTC

thermistorthermallycoupledtothebatterypack.Toenable

this feature, connect the thermistor between the NTC and

the GND pins, and a corresponding resistor from the BIAS

pin to the NTC pin. The LTC4000 also provides a charging

status indicator through the FLT and the CHRG pins.

Aside from biasing the thermistor-resistor network, the

BIAS pin can also be used for a convenient pull up voltage.

This pin is the output of a low dropout voltage regulator

that is capable of providing up to 0.2mA of current. The

regulated voltage on the BIAS pin is available as soon as

the IN pin is within its operating range (≥3V%.

The LTC4000 features an ideal diode controller at the input

from the IID pin to the CSP pin and a PowerPath controller

at the output from the BAT pin to the CSN pin. The output

PowerPath controller behaves as an ideal diode controller

whennotcharging. Whencharging, theoutputPowerPath

controller has two modes of operation. If V

is greater

OFB

Input Ideal Diode

than V

, BGATE is driven low. When V

is

OUT(INST_ON%

OFB

less than V

, a linear regulator implements

OUT(INST_ON%

Theinputidealdiodefeatureprovideslowlossconduction

and reverse blocking from the IID pin to the CSP pin. This

reverse blocking prevents reverse current from the output

(CSP pin% to the input (IID pin% which causes unneces-

sary drain on the battery and in some cases may result

in unexpected DC/DC converter behavior.

the instant-on feature. This feature provides regulation of

the BGATE pin so that a valid voltage level is immediately

available at the output when the LTC4000 is charging an

over-discharged, dead or short faulted battery.

The state of the ENC pin determines whether charging

is enabled. When ENC is grounded, charging is disabled

4000f

13

LTC4000

operaTion

The ideal diode behavior is achieved by controlling an

external PMOS connected to the IID pin (drain% and the

CSPpin(source%.Thecontroller(A1%regulatestheexternal

PMOSbydrivingthegateofthePMOSdevicesuchthatthe

voltage drop across IID and CSP is 8mV (typical%. When

the external PMOS ability to deliver a particular current

with an 8mV drop across its source and drain is exceeded,

OncethebatteryvoltageisaboveV

,thechargecurrent

LOBAT

regulation loop begins charging in full power constant-

current mode. In this case, the programmed full charge

current is set with a resistor on the CL pin.

Depending on available input power and external load

conditions, the battery charger may not be able to charge

at the full programmed rate. The external load is always

prioritized over the battery charge current. The input

current limit programming is always observed, and only

additional power is available to charge the battery. When

systemloadsarelight,batterychargecurrentismaximized.

the voltage at the gate clamps at V

behaves like a fixed value resistor (R

and the PMOS

DS(ON%

IGATE(ON%

%.

Input Current Regulation and Monitoring

One of the loops driving the ITH and CC pins is the input

current regulation loop (Figure ꢀ%. This loop prevents

the input current sensed through the input current sense

Once the float voltage is achieved, the battery float volt-

age regulation loop takes over from the charge current

regulation loop and initiates constant voltage charging. In

constantvoltagecharging,chargecurrentslowlydeclines.

resistor (R % from exceeding the programmed input

IS

current limit.

R

IS

Charge termination can be configured with the TMR pin

in several ways. If the TMR pin is tied to the BIAS pin,

C/X termination is selected. In this case, charging is

terminated when constant voltage charging reduces the

charge current to the C/X level programmed at the CX

pin. Connecting a capacitor to the TMR pin selects the

charge timer termination and a charge termination timer

is started at the beginning of constant voltage charging.

Charging terminates when the termination timer expires.

When continuous charging at the float voltage is desired,

tie the TMR pin to GND to disable termination.

IN

LOAD

C

CLN

(OPTIONAL)

C

IN

CLN

A8

LTC4000

CC

A8

g

= 0.33m

m

IIMON

BIAS

C

IIMON

(OPTIONAL)

60k

+

–

R

C

–

50µA

ITH

TO DC/DC

1V

–

+

R

IL

A4

IL

4000 FO2

Figure ꢁ. Input Current Regulation Loop

Upon charge termination, the PMOS connected to BGATE

behaves as an ideal diode from BAT to CSN. The diode

function prevents charge current but provides current

to the system load as needed. If the system load can be

completelysuppliedfromtheinput,thebatteryPMOSturns

off. While terminated, if the input current limit is not in

regulation,theoutputvoltageregulationlooptakesoverto

ensure that the output voltage at CSP remains in control.

The output voltage regulation loop regulates the voltage

at the CSP pin such that the output feedback voltage at

the OFB pin is 1.193V.

Battery Charger Overview

In addition to the input current regulation loop, the

LTC4000 regulates charge current, battery voltage and

output voltage.

When a battery charge cycle begins, the battery charger

firstdeterminesifthebatteryisover-discharged. Ifthebat-

tery feedback voltage is below V

charge feature uses the charge current regulation loop to

set the battery charge current to 105 of the programmed

full scale value. If the TMR pin is connected to a capacitor

or open, the bad battery detection timer is enabled. When

thisbadbatterydetectiontimerexpiresandthebatteryvolt-

, an automatic trickle

LOBAT

If the system load requires more power than is available

from the input, the battery ideal diode controller provides

supplemental power from the battery. When the battery

voltage discharges below 97.15 of the float voltage

age is still below V

, the battery charger automatically

LOBAT

terminates and indicates, via the FLT and CHRG pins, that

(V

< V

%, the automatic recharge feature

BFB

RECHRG(FALL%

the battery was unresponsive to charge current.

initiates a new charge cycle.

4000f

14

LTC4000

operaTion

LTC4000

Charge Current Regulation

CC

BAT

BFB

R

C

BFB1

The first loop involved in a normal charging cycle is the

chargecurrentregulationloop(Figure3%.Aswiththeinput

current regulation loop, this loop also drives the ITH and

CC pins. This loop ensures that the charge current sensed

through the charge current sense resistor (R % does not

exceed the programmed full charge current.

+

–

R

C

–

+

ITH

1.136V

TO DC/DC

BFB2

FBG

A6

4000 FO4

CS

Figure 4. Battery Float Voltage Regulation Loop with FBG

TO SYSTEM

R

IS

CSP

BAT PMOS

LTC4000

CC

CSP

OFB

C

CSP

R

C

OFB1

C

+

–

R

C

–

+

CSP

CSN

A9

LTC4000

CC

ITH

1.193V

TO DC/DC

OFB2

FBG

A7

g

= 0.33m

m

IBMON

C

IBMON

4000 FO5

60k

+

–

(OPTIONAL)

BIAS

R

C

–

+

ITH

Figure 2. Output Voltage Regulation Loop with FBG

TO DC/DC

1V

–

50µA AT NORMAL

5µA AT TRICKLE

A5

R

CL

Battery Instant-On and Ideal Diode

4000 FO3

TheLTC4000controlstheexternalPMOSconnectedtothe

BGATE pin with a controller similar to the input ideal diode

controller driving the IGATE pin. When not charging, the

PMOS behaves as an ideal diode between the BAT (anode%

and the CSN (cathode% pins. The controller (Aꢀ% regulates

the external PMOS to achieve low loss conduction by driv-

ing the gate of the PMOS device such that the voltage drop

from the BAT pin to the CSN pin is 8mV. When the ability

to deliver a particular current with an 8mV drop across

the PMOS source and drain is exceeded, the voltage at

Figure 3. Charge Current Regulation Loop

Battery Voltage Regulation

Once the float voltage is reached, the battery voltage regu-

lation loop takes over from the charge current regulation

loop (Figure 4%.

The float voltage level is programmed using the feedback

resistor divider between the BAT pin and the FBG pin with

the center node connected to the BFB pin. Note that the

ground return of the resistor divider is connected to the

FBG pin. The FBG pin disconnects the resistor divider

the gate clamps at V

and the PMOS behaves like

%.

BGATE(ON%

a fixed value resistor (R

DS(ON%

load when V < 3V to ensure that the float voltage resis-

IN

The ideal diode behavior allows the battery to provide cur-

rent to the load when the input supply is in current limit

or the DC/DC converter is slow to react to an immediate

load increase at the output. In addition to the ideal diode

behavior, BGATE also allows current to flow from the CSN

pin to the BAT pin during charging.

tor divider does not consume battery current when the

battery is the only available power source. For V ≥ 3V,

IN

the typical resistance from the FBG pin to GND is 100Ω.

Output Voltage Regulation

When charging terminates and the system load is com-

pletely supplied from the input, the PMOS connected to

BGATE is turned off. In this scenario, the output voltage

regulation loop takes over from the battery float voltage

regulation loop (Figure 2%. The output voltage regulation

loop regulates the voltage at the CSP pin such that the

output feedback voltage at the OFB pin is 1.193V.

Therearetworegionsofoperationwhencurrentisflowing

from the CSN pin to the BAT pin. The first is when charg-

ing into a battery whose voltage is below the instant-on

threshold (V < V

%. In this region of opera-

OFB

OUT(INST_ON%

tion, the controller regulates the voltage at the CSP pin

4000f

15

LTC4000

operaTion

to be approximately 865 of the final float voltage level

Input UVLO and Voltage Monitoring

(V %. This feature provides a CSP voltage sig-

OUT(INST_ON%

The regulated voltage on the BIAS pin is available as soon

nificantly higher than the battery voltage when charging

into a heavily discharged battery. This instant-on feature

allows the LTC4000 to provide sufficient voltage at the

output (CSP pin%, independent of the battery voltage.

as V ≥ 3V. When V ≥ 3V, the FBG pin is pulled low to

IN

GND with a typical resistance of 100Ω and the rest of the

chip functionality is enabled.

When the IN pin is high impedance and a battery is con-

nected to the BAT pin, the BGATE pin is pulled down with

a ꢀμA (typical% current source to hold the battery PMOS

Thesecondregionofoperationiswhenthebatteryfeedback

voltage is greater than or equal to the instant-on threshold

(V

%. In this region, the BGATE pin is driven

OUT(INST_ON%

low and clamped at V

gate voltage at V

below V . This allows the

BGATE(ON%

BAT

to allow the PMOS to turn

BGATE(ON%

battery to power the output. The total quiescent current

consumed by LTC4000 from the battery when IN is not

valid is typically ≤ 10µA.

completely on, reducing any power dissipation due to the

charge current.

Battery Temperature Qualified Charging

BesidestheinternalinputUVLO,theLTC4000alsoprovides

voltage monitoring through the VM pin. The RST pin is

pulled low when the voltage on the VM pin falls below

1.193V (typical%. On the other hand, when the voltage on

the VM pin rises above 1.ꢀ33V (typical%, the RST pin is

high impedance.

The battery temperature is measured by placing a nega-

tive temperature coefficient (NTC% thermistor close to the

battery pack. The comparators CP3 and CP4 implement

the temperature detection as shown in the Block Diagram

in Figure 1. The rising threshold of CP4 is set at 725 of

V

(cold threshold% and the falling threshold of CP3 is

One common use of this voltage monitoring feature is to

ensure that the converter is turned off when the voltage

at the input is below a certain level. In this case, connect

the RST pin to the DC/DC converter chip select or enable

pin (see Figure 6%.

BIAS

set at 325 of V

(hot threshold%. When the voltage at

BIAS

the NTC pin is above 725 of V

or below 325 of V

BIAS

then the LTC4000 pauses any charge cycle in progress.

When the voltage at the NTC pin returns to the range of

405 to 705 of V

, charging resumes.

BIAS

R

IS

DC/DC

IN CONVERTER

When charging is paused, the external charging PMOS

turns off and charge current drops to zero. If the LTC4000

is charging in the constant voltage mode and the charge

termination timer is enabled, the timer pauses until the

thermistor indicates a return to a valid temperature. If the

battery charger is in the trickle charge mode and the bad

battery detection timer is enabled, the bad battery timer

pauses until the thermistor indicates a return to a valid

temperature.

IN

EN

R

VM1

VM2

IN

CLN

RST

CP1

VM

–

1.193V

+

LTC4000

4000 FO6

Figure 6. Input Voltage Monitoring with RST Connected to

the EN Pin of the DC/DC Converter

4000f

16

LTC4000

applicaTions inForMaTion

Input Ideal Diode PMOS Selection

The input current through the sense resistor is available

for monitoring through the IIMON pin. The voltage on

the IIMON pin varies with the current through the sense

resistor as follows:

TheinputexternalPMOSisselectedbasedontheexpected

maximum current, power dissipation and reverse volt-

age drop. The PMOS must be able to withstand a gate to

source voltage greater than V

(12V maximum% or

V

= ꢀ0 •I_RIS•R = ꢀ0 • V – V

IN

IS CLN

(

)

IGATE(ON%

IIMON

the maximum regulated voltage at the IID pin, whichever

is less. A few appropriate external PMOS for a number of

different requirements are shown at Table 1.

The regulation voltage level at the IIMON pin is clamped

at 1V with an accurate internal reference. At 1V on the

IIMON pin, the input current limit is regulated at the fol-

lowing value:

Table 1. PMOS

R

V

AT

DS(ON)

GS

(Ω)

= 10V MAX ID MAX VDS

0.020V

R_IS(Ω%

I_ILIM(MAX%(A% =

PART NUMBER

SiA9ꢀ3EDJ

Si9407BDY

Si4401BDY

Si4432DDY

SUD19P06-60

Si7132DP

(A)

(V)

–ꢀ0

–60

–40

–30

–60

–30

MANUFACTURER

Vishay

0.024

0.1ꢀ0

0.014

0.0ꢀ4

0.060

0.004

4.2

4.7

Vishay

When this maximum current limit is desired, leave the IL

pin open or set it to a voltage >1.02V such that amplifier

A4canregulatetheIIMONvoltageaccuratelytotheinternal

reference of 1V.

10.2

11.4

18.3

60

Vishay

If the input current is noisy, add a filter capacitor to the

CLN pin to reduce the AC content. For example, when us-

Note that in general the larger the capacitance seen on

the IGATE pin, the slower the response of the ideal diode

driver. The fast turn off and turn on current is limited to

ing a buck DC/DC converter, the use of a C

capacitor

CLN

is strongly recommended. Where the highest accuracy is

important, pick the value of C such that the AC content

CLN

–0.2mAand0.7mAtypicalrespectively(I

IGATE(FASTON%

and

IGATE(FASTOFF%

%. If the driver can not react fast enough to a

is less than or equal to 205 of the average voltage across

the sense resistor.

I

sudden increase in load current, most of the extra current

is delivered through the body diode of the external PMOS.

This increases the power dissipation momentarily. It is

important to ensure that the PMOS is able to withstand

this momentary increase in power dissipation.

The voltage on the IIMON pin can be filtered further by

putting a capacitor on the pin (C %. The voltage on the

IIMON

IIMON pin is also the feedback input to the input current

regulation error amplifier. Any capacitor connected to

this pin places a pole in the input current regulation loop.

Therefore, this filter capacitor should NOT be arbitrarily

large as it will slow down the overall compensated loop.

For details on loop compensation please refer to the

Compensation section.

Input Current Limit Setting and Monitoring

The regulated input current limit is set using a resistor at

the IL pin according to the following formula:

V

IL

R_IS=

ꢀ0 •I

ILIM

whereV isthevoltageontheILpin.TheILpinisinternally

IL

pulledupwithanaccuratecurrentsourceof20µA.Therefore

an equivalent formula to obtain the input current limit is:

I_LIM•R_IS

ꢀ.2µA

R_IL

R_IS

R_IL=

⇒ I

=

• ꢀ.2µA

ILIM

4000f

17

LTC4000

applicaTions inForMaTion

Charge Current Limit Setting and Monitoring

currentregulation loop. Fordetails on theloop compensa-

tion, refer to the Compensation section.

The regulated full charge current is set according to the

following formula:

Battery Float Voltage Programming

V_CL

ꢀ0 •I_CLIM

WhenthevalueofR

ismuchlargerthan100Ω,thefinal

R_CS

=

BFB1

float voltage is determined using the following formula:

where V is the voltage on the CL pin. The CL pin is

CL

⎛

⎞

V

FLOAT

R_BFB1

=

– 1 R

⎟

BFBꢀ

⎜

⎝

internally pulled up with an accurate current source of

20µA. Therefore, an equivalent formula to obtain the input

current limit is:

⎠

1.136V

When higher accuracy is important, a slightly more ac-

curate final float voltage can be determined using the

following formula:

I_CLIM•R_CS

R_CL

R_CS

R_CL

=

⇒ I_CLIM

=

• ꢀ.2µA

ꢀ.2µA

⎛

⎜

⎝

⎞ ⎛

⎞

⎟

⎠

R

_BFB1+R_BFBꢀ

R_BFB1

The charge current through the sense resistor is available

for monitoring through the IBMON pin. The voltage on

the IBMON pin varies with the current through the sense

resistor as follows:

V

=

• 1.136V –

⎟ ⎜

• V

FBG

FLOAT

R_BFBꢀ

R

⎠ ⎝

BFBꢀ

where V

is the voltage at the FBG pin during float

FBG

voltage regulation, which accounts for all the current

from all resistor dividers that are connected to this pin

V

= ꢀ0 •I_RCS•R_CS= ꢀ0 • V

– V_CSN

(

)

IBMON

CSP

(R

= 100Ω typical%.

FBG

Similar to the IIMON pin, the regulation voltage level at

the IBMON pin is clamped at 1V with an accurate internal

reference. At 1V on the IBMON pin, the charge current

limit is regulated to the following value:

Low Battery Trickle Charge Programming and Bad

Battery Detection

When charging into an over-discharged or dead battery

0.020V

R_CS(Ω%

(V <V

%,thepull-upcurrentattheCLpinisreduced

BFB

LOBAT

I_CLIM(MAX%(A% =

to105ofthenormalpull-upcurrent.Therefore,thetrickle

charge current is set using the following formula:

When this maximum charge current limit is desired, leave

the CL pin open or set it to a voltage >1.02V such that

amplifierA2canregulatetheIBMONpinvoltageaccurately

to the internal reference of 1V.

I_CLIM(TRKL%•R_CS

R_CL

R_CS

R_CL

=

⇒ I_CLIM(TRKL%= 0.ꢀ2µA •

0.ꢀ2µA

Therefore, when 50µA•R is less than 1V, the following

relation is true:

CL

WhentheoutputcurrentwaveformoftheDC/DCconverter

orthesystemloadcurrentisnoisy, itisrecommendedthat

I_CLIM

10

a capacitor is connected to the CSP pin (C %. This is to

CSP

I_CLIM(TRKL%

=

reduce the AC content of the current through the sense

resistor (R %. Where the highest accuracy is important,

CS

Oncethebatteryvoltagerisesabovethelowbatteryvoltage

threshold, the charge current level rises from the trickle

charge current level to the full charge current level.

pick the value of C

such that the AC content is less

CSP

than or equal to 205 of the average voltage across the

sense resistor. Similar to the IIMON pin, the voltage on the

IBMON pin is filtered further by putting a capacitor on the

The LTC4000 also features bad battery detection. This

detection is disabled if the TMR pin is grounded or tied

to BIAS. However, when a capacitor is connected to the

pin (C

%. This filter capacitor should not be arbitrarily

IBMON

large as it will slow down the overall compensated charge

4000f

18

LTC4000

applicaTions inForMaTion

TMR pin, a bad battery detection timer is started as soon

as trickle charging starts. If at the end of the bad battery

detection time the battery voltage is still lower than the

low battery threshold, charging is terminated and the part

indicates a bad battery condition by pulling the FLT pin low

and leaving the CHRG pin high impedance.

Forexample,atypicalcapacitanceof1nFrequiresacapaci-

tor greater than 100nF connected to the CX pin to ensure

proper C/X termination behavior.

If a capacitor is connected to the TMR pin, as soon as the

constant voltage charging is achieved, a charge termina-

tion timer is started. When the charge termination timer

expires, the charge cycle terminates. The total charge

termination time can be programmed according to the

following formula:

The bad battery detection time can be programmed ac-

cording to the following formula:

C_TMR(nF% = t_BADBAT(h% • 138.2

C_TMR(nF% = t_TERMINATE(h% • 34.6

Note that once a bad battery condition is detected, the

condition is latched. In order to re-enable charging, re-

movethebatteryandconnectanewbatterywhosevoltage

causes BFB to rise above the recharge battery threshold

RECHRG(RISE%

and reapply power to IN.

IftheTMRpinisgrounded, chargingneverterminatesand

the battery voltage is held at the float voltage. Note that

regardless of which termination behavior is selected, the

CHRG and FLT pins will both assume a high impedance

state as soon as the charge current falls below the pro-

grammed C/X level.

(V

%.AlternativelytoggletheENCpinorremove

C/X Detection, Charge Termination and Automatic

Recharge

After the charger terminates, the LTC4000 automatically

restartsanotherchargecycleifthebatteryfeedbackvoltage

drops below 97.15 of the programmed final float voltage

Once the constant voltage charging is reached, there are

two ways in which charging can terminate. If the TMR pin

is tied to BIAS, the battery charger terminates as soon as

the charge current drops to the level programmed by the

CX pin. The C/X current termination level is programmed

according to the following formula:

(V

%. When charging restarts, the CHRG pin

RECHRG(FALL%

pulls low and the FLT pin remains high impedance.

Output Voltage Regulation Programming

The output voltage regulation level is determined using

the following formula:

0.ꢀ2µA •R − 0.2mV

I_C/X•R_CS

0.ꢀ2µA

(

+ 0.2mV ⇒ I_C/X=

)

CX

R_CX

=

⎛

⎞

R_CS

V_OUT

1.193

R_OFB1

=

−1 •R

⎟

OFBꢀ

⎜

⎝

⎠

where R is the charge current sense resistor connected

CS

between the CSP and the CSN pins.

As in the battery float voltage calculation, when higher

accuracy is important, a slightly more accurate output is

determined using the following formula:

When the voltage at BFB is higher than the recharge

threshold (97.65 of float%, the C/X comparator is enabled.

In order to ensure proper C/X termination coming out of

a paused charging condition, connect a capacitor on the

CX pin according to the following formula:

⎛

⎜

⎝

⎞ ⎛

⎞

⎟

⎠

R

_OFB1+R_OFBꢀ

R_OFB1

V_OUT

=

• 1.193V –

• V

FBG

⎟ ⎜

⎠ ⎝

R_OFBꢀ

R

OFBꢀ

C

= 100C

BGATE

CX

where V

is the voltage at the FBG pin during output

FBG

voltage regulation, which accounts for all the current from

all resistor dividers that are connected to this pin.

where C

is the total capacitance connected to the

BGATE

BGATE pin.

4000f

19

LTC4000

applicaTions inForMaTion

Battery Instant-On and Ideal Diode External PMOS

Consideration

On the other hand, when the battery voltage is above the

low battery threshold but still belowthe instant-on thresh-

old, the power dissipation can be calculated as follows:

The instant-on voltage level is determined using the fol-

lowing formula:

P

= 0.86 • V

– V

•I

BAT

CLIM

[

]

INST _ON

FLOAT

R

_OFB1+R_OFBꢀ

where I

is the full scale charge current limit.

CLIM

V_{OUT(INST _ON%}

Note that R

=

• 0.974V

R_OFBꢀ

For example, when charging a 3-cell Lithium Ion battery

with a programmed full charged current of 1A, the float

voltage is 1ꢀ.6V, the bad battery voltage level is 8.22V and

the instant-on voltage level is 10.8V. During instant-on

operation and in the trickle charge mode, the worst case

maximum power dissipation in the PMOS is 1.08W. When

the battery voltage is above the bad battery voltage level,

thentheworstcasemaximumpowerdissipationisꢀ.ꢀ2W.

and R

are the same resistors that

OFB1

OFBꢀ

program the output voltage regulation level. Therefore,

the output voltage regulation level is always 1ꢀꢀ.25 of

the instant-on voltage level.

During instant-on operation, it is critical to consider the

charging PMOS power dissipation. When the battery volt-

age is below the low battery threshold (V

dissipation in the PMOS can be calculated as follows:

%, the power

LOBAT

When overheating of the charging PMOS is a concern, it is

recommended that the user add a temperature detection

circuit that pulls down on the NTC pin. This pauses charg-

ing whenever the external PMOS temperature is too high.

A sample circuit that performs this temperature detection

function is shown in Figure 7.

P_TRKL= 0.86 • V – V •I

[

]

BAT

FLOAT

CLIM(TRKL%

where I

is the trickle charge current limit.

CLIM(TRKL%

TO SYSTEM

VISHAY CURVE 2

NTC RESISTOR

THERMALLY COUPLED

WITH CHARGING PMOS

CSP

R

CS

LTC4000

R

NTC2

CSN

BGATE

BAT

M2

R4 = R

AT 25°C

NTC2

BIAS

NTC

C

BIAS

162k

R3

2N7002L

RISING

–

+

TEMPERATURE

THRESHOLD

SET AT 90°C

Li-Ion

BATTERY PACK

LTC1540

R

20k

NTC1

VOLTAGE HYSTERESIS CAN

BE PROGRAMMED FOR

TEMPERATURE HYSTERESIS

86mV ≈ 10°C

4000 F07

Figure 7. Charging PMOS Overtemperature Detection Circuit

Protecting PMOS from Overheating

4000f

20

LTC4000

applicaTions inForMaTion

Similar to the input external PMOS, the charging external

In the typical application, V

is set higher than V

OUT FLOAT

to ensure that the battery is charged fully to its intended

PMOS must be able to withstand a gate to source voltage

greater than V

(12V maximum% or the maximum

float voltage. On the other hand, V

programmed too high since V

voltage on CSP, depends on the same resistors R

should not be

, the minimum

BGATE(ON%

OUT

OUT(INST_ON%

regulatedvoltageattheCSPpin,whicheverisless.Consider

the expected maximum current, power dissipation and

instant-on voltage drop when selecting this PMOS. The

PMOS suggestions in Table 1 are an appropriate starting

point depending on the application.

and

OFB1

R

that set V . As noted before, this means that the

OFBꢀ

OUT

output voltage regulation level is always 1ꢀꢀ.25 of the

instant-on voltage. The higher the programmed value of

V

, the larger the operating region when the

OUT(INST_ON%

Float Voltage, Output Voltage and Instant-On Voltage

Dependencies

charger PMOS is driven in the linear region where it is

less efficient.

The formulas for setting the float voltage, output voltage

and instant-on voltage are repeated here:

If R

and R

are set to be equal to R

and R

OFB1

OFBꢀ

BFB1 BFBꢀ

respectively, then the output voltage is set at 1025 of

the float voltage and the instant-on voltage is set at 865

of the float voltage. Figure 8 shows the range of possible

R

_BFB1+R_BFBꢀ

V

=

• 1.136V

FLOAT

R_BFBꢀ

_OFB1+R_OFBꢀ

R_OFBꢀ

output voltages that can be set for V

with respect to V

charged in an ideal scenario.

and V

OUT(INST_ON%

OUT

R

to ensure the battery can be fully

FLOAT

V_OUT

=

• 1.193V

R

_OFB1+R_OFBꢀ

Taking into account possible mismatches between the

resistor dividers as well as mismatches in the various

V_{OUT(INST _ON%}

=

• 0.974V

R_OFBꢀ

regulation loops, V

should not be programmed to

OUT

be less than 1025 of V

to ensure that the battery

FLOAT

can be fully charged. This automatically means that the

instant-on voltage level should not be programmed to be

less than 865 of V

.

FLOAT

POSSIBLE POSSIBLE

OUTPUT INSTANT-ON

VOLTAGE RANGE VOLTAGE RANGE

105%

100%

MINIMUM PRACTICAL

OUTPUT VOLTAGE

NOMINAL OUTPUT VOLTAGE

NOMINAL FLOAT VOLTAGE

100%

86%

MINIMUM PRACTICAL

INSTANT-ON VOLTAGE

NOMINAL INSTANT-ON VOLTAGE

81.6%

75%

4000 F08

Figure 8. Possible Voltage Ranges for V_OUTand

V_{OUT(INST_ON)}in Ideal Scenario

4000f

21

LTC4000

applicaTions inForMaTion

Battery Temperature Qualified Charging

Notice that with only one degree of freedom (i.e. adjusting

the value of R3%, the user can only use one of the formu-

las above to set either the cold or hot threshold but not

both. If the value of R3 is set to adjust the cold threshold,

the value of the NTC resistor at the hot threshold is then

To use the battery temperature qualified charging feature,

connect an NTC thermistor, R , between the NTC pin

NTC

and the GND pin, and a bias resistor, R3, from the BIAS

pin to the NTC pin (Figure 9%. Thermistor manufacturer

datasheets usually include either a temperature lookup

table or a formula relating temperature to the resistor

value at that corresponding temperature.

equal to 0.179 • R

at cold_threshold. Similarly, if the

NTC

value of R3 is set to adjust the hot threshold, the value

of the NTC resistor at the cold threshold is then equal to

5.571 • R

at cold_threshold.

NTC

Note that changing the value of R3 to be larger than Rꢀ2

will move both the hot and cold threshold lower and vice

versa. For example, using a Vishay Curve ꢀ thermistor

whose nominal value at ꢀ2°C is 100k, the user can set

the cold temperature to be at 2°C by setting the value of

R3 = 72k, which automatically then sets the hot threshold

at approximately 20°C.

BIAS

C

BIAS

LTC4000

R3

NTC

BAT

NTC RESISTOR

THERMALLY COUPLED

WITH BATTERY PACK

R

NTC

4000 F09

It is possible to adjust the hot and cold threshold indepen-

dently by introducing another resistor as a second degree

Figure 9. NTC Thermistor Connection

of freedom (Figure 10%. The resistor R in effect reduces

D

In a simple application, R3 is a 15 resistor with a value

equal to the value of the chosen NTC thermistor at ꢀ2°C

(Rꢀ2%. In this simple setup, the LTC4000 will pause charg-

ing when the resistance of the NTC thermistor drops to

0.24 times the value of Rꢀ2. For a Vishay Curve ꢀ therm-

istor, this corresponds to approximately 41.2°C. As the

temperature drops, the resistance of the NTC thermistor

rises. The LTC4000 is also designed to pause charging

when the value of the NTC thermistor increases to three

times the value of Rꢀ2. For a Vishay Curve ꢀ thermistor,

this corresponds to approximately –1.2°C. With Vishay

Curve ꢀ thermistor, the hot and cold comparators each

haveapproximately2°Cofhysteresistopreventoscillation

about the trip point.

the sensitivity of the resistance between the NTC pin and

ground.Therefore,intuitivelythisresistorwillmovethehot

threshold to a hotter temperature and the cold threshold

to a colder temperature.

BIAS

C

BIAS

LTC4000

R3

NTC

BAT

R

D

NTC RESISTOR

THERMALLY COUPLED

WITH BATTERY PACK

R

NTC

4000 F10

Figure 10. NTC Thermistor Connection with

Desensitizing Resistor R_D

The hot and cold threshold can be adjusted by changing

the value of R3. Instead of simply setting R3 to be equal to

Rꢀ2, R3 is set according to one of the following formulas:

R_NTCat cold_ threshold

R3 =

3

or

R3 = 1.827 •R_NTCat hot_ threshold

4000f

22

LTC4000

applicaTions inForMaTion

The value of R3 and R can now be set according to the

The FLT and CHRG Indicator Pins

D

following formula:

The FLT and CHRG pins in the LTC4000 provide status

indicators. Table ꢀ summarizes the mapping of the pin

states to the part status.

R_NTCat cold_ threshold – R_NTCat hot_ threshold

R3 =

ꢀ.461

R_D= 0.ꢀ19 •R_NTCat cold_ threshold –

Table ꢁ. FLT and CHRG Status Indicator

1.ꢀ19 •R_NTCat hot_ threshold

FLT

0

CHRG STATUS

0

1

NTC Over Ranged – Charging Paused

Note the important caveat that this method can only be

used to desensitize the thermal effect on the thermistor

and hence push the hot and cold temperature thresholds

apart from each other. When using the formulas above,

1

Charging Normally

0

Charging Terminated and Bad Battery Detected

1

V < (V – 10mV%

IBMON C/X

if the user finds that a negative value is needed for R ,

where 1 indicates a high impedance state and 0 indicates

a low impedance pull-down state.

D

the two temperature thresholds selected are too close to

each other and a higher sensitivity thermistor is needed.

Note that V

< (V – 10mV% corresponds to charge

CX

IBMON

For example, this method can be used to set the hot

and cold thresholds independently to 60°C and –2°C.

Using a Vishay Curve ꢀ thermistor whose nominal value

at ꢀ2°C is 100k, the formula results in R3 = 130k and

termination only if the C/X termination is selected. If the

charger timer termination is selected, constant voltage

charging may continue for the remaining charger timer

period even after the indicator pins indicate that V

IBMON

R = 41.ꢀk for the closest 15 resistors values.

< (V – 10mV%. This is also true when no termination is

D

CX

selected,constantvoltagechargingwillcontinueevenafter

Toincreasethermalsensitivitysuchthatthevalidcharging

temperature band is much smaller than 40°C, it is pos-

sible to put a PTC (positive thermal coefficient% resistor

in series with R3 between the BIAS pin and the NTC pin.

This PTC resistor also needs to be thermally coupled with

the battery. Note that this method increases the number of

thermal sensing connections to the battery pack from one

wire to three wires. The exact value of the nominal PTC

resistor required can be calculated using a similar method

as described above, keeping in mind that the threshold at

the indicator pins indicate that V

< (V – 10mV%.

IBMON

CX

The BIAS Pin

For ease of use the LTC4000 provides a low dropout volt-

age regulator output on the BIAS pin. Designed to provide

up to 0.2mA of current at ꢀ.9V, this pin requires at least

470nF of low ESR bypass capacitance for stability.

Use the BIAS pin as the pull-up source for the NTC resis-

tor networks, since the internal reference for the NTC

circuitry is based on a ratio of the voltage on the BIAS

pin. Furthermore, various 100k pull-up resistors can be

conveniently connected to the BIAS pin.

the NTC pin is always 725 and 325 of V

.

BIAS

LeavingtheNTC pinfloating orconnectingitto acapacitor

disables all NTC functionality.

4000f

23

LTC4000

applicaTions inForMaTion

Setting the Input Voltage Monitoring Resistor Divider

LTC4000

CC

A4-A7

= 0.2m

A10

= 0.1m

g

m4-7

The falling threshold voltage level for this monitoring

function can be calculated as follows:

C

g

m10

+

–

R

C

–

+

ITH

O10

R

O4-7

⎛

⎞

V_{VM_RST}

1.193V

R

R_VM1

=

– 1 •R

⎜

⎟

VMꢀ

⎝

⎠

4000 F11

where R

and R

form a resistor divider connected

VMꢀ

VM1

Figure 11. Error Amplifier Followed by Output Amplifier Driving

CC and ITH Pins

between the monitored voltage and GND, with the center

tappointconnectedtotheVMpinasshowninFigure6.The

rising threshold voltage level can be calculated similarly.

Empirical Loop Compensation

Compensation

Based on the five analytical expressions given in the Ap-

pendix section, and the transfer function from the ITH

pin to the input and output current of the external DC/DC

converter,theusercananalyticallydeterminethecomplete

loop transfer function of each of the loops. Once these are

obtained, it is a matter of analyzing the gain and phase

bode plots to ensure that there is enough phase and gain

In order for the LTC4000 to control the external DC/DC

converter, it has to be able to overcome the sourcing bias

current of the ITH or VC pin of the DC/DC converter. The

typical sinking capability of the LTC4000 at the ITH pin is

1mA at 0.4V with a maximum voltage range of 0V to 6V.

It is imperative that the local feedback of the DC/DC

converter be set up such that during regulation of any of

the LTC4000 loops this local loop is out of regulation and

sources as much current as possible from its ITH/VC pin.

For example for a DC/DC converter regulating its output

voltage, it is recommended that the converter feedback

divider is programmed to be greater than 1105 of the

outputvoltageregulationlevelprogrammedattheOFBpin.

margin at unity crossover with the selected values of R

C

and C for all operating conditions.

C

Even though it is clear that an analytical compensation

method is possible, sometimes certain complications

render this method difficult to tackle. These complica-

tions include the lack of easy availability of the switching

converter transfer function from the ITH or VC control

node to its input or output current, and the variability of

parameter values of the components such as the ESR of

There are four feedback loops to consider when setting up

the compensation for the LTC4000. As mentioned before

these loops are: the input current loop, the charge current

loop, the float voltage loop and the output voltage loop.

All of these loops have an error amp (A4-A7% followed by

another amplifier (A10% with the intermediate node driv-

ing the CC pin and the output of A10 driving the ITH pin

as shown in Figure 11. The most common compensation

the output capacitor or the R

of the external PFETs.

DS(ON%

Therefore a simpler and more practical way to compen-

sate the LTC4000 is provided here. This empirical method

involves injecting an AC signal into the loop, observing

the loop transient response and adjusting the C and R

C

values to quickly iterate towards the final values. Much

of the detail of this method is derived from Application

Note19whichcanbefoundatwww.linear.comusingAN19

in the search box.

networkofaseriescapacitor(C %andresistor(R %between

the CC pin and the ITH pin is shown here.

C

Each of the loops has slightly different dynamics due to

differencesinthefeedbacksignalpath.Theanalyticdescrip-

tion of each of the loops is included in the Appendix sec-

tion. In most situations, an alternative empirical approach

to compensation, as described here, is more practical.

Figure 1ꢀ shows the recommended setup to inject an

AC-coupled output load variation into the loop. A function

generator with 20Ω output impedance is coupled through

a 20Ω/1000µF series RC network to the regulator output.

4000f

24

LTC4000

applicaTions inForMaTion

A

B

SWITCHING

CONVERTER

1k

10k

GND

ITH

0.015µF

1500pF

R

C

50Ω

1W

I

OUT

C

SCOPE

GROUND

CLIP

ITH

CC

1000µF

(OBSERVE

POLARITY)

CLN

IN

CSP

CSN

LTC4000

GND BAT BGATE

50Ω

GENERATOR

f = 50Hz

V

IN

4000 F12

Figure 1ꢁ. Empirical Loop Compensation Setup

Generator frequency is set at 20Hz. Lower frequencies

may cause a blinking scope display and higher frequen-

cies may not allow sufficient settling time for the output

transient. Amplitude of the generator output is typically

of the second probe connected to exactly the same place

as channel A ground. The standard 20Ω BNC sync output

of the generator should not be used because of ground

loop errors. It may also be necessary to isolate either

the generator or oscilloscope from its third wire (earth

ground% connection in the power plug to prevent ground

loop errors in the scope display. These ground loop errors

are checked by connecting channel A probe tip to exactly

the same point as the probe ground clip. Any reading on

channel A indicates a ground loop problem.

set at 2V to generate a 100mA load variation. For

P-P

lightly loaded outputs (I

< 100mA%, this level may be

OUT

too high for small signal response. If the positive and

negative transition settling waveforms are significantly

different, amplitude should be reduced. Actual amplitude

is not particularly important because it is the shape of

the resulting regulator output waveform which indicates

loop stability.

Once the proper setup is made, finding the optimum

values for the frequency compensation network is fairly

A ꢀ-pole oscilloscope filter with f = 10kHz is used to

block switching frequencies. Regulators without added

LC output filters have switching frequency signals at their

outputs which may be much higher amplitude than the

low frequency settling waveform to be studied. The filter

frequency is high enough for most applications to pass

the settling waveform with no distortion.

straightforward. Initially, C is made large (≥1μF% and R

C C

is made small (≈10k%. This nearly always ensures that the

regulator will be stable enough to start iteration. Now, if

theregulatoroutputwaveformissingle-poleoverdamped

(see the waveforms in Figure 13%, the value of C is re-

C

duced in steps of about ꢀ:1 until the response becomes

slightly under damped. Next, R is increased in steps of

C

ꢀ:1 to introduce a loop zero. This will normally improve

Oscilloscope and generator connections should be made

exactly as shown in Figure 1ꢀ to prevent ground loop er-

rors. The oscilloscope is synced by connecting the chan-

nel B probe to the generator output, with the ground clip

damping and allow the value of C to be further reduced.

C

Shifting back and forth between R and C variations will

C

allow one to quickly find optimum values.

4000f

25

LTC4000

applicaTions inForMaTion

problemsonstartuporshortcircuitrecovery.Toguarantee

acceptable loop stability under all conditions, the initial

GENERATOR OUTPUT

values chosen for R and C should be checked under all

C

REGULATOR OUTPUT

conditions of input voltage and load current. The simplest

way of accomplishing this is to apply load currents of

minimum, maximum and several points in between. At

each load current, input voltage is varied from minimum

to maximum while observing the settling waveform.

WITH LARGE C , SMALL R

C

WITH REDUCED C , SMALL R

C

EFFECT OF INCREASED R

C

Iflargetemperaturevariationsareexpectedforthesystem,

stability checks should also be done at the temperature

extremes. There can be significant temperature varia-

tions in several key component parameters which affect

stability; in particular, input and output capacitor value

and their ESR, and inductor permeability. The external

converter parametric variations also need some consid-

eration especially the transfer function from the ITH/VC

pin voltage to the output variable (voltage or current%. The

LTC4000 parameters that vary with temperature include

the transconductance and the output resistance of the

error amplifiers (A4-A7%. For modest temperature varia-

tions, conservative over damping under worst-case room

temperature conditions is usually sufficient to guarantee

adequate stability at all temperatures.

FURTHER REDUCTION IN C

MAY BE POSSIBLE

C

IMPROPER VALUES WILL

CAUSE OSCILLATIONS

4000 F13

Figure 13. Typical Output Transient Response at Various

Stability Level

If the regulator response is under damped with the initial

largevalueofC ,R shouldbeincreasedimmediatelybefore

C

larger values of C are tried. This will normally bring about

the over damped starting condition for further iteration.

The optimum values for R and C normally means the

C

smallest value for C and the largest value for R which

C

still guarantee well damped response, and which result in

the largest loop bandwidth and hence loop settling that is

as rapid as possible. The reason for this approach is that

it minimizes the variations in output voltage caused by

input ripple voltage and output load transients.

One measure of stability margin is to vary the selected

values of both R and C by ꢀ:1 in all four possible com-

C

binations. If the regulator response remains reasonably

well damped under all conditions, the regulator can be

considered fairly tolerant of parametric variations. Any

tendency towards an under damped (ringing% response

indicates that a more conservative compensation may

be needed.

A switching regulator which is grossly over damped will

never oscillate, but it may have unacceptably large output

transients following sudden changes in input voltage or

outputloading.Itmayalsosufferfromexcessiveovershoot

4000f

26

LTC4000

applicaTions inForMaTion

DESIGN EXAMPLE

• R is set at ꢀ4.9kΩ such that the voltage at the CL pin

CL

is1.ꢀ2V.SimilartotheIIMONpin,theregulationvoltage

on the IBMON pin is clamped at 1V with an accurate

internal reference. Therefore, the charge current limit

is set at 10A according to the following formula:

In this design example, the LTC4000 is paired with the

LT3842 buck converter to create a 10A, 3-cell LiFePO

4

battery charger. The circuit is shown on the front page

and is repeated here in Figure 14.

0.020V 0.020V

• The input voltage monitor falling threshold is set at

I_CLIM(MAX%

=

= 10A

R_CS

2mΩ

14.3V according to the following formula:

• The trickle charge current level is consequently set at

⎛

⎜

⎝

⎞

14.3V

1.193V

R_VM1

=

−1 • 100kΩ ≈ 1.10MΩ

⎟

1.ꢀ2A, according to the following formula:

⎠

ꢀ4.9kΩ

2mΩ

I_CLIM(TRKL%= 0.ꢀ2µA •

= 1.ꢀ2A

• The IL pin is left open such that the voltage on this pin

is >1.02V. The regulation voltage on the IIMON pin is

clamped at 1.0V with an accurate internal reference.

Therefore, theinputcurrentlimitissetat10Aaccording

to the following formula:

• The battery float voltage is set at 10.8V according to

the following formula:

⎛

⎜

⎝

⎞

10.8

1.136

R_BFB1

=

−1 • 133kΩ ≈ 1.13MΩ

⎟

0.020V

10A

⎠

R_IS=

= 2mΩ

• The bad battery detection time is set at 43 minutes

according to the following formula:

43

60

C_TMR(nF% = t_BADBAT(h% • 138.2 =

• 138.2 = 100nF

5mΩ

Si7135DP

LT3845

IN

OUT

15V TO 60V

12V, 15A

V

SHDN

C

100µF

47nF

1.15M

5mΩ

Si7135DP

14.7k

ITH

CC

IID IGATE CSP

RST

CLN

IN

CSN

BGATE

BAT

OFB

1µF

1.10M

100k

127k

VM

LTC4000

FBG

3.0V

ENC

CHRG

FLT

133k

10.8V FLOAT

10A MAX CHARGE

CURRENT

BFB

NTC

1.13M

IIMON

10nF

IBMON

10k

10nF

TMR

IL CL

CX

GND BIAS

3-CELL Li-Ion

BATTERY PACK

10k

22.1k

0.1µF

1µF

NTHS0603

N02N1002J

4000 F14

Figure 14. 48V to 10.8V at 10A Buck Converter Charger for Three LiFePO₄Cells

4000f

27

LTC4000

applicaTions inForMaTion

• The charge termination time is set at 2.9 hours accord-

• The range of valid temperature for charging is set at

–1.2°C to 41.2°C by picking a 10k Vishay Curve ꢀ NTC

thermistor that is thermally coupled to the battery, and

connecting this in series with a regular 10k resistor to

the BIAS pin.

ing to the following formula:

C_TMR(nF% = t_TERMINATE(h% • 34.6 = ꢀ.9 • 34.6 = 100nF

• The C/X current termination level is programmed at 1A

according to the following formula:

• For compensation, the procedure described in the

empirical loop compensation section is followed. As

1A • 2mΩ + 0.2mV

(

)

R_CX

=

≈ ꢀꢀ.1kΩ

recommended, first a 1µF C and 10k R is used, which

C

0.ꢀ2µA

sets all the loops to be stable. For an example of typical

Note that in this particular solution, the timer termina-

tion is selected since a capacitor connects to the TMR

pin. Therefore, this C/X current termination level only

applies to the CHRG indicator pin.

transient responses, the charge current regulation loop

when V

is regulated to V

is used here.

OFB

OUT(INST_ON%

Figure 12 shows the recommended setup to inject a

DC-coupledchargecurrentvariationintothisparticular

loop. The input to the CL pin is a square wave at 70Hz

with the low level set at 1ꢀ0mV and the high level set

at 130mV, corresponding to a 1.ꢀA and 1.3A charge

current (100mA charge current step%. Therefore, in this

particular example the trickle charge current regulation

stability is examined. Note that the nominal trickle

charge current in this example is programmed at 1.ꢀ2A

• The output voltage regulation level is set at 12V accord-

ing to the following formula:

⎛

⎜

⎝

⎞

1ꢀ

1.193

R_OFB1

=

−1 • 1ꢀ7kΩ ≈ 1.12MΩ

⎟

⎠

• Theinstant-onvoltagelevelisconsequentlysetat9.79V

according to the following formula:

(R = ꢀ4.9kΩ%.

CL

1120kΩ+1ꢀ7kΩ

V

=

• 0.974V = 9.79V

INST _ON

1ꢀ7kΩ

The worst-case power dissipation during instant-on

operation can be calculated as follows:

B

A

10k

1k

IBMON

1500pF

0.015µF

• During trickle charging:

LTC4000

P_TRKL= 0.86 • V

– V

•I

BAT

CLIM_ TRKL

[

]

FLOAT

CL

= 0.86 • 10.8 • 1A

[

]

SQUARE WAVE

GENERATOR

f = 60Hz

= 9.3W

4000 F15

• And beyond trickle charging:

= 0.86 • V – V

P

•I

CLIM

[

]

BAT

INST _ON

FLOAT

= 0.86 • 10.8 – 7.33 • 10A

[

]

Figure 12. Charge Current Regulation Loop Compensation Setup

= 19.3W

Therefore, depending on the layout and heat sink avail-

able to the charging PMOS, the suggested PMOS over

temperature detection circuit included in Figure 7 may

needtobeincluded.Forthecompleteapplicationcircuit,

please refer to Figure ꢀ2.

4000f

28

LTC4000

applicaTions inForMaTion

With C = 1µF, R = 10k at V = ꢀ0V, V

= 7V, V

The transient response now indicates an overall under

dampedsystem.Asnotedintheempiricalloopcompensa-

C

IN

BAT

CSP

regulated at 9.8V and a 0.ꢀA output load condition at

CSP, the transient response for a 100mA charge current

step observed at IBMON is shown in Figure 16.

tion section, the value of R is now increased iteratively

C

until R = ꢀ0k. The transient response of the same loop

C

with C = ꢀꢀnF and R = ꢀ0k is shown in Figure 18.

C

15

10

5

15

10

5

0

–5

–10

–15

0

–5

–10

–15

–20 –15 –10 –5

0

5

10 15 20 25

5ms/DIV

4000 F16

–20 –15 –10 –5

0

5

10 15 20 25

5ms/DIV

Figure 16. Transient Response of Charge Current Regulation Loop

Observed at IBMON When V_OFBis Regulated to V_{OUT(INST_ON)}with

C_C= 1µF, R_C= 10k for a 100mA Charge Current Step

4000 F18

Figure 18. Transient Response of Charge Current Regulation Loop

Observed at IBMON When V_OFBis Regulated to V_{OUT(INST_ON)}with

C_C= ꢁꢁnF, R_C= ꢁ0k for a 100mA Charge Current Step

Thetransientresponseshowsasmallovershootwithslow

settling indicating a fast minor loop within a well damped

Note that the transient response is close to optimum

with some overshoot and fast settling. If after iteratively

overall loop. Therefore, the value of C is reduced itera-

C

tively until C = ꢀꢀnF. The transient response of the same

C

increasing the value of R , the transient response again

C

loop with C = ꢀꢀnF and R = 10k is shown in Figure 17.

C

indicates an over damped system, the step of reducing

C can be repeated. These steps of reducing C followed

C

15

by increasing R can be repeated continuously until one

C

10

5

arrives at a stable loop with the smallest value of C and

C

the largest value of R . In this particular example, these

C

values are found to be C = ꢀꢀnF and R = ꢀ0kΩ.

0

C

–5

–10

–15

AfterarrivingatthesefinalvaluesofR andC ,thestability

C

margin is checked by varying the values of both R and

C

C by ꢀ:1 in all four possible combinations. After which

C

the setup condition is varied, including varying the input

voltage level and the output load level and the transient

response is checked at these different setup conditions.

Once the desired responses on all different conditions are

–20 –15 –10 –5

0

5

10 15 20 25

5ms/DIV

4000 F17

Figure 17. Transient Response of Charge Current Regulation Loop

Observed at IBMON When V_OFBis Regulated to V_{OUT(INST_ON)}with

C_C= ꢁꢁnF, R_C= 10k for a 100mA Charge Current Step

obtained, the values of R and C are noted.

C

4000f

29

LTC4000

applicaTions inForMaTion

This same procedure is then repeated for the other four

loops: the input current regulation, the output voltage

regulation, the battery float voltage regulation and finally

For accurate current sensing, the sense lines from R

IS

and R (Figure 19% must be Kelvined back all the way

CS

to the sense resistors terminals. The two sense lines of

each resistor must also be routed close together and away

from noise sources to minimize error. Furthermore, cur-

rent filtering capacitors should be placed strategically to

ensure that very little AC current is flowing through these

sense resistors as mentioned in the applications section.

the charge current regulation when V > V

.

OFB

OUT(INST_ON%

Notethattheresultingoptimumvaluesforeachoftheloops

may differ slightly. The final values of C and R are then

C

selected by combining the results and ensuring the most

conservativeresponseforalltheloops.Thisusuallyentails

picking the largest value of C and the smallest value of

C

The decoupling capacitors C and C

must be placed

BIAS

IN

R based on the results obtained for all the loops. In this

C

as close to the LTC4000 as possible. This allows as short

particular example, the value of C is finally set to 47nF

C

a route as possible from C to the IN and GND pins, as

IN

and R = 14.7kΩ.

C

well as from C

to the BIAS and GND pins.

BIAS

In a typical application, the LTC4000 is paired with an

external DC/DC converter. The operation of this converter

often involves high dV/dt switching voltage as well as high

currents. Isolate these switching voltages and currents

from the LTC4000 section of the board as much as pos-

sible by using good board layout practices. These include

separatingnoisypowerandsignalgrounds,havingagood

low impedance ground plane, shielding whenever neces-

sary, and routing sensitive signals as short as possible

and away from noisy sections of the board.

BOARD LAYOUT CONSIDERATIONS

In the majority of applications, the most important param-

eter of the system is the battery float voltage. Therefore,

theuserneedstobeextracarefulwhenplacingandrouting

the feedback resistor R

and R

. In particular, the

BFB1

BFBꢀ

batterysenselineconnectedtoR

andthegroundreturn

BFB1

line for the LTC4000 must be Kelvined back to where the

battery output and the battery ground are located respec-

tively. Figure 19 shows this Kelvin sense configuration.

SWITCHING

CONVERTER

SYSTEM LOAD

GND ITH

R

C

ITH

CC

IID

IGATE

CSP

CLN

R

CS

R

IS

LTC4000

CSN

IN

BGATE

BAT

BFB

FBG

R

BFB1

V

IN

BFB2

GND

4000 F19

Figure 19. Kelvin Sense Lines Configuration for LTC4000

4000f

30

LTC4000

applicaTions inForMaTion

APPENDIX—THE LOOP TRANSFER FUNCTIONS

The Input Current Regulation Loop

When a series resistor (R % and capacitor (C % is used

The feedback signal for the input current regulation loop

is the sense voltage across the input current sense resis-

C

as the compensation network as shown in Figure 11, the

transfer function from the input of A4-A7 to the ITH pin

is simply as follows:

tor (R %.

IS

This voltage is amplified by a factor of ꢀ0 and compared

to the voltage on the IL pin by the transconductance er-

ror amplifier (A4%. This amplifier then drives the output

transconductance amplifier (A10% to appropriately adjust

the voltage on the ITH pin driving the external DC/DC

converter to regulate the input current across the sense

⎡

⎢

⎣

⎤

⎛

⎜

⎝

⎞

⎟

⎠

1

g_m10

R –

C s+1

⎥

⎦

C

V

^ITH(s% = g_m4-7

R_O4-7• C_Cs

FB

resistor (R %. This loop is shown in detail in Figure ꢀ0.

IS

whereg

isthetransconductanceoferroramplifierA4-

m4-7

The simplified loop transmission is:

A7, typically 0.2mA/V; g

is the output amplifier (A10%

m10

⎡

⎢

⎣

⎤

⎛

⎜

⎝

⎞

⎟

⎠

transconductance, R

error amplifier, typically 20mΩ; and R

output impedance of the output amplifier, typically 10mΩ

with the ITH pin open circuit.

is the output impedance of the

1

g_m10

C_Cs

O4-7

R –

C s+1

⎥

⎦

C

is the effective

O10

L_IC(s% = g_m4

•

Note this simplification is valid when g

• R

m10

O10 O4-7

⎡

⎤

• C = A

• R

• C is much larger than any other

C

V10

O4-7 C

ꢀ0R Rꢀ

s+1

(

)

IS

CIIMON

• Gmi (s%

⎢

⎥

poles or zeroes in the system. Typically A • R

= 5 •

O4-7

p

V10

R1+Rꢀ C

s+1 ⎥

⎢

⎣

(

)

10

⎦

IIMON

10 with the ITH pin open circuit. The exact value of g

m10

and R

depends on the pull-up current and impedance

O10

where Gmi (s% is the transfer function from V to the

p

ITH

connected to the ITH pin respectively.

In most applications, compensation of the loops involves

picking the right values of R and C . Aside from picking

input current of the external DC/DC converter.

R

IS

IN

I

IN

C

the values of R and C , the value of g may also be

IN

C

m10

adjusted. The value of g

can be adjusted higher by

m10

IN

CLN

A8

LTC4000

CC

increasing the pull-up current into the ITH pin and its

value can be approximated as:

R2

20k

g

= 0.33m

m8

A4

IIMON

g

= 0.5m

m4

I

_ITH+ 2µA

20mV

A10

m10

C

BIAS

C

R1

60k

C

g_m10

=

IIMON

g

= 0.1m

+

–

R

C

–

+

50µA

ITH

1V

The higher the value of g , the smaller the lower limit

m10

IL

R

O4

R

O10

of the value of R would be. This lower limit is to prevent

C

R

IL

4000 F20

the presence of the right half plane zero.

Even though all the loops share this transfer function from

the error amplifier input to the ITH pin, each of the loops

has a slightly different dynamic due to differences in the

feedback signal path.

Figure ꢁ0. Simplified Linear Model of the Input Current

Regulation Loop

4000f

31

LTC4000

applicaTions inForMaTion

The Output Voltage Regulation Loop

The Battery Float Voltage Regulation Loop

The feedback signal for the output voltage regulation loop

is the voltage on the OFB pin, which is connected to the

center node of the resistor divider between the output

The battery float voltage regulation loop is very similar to

theoutputfloatvoltageregulationloop. Insteadofobserv-

ing the voltage at the OFB pin, the battery float voltage

regulation loop observes the voltage at the BFB pin.

voltage (connected to C % and the FBG pin. This voltage

SP

is compared to an internal reference (1.193V typical% by

the transconductance error amplifier A7. This amplifier

then drives the output transconductance amplifier (A10%

to appropriately adjust the voltage on the ITH pin driving

the external DC/DC converter to regulate the output volt-

age observed by the OFB pin. This loop is shown in detail

in Figure ꢀ1.

One significant difference is that while the value of R

L

in the output voltage loop can vary significantly, the

output resistance of the battery float voltage loop is a

small constant value approximately equal to the sum

of the on-resistance of the external PFET (R

% and

DS(ON%

the series internal resistance of the battery (R %. This

BAT

approximation is valid for any efficient system such that

most of the output power from the battery is delivered to

the system load and not dissipated on the battery inter-

nal resistance or the charging PFET on-resistance. For a

LTC4000

INPUT

CC

A10

m10

C

g

= 0.1m

R

C

typical system, minimum R is at least five times larger

–

+

L

ITH

+

6

than R

+ R and R is at least 10 times larger

Gmo (s)

p

DS(ON%

BAT

BFB

R

O10

–

than R . Figure ꢀꢀ shows the detail of the battery float

LOAD

voltage regulation loop.

CSP

OFB

A7

= 0.5m

g

R

m7

OFB1

OFB2

C

R

L

LTC4000

INPUT

CC

+

A10

C

1.193V

–

g

= 0.1m

R

m10

R

O7

R

FBG

C

–

+

ITH

+

INTERNALLY

PULLED HIGH

Gmo (s)

p

O10

–

LOAD

4000 F21

BAT

BFB

A7

g

= 0.5m

R

m6

R

BFB1

C

L

R

L

CS

Figure ꢁ1. Simplified Linear Model of the Output Voltage

Regulation Loop

+

–

DS(ON)

1.136V

BFB2

R

O6

FBG

The simplified loop transmission is as follows:

R

BAT

INTERNALLY

⎡

⎢

⎣

⎤

⎛

⎜

⎝

⎞

⎟

⎠

PULLED HIGH

1

R –

C s + 1

⎥

⎦

C

g

4000 F22

m10

L

(s% = g

•

m7

OV

C s

C

Figure ꢁꢁ. Simplified Linear Model of the Battery Float

Voltage Regulation Loop

⎡

⎤

⎥

⎦

⎡

⎤

R

OFBꢀ

L

•

• Gmo (s%

p

⎢

⎥

R

R • C s + 1

⎦

L L

⎣

OFB

where Gmo (s% is the transfer function from V

to

ITH

p

the output current of the external DC/DC converter, and

= R + R

R

.

OFBꢀ

OFB

OFB1

4000f

32

LTC4000

applicaTions inForMaTion

In Figure ꢀꢀ the battery is approximated to be a signal

The Battery Charge Current Regulation Loop when

OFB OUT(INST_ON)

ground in series with the internal battery resistance R

.

V

> V

BAT

Therefore, the simplified loop transmission is as follows:

In this operating region, the external charging PFET’s gate

is driven low and clamped at V

loop is shown in Figure ꢀ3.

. The detail of this

BGATE(ON%

⎡

⎢

⎣

⎤

⎛

⎜

⎝

⎞

⎟

⎠

1

g_m10

C_Cs

R –

C s+1

⎥

⎦

C

L_BV(s% = g_m6

•

The simplified loop transmission is:

⎡

⎢

⎣

⎤

⎛

⎜

⎝

⎞

⎟

⎠

1

g_m10

C_Cs

R –

C s+1

⎥

⎦

C

⎡

⎤ ⎡

⎤

R_BFBꢀ

R_LB

L_CC(s% = g_m2

•

• Gmo (s%

p

⎢

⎥ ⎢

⎥

R

R • C s+1

⎦

LB L

⎣

⎦ ⎣

BFB

where Gmo (s% is the transfer function from V

to

ITH

p

⎡

⎤

⎥

Rꢀ • C

s+1

R_L

(

)

IBMON

the output current of the external DC/DC converter,

ꢀ0R_CS

•

⎢

⎢ R1+Rꢀ C

⎣

s+1⎥ R +R

(

)

⎦

f

L

IBMON

R

= R

+ R

, and R = R //(R

+ R

+

BFB

BAT

BFB1

BFBꢀ

LB

L

DS(ON%

CS

% represents the effective output resistance from the

⎡

⎢

⎤

⎥

⎦

1

LOAD node to GND.

• Gmo (s%

p

R R C s+1⎥

⎢

(

)

⎣

L

f

L



The Battery Charge Current Regulation Loop

where Gmo (s% is the transfer function from V

to

ITH

p

This final regulation loop combines certain dynamic char-

acteristics that are found in all the other three loops. The

feedback signal for this charge current regulation loop is

the sense voltage across the charge current sense resis-

the output current of the external DC/DC converter, R =

f

R

+ R

+ R , and R //R represents the effective

CS

DS(ON% BAT L f

resistance value resulting from the parallel combination

of R and R .

L

f

tor (R %. This voltage is amplified by a factor of ꢀ0 and

CS

compared to the voltage on the CL pin by the transcon-

ductance error amplifier (A2%. In a familiar fashion, this

amplifier drives the output transconductance amplifier

(A10% to appropriately adjust the voltage on the ITH pin

driving the external DC/DC converter to regulate the input

C

R

C

ITH

CC

LTC4000

R

O10

INPUT

A10

= 0.1m

g

m10

+

current across the sense resistor (R %.

CS

Gmo (s)

p

–

Due to the presence of the instant-on feature, description

of thechargecurrentregulation loophastobe divided into

twoseparateoperatingregions.Theseregionsofoperation

depend on whether the voltage on the OFB pin is higher

R

O5

A5

= 0.5m

g

m5

A8

C

R

L

CSP

CSN

g

= 0.33m

m8

BIAS

+

–

1V

or lower than the instant-on threshold (V

%.

R

OUT(INST_ON%

CS

50µA/

5µA

R1

60k

R2

20k

DS(ON)

BAT

CL

R

IBMON

C

4000 F23

IBMON

CL

Figure ꢁ3. Simplified Linear Model of the Charge Current

Regulation Loop with the External Charging PFET Driven On

4000f

33

LTC4000

applicaTions inForMaTion

The Battery Charge Current Regulation Loop when

The simplified loop transmission is:

V

is Regulated to V

OFB

OUT(INST_ON)

⎡

⎢

⎣

⎤

⎛

⎜

⎝

⎞

⎟

⎠

1

R –

C s + 1

⎥

⎦

C

When the battery voltage is below the instant-on level,

the external charging PFET is driven linearly to regulate

the voltage at the output (connected to the CSP pin%. The

outputvoltageisregulatedsuchthatthevoltageattheOFB

g

m10

L

(s% = g

•

m2

CCꢀ

C s

C

pin is equal to the instant-on threshold (V

%.

OUT(INST_ON%

⎡

⎤

Rꢀ • C

s + 1

(

)

IBMON

ꢀ0R

•

⎥

⎢

If this external PFET regulation is fast compared to the

unity crossover frequency of the battery charge current

regulation loop, then the voltage at the output can be con-

sidered a small signal ground. However, in the LTC4000

the external PFET regulation is purposely made slow to

allow for a broader selection of possible PFETs to be used.

Therefore, the linear model of the PFET has to be included

in the analysis of the charge current regulation loop. The

detail of this loop is shown in Figure ꢀ4.

CS

R1+ Rꢀ C

s + 1

⎥

⎦

⎢

⎣

(

)

IBMON

⎡

⎤

⎥

⎦

R

1

L

•

⎢

R

+ R

R  R

C s + 1

fIDC

⎢

⎣

⎥

(

)

L

fIDC

⎡

⎢

⎤

C

g

⎥

s + 1

g

mEXT

• Gmo (s%

p

⎢

⎛

⎜

⎝

⎞

⎟

⎠

C

R

+ R

BAT

g

CS

⎥

⎦

s + 1

R

g

⎢

⎣

mEXT

fIDC



C

R

C

where Gmo (s% is the transfer function from V to the

p

ITH

output current of the external DC/DC converter, g

is

mEXT

ITH

CC

LTC4000

R

O10

INPUT

the small signal transconductance of the output PFET,

= R + 1/g + R and R //R represents

A10

= 0.1m

g

m10

R

flDC

CS

mEXT

BAT

L

flDC

+

Gmo (s)

p

the effective resistance value resulting from the parallel

combination of R and R

–

.

flDC

L

R

O5

A5

= 0.5m

g

m5

A8

C

R

L

CSP

CSN

g

= 0.33m

m8

BIAS

+

–

1V

R

CS

50µA/

5µA

R1

60k

R2

20k

1

C

g

mEXT

BAT

CL

R

IBMON

C

4000 F24

R

BAT

IBMON

CL

Figure ꢁ4. Simplified Linear Model of the Charge

Current Regulation Loop with the External Charging

PFET Linearly Regulated

4000f

34

LTC4000

Typical applicaTions

5mΩ

V

IN

15V TO 60V

10A MAX

2.2µF

BSC123NO8NS3

WÜRTH ELEKTRONIC

74435561100

10µH

47µF

V

IN

TG

Si7135DP

V

OUT

12V, 15A

SW

BG

3mΩ

33µF

×3

C

SS

B160

1.5nF

BSC123NO8NS3

0.1µF

BURST_EN

SYNC

BOOST

BAS521

SGND

1.15M

V

CC

1µF

1N4148

LT3845A

182k

V

f

FB

SET

49.9k

16.2k

+

SENSE

5mΩ

–

V

C

SHDN

NTHS0603

N02N1002J

14.7k

47nF

RST ITH

CC

IID IGATE CSP

Si7135DP

CSN

BGATE

CLN

IN

10nF

1µF

1.10M

100k

BAT

OFB

VM

LTC4000

ENC

BZX84C3VO

127k

133k

CHRG

FLT

FBG

1.13M

IIMON

BFB

NTC

10nF

IBMON

IL CL

TMR

CX

GND BIAS

22.1k

10nF

3-CELL

LiFePO

BATTERY

PACK

24.9k

4

0.1µF

R

NTC

10k

1µF

162k

10k

2N7002L

38.3k

+

–

V

OUT

IN

NTHS0603

N02N1002J

LTC1540

HYST

REF

GND

20k

–

V

1M

4000 F25

Figure ꢁ2. 48V to 10.8V at 10A Buck Converter 3-Cell LiFePO₄Battery Charger with ꢁ.9h Termination Timer,

1.ꢁ2A Trickle Charge Current and Charging PFET Thermal Protection

4000f

35

LTC4000

Typical applicaTions

PA1494.362NL

3.3µH

V

IN

3.3mΩ

2.5mΩ

6V TO 18V

15A MAX

10Ω

1nF

150µF

22µF

×4

INTV

CC

BAS140W

10Ω

BSC027N04

Si7135DP

V

OUT

22V, 5A

+

–

SENSE

22µF

×5

INTV

BOOST

CC

0.1µF

PLLINMODE

INTV

150µF

SW

BG

CC

100k

BSC027N04

1.87M

PGOOD

4.7µF

LTC3786

TG

V

RUN

SS

BIAS

232k

V

FB

0.1µF

FREQ GND

ITH

12.1k

10mΩ

28.7k

22nF

RST

CLN

IN

ITH

CC

IID IGATE CSP

CSN

BGATE

Si7135DP

10nF

1µF

383k

100k

BAT

OFB

VM

LTC4000

ENC

CHRG

FLT

107k

FBG

1.87M

IIMON

BFB

NTC

10nF

IBMON

IL CL

CX

GND BIAS TMR

10nF

5-CELL

Li-Ion

BATTERY

PACK

4000 F26

10k

R

NTC

10µF

22.1k

TENERGY

SSIP PACK

30104

1µF

NTHS0603

N02N1002J

Figure ꢁ6. 6V to ꢁ1V at 2A Boost Converter 2-Cell Li-Ion Battery Charger with C/10 Termination and 0.22A Trickle Charge Current

4000f

36

LTC4000

Typical applicaTions

4000f

37

LTC4000

package DescripTion

UFD Package

ꢁ8-Lead Plastic QFN (4mm × 2mm)

(Reference LTC DWG # 02-08-171ꢀ Rev B%

0.70 0.05

4.50 0.05

3.10 0.05

2.50 REF

2.65 0.05

3.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

3.50 REF

4.10 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 0.05

4.00 0.10

(2 SIDES)

27

28

0.40 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 0.10

(2 SIDES)

3.50 REF

3.65 0.10

2.65 0.10

(UFD28) QFN 0506 REV B

0.25 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

4000f

38

LTC4000

package DescripTion

GN Package

ꢁ8-Lead Plastic SSOP (Narrow .120 Inch)

(Reference LTC DWG # 02-08-1641%

.386 – .393*

(9.804 – 9.982)

.045 .005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

(0.38 0.10)

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

4000f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

39

LTC4000

Typical applicaTion

IHLP6767GZ

ER4R7M01

4.7µH

390pF

5.6Ω

1800pF

Q5

3.6Ω

B240A

0.01Ω

V

4mΩ

Si7135DP

IN

Q2

Q4

Q3

V

OUT

15V, 5A

6V TO 36V

12.5A MAX

330µF

×2

270µF

0.22µF

0.01Ω

1.24k

+

3.3µF

×5

22µF

×2

–

TG1 SW1 BG1 SENSE SENSE BG2 SW2 TG2

BOOST1

BOOST2

DFLS160

INTV

CC

10µF

MODE/PLLIN

100k

V

IN

LTC3789

PGOOD

+

1µF

309k

INSNS

I

OSENSE

–

OSENSE

V

OUTSNS

BZT52C5V6

154k

121k

FREQ

ILIM

EXTV

CC

V

FB

10µF

RUN ITH SS

SGND PGND1

8.06k

0.01µF

10mΩ

14.7k

100nF

RST ITH

CC

IID IGATE CSP

CLN

IN

CSN

BGATE

Si7135DP

10nF

1µF

365k

100k

BAT

OFB

VM

LTC4000

ENC

CHRG

FLT

BZX84C3VO

26.7k

FBG

118k

IIMON

Q2: SiR422DP

Q3: SiR496DP

Q4: SiR4840BDY

Q5: SiR496DP

BFB

NTC

10nF

IBMON

1.37M

IL

CL

TMR

CX

GND BIAS

10nF

4000 F28

4-CELL

LiFePO

4

BATTERY

PACK

18.2k

22.1k

0.1µF

R

NTC

10k

1µF

NTHS0603

N02N1002J

Figure ꢁ8. 6V to 36V_INto 14.4V at 4.2A Buck Boost Converter 4-Cell LiFePO₄Battery Charger

with ꢁ.9h Timer Termination and 0.42A Trickle Charge Current

relaTeD parTs

PART NUMBER

LTC3789

DESCRIPTION

COMMENTS

Improved LTC3780 with More Features

High Efficiency, Synchronous, 4 Switch Buck-Boost Controller

LT3842

High Voltage Synchronous Current Mode Step-Down Controller with

Adjustable Operating Frequency

For Medium/High Power, High Efficiency Supplies

LT3620

LT3621

High Voltage ꢀA Monolithic Li-Ion Battery Charger

High Voltage 4A Monolithic Li-Ion Battery Charger

3mm × 3mm DFN-1ꢀ and MSOP-1ꢀ Packages

4A Synchronous Version of LT3620 Family

LT362ꢀ/LT362ꢀHV Power Tracking ꢀA Battery Chargers

Multi-Chemistry, Onboard Termination

LTC4009

LTC401ꢀ

LT3741

High Efficiency, Multi-Chemistry Battery Charger

Low Cost Version of LTC4008, 4mm × 4mm QFN-ꢀ0

High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control Similar to LTC4009 Adding PowerPath Control

High Power, Constant Current, Constant Voltage, Step-Down Controller

Thermally Enhanced 4mm × 4mm QFN and ꢀ0-Pin TSSOP

4000f

LT 0411 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 92032-7417

40

●

 LINEAR TECHNOLOGY CORPORATION 2011

(408% 43ꢀ-1900 FAX: (408% 434-0207 www.linear.com


型号：	LT3651
厂家：	Linear
描述：	High Voltage High Current Controller for Battery Charging and Power Management 高电压，大电流控制器的电池充电和电源管理电池控制器
文件：	总40页 (文件大小：427K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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