LT3579IFE-1-PBF_技术文档

LT3579/LT3579-1

6A Boost/Inverting

DC/DC Converter with Fault Protection

FEATURES

DESCRIPTION

The LT^®3579 is a PWM DC/DC converter with built-in fault

protection features to aid in protecting against output shorts,

input/output overvoltage, and overtemperature conditions.

Thepartconsistsofa42Vmasterswitch,anda42Vslaveswitch

that can be tied together for a total current limit of 6A.

n

6A, 42V Combined Power Switch

n

Output Short Circuit Protection

Wide Input Range: 2.5V to 16V Operating,

40V Maximum Transient

LT3579-1: Dual-Phase Capable

n

Master/Slave (3.4A/2.6A) Switch Design

User Conﬁgurable Undervoltage Lockout

Easily Conﬁgurable as a Boost, SEPIC, Inverting, or

Flyback Converter

The LT3579 is ideal for many local power supply designs. It

canbeeasilyconﬁguredinBoost,SEPIC,Inverting,orFlyback

conﬁgurations, and is capable of generating 12V at 1.7A, or

–12Vat1.2Afroma5Vinput. Inaddition, theLT3579’sslave

switch allows the part to be conﬁgured in high voltage, high

power charge pump topologies that are very efﬁcient and

require fewer components than traditional circuits.

n

Low V

Switch: 250mV at 5.5A (Typical)

CESAT

Can be Synchronized to External Clock

Can Synchronize other Switching Regulators

High Gain SHDN Pin Accepts Slowly Varying Input

Signals

TheLT3579’sswitchingfrequencyrangecanbesetbetween

200kHz and 2.5MHz. The part may be clocked internally at

a frequency set by the resistor from the RT pin to ground,

or it may be synchronized to an external clock. A buffered

version of the clock signal is driven out of the CLKOUT

pin, and may be used to synchronize other compatible

switching regulator ICs to the LT3579.

n

20-Lead TSSOP and 20-Pin 4mm × 5mm QFN

Packages

APPLICATIONS

n

Local Power Supply

n

Vacuum Flourescent Display (VFD) Bias Supplies

TheLT3579alsofeaturesinnovativeSHDNpincircuitrythat

allows for slowly varying input signals and an adjustable

undervoltage lockout function. Additional features such

as frequency foldback and soft-start are integrated. The

LT3579 is available in 20-lead TSSOP and 20-pin 4mm ×

5mm QFN packages.

n

TFT-LCD Bias Supplies

Automotive Engine Control Unit (ECU) Power

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 7579816.

TYPICAL APPLICATION

Efﬁciency and Power Loss

100

90

80

70

60

50

40

30

20

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

1MHz, 5V to 12V Boost Converter with Output Short Circuit Protection

2.2μH

V

12V

OUT

V

5V

IN

1.7A

10μF

SW1 SW2

130k 6.3k

10μF

FB

GATE

V

IN

22μF

100k

200k

FAULT

V

IN

LT3579

TEMPERATURE

MONITOR

SHDN

CLKOUT

V

C

RT

8k

2.2nF

SYNC GND SS

86.6k

0.1μF

47pF

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

3579 TA01

LOAD CURRENT (A)

35791 TA02

35791f

1

LT3579/LT3579-1

ABSOLUTE MAXIMUM RATINGS

(Note 1)

V Voltage.................................................–0.3V to 40V

FAULT.........................................................–0.3V to 40V

FAULT Current..................................................... 0.5mA

CLKOUT .......................................................–0.3V to 3V

CLKOUT Current .................................................... 1mA

Operating Junction Temperature Range

IN

SW1/SW2 Voltage .....................................–0.4V to 42V

R Voltage....................................................–0.3V to 5V

T

SS, FB Voltage .........................................–0.3V to 2.5V

V Voltage ...................................................–0.3V to 2V

C

SHDN Voltage ............................................–0.3V to 40V

SYNC Voltage............................................–0.3V to 5.5V

GATE Voltage .............................................–0.3V to 80V

LT3579E (Notes 2, 4).........................–40°C to 125°C

LT3579I (Notes 2, 4)..........................–40°C to 125°C

Storage Temperature Range...................–65°C to 150°C

PIN CONFIGURATION

TOP VIEW

FB

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

SYNC

SS

V

C

20 19 18 17

GATE

R

T

GATE

1

2

3

4

5

6

16 R

T

FAULT

SHDN

CLKOUT

SW2

FAULT

15 SHDN

14 CLKOUT

13 SW2

V

21

GND

V

IN

21

GND

SW1

12 SW2

SW2

11 SW2

SW2

7

8

9 10

SW1 10

SW2

FE PACKAGE

20-LEAD PLASTIC TSSOP

UFD PACKAGE

20-LEAD (4mm s 5mm) PLASTIC QFN

T

= 125°C, θ = 38°C/W, θ = 10°C/W

JA JC

JMAX

T

= 125°C, θ = 34°C/W, θ = 2.7°C/W

JMAX JA JC

EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

LT3579FE

3579

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT3579EFE#PBF

LT3579EFE#TRPBF

LT3579IFE#TRPBF

LT3579EUFD#TRPBF

LT3579IUFD#TRPBF

LT3579EFE-1#TRPBF

LT3579IFE-1#TRPBF

LT3579EUFD-1#TRPBF

LT3579IUFD-1#TRPBF

20-Lead Plastic TSSOP

–40°C to 125°C

LT3579IFE#PBF

20-Lead Plastic TSSOP

LT3579EUFD#PBF

LT3579IUFD#PBF

LT3579EFE-1#PBF

LT3579IFE-1#PBF

LT3579EUFD-1#PBF

LT3579IUFD-1#PBF

20-Lead (4mm × 5mm) Plastic QFN

20-Lead Plastic TSSOP

3579

LT3579FE-1

35791

20-Lead Plastic TSSOP

20-Lead (4mm × 5mm) Plastic QFN

35791

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

35791f

2

LT3579/LT3579-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 5V, V_SHDN= V_IN,V_FAULT= V_INunless otherwise noted. (Note 2).

PARAMETER

CONDITIONS

MIN

TYP

2.3

MAX

2.5

UNITS

V

l

Minimum Input Voltage

V

Overvoltage Lockout

16.2

1.195

3

18.7

1.215

9

21.2

1.230

16

V

IN

l

Positive Feedback Voltage

Negative Feedback Voltage

Positive FB Pin Bias Current

Negative FB Pin Bias Current

Error Amp Transconductance

Error Amp Voltage Gain

V

mV

μA

V

=Positive Feedback Voltage, Current into Pin

=Negative Feedback Voltage, Current out of Pin

80.5

81

83.3

250

70

85

FB

85.5

μA

FB

μmhos

V/V

mA

μA

ΔI=10ꢀA

Quiescent Current

Not Switching

1.9

2.4

1

Quiescent Current in Shutdown

Reference Line Regulation

V

SHDN

= 0V

0

2.5V ≤ V ≤ 15V

0.01

2.5

0.05

2.8

225

%/V

MHz

kHz

ratio

kHz

V

IN

l

Switching Frequency, f

R = 34kΩ

2.2

OSC

T

R = 432kΩ

175

200

1/6

T

Switching Frequency in Foldback

Switching Frequency Range

SYNC High Level for Sync

Compared to Normal f

OSC

l

Free-Running or Synchronizing

200

1.3

2500

SYNC Low Level for Sync

0.4

80

V

SYNC Clock Pulse Duty Cycle

Recommended Minimum SYNC Ratio

V

SYNC

= 0V to 2V

20

%

3/4

f

/f

SYNC OSC

Minimum Off-Time

Minimum On-Time

SW1 Current Limit

SW Current Sharing, I

45

55

nS

A

l

At All Duty Cycles (Note 3)

SW1 and SW2 Tied Together

3.4

6

4.2

5.1

/I

0.78

7.5

A/A

A

SW2 SW1

SW1 + SW2 Current Limit

Switch V

I

/I

= 0.78, At All Duty Cycles (Note 3)

9.4

350

1

SW2 SW1

SW1 and SW2 Tied Together, I

+ I = 5.5A

SW2

250

0.01

mV

μA

CESAT

SW1

SW1 Leakage Current

SW2 Leakage Current

V

SW1

V

SW2

= 5V

1

35791f

3

LT3579/LT3579-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 5V, V_SHDN= V_IN, V_FAULT= V_INunless otherwise noted. (Note 2).

PARAMETER

CONDITIONS

= 30mV, Current Flows Out of SS pin

MIN

TYP

MAX

UNITS

l

Soft-Start Charge Current

Soft-Start Discharge Current

V

SS

5.7

8.7

11.3

μA

Part in FAULT

= 2.1V,

V

SS

5.7

8.7

11.3

μA

Current Flows into SS Pin

l

Soft-Start High Detection Voltage

Soft-Start Low Detection Voltage

SHDN Minimum Input Voltage High

Part in FAULT

1.65

30

1.8

50

1.95

85

V

Part Exiting FAULT

mV

l

Active Mode, SHDN Rising

Active Mode, SHDN Falling

1.27

1.24

1.33

1.3

1.41

1.38

V

l

SHDN Input Voltage Low

SHDN Pin Bias Current

Shutdown Mode

.3

V

SHDN

V

SHDN

V

SHDN

= 3V

= 1.3V

= 0V

40

11.4

0

60

13.4

0.1

μA

9.5

1.9

CLKOUT Output Voltage High

CLKOUT Output Voltage Low

CLKOUT Duty Cycle

C

= 50pF

2.1

100

42

50

12

8

2.3

V

mV

%

CLKOUT

200

LT3579, T = 25°C

J

LT3579-1, All T

%

J

CLKOUT Rise Time

CLKOUT Fall Time

C

= 50pF

ns

CLKOUT

= 50pF

l

GATE Pull Down Current

V

GATE

V

GATE

= 3V

= 80V

800

933

1100

μA

GATE Leakage Current

V

= 50V, GATE Off

0.01

150

1

300

1

μA

mV

μA

GATE

l

FAULT Output Voltage Low

FAULT Leakage Current

100ꢀA into FAULT Pin

= 40V, FAULT Off

V

0.01

750

FAULT

l

FAULT Input Voltage Low Threshold

FAULT Input Voltage High Threshold

700

950

800

1050

mV

1000

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT3579E is guaranteed to meet performance speciﬁcations

from 0°C to 125°C junction temperature. Speciﬁcations over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT3579I is guaranteed over the full –40°C to 125°C operating junction

temperature range.

Note 3: Current limit guaranteed by design and/or correlation to static test.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation over the speciﬁed maximum operating junction

temperature may impair device reliability.

35791f

4

LT3579/LT3579-1

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Switch Current Limit

Switch Saturation Voltage

Switch Current Sharing

10

9

8

7

6

5

4

3

2

1

0

350

300

250

200

150

100

50

1.0

0.9

V

= V

SW2

0.8

0.7

SW1

0.6

0.5

0.4

0.3

0.2

0.1

0

0.0

20

30

40

50

60

70

80

0

1

2

3

4

5

6

7

8

0

0.5

1

1.5

2

2.5

3

3.5

4

DUTY CYCLE (%)

SW1 + SW2 CURRENT (A)

SW1 CURRENT (A)

35791 G01

35791 G02

35791 G03

Switch Current Limit

vs Temperature

Commanded Switch Current vs SS

Positive Feedback Voltage

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

1.23

1.225

1.22

1.215

1.21

1.205

1.2

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

0

0.2

0.4

0.6

0.8

1

1.2

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

SS VOLTAGE (V)

35791 G04

35791 G05

35791 G06

Oscillator Frequency During

Soft-Start

Oscillator Frequency

CLKOUT Duty Cycle

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1

80

70

60

50

40

30

20

0

R

= 34k

T

1/2

1/3

1/4

1/5

1/6

R

T

= 432k

INVERTING

CONFIGURATIONS

BOOSTING

CONFIGURATIONS

0

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

0

0.2

0.4

0.6

0.8 1.2

1

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

FB VOLTAGE (V)

35791 G07

35791 G08

35791 G09

35791f

5

LT3579/LT3579-1

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

CLKOUT Rise Time at 1MHz

Gate Pin Current (V_SS= 2.1V)

Gate Pin Current (V_GATE= 5V)

50

45

40

35

30

25

20

15

10

5

1000

900

800

700

600

550

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

0

T

= –40°C

T

= 25°C

T = 125°C

A

CLKOUT RISE TIME

A

CLKOUT FALL TIME

0

50

100

150

200

250

0

10 20 30 40 50 60 70 80

GATE PIN VOLTAGE (V)

0

0.25

0.5

0.75

1

1.25

1.5

CLKOUT CAPACITIVE LOAD (pF)

SS VOLTAGE (V)

35791 G10

35791 G11

35791 G12

Active/Lockout Threshold

SHDN Pin Current

1.4

1.38

1.36

1.34

1.32

1.3

30

25

20

15

10

5

250

200

150

100

50

T

= –40°C

A

T

= 25°C

A

SHDN RISING

T

A

= 125°C

SHDN FALLING

1.28

1.26

1.24

1.22

1.2

T

= 25°C

A

T

= 125°C

A

T

= –40°C

A

0

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

0

5

10 15 20 25 30 35 40

SHDN VOLTAGE (V)

35791 G13

35791 G14

35791 G15

Internal UVLO

V_INOVLO

Fault Input Threshold

22

21

20

19

18

17

16

15

14

13

12

2.5

1.25

1

FAULT RISING

2.45

2.4

2.35

2.3

0.75

0.5

0.25

0

FAULT FALLING

2.25

2.2

2.15

2.1

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

35791 G17

35791 G16

35791 G18

35791f

6

LT3579/LT3579-1

PIN FUNCTIONS ^(QFN/TSSOP)

GATE (Pin 1/Pin 3): PMOS Gate Drive Pin. The GATE pin

is a pull-down current source, and can be used to drive

the gate of an external PMOS transistor for output short

circuit protection or output disconnect. The GATE pin

current increases linearly with the SS pin’s voltage, with

a maximum pull-down current of 933μA at SS voltages

exceeding 500mV. Note that if the SS voltage is greater

than 500mV, and the GATE pin voltage is less than 2V, the

GATE pin looks like a 2kΩ impedance to ground. See the

Appendix for more information.

a temperature monitor since the CLKOUT pin’s duty cycle

varies linearly with the part’s junction temperature. The

CLKOUT pin signal of the LT3579-1 is 180° out of phase

with the internal oscillator or SYNC pin, and the duty cycle

is ﬁxed at ~50%. The LT3579-1 is useful for multiphase

switching regulators.

SHDN (Pin 15/Pin 17): Shutdown Pin. In conjunction

with the UVLO (undervoltage lockout) circuit, this pin is

used to enable/disable the chip and restart the soft-start

sequence. Drive below 0.3V to disable the chip with very

low quiescent current. Drive above 1.33V (typical) to

activate the chip and restart the soft-start sequence. Do

not ﬂoat this pin.

FAULT (Pin 2/Pin 4): Fault Indication Pin. This active

low, bidirectional pin can either be pulled low (below

750mV) by an external source, or internally by the chip

to indicate a fault. When pulled low, this pin causes the

power switches to turn off, the GATE pin to become high

impedance, the CLKOUT pin to become disabled, and the

SS pin to go through a charge/discharge sequence. The

end/absenceofafaultisindicatedwhenthevoltageonthis

pin exceeds 1V. A pull-up resistor or some other form of

pull-up network needs to exist on this pin to pull it above

1V in the absence of a fault.

RT (Pin 16/Pin 18): Timing Resistor Pin. Adjusts the

LT3579’s switching frequency. Place a resistor from this

pin to ground to set the frequency to a ﬁxed free running

level. Do not ﬂoat this pin.

SYNC (Pin 17/Pin 20): To synchronize the switching

frequency to an outside clock, simply drive this pin with

a clock. The high voltage level of the clock must exceed

1.3V, and the low level must be less than 0.4V. Drive this

pin to less than 0.4V to revert to the internal free running

clock. See the Applications Information section for more

information.

V

(Pin 3/Pin 5): Input Supply Pin. Must be locally

IN

bypassed.

SW1(Pins4-7/Pins6-10):MasterSwitchPin. Thisisthe

collector of the internal master NPN power switch. SW1

is designed to handle a peak collector current of 3.4A

(minimum). Minimize the metal trace area connected to

this pin to minimize EMI.

SS (Pin 18/Pin 19): Soft-Start Pin. Place a soft-start

capacitor here. Upon start-up, the SS pin will be charged

by a (nominally) 250kΩ resistor to ~2.1V. During a fault,

the SS pin will be slowly charged up and discharged as

part of a timeout sequence.

GND(Pins8,9,ExposedPadPin21/ExposedPadPin21):

Ground. Must be soldered directly to local ground

plane.

V (Pin 19/Pin 2): Error Ampliﬁer Output Pin. Tie external

C

compensation network to this pin.

SW2 (Pins 10-13/Pins 11-15): Slave Switch Pin. This is

the collector of the internal slave NPN power switch. SW2

is designed to handle a peak collector current of 2.6A

(minimum). Minimize the metal trace area connected to

this pin to minimize EMI.

FB (Pin 20/Pin 1): Positive and Negative Feedback Pin.

For a Boost or Inverting Converter, tie a resistor from the

FB pin to V

according to the following equations:

OUT

⎛

⎞

V_OUT–1.215V

83.3µA

R =

;Boost or SEPIC Converter

⎜

⎟

FB

⎝

⎠

CLKOUT (Pin 14/Pin 16): Clock Output Pin. Use this pin to

synchronize one or more other ICs to the LT3579. This pin

oscillatesatthesamefrequencyastheinternaloscillatorof

the part or as the SYNC pin. CLKOUT may also be used as

⎛

⎞

|V_OUT|+9mV

R =

;Inverting Converter

⎜

⎟

FB

83.3µA

⎝

⎠

35791f

7

LT3579/LT3579-1

BLOCK DIAGRAM

OPTIONAL

D1

L1

M

1

V

OUT

IN

C

OUT

C

IN

OUT1

R

GATE

FAULT

GATE

933μA

SOFT-

START

DIE TEMP

16.2V

V

C

V

IN

165°C

750mV

SW1

+

–

2.1V

**

+

–

42V (MIN)

1.17V

SW2

+

–

50mV

+

–

FB

STARTUP

& FAULT

LOGIC

42V (MIN)

+

–

1.8V

+

–

I

SW1

+

–

45mV

250k

3.4A (MIN)

SS

SW2

TD ~ 30ns

DRIVER

DISABLE

–

C

SS

VBE • 0.9

+

Q2

SW1

+

–

SHDN

COMPARATOR

1.33V

15.4m

SR1

S

DRIVER

UVLO

–

Q1

V

R

Q

IN

A3

1.215V

REFERENCE

+

R

+

–

S

R

FB

12m

A4

∑

14.6k

A1

–

FB

GND

RAMP

GENERATOR

+

–

÷N

FREQUENCY

FOLDBACK

ADJUSTABLE

OSCILLATOR

14.6k

A2

SS

SYNC

BLOCK

V

RT

SYNC

CLKOUT

C

R

C

R

T

C

3579 BD

** SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3579/LT3579-1 DURING SW OVERVOLTAGE EVENTS.

Figure 1. Block Diagram

35791f

8

LT3579/LT3579-1

STATE DIAGRAM

SHDN < 1.33V

OR

< 2.3V

V

IN

CHIP OFF

• ALL SWITCHES DISABLED

• I

OFF

GATE

• FAULTS CLEARED

SHDN > 1.33V

AND

> 2.3V

V

IN

INITIALIZE

• SS PULLED LOW

FAULT1

FAULT2

SS < 50mV

FAULT DETECTED

• SS CHARGES UP

• IGATE OFF

SOFT START

ENABLED

• FAULT PULLED LOW INTERNALLY BY LT3579

• SWITCHER DISABLED

• CLKOUT DISABLED

• I

GATE

• SS CHARGES UP

• SWITCHER ENABLED

SS > 1.8V

AND NO FAULT1

CONDITIONS STILL DETECTED

POST FAULT DELAY

• SS SLOWLY DISCHARGES

FAULT1

SAMPLE MODE

• Q1 & Q2 SWITCHES

FORCED ON EVERY CYCLE

FOR AT LEAST MINIMUM

ON-TIME

FAULT1

SS < 50mV

• I

FULLY ACTIVATED

GATE

WHEN SS > 500mV

LOCAL FAULT OVER

• INTERNAL FAULT PULLDOWN

FAULT1

RELEASED BY LT3579

• SS CONTINUES DISCHARGING

TO GND

IF |V | DROPS CAUSING:

OUT

NORMAL MODE

FB < 1.17V (BOOST)

FAULT > 1.0V

OR

• NORMAL OPERATION

• CLKOUT ENABLED WHEN

SS > 1.8V

FB > 45mV (INVERTING)

FAULT1

FAULT1 = OVER VOLTAGE PROTECTION ON V (V > 16.2V (MIN))

FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V)

IN IN

OVER TEMPERATURE (T

> 165°C (TYP))

JUNCTION

> 3.4A (MIN))

OVER CURRENT ON SW1 (I

SW1

OVER VOLTAGE PROTECTION ON SW1 (V

> 42V (MIN))

SW1

SW2

3759 SD

Figure 2. State Diagram

35791f

9

LT3579/LT3579-1

OPERATION

OPERATION – OVERVIEW

V

IN

V

IN

The LT3579 uses a constant-frequency, current mode

controlschemetoprovideexcellentlineandloadregulation.

Thepart’sundervoltagelockout(UVLO)function,together

with soft-start and frequency foldback, offers a controlled

means of starting up. Fault features are incorporated in

the LT3579 to aid in the detection of output shorts, over-

voltage,andovertemperatureconditions.RefertotheBlock

Diagram (Figure 1) and the State Diagram (Figure 2) for

the following description of the part’s operation.

ACTIVE/

1.33V

–

+

R

UVLO1

LOCKOUT

SHDN

11.6μA

AT 1.33V

R

UVLO2

(OPTIONAL)

GND

3579 F03

Figure 3. Conﬁgurable UVLO

OPERATION – START-UP

The LT3579 also has internal UVLO circuitry that disables

the chip when V < 2.3V (typical).

IN

Several functions are provided to enable a very clean

start-up for the LT3579.

Soft-Start of Switch Current

Precise Turn-On Voltage

The soft-start circuitry provides for a gradual ramp-up of

theswitchcurrent(refertoCommandedSwitchCurrentvs.

SSinTypicalPerformanceCharacteristics). Whenthepart

is brought out of shutdown, the external SS capacitor is

ﬁrstdischargedwhichresetsthestatesofthelogiccircuits

in the chip. Then an integrated 250k resistor pulls the SS

pin to ~1.8V at a ramp rate set by the external capacitor

connected to the pin. Once SS gets to 1.8V, the CLKOUT

pin is enabled, and an internal regulator pulls the pin up

quickly to ~2.1V. Typical values for the external soft-start

capacitor range from 100nF to 1ꢀF.

TheSHDNpincomparestoaninternalvoltagereferenceto

give a precise turn on voltage level. Taking the SHDN pin

above1.33V(typical)enablesthepart.TakingtheSHDNpin

below0.3Vshutsdownthechip,resultinginextremelylow

quiescent current. The SHDN pin has 30mV of hysteresis

to protect against glitches and slow ramping.

Undervoltage-Lockout (UVLO)

The SHDN pin can also be used to create a conﬁgurable

UVLO.TheUVLOfunctionsetstheturnon/offoftheLT3579

at a desired input voltage (VIN

). Figure 3 shows how

Soft-Start of External PMOS (if used)

UVLO

a resistor divider (or single resistor) from V to the SHDN

IN

The soft-start circuitry also gradually ramps up the GATE

pin pull-down current which allows an external PMOS

to slowly turn on (M1 in Block Diagram). The GATE pin

currentincreaseslinearlywithSSvoltage,withamaximum

current of 933μA when the SS voltage gets above 500mV.

Note that if the GATE pin voltage is less than 2V for SS

voltages exceeding 500mV, then the GATE pin impedance

to ground is 2kΩ. The soft turn on of the external PMOS

helps limit inrush current at start-up, making hot plugs

of the LT3579 feasible and safe.

pin can be used to set VIN

. R

is optional. It may

UVLO UVLO2

be left out, in which case set it to inﬁnite in the equation

below. For increased accuracy, set R ≤ 10kΩ. Pick

UVLO2

R

as follows:

UVLO1

VIN_UVLO–1.33V

R_UVLO1

=

⎛

⎜

⎞

⎟

1.33V

+ 11.6µA

⎜

R_UVLO2

⎝

⎠

35791f

10

LT3579/LT3579-1

OPERATION

Sample Mode

sense resistor (R ) generating a voltage proportional to

S

the total switch current. This voltage (ampliﬁed by A4) is

added to a stabilizing ramp and the resulting sum is fed

into the positive terminal of the PWM comparator A3.

When the voltage on the positive input of A3 exceeds

the voltage on the negative input, the SR latch is reset,

turning off the master and slave power switches. The

Sample Mode is the mechanism used by the LT3579 to

aid in the detection of output shorts. It refers to a state of

the LT3579 where the master and slave power switches

(Q1 and Q2) are turned on for a minimum period of time

every clock cycle (or every few clock cycles in frequency

foldback) in order to “sample” the inductor current. If the

sampled current through Q1 exceeds the master switch

current limit of 3.4A (minimum), the LT3579 triggers an

overcurrentfaultinternally(seeOperation-Faultsectionfor

details). Sample Mode exists when FB is out of regulation

by more than 3.7% or 45mV < FB < 1.17V (typical). The

LT3579’s power switches are designed to handle a total

peak current of 6A (minimum).

voltage on the negative input of A3 (V pin) is set by A1

C

(or A2), which is simply an ampliﬁed difference between

the FB pin voltage and the reference voltage (1.215V if

the LT3579 is conﬁgured as a boost converter, or 9mV

if conﬁgured as an inverting converter). In this manner,

the error amplifer sets the correct peak current level to

maintain output regulation.

As long as the part is not in fault (see Operation – FAULT

section)andtheSSpinexceeds1.8V, theLT3579drivesits

CLKOUTpinatthefrequencysetbytheRTpinortheSYNC

pin. The CLKOUT pin can synchronize other compatible

switchingregulatorICs(includingadditionalLT3579s)with

the LT3579. Additionally, the duty cycle of CLKOUT varies

linearly with the part’s junction temperature and may be

used as a temperature monitor. The CLKOUT signal on the

LT3579-1 is ~180° out of phase with the internal oscillator

and has a ﬁxed duty cycle of ~50%.

Frequency Foldback

The frequency foldback circuit reduces the switching

frequency when 350mV < FB < 900mV (typical). This

feature lowers the minimum duty cycle that the part can

achieve,thusallowingbettercontroloftheinductorcurrent

during start-up. When the FB voltage is pulled outside of

this range, the switching frequency returns to normal.

Note that the peak inductor current at start-up is a

function of many variables including load proﬁle, output

capacitance,targetV ,V ,switchingfrequency,etc.Test

OUT IN

OPERATION – FAULT

the application’s performance at start-up to ensure that

the peak inductor current does not exceed the minimum

current limit.

The LT3579’s FAULT pin is an active low, bidirectional

pin (refer to Block Diagram) that pulls low to indicate a

fault. Each of the following events can trigger a fault in

the LT3579:

OPERATION – REGULATION

A. FAULT1 Events:

1.SW Overcurrent

The following description of the LT3579’s operation

assumes the FB voltage is close enough to its regulation

target so that the part is not in Sample Mode. Use the

Block Diagram as a reference when stepping through

the following description of the LT3579 operating in

regulation. At the start of each oscillator cycle, the SR

latch (SR1) is set, which turns on the power switches Q1

and Q2. The collector current through the master switch,

Q1, is ~1.3 times the collector current through the slave

switch, Q2, when the collectors of the two switches are

tied together. Q1’s emitter current ﬂows through a current

a. I

> 3.4A (minimum)

SW1

b. (I

+ I

) > 6A (minimum)

SW1

SW2

2.V Voltage > 16.2V (minimum)

IN

3.SW1 Voltage and/or SW2 Voltage > 42V

(minimum)

4.Die Temperature > 165°C

B. FAULT2 Events:

1.Pulling the FAULT pin low externally

35791f

11

LT3579/LT3579-1

OPERATION

When a fault is detected, in addition to the FAULT pin

being pulled low internally, the LT3579 also disables

its CLKOUT pin, turns off its power switches, and the

GATE pin becomes high impedance (refer to the State

Diagram). The external PMOS, M1, turns off when the

gate of M1 is pulled up to its source by the external

V

OUT

10V/DIV

CLKOUT

2V/DIV

IL

5A/DIV

R

resistor (see Block Diagram) With the external

FAULT

5V/DIV

GATE

PMOS turned off, the power path from V to V

is

IN

OUT

35791 F04

10μs/DIV

cut off, protecting power components downstream.

Figure 4. Output Short Circuit Protection of the LT3579

At the same time, a timeout sequence commences where

the SS pin is charged up to 1.8V(the SS pin will continue

charging up to ~2.1V and be held there in the case of

a FAULT1 event still existing), and then discharged to

50mV. This timeout period relieves the part, the PMOS,

and other downstream power components from electrical

and thermal stress for a minimum amount of time as set

by the voltage ramp rate on the SS pin.

SS

2V/DIV

GATE

5V/DIV

IL

5A/DIV

FAULT

In the absence of faults, the FAULT pin is pulled high by

5V/DIV

the external R

resistor (typically 100k). Figures 4

35791 F05

FAULT

50ms/DIV

and 5 show the events that accompany the detection of

an output short on the LT3579.

Figure 5. Continuous Output Short Showing FAULT Timeout Cycle

35791f

12

LT3579/LT3579-1

APPLICATIONS INFORMATION

BOOST CONVERTER COMPONENT SELECTION

Table 1. Boost Design Equations

PARAMETERS/EQUATIONS

to calculate equations below.

D1

30V, 4A

L1

2.2μH

OPTIONAL

Step 1: Pick V , V , and f

IN OUT OSC

V

12V

1.7A

OUT

M

1

V

5V

IN

Inputs

C

10μF

OUT1

V_OUT– V +0.5V

_OUT+ 0.5V – 0.27V

Step 2:

DC

IN

R

130k

R

6.3k

DC ≅

FB

GATE

V

SW1 SW2

C

10μF

OUT

V

FB

IN

100k

200k

FAULT

GATE

V

IN

V – 0.27V •DC

(

)

IN

L_TYP

L_MIN

L_MAX

=

(1)

(2)

(3)

LT3579

f_OSC•1.8A

CLKOUT

SHDN

C

22μF

V – 0.27V • 2•DC – 1

IN

) (

)

IN

V

C

RT

=

R

8k

C

47pF

4A •f_OSC• 1– DC

F

(

)

SYNC GND

SS

Step 3:

L1

R

C

SS

0.1μF

T

C

2.2nF

C

V – 0.27V •DC

(

)

86.6k

IN

=

f_OSC• 0.5A

37591 F06

• Solve equations 1, 2, and 3.

Figure 6. Boost Converter – The Component Values Given Are

Typical Values for a 1MHz, 5V to 12V Boost

• Choose the higher value between L and L

for L1.

TYP

MIN

L1 should never exceed L

.

MAX

The LT3579 can be conﬁgured as a Boost converter as in

Figure 6. This topology allows for positive output voltages

that are higher than the input voltage. An external PMOS

(optional)drivenbytheGATEpinoftheLT3579canachieve

input or output disconnect during a FAULT event. A single

feedback resistor sets the output voltage. For output

voltages higher than 40V, see the Charge Pump topology

in the Charge Pump Aided Regulators section.

V – 0.27V •DC

(

)

IN

Step 4:

RIPPLE

I_RIPPLE

=

I

f_OSC•L1

⎛

⎞

I_RIPPLE

2

Step 5:

I_OUT= 6A –

• 1– DC

(

)

⎜

⎟

I

OUT

⎝

⎠

Step 6:

D1

V_R> V_OUT;I_AVG>I_OUT

I_OUT• DC

Step 7:

C

_OUT=C_OUT1=

C

OUT,

OUT1

Table 1 is a step-by-step set of equations to calculate

component values for the LT3579 when operating as a

Boost converter. Input parameters are input and output

f_OSC• 0.01•V –0.5•I_OUT•R_{DSON_PMOS}

(

)

OUT

C_IN=C_PWR+C_VIN

Step 8:

voltage, and switching frequency (V , V

and f

I_RIPPLE

6A •DC

40 • f_OSC• 0.005• V

IN

OUT

OSC

C

C_IN=

+

IN

respectively). RefertotheAppendixforfurtherinformation

8 • f_OSC•0.005• V

IN

on the design equations presented in Table 1.

V_OUT– 1.215V

83.3μA

Step 9:

R_FB

=

R

FB

Variable Deﬁnitions:

V = Input Voltage

OUT

DC = Power Switch Duty Cycle

87.6

f_OSC

IN

Step 10:

T

R_T=

–1; f_OSCinMHz andR_Tin kΩ

R

V

= Output Voltage

Only needed for input or output disconnect. See PMOS

Selection in the Appendix for information on sizing the PMOS

and the biasing resistor, R

Step 11:

PMOS

f

I

= Switching Frequency

OSC

OUT

.

GATE

= Maximum Output Current

Note: The maximum design target for peak switch current is 6A and

is used in this table. The ﬁnal values for C and C may deviate

from the above equations in order to obtain desired load transient

= Inductor Ripple Current

RIPPLE

OUT

IN

R

= R

of External PMOS (set to 0 if not

DSON_PMOS

DSON

using PMOS)

performance for a particular application.

35791f

13

LT3579/LT3579-1

APPLICATIONS INFORMATION

SEPIC CONVERTER COMPONENT SELECTION

– COUPLED OR UN-COUPLED INDUCTORS

Table 2. SEPIC Design Equations

PARAMETERS/EQUATIONS

Pick V , V , and f to calculate equations below.

Step 1:

Inputs

IN OUT

OSC

C1

4.7μF

D1

60V, 3A

L1

6.8μH

V

12V

1.6A (V

1.9A (V

OUT

V

PWR

V_OUT+0.5V

9V TO 16V

>9V)

>12V)

PWR

DC ≅

C

4.7μF

PWR

Step 2: DC

L2

6.8μH

V_{IN +}V_OUT+ 0.5V – 0.27V

R

130k

FB

C

10μF

s3

OUT

SW1 SW2

V

3.3V

TO 5V

IN

V – 0.27V •DC

(

)

IN

V

FB

IN

L_TYP

L_MIN

L_MAX

=

(1)

(2)

(3)

f_OSC•1.8A

SHDN

GATE

LT3579

100k

V – 0.27V • 2•DC – 1

) (

4A •f_OSC• 1– DC

)

IN

=

C

FAULT

CLKOUT

VIN

4.7μF

(

)

V

C

RT

C

47pF

V – 0.27V •DC

F

(

=

)

IN

R

9.53k

C

SYNC GND

SS

Step 3: L

R

T

86.6k

f_OSC• 0.5A

C

SS

C

2.2nF

C

0.22μF

• Solve equations 1, 2, and 3.

• Choose the higher value between L and L

3759 F07

for L.

MIN

TYP

L should never exceed L

.

MAX

• L = L1 = L2 for coupled inductors.

Figure 7. SEPIC Converter – The Component Values Given Are

Typical Values for a 1MHz, 9V–16V to 12V SEPIC Topology Using

Coupled Inductors

• L = L1⏐⏐L2 for un-coupled inductors.

V – 0.27V •DC

(

=

)

IN

Step 4:

RIPPLE

I_RIPPLE

The LT3579 can also be conﬁgured as a SEPIC as in

Figure 7. This topology allows for positive output voltages

thatarelower,equal,orhigherthantheinputvoltage.Output

disconnect is inherently built into the SEPIC topology,

meaning no DC path exists between the input and output

due to capacitor C1. This implies that a PMOS controlled

by the GATE pin is not required in the power path.

I

f_OSC•L

⎛

⎞

I_RIPPLE

2

I_OUT= 6A –

• 1– DC

(

Step 5: I

)

⎜

⎟

OUT

⎝

⎠

V_R> V + V_OUT;I_AVG>I_OUT

Step 6: D1

Step 7: C1

IN

4.7μF (typical); V_RATING> V

IN

Table 2 is a step-by-step set of equations to calculate

component values for the LT3579 when operating as a

SEPICconverterusingcoupledinductors.Inputparameters

are input and output voltage, and switching frequency

I_OUT• DC

_OSC• 0.005 •V

C_OUT

=

Step 8: C

OUT

f

OUT

I_RIPPLE

8 • f_OSC• 0.005• V

C_PWR

=

(V , V

and f

respectively). Refer to the Appendix

Step 9: C

PWR

IN OUT

OSC

IN

for further information on the design equations presented

in Table 2.

6A •DC

40 • f_OSC• 0.005• V

C_VIN

=

Step 10: C

Step 11: R

VIN

FB

T

IN

Variable Deﬁnitions:

V_OUT– 1.215V

83.3μA

R_FB

=

V = Input Voltage

IN

OUT

V

= Output Voltage

DC = Power Switch Duty Cycle

87.6

f_OSC

R_T=

–1; f_OSCinMHz andR_Tin kΩ

Step 12: R

f

I

= Switching Frequency

OSC

OUT

= Maximum Output Current

Note: The maximum design target for peak switch current is 6A and

is used in this table. The ﬁnal values for C , C , and C may

= Inductor Ripple Current

RIPPLE

OUT PWR

VIN

deviate from the above equations in order to obtain desired load

transient performance for a particular application.

35791f

14

LT3579/LT3579-1

APPLICATIONS INFORMATION

DUAL INDUCTOR INVERTING CONVERTER COMPONENT

SELECTION – COUPLED OR UN-COUPLED INDUCTORS

Table 3. Dual Inductor Inverting Design Equations

PARAMETERS/EQUATIONS

to calculate equations below.

Pick V , V , and f

Step 1: Inputs

Step 2: DC

IN OUT

OSC

C1

4.7μF

L2

3.3μH

L1

3.3μH

V

–12V

1.2A

OUT

|V_OUT|+0.5V

V +|V_OUT|+0.5V – 0.27V

V

5V

IN

DC ≅

D1

30V, 2A

R

144k

IN

FB

SW1 SW2

V – 0.27V •DC

(

)

V

IN

FB

GATE

L_TYP

L_MIN

L_MAX

=

(1)

(2)

(3)

C

10μF

OUT

f_OSC•1.8A

C

22μF

SHDN

IN

s2

V – 0.27V • 2•DC – 1

LT3579

(

) (

4A •f_OSC• 1– DC

)

IN

100k

FAULT

RT

CLKOUT

(

)

V

C

R

C

V – 0.27V •DC

(

)

IN

SYNC

GND

SS

C

F

27pF

=

20k

Step 3: L

f_OSC• 0.5A

R

T

C

1nF

SS

C

72k

0.22μF

• Solve equations 1, 2, and 3.

• Choose the higher value between L and L

3759 F08

for L.

MIN

TYP

L should never exceed L

.

MAX

Figure 8. Dual Inductor Inverting Converter – The Component

Values Given Are Typical Values for a 1.2MHz, 5V to –12V Inverting

Topology Using Coupled Inductors

• L = L1 = L2 for coupled inductors.

• L = L1⏐⏐L2 for un-coupled inductors.

V – 0.27V •DC

(

=

)

IN

Due to its unique FB pin, the LT3579 can work in a Dual

Inductor Inverting conﬁguration as in Figure 8. Changing

the connections of L2 and the Schottky diode in the

SEPIC topology, results in generating negative output

voltages. This solution results in very low output voltage

ripple due to inductor L2 in series with the output. Output

disconnect is inherently built into this topology due to the

capacitor C1.

I_RIPPLE

Step 4: I

Step 5: I

RIPPLE

f_OSC•L

⎛

⎞

I_RIPPLE

2

I_OUT= 6A –

• 1– DC

(

)

⎜

⎟

OUT

⎝

⎠

V_R> V +|V_OUT|;I_AVG>I_OUT

Step 6: D1

Step 7: C1

IN

4.7μF (typical); V_RATING> V +|V_OUT

|

IN

I_RIPPLE

8 • f_OSC•0.005•|V_OUT

Table 3 is a step-by-step set of equations to calculate

componentvaluesfortheLT3579whenoperatingasaDual

InductorInvertingconverterusingcoupledinductors.Input

parameters are input and output voltage, and switching

C_OUT

=

Step 8: C

Step 9: C

OUT

|

C_IN=C_PWR+C_VIN

I_RIPPLE

8 • f_OSC•0.005• V

6A •DC

40 • f_OSC•0.005• V

IN

C_IN=

+

frequency (V , V

and f

respectively). Refer to the

IN OUT

OSC

IN

Appendix for further information on the design equations

presented in Table 3.

|V_OUT|+ 9mV

R_FB

=

Step 10: R

Step 11: R

FB

83.3μA

Variable Deﬁnitions:

87.6

f_OSC

R_T=

–1; f_OSCinMHz andR_Tin kΩ

V = Input Voltage

T

IN

OUT

V

= Output Voltage

Note: The maximum design target for peak switch current is 6A and

is used in this table. The ﬁnal values for C and C may deviate

DC = Power Switch Duty Cycle

OUT

IN

f

I

= Switching Frequency

OSC

OUT

from the above equations in order to obtain desired load transient

performance for a particular application.

= Maximum Output Current

= Inductor Ripple Current

RIPPLE

35791f

15

LT3579/LT3579-1

APPLICATIONS INFORMATION

LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL

INDUCTOR INVERTING TOPOLOGIES

• Place the bypass capacitor for the inductor (C

close as possible to the inductor.

) as

PWR

• Bypass capacitors, C

and C , may be combined

VIN

PWR

General Layout Guidelines

intoasinglebypasscapacitor,C ,iftheinputsideofthe

IN

• To optimize thermal performance, solder the exposed

ground pad of the LT3579 to the ground plane with

multiple vias around the pad connecting to additional

ground planes.

inductor can be close to the V pin of the LT3579.

• The load should connect directly to the positive and

negative terminals of the output capacitor for best load

regulation.

• Agroundplaneshouldbeusedundertheswitchercircuitry

to prevent interplane coupling and overall noise.

Boost Topology Speciﬁc Layout Guidelines

• Highspeedswitchingpath(seespeciﬁctopologybelowfor

more information) must be kept as short as possible.

• Keep length of loop (high speed switching path)

governingswitch, diodeD1, outputcapacitorC , and

OUT

groundreturnasshortaspossibletominimizeparasitic

inductive spikes at the switch node during switching.

• The V , FB, and RT components should be placed as

C

close to the LT3579 as possible, while being as far

away as practically possible from the switch node. The

groundforthesecomponentsshouldbeseparatedfrom

the switch current path.

SEPIC Topology Speciﬁc Layout Guidelines

• Keeplengthofloop(highspeedswitchingpath)governing

switch,ﬂyingcapacitorC1,diodeD1,outputcapacitorC

,

OUT

• Place the bypass capacitor for the V pin (C ) as

IN

VIN

andgroundreturnasshortaspossibletominimizeparasitic

inductive spikes at the switch node during switching.

close as possible to the LT3579.

VIAS TO GROUND PLANE REQUIRED TO IMPROVE

THERMAL PERFORMANCE

GND

21

1

20

SYNC

2

3

4

5

19

18

17

16

15

14

13

12

11

SHDN

CLKOUT

C

IN

6

7

–

A

B

C

8

–

9

V

IN

C

OUT1

D1

OUT

10

V

OUT

+

M1

L1

+

D2

3579 F08

A– RETURN C GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C GROUND

IN

WITH GND EXCEPT AT THE EXPOSED PAD.

B– RETURN C

AND C

GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE

OUT

OUT1

C

AND C

GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

OUT1

OUT

Figure 9. Suggested Component Placement for Boost Topology in FE20 Package

35791f

16

LT3579/LT3579-1

APPLICATIONS INFORMATION

Inverting Topology Speciﬁc Layout Guidelines

• Keep ground return path from the cathode of D1 (to

the heat generated within the package. This can be

accomplished by taking advantage of the thermal pad on

the underside of the IC. It is recommended that multiple

vias in the printed circuit board be used to conduct heat

away from the IC and into a copper plane with as much

area as possible.

chip) separated from output capacitor C ’s ground

OUT

return path (to chip) in order to minimize switching

noise coupling into the output. Notice the separate

ground return for D1’s cathode in Figure 11.

• Keep length of loop (high speed switching path)

governing switch, ﬂying capacitor C1, diode D1, and

groundreturnasshortaspossibletominimizeparasitic

inductive spikes at the switch node during switching.

Power & Thermal Calculations

Power dissipation in the LT3579 chip comes from four

2

primary sources: switch I R loss, NPN base drive loss

(AC), NPN base drive loss (DC), and additional V pin

IN

current. These formulas assume continuous mode

operation, so they should not be used for calculating

thermal losses or efﬁciency in discontinuous mode or at

light load currents.

THERMAL CONSIDERATIONS

For the LT3579 to deliver its full output power, it is imp-

erative that a good thermal path be provided to dissipate

VIAS TO GROUND PLANE REQUIRED TO IMPROVE

THERMAL PERFORMANCE

GND

21

1

2

3

4

5

20

19

18

17

16

15

14

13

12

11

SYNC

SHDN

CLKOUT

C

IN

6

7

–

8

A

B

9

V

+

IN

10

–

C

OUT

V

OUT

C1

D1

L1

L2

+

3579 F10

A– RETURN C AND L2 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

IN

OUT

IN

B– RETURN C

GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C

GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

OUT

L1, L2 –MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.

Figure 10. Suggested Component Placement for SEPIC Topology in FE20 Package

35791f

17

LT3579/LT3579-1

APPLICATIONS INFORMATION

VIAS TO GROUND PLANE REQUIRED TO IMPROVE

THERMAL PERFORMANCE

GND

21

1

2

3

4

20

19

18

17

16

15

14

13

12

11

SYNC

SHDN

CLKOUT

5

C

IN

6

7

–

8

9

A

C

B

V

+

IN

10

GND

C

OUT

C1

D1

–V

OUT

L1

L2

3579 F11

A– RETURN C GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

IN

OUT

IN

OUT

B– RETURN C

GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C

GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

C– RETURN D1 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.

L1, L2 – MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE.

Figure11. SuggestedComponentPlacementforInvertingTopologyinFE20Package.

Note Separate Ground Path for D1’s Cathode

35791f

18

LT3579/LT3579-1

APPLICATIONS INFORMATION

The following example calculates the power dissipation

in the LT3579 for a particular boost application:

where T =Die Junction Temperature, T =Ambient

J

A

Temperature,P

istheﬁnalresultfromthecalculations

TOTAL

(V = 5V, V

= 12V, I

= 1.5A, f

= 1MHz,

shown in Table 4, and θ is the thermal resistance from

IN

OUT

= 0.185V).

OSC

JA

V = 0.5V, V

the silicon junction to the ambient air.

D

CESAT

To calculate die junction temperature, use the appropriate

thermalresistancenumberandaddinworst-caseambient

temperature:

T = T + θ • P

J

A

JA

TOTAL

Table 4. Boost Power Calculations Example with V_IN= 5V, V_OUT= 12V, I_OUT= 1.5A, f_OSC= 1MHz, V_D= 0.5V, V_CESAT= 0.185V

DEFINITION OF VARIABLES

EQUATIONS

DESIGN EXAMPLE

VALUE

DC = Switch Duty Cycle

DC = 60.9%

V_OUT– V + V_D

V_OUT+ V_D– V_CESAT

12V – 5V + 0.5V

12V +0.5V –.185V

IN

DC =

I

= Average Input Current

I

= 4A

IN

V

_OUT•I_OUT

12V •1.5A

5V • 0.9

I

=

I

=

IN

η = Power Conversion Efﬁciency

(typically 90% at high currents)

IN

V • η

IN

2

P

= Switch I R Loss

P

SW

= 438mW

SW

P_SW=DC•I ²•R_SW

P_SW= 0.609 •(4A)²• 45mΩ

IN

R

= Switch Resistance (typically

45mꢁ combined SW1 and SW2)

SW

P

= Base Drive Loss (AC)

= Base Drive Loss (DC)

P

= 624mW

= 305mW

BAC

BDC

BAC

P_BAC= 13ns•I_IN• V_OUT• f_OSC

P_BAC= 13ns• 4A •12V •1MHz

5V •4A •0.609

P

BDC

V •I_IN•DC

IN

P_BDC

=

P_BDC

=

40

P

INP

= Input Power Loss

P

INP

= 70mW

P

= 14mA • V

P = 14mA • 5V

INP

IN

P

TOTAL

= 1.437W

35791f

19

LT3579/LT3579-1

APPLICATIONS INFORMATION

The published (http://www.linear.com/designtools/

SWITCHING FREQUENCY

packaging/Linear_Technology_Thermal_Resistance_

Thereareseveralconsiderationsinselectingtheoperating

frequency of the converter. The ﬁrst is staying clear of

sensitive frequency bands, which cannot tolerate any

spectral noise. For example, in products incorporating RF

communications, the 455kHz IF frequency is sensitive to

any noise, therefore switching above 600kHz is desired.

Some communications have sensitivity to 1.1MHz and in

that case a 1.5MHz switching converter frequency may be

employed. The second consideration is the physical size

of the converter. As the operating frequency goes up, the

inductor and ﬁlter capacitors go down in value and size.

Thetradeoffisefﬁciency, sincetheswitchinglossesdueto

NPN base charge (see Thermal Considerations), Schottky

diode charge, and other capacitive loss terms increase

proportionally with frequency.

Table.pdf)θ valueis38°C/WfortheTSSOPExposedPad

JA

packageand34°C/Wforthe4mm×5mmQFNpackage. In

practice, lower θ values are realizable if board layout is

JA

performedwithappropriategrounding(accountingforheat

sinking properties of the board) and other considerations

listed in the Layout Guidelines section. For instance, a θ

JA

valueof~22°C/WwasconsistentlyachievedforbothTSSOP

and QFN packages of the LT3579 (at V = 5V, V = 12V,

IN

OUT

I

=1.7A,f =1MHz)whenboardlayoutwasoptimized

as per the suggestions in the Layout Guidelines section.

OUT

OSC

Junction Temperature Measurement

ThedutycycleoftheCLKOUTsignalontheLT3579islinearly

proportional to die junction temperature, T (the CLKOUT

J

duty cycle on the LT3579-1 is ﬁxed at ~50%). To get an

accurate reading, measure the duty cycle of the CLKOUT

signal and use the following equation to approximate the

junction temperature:

Oscillator Timing Resistor (R )

T

The operating frequency of the LT3579 can be set by the

internalfree-runningoscillator.WhentheSYNCpinisdriven

low (< 0.4V), the frequency of operation is set by a resistor

from the RT pin to ground. An internally trimmed timing

capacitor resides inside the IC. The oscillator frequency

is calculated using the following formula:

DC_CLKOUT– 35%

T_J=

0.3%

where DC

is the CLKOUT duty cycle in % and T is

J

CLKOUT

the die junction temperature in °C. Although the absolute

die temperature can deviate from the above equation by

15°C, the relationship between change in CLKOUT duty

cycle and change in die temperature is well deﬁned. A

3% increase in CLKOUT duty cycle corresponds to ~10°C

increase in die temperature:

87.6

R_T+ 1

f_OSC

=

where f

is in MHz and R is in kꢁ. Conversely, R (in

T T

OSC

kꢁ) can be calculated from the desired frequency (in

MHz) using:

Note that the CLKOUT pin is only meant to drive capacitive

loads up to 50pF.

87.6

f_OSC

R_T=

–1

Thermal Lockout

Afaultconditionoccurswhenthedietemperatureexceeds

~165°C(seeOperation–FAULTSection),andthepartgoes

into thermal lockout. The fault condition ceases when the

die temperature drops by ~5°C (nominal).

35791f

20

LT3579/LT3579-1

APPLICATIONS INFORMATION

Clock Synchronization

V

18V

1A

3.3μH

OUT

10μF

An external source can set the operating frequency of the

LT3579 by providing a digital clock signal into the SYNC

SW1 SW2

CLKOUT

200k

10μF

s2

GATE

V

pin (R resistor still required). The LT3579 will operate at

FB

IN

T

LT3579

SLAVE

4.7μF

the SYNC clock frequency. The LT3579 will revert to its

internalfree-runningoscillatorclockwhentheSYNCpinis

driven below 0.4V for a few free-running clock periods.

V

C

SS

FAULT

SHDN

RT

68pF

8k

SYNC GND

0.1μF

3.3nF

86.6k

Driving SYNC high for an extended period of time

effectively stops the operating clock and prevents latch

SR1 from becoming set (see Block Diagram). As a result,

the switching operation of the LT3579 will stop and the

CLKOUT pin will be held at ground.

V

12V

2.2μH

GATE

OUT

V

5V

IN

10μF

1.7A

SW1 SW2

CLKOUT

10k

130k

10μF

s3

The duty cycle of the SYNC signal must be between 20%

and 80% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

LT3579

FB

V

IN

MASTER

100k

110k

FAULT

V

C

47pF

SHDN

RT

SS

SYNC GND

1. SYNC may not toggle outside the frequency

range of 200kHz-2.5MHz unless it is stopped

below 0.4V to enable the free-running oscillator.

8k

4.7μF

0.1μF

2.2nF

86.6k

3579 F12

2. The SYNC frequency can always be higher than

thefree-runningoscillatorfrequency(assetbythe

Figure 12. Synchronize Multiple LT3579s. The External PMOS

Disconnects the Input from Both Power Paths During FAULT Events

R resistor),f ,butshouldnotbelessthan25%

T

OSC

below f

.

OSC

Also, the FAULT pins can be tied together so that a fault

condition from one LT3579 causes all of the LT3579s to

enter fault, until the fault condition disappears.

CLOCK SYNCHRONIZATION OF ADDITIONAL

REGULATORS

The CLKOUT pin of the LT3579 can synchronize additional

switching regulators and/or additional LT3579s as shown

in Figure 12.

2-Phase Converters using LT3579-1

The CLKOUT pin on the LT3579-1 is ~180° out of phase

with the internal oscillator, which allows two LT3579-1s to

operate in parallel for a high current, high power output.

The advantage of multiphase converters is that the ripple

current ﬂowing into the output node is divided by the

number of phases or ICs used to generate the output

The frequency of the master LT3579 is set by the external

R resistor. The SYNC pin of the slave LT3579 is driven

T

by the CLKOUT pin of the master LT3579. Note that the

RT pin of the slave LT3579 must have a resistor tied to

ground. It takes a few clock cycles for the CLKOUT signal

to begin oscillating, and it’s preferable for all LT3579s to

have the same internal free-running frequency. Therefore,

voltage. The V , SHDN, FAULT, FB, and V pins of all the

IN

C

LT3579-1sshouldbeconnectedtogether.Figure13shows

a typical application of a 2-phase 12V to 24V boost with

output disconnect.

in general, use the same value R resistor for all of the

T

synchronized LT3579s.

35791f

21

LT3579/LT3579-1

APPLICATIONS INFORMATION

Use the following equations to calculate the FB resistor

for 2-phase converters:

4.7μH

V

FAULT

LT3579-1

SLAVE

4.7μF

s2

10μF

SW1 SW2

CLKOUT

IN

⎛

⎜

⎝

⎞

⎟

⎠

V_OUT–1.215V

2• 83.3μA

FB

R =

; Boost or SEPIC

Multiphase Converter

FB

4.7μF

SHDN

RT

GATE

V

C

⎛

⎜

⎝

⎞

|V_OUT|+9mV

2• 83.3μA

R =

; Inverting Multiphase

Converter

⎟

SYNC GND SS

FB

⎠

0.22μF

86.6k

V

24V

OUT

V

OUT1

Note that the CLKOUT pin on the LT3579-1 runs at a ﬁxed

duty cycle of ~50%. If monitoring the die temperature is

desired, the slave IC can be a LT3579.

3.7A,

89W

4.7μH

V

PWR

12V

6.4k

4.7μF

s2

10μF

OUT1

4.7μF

s2

ItispossibletousetheLT3579-1inamultiphaseconverter

of more than 2 phases. Consult the LTC Applications

Engineering Department for more information.

SW1 SW2

V

IN

137k

V

IN

CLKOUT

5V

V

100k

FAULT

FB

LT3579-1

MASTER

V

500k

21.5k

PWR

SHDN GATE

RT

CHARGE PUMP AIDED REGULATORS

V

C

DesigningchargepumpswiththeLT3579canofferefﬁcient

solutions with fewer components than traditional circuits

because of the master/slave switch conﬁguration on the

IC. The current in the master switch (SW1) is sensed by

the current comparator (A4 in Block Diagram), but the

currentintheslaveswitch(SW2)isnot.Notethattheslave

switch, SW2, operates in phase with SW1. This method

of operation by the master/slave switches can offer the

following beneﬁts to charge pump designs:

4.7μF

47pF 7k

2.2nF

SYNC GND SS

86.6k

5k

0.22μF

3579 F13

Figure 13. 2-Phase Converters Using LT3579-1

High V

Charge Pump Topology

OUT

The LT3579 can be used in a charge-pump topology (refer

to Figure 16), multiplying the output of an inductive boost

converter. The master switch (SW1) can be used to drive

theinductiveboostconverter,whiletheslaveswitch(SW2)

canbeusedtodriveoneormorechargepumpstages.This

topology is useful for high voltage applications including

VFD Bias Supplies.

• The slave switch, by not performing a current sense

operation like the master switch, can sustain fairly

large current spikes when the ﬂying capacitors charge

up. Since this current spike ﬂows through SW2, it

does not affect the operation of the current comparator

(A4 in Block Diagram).

Single Inductor Inverting Topology

• The master switch, immune from the capacitor current

spike, can sense the inductor current more accurately.

If there is a need to use just 1 inductor to generate a

negative output voltage whose magnitude is greater than

V , the Single Inductor Inverting topology (shown in

Figure15)canbeused.Sincethemasterandslaveswitches

areisolatedbyanexternalSchottkydiode,thecurrentspike

through C1 will ﬂow through the slave switch, thereby

preventing the current comparator (A4 in Block Diagram)

from falsely tripping. Output disconnect is inherently built

into the single inductor topology.

• Since the slave switch can sustain large current spikes,

the diodes that feed current into the ﬂying capacitors

do not need current limiting resistors, leading to

efﬁciency and thermal improvements.

IN

35791f

22

LT3579/LT3579-1

APPLICATIONS INFORMATION

HOT PLUG

C1

D1

D3

L1

V

–V

IN

OUT

D2

The high inrush current associated with hot-plugging V

IN

R

FB

canbelargelyrejectedwiththeuseofanexternalPMOS. A

SW1

SW2

V

FB

IN

simple hot-plug controller can be designed by connecting

C

OUT

SHDN

GATE

an external PMOS in series with V , with the gate of the

IN

LT3579

100k

FAULT

PMOS being driven by the GATE pin of the LT3579. Since

the GATE pin pull-down current is linearly proportional to

theSSvoltage,andtheSSchargeuptimeisrelativelyslow,

the GATE pin pull-down current will increase gradually,

thereby turning on the external PMOS slowly. Controlled

in this manner, the PMOS acts as an input current limiter

CLKOUT

C

IN

RT

V

C

R

C

SYNC GND

SS

C

F

R

T

C

SS

3579 F15

Figure 15. Single Inductor Inverting Topology

when V hot-plugs or ramps up sharply.

IN

Likewise, when the PMOS is connected in series with the

output, inrush currents into the output capacitor can be

limitedduringahot-plugevent.Toillustratethis,thecircuit

in Figure 6 was re-conﬁgured by adding a large 1500μF

capacitor to the output. An 18ꢁ resistive load was used

and a 2.2μF capacitor was placed on SS. Figure 14 shows

the result of hot-plugging this re-conﬁgured circuit. The

V

100V

200mA

OUT2

4.7μF

V

67V

4.7μF

OUT1

100mA

10μH

inductor current is well behaved and V

comes up once

V

12V

OUT

IN

V settles out.

IN

6.8μF

383k

V

6.5k

6.8μF

IN

SW1 SW2

5V/DIV

V

FB

IN

100k

536k

FAULT

GATE

V

IN

OUT

LT3579

10V/DIV

SHDN

CLKOUT

I

L

5A/DIV

V

C

RT

10μF

SYNC GND

SS

27pF

34k

SS

1V/DIV

86.6k

2.2μF

470pF

3579 F16

3579 F14

1s/DIV

Figure 16. High V_OUTCharge Pump Topology

Figure 14. V_INHot-Plug Control. Inrush Current is Well Controlled

35791f

23

LT3579/LT3579-1

APPENDIX

SETTING THE OUTPUT VOLTAGE

For the boost topology (see Figure 6):

The output voltage is set by connecting a resistor (R )

V_OUT– V + V_D

_OUT+ V_D– V_CESAT

FB

IN

DC_BOOST

≅

from V

to the FB pin. R is determined from the

OUT

FB

V

following equation:

For the SEPIC or Dual Inductor Inverting topology (see

Figures 7 and 8):

|V_OUT– V |

FB

R_FB=

83.3μA

V_D+|V_OUT

V +|V_D|+ V_OUT− V_CESAT

|

DC_{SEPIC_&_INVERT}

≅

where V is 1.215V (typical) for non-inverting topologies

FB

IN

(i.e. boost and SEPIC regulators) and 9mV (typical) for

inverting topologies (see Electrical Characteristics).

FortheSingleInductorInvertingtopology(seeFigure14):

|V_OUT|−V + V_CESAT+3•V_D

IN

DC_{SI_INVERT}

≅

POWER SWITCH DUTY CYCLE

|V_OUT|+3•V_D

In order to maintain loop stability and deliver adequate

current to the load, the power NPNs (Q1 and Q2 in the

BlockDiagram)cannotremain“on”for100%ofeachclock

cycle. The maximum allowable duty cycle is given by:

The LT3579 can be used in conﬁgurations where the duty

cycle is higher than DC , but it must be operated in

MAX

the discontinuous conduction mode so that the effective

duty cycle is reduced.

T –MinOffTime

(

)

•100%

P

DC_MAX

=

INDUCTOR SELECTION

T_P

The high frequency operation of the LT3579 allows for

the use of small surface mount inductors. For high

efﬁciency, choose inductors with high frequency core

material, such as ferrite, to reduce core losses. Also to

improve efﬁciency, choose inductors with more volume

for a given inductance. The inductor should have low

where T is the clock period and MinOffTime (found in the

P

Electrical Characteristics) is typically 45nS.

Conversely, the power NPNs (Q1 and Q2 in the Block

Diagram) cannot remain “off” for 100% of each clock

cycle, and will turn on for a minimum time (MinOnTime)

wheninregulation.ThisMinOnTimegovernstheminimum

allowable duty cycle given by:

2

DCR (copper-wire resistance) to reduce I R losses, and

must be able to handle the peak inductor current without

saturating. Note that in some applications, the current

handling requirements of the inductor can be lower, such

as in the SEPIC topology where each inductor only carries

one half of the total switch current. Multilayer chokes or

chip inductors usually do not have enough core volume to

support peak inductor currents in the 4A to 7A range. To

minimizeradiatednoise,useatoroidalorshieldedinductor.

See Table 5 for a list of inductor manufacturers.

MinOnTime

(

)

•100%

DC_MIN

=

T_P

where T is the clock period and MinOnTime (found in the

P

Electrical Characteristics) is typically 55nS.

Theapplicationshouldbedesignedsuchthattheoperating

duty cycle is between DC

and DC

.

MIN

MAX

Duty cycle equations for several common topologies are

given below where V is the diode forward voltage drop

D

and V

is typically 250mV at 5.5A for a combined

SW1 and SW2 current.

CESAT

35791f

24

LT3579/LT3579-1

APPENDIX

where:

Table 5. Inductor Manufacturers

Vishay

IHLP-2020BZ-01 and

IHLP-2525CZ-01 Series

www.vishay.com

L

= L1 for Boost Topologies (see Figure 6)

= L1 = L2 for Coupled Dual Inductor

Topologies (see Figures 7 and 8)

= L1 || L2 for Uncoupled Dual Inductor

Topologies (see Figures 7 and 8)

= Switch Duty Cycle (see Power Switch Duty

Cycle section in Appendix)

= Maximum Peak Switch Current; Should

Not Exceed 6A for a Combined SW1 +

SW2 Current or 3.4A of SW1 Current (see

Electrical Characteristics section.)

= Power Conversion Efﬁciency (typically 90%

for Boost and 85% for Dual Inductor

Topologies at high currents)

BOOST

DUAL

Coilcraft

XLP, MLC and MSS Series www.coilcraft.com

Cooper Bussmann DRQ125 and DRQ127

Series

www.cooperbussmann.

com

L

DUAL

Sumida

TDK

CDRH series

www.sumida.com

www.tdk.com

DC

RLF and SLF series

Würth

WE-PD, WE-PDF, WE-HC

and WE-DD Series

www.we-online.com

I

PK

Minimum Inductance

Although there can be a tradeoff with efﬁciency, it is often

desirable to minimize board space by choosing smaller

inductors. When choosing an inductor, there are three

conditionsthatlimittheminimuminductance;(1)providing

adequate load current, (2) avoidance of subharmonic

oscillation, and (3) supplying a minimum ripple current

to avoid false tripping of the current comparator.

η

f

I

= Switching Frequency

= Maximum Output Current

OSC

OUT

Negative values of L

or L

indicate that the

BOOST

DUAL

output load current, I , exceeds the switch current limit

OUT

Adequate Load Current

capability of the LT3579.

Smallvalueinductorsresultinincreasedripplecurrentsand

thus, due to the limited peak switch current, decrease the

average current that can be provided to the load. In order

to provide adequate load current, L should be at least:

Avoiding Sub-Harmonic Oscillations

The LT3579’s internal slope compensation circuit will

prevent sub-harmonic oscillations that can occur when

the duty cycle is greater than 50%, provided that the

inductance exceeds a minimum value. In applications that

operate with duty cycles greater than 50%, the inductance

must be at least:

DC • V − V

(

)

Boost

Topology

IN

CESAT

L_BOOST

>

⎛

⎞

⎟

V_OUT•I_OUT

2• f_OSC• I

−

⎜

PK

V • η

⎝

⎠

IN

V − V

( _CESAT) (

=

• 2•DC−1

)

or

IN

L_MIN

SEPIC

or

4A•f_OSC• 1−DC

(

)

DC • V − V

(

)

IN

CESAT

L_DUAL

>

where:

Inverting

⎛

⎞

|V_OUT|•I_OUT

2• f_OSC• I −

−I_OUT

Topologies

⎜

⎟

PK

L

= L1 for Boost Topologies (see Figure 6)

= L1 = L2 for Coupled Dual Inductor

Topologies (see Figures 7 and 8)

= L1 || L2 for Uncoupled Dual Inductor

Topologies (see Figures 7 and 8)

MIN

V • η

⎝

⎠

IN

L

MIN

35791f

25

LT3579/LT3579-1

APPENDIX

Maximum Inductance

DIODE SELECTION

Excessive inductance can reduce ripple current to levels

thataredifﬁcultforthecurrentcomparator(A4intheBlock

Diagram) to cleanly discriminate, thus causing duty cycle

jitter and/or poor regulation. The maximum inductance

can be calculated by:

Schottky diodes, with their low forward voltage drops and

fast switching speeds, are recommended for use with the

LT3579. Choose a Schottky with low parasitic capacitance

toreducereversecurrentspikesthroughthepowerswitch

of the LT3579. The Diodes Inc. MBRM360 is a very good

choice with a 60V reverse voltage rating and an average

forward current of 3A.

V − V

•DC

(

=

)

IN

CESAT

L_MAX

where:

f_OSC• 0.5A

OUTPUT CAPACITOR SELECTION

L

= L1 for Boost Topologies (see Figure 6)

= L1 = L2 for Coupled Dual Inductor

Topologies (see Figures 7 and 8)

= L1 || L2 for Uncoupled Dual Inductor

Topologies (see Figures 7 and 8)

Low ESR (equivalent series resistance) capacitors should

beusedattheoutputtominimizetheoutputripplevoltage.

Multilayer ceramic capacitors are an excellent choice, as

they have an extremely low ESR and are available in very

small packages. X5R or X7R type are preferred, as these

materials retain their capacitance over wide voltage and

temperature ranges. A 22ꢀF to 47ꢀF output capacitor is

sufﬁcient for most applications, but systems with low

output currents may need only 4.7ꢀF to 22ꢀF. Always

use a capacitor with a sufﬁcient voltage rating. Many

ceramic capacitors, particularly 0805 or 0603 case sizes,

have greatly reduced capacitance at the desired output

voltage. Tantalum polymer or OS-CON capacitors can be

used, but it is likely that these capacitors will occupy more

board area than a ceramic, and will have higher ESR with

greater output ripple.

MAX

L

MAX

Inductor Current Rating

The inductor(s) must have a rating greater than its (their)

peakoperatingcurrenttopreventinductorsaturation,which

would result in catastrophic failure and efﬁciency losses.

The maximum inductor current (considering start-up and

steady-state conditions) is given by:

V • T_{MIN_PROP}

IN

I_{L_PEAK}=I_LIM

where:

+

L

I

= Peak Inductor Current in L1 for a Boost

Topology, or the sum of the Peak

Inductor Currents in L1 and L2 for Dual

Inductor Topologies.

= For Hard-Saturation Inductors, 9.4A with

SW1 and SW2 Tied Together, or 5.1A

with just SW1 used. For Soft-Saturation

Inductors, 6A with SW1 and SW2 Tied

Together, or 3.4A with just SW1 used.

= 100ns (Propagation Delay through the

Current Feedback Loop).

L_PEAK

INPUT CAPACITOR SELECTION

Ceramic capacitors make a good choice for the input

decoupling capacitor, C , which should be placed as

VIN

I

LIM

closeaspossibletotheV pinoftheLT3579.Thisensures

IN

that the voltage seen at the V pin of the LT3579 remains

IN

a nearly ﬂat DC voltage. A 1ꢀF to 4.7ꢀF input capacitor is

sufﬁcient for most applications.

T

A ceramic bypass capacitor, C

, should also be placed

MIN_PROP

PWR

as close as possible to the input of the inductor. This

ensures that the inductor ripple current is supplied from

the bypass capacitor and provides a nearly ﬂat DC voltage

to the input of the voltage converter. A 4.7μF to 10μF input

power capacitor is sufﬁcient for most applications.

Note that these equations offer conservative results for

the required inductor current ratings. The current ratings

could be lower for applications with light loads, provided

the SS capacitor is sized appropriately to limit inductor

currents at start-up.

35791f

26

LT3579/LT3579-1

APPENDIX

Table 6 shows a list of several ceramic capacitor man-

ufacturers. Consult the manufacturers for detailed infor-

mation on their entire selection of ceramic parts.

the relationship between R

(see Block Diagram) and

GATE

the desired V that the PMOS is biased with:

SG

⎧

R_GATE

V

if V_GATE<2V

⎪

^SR_GATE+ 2kΩ

V =

⎨

⎪

⎩

Table 6. Ceramic Capacitor Manufacturers

TDK

SG

www.tdk.com

933μA•R_GATEif V_GATE>2V

Murata

www.murata.com

www.t-yuden.com

Taiyo Yuden

WhenusingaPMOS,itisadvisabletoconﬁgurethespeciﬁc

application for undervoltage lockout (see the Operations

section). The goal is to have V get to a certain minimum

IN

PMOS SELECTION

voltage where the PMOS has sufﬁcient headroom to attain

An external PMOS, controlled by the LT3579’s GATE pin,

can be used to facilitate input or output disconnect. The

GATE pin turns on the PMOS gradually during start-up

(seeSoft-StartofExternalPMOSintheOperationsection),

and turns the PMOS off when the LT3579 is in shutdown

or in fault.

a high enough V , which prevents it from entering the

SG

saturation mode of operation during start-up.

Figure 6 shows the PMOS connected in series with the

output to act as an output disconnect during a fault

condition.TheSchottkydiodefromtheV pintotheGATE

IN

pin is optional and helps turn off the PMOS quicker in the

The use of the external PMOS, controlled by the GATE pin,

is particularly beneﬁcial when dealing with unintended

output shorts in a boost regulator. In a conventional boost

regulator,theinductor,Schottkydiode,andpowerswitches

are susceptible to damage in the event of an output short

toground.UsinganexternalPMOSintheboostregulator’s

event of hard shorts. The resistor from V to the SHDN

IN

pin sets a UVLO of 4V for this application.

ConnectingthePMOSinserieswiththeoutputofferscertain

advantages over connecting it in series with the input:

• Since the load current is always less than the input

current for a boost converter, the current rating of the

PMOS goes down when connected in series with the

output as opposed to the input.

powerpath(pathfromV toV )controlledbytheGATE

IN

OUT

pin, will serve to disconnect the input from the output

when the output has a short to ground, thereby helping

save the IC, and the other components in the power path

from damage.

• A PMOS in series with the output can be biased with

a higher overdrive voltage than a PMOS used in series

The PMOS chosen must be capable of handling the

maximum input or output current depending on whether

the PMOS is used at the input (see Figure 12) or the output

(see Figure 13).

with the input, since V

> V . This higher overdrive

OUT

IN

resultsinalowerR

forthePMOS,therebyimproving

DSON

the efﬁciency of the regulator.

In contrast, an input connected PMOS works as a simple

hot-plug controller (covered in more detail in the Hot-Plug

section). The input connected PMOS also functions as an

inexpensive means of protecting against multiple output

shorts in boost applications that synchronize the LT3579

with other compatible ICs (see Figure 12).

EnsurethatthePMOSisbiasedwithenoughsourcetogate

voltage (V ) to enhance the device into the triode mode

SG

of operation. The higher the V voltage that biases the

SG

PMOS,thelowertheR

ofthePMOS,therebylowering

DSON

power dissipation in the device during normal operation,

as well as improving the efﬁciency of the application in

which the PMOS is used. The following equations show

35791f

27

LT3579/LT3579-1

APPENDIX

Table 7 shows a list of several discrete PMOS manufa-

cturers.Consultthemanufacturersfordetailedinformation

on their entire selection of PMOS devices.

V

OUT

500mV/DIV

AC COUPLED

I

L

Table 7. Discrete PMOS Manufacturers

2A/DIV

Vishay

www.vishay.com

Fairchild Semiconductor

Central Semiconductor

www.fairchildsemi.com

www.centralsemi.com

I

LOAD

1A/DIV

3579 F17a

R

C

= 1k

100μs/DIV

COMPENSATION – ADJUSTMENT

Figure 17a. Transient Response Shows Excessive Ringing

To compensate the feedback loop of the LT3579, a series

resistor-capacitornetworkinparallelwithanoptionalsingle

V

OUT

500mV/DIV

capacitor must be connected from the V pin to GND. For

C

AC COUPLED

most applications, choose a series capacitor in the range

of 1nF to 10nF with 2.2nF being a good starting value.

The optional parallel capacitor should range in value from

22pF to 180pF with 47pF being a good starting value. The

I

L

2A/DIV

I

compensation resistor, R , is usually in the range of 5k to

LOAD

1A/DIV

C

50k. A good technique to compensate a new application is

3579 F17b

R

= 3.5k

C

tousea100kꢁpotentiometerinplaceoftheseriesresistor

100μs/DIV

R . With the series and parallel capacitors at 2.2nF and

C

Figure 17b. Transient Response Is Better

47pFrespectively,adjustthepotentiometerwhileobserving

the transient response and the optimum value for R can

C

V

OUT

be found. Figures 17a to 17c illustrate this process for the

circuit of Figure 20 with a load current stepped between

0.7A and 1.5A. Figure 17a shows the transient response

500mV/DIV

AC COUPLED

I

L

withR equalto1k.Thephasemarginispoorasevidenced

C

2A/DIV

bytheexcessiveringingintheoutputvoltageandinductor

current. In Figure 17b, the value of R is increased to 3.5k,

C

I

LOAD

1A/DIV

which results in a more damped response. Figure 17c

shows the results when R is increased further to 8k. The

3579 F17c

C

R

= 8k

C

100μs/DIV

transientresponseisnicelydampedandthecompensation

Figure 17c. Transient Response Is Well Damped

procedure is complete.

COMPENSATION – THEORY

Like all other current mode switching regulators, the

LT3579 needs to be compensated for stable and efﬁcient

operation. Two feedback loops are used in the LT3579: a

fast current loop which does not require compensation,

and a slower voltage loop which does. Standard Bode plot

analysis can be used to understand and adjust the voltage

35791f

28

LT3579/LT3579-1

APPENDIX

feedback loop.

are ﬁnite. The output of the g stage is limited by the

mp

minimumswitchcurrentlimit(seeElectricalSpeciﬁcations)

As with any feedback loop, identifying the gain and phase

contribution of the various elements in the loop is critical.

Figure 18 shows the key equivalent elements of a boost

converter. Because of the fast current control loop, the

powerstageoftheIC,inductoranddiodehavebeenreplaced

by a combination of the equivalent transconductance

and g is nominally limited to about 12ꢀA.

ma

From Figure 18, the DC gain, poles and zeros can be

calculated as follows:

DC Gain:

V

R_L

0.5R₂

IN

A_DC= g_ma•R_O•g_mp•η•

•

ampliﬁer g and the current controlled current source

mp

V_OUT2 R₁+0.5R₂

ηV

(which converts I to

). G acts as a current

IN

VIN

mp

I

VIN

2

V

OUT

Output Pole:P1=

Error Amp Pole :P 2 =

Error Amp Zero: Z1=

ESR Zero: Z2 =

2•π•R_L•C_OUT

–

1

V

OUT

g

2•π• R +R •C

mp

(

1

)

I

O

C

VIN

H

V

IN

+

•

I

R

L

•

VIN

ESR

V

OUT

C

OUT

2•π•R_C•C_C

1.215V

C

R1

PL

REFERENCE

1

+

2•π•R_ESR•C_OUT

g

R2

ma

C

F

FB

R

2

C

O

–

V •R_L

IN

2•π•V_OUT²•L

RHP Zero: Z3 =

C

R2

C

3579 F18

f

3

C : COMPENSATION CAPACITOR

C

S

HighFrequency Pole:P3>

C

: OUTPUT CAPACITOR

: PHASE LEAD CAPACITOR

OUT

PL

F

C : HIGH FREQUENCY FILTER CAPACITOR

1

g

: TRANSCONDUCTOR AMPLIFIER INSIDE IC

: POWER STAGE TRANSCONDUCTANCE AMPLIFIER

ma

mp

Phase Lead Zero: Z4 =

2•π•R₁•C_PL

R : COMPENSATION RESISTOR

C

L

O

R : OUTPUT RESISTANCE DEFINED AS V /I

R : OUTPUT RESISTANCE OF gma

R1, R2; FEEDBACK RESISTOR DIVIDER NETWORK

OUT LOADMAX

1

Phase Lead Pole:P4 =

R₁•0.5R

R₁+0.5R₂

R

ESR

: OUTPUT CAPACITOR ESR

2•π•

²•C_PL

H: CONVERTER EFFICIENCY (~90% AT HIGHER CURRENTS)

Figure 18. Boost Converter Equivalent Model

Error Amp Filter Pole:

C_C

10

1

source where the peak input current, I , is proportional

P5 =

, C_F<

VIN

R_C•R

R_C+R_O

to the V voltage.

2•π•

^OC_F

C

Note that the maximum output currents of g and g

mp

ma

35791f

29

LT3579/LT3579-1

APPENDIX

140

120

100

80

0

–45

–90

PHASE

The current mode zero (Z3) is a right half plane zero

which can be an issue in feedback control design, but is

manageable with proper external component selection.

–135

60

–180

–225

46° AT

8kHz

40

GAIN

100

UsingthecircuitinFigure20asanexample, Table8shows

the parameters used to generate the Bode plot shown in

Figure 19.

20

–270

–315

–360

0

–20

10

1k

10k

100k

1M

FREQUENCY (Hz)

Table 8. Bode Plot Parameters

3060 TA02

PARAMETER

VALUE

7

UNITS

ꢁ

COMMENT

Application Specific

Not Adjustable

Adjustable

Figure 19. Bode Plot for Example Boost Converter

R

L

C

30

μF

OUT

R

ESR

2

mꢁ

kꢁ

pF

L1

2.2μH

D1

V

OUT

R0

305

2200

47

V

5V

IN

12V

1.7A

C

130k

SW1 SW2

LT3579

C

F

pF

Optional/Adjustable

Adjustable

V

IN

FB

C

PL

0

pF

100k

C

GATE

FAULT

OUT

C

IN

R

8

kꢁ

V

10μF

C

22μF

s3

SHDN

CLKOUT

VC

R1

R2

130

14.6

12

Adjustable

RT

Not Adjustable

Application Specific

Not Adjustable

Application Specific

Adjustable

SYNC GND SS

47pF

8k

2.2nF

V

86.6k

OUT

0.1μF

V

IN

5

V

3579 F20

g

250

28

μmho

mho

μH

ma

mp

Figure 20. 5V to 12V Boost Converter

L

2.2

1.0

f

MHz

OSC

From Figure 19, the phase is –134° when the gain reaches

0dBgivingaphasemarginof46°.Thecrossoverfrequency

35791f

30

LT3579/LT3579-1

TYPICAL APPLICATION

1MHz, 5V to 12V Boost Converter can Survive Output Shorts

L1

2.2μH

D1

V

12V

1.7A

M1

OUT

V

5V

IN

C

10μF

OUT1

C

10μF

OUT

130k

6.3k

SW1 SW2

V

FB

IN

D2

100k

200k

V

FAULT

GATE

IN

LT3579

SHDN

CLKOUT

C

22μF

IN

V

C

RT

SYNC GND

SS

47pF

8k

86.6k

0.1μF

2.2nF

3579 TA03a

C

: 22μF, 16V, X7R, 1210

, C : 10μF, 25V, X7R, 1210

IN

OUT1 OUT

D1: VISHAY SSB43L

D2: CENTRAL SEMI CMDSH-3TR

L1: WÜRTH WE-PD 744771002

M1: SILICONIX SI7123DN

Efﬁciency and Power Loss

100

90

80

70

60

50

40

30

20

3.2

2.8

2.4

2

1.6

1.2

0.8

0.4

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

LOAD CURRENT (A)

3579 TA03

Output Short

Transient Response with 0.7A to 1.5A to 0.7A Output Load Step

V

OUT

V

OUT

10V/DIV

500mV/DIV

AC COUPLED

CLKOUT

2V/DIV

I

L

2A/DIV

I

L

2A/DIV

I

FAULT

5V/DIV

LOAD

1A/DIV

3579 TA05

3579 TA06

10μs/DIV

100μs/DIV

35791f

31

LT3579/LT3579-1

TYPICAL APPLICATION

500kHz SEPIC Converter Generates 3.3V from a 3V to 33V Input

D3

C2

4.7μF

V

OUT

L1

3.3V

D2

3.3μH

V

BAT

•

1.8A (V

3.1A (V

3.4A (V

= 3V)

BAT

3V TO 33V (OPERATING)

6V TO 16V (START-UP)

= 9V)

C

PWR

D4

≥ 12V)

4.7μF

L

2

s2

3.3μH

10k

•

200k

24.9k

4.7nF

M1

C

OUT

SW1 SW2

47μF

C1

10nF

V

FB

IN

s6

D1

15V

SHDN

GATE

LT3579

100k

C

FAULT

VC

VIN

100pF

10μF

RT

CLKOUT

8.25k

SYNC GND SS

174k

10k

Q1

0.22μF

4.7nF

3579 TA07a

C1: 10nF, 16V, X7R, 0603

C

: 10μF, 16V, X7R, 1206

VIN

, C2: 4.7μF, 50V, X7R, 1210

: 47μF, 6.3V, X7R, 1210

PWR

OUT

D1: CENTRAL SEMI CMHZ5245B-LTZ

D2: VISHAY SS5P6

D3: CENTRAL SEMI CMMSH2-40

D4: CENTRAL SEMI CMMSH2-40

L1, L2: WÜRTH WE-DD 744870003

M1: 2N7002

Q1: MMBT3904

Efﬁciency and Power Loss

Transient Response with 9V to 33V to 9V V_BATGlitch (R_LOAD= 1.5Ω)

90

80

70

60

50

40

30

20

10

4

V

OUT

2V/DIV

3.5

3

V

BAT

2.5

2

10V/DIV

V

= 12V

BAT

V

= 3V

BAT

1.5

1

I

L1 + L2

1A/DIV

3579 TA08b

50ms/DIV

0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

LOAD CURRENT (A)

3579 TA08a

35791f

32

LT3579/LT3579-1

TYPICAL APPLICATION

1.2MHz, 5V to -12V Inverting Converter

C1

4.7μF

L1

3.3μH

L2

3.3μH

V

–12V

1.2A

OUT

V

5V

IN

D1

143k

SW1 SW2

V

IN

FB

GATE

C

SHDN

OUT

10μF

LT3579

100k

s2

FAULT

CLKOUT

VC

C

IN

22μF

RT

SYNC GND SS

27pF

20k

71.5k

0.22μF

1nF

3579 TA14

C

: 22μF, 16V, X7R, 1210

IN

C1: 4.7μF, 25V, X7R, 1206

: 10μF, 25V, X7R, 1210

C

OUT

D1: DIODES INC B230A

L1, L2: COOPER BUSSMANN DRQ125-3R3-R

Efﬁciency and Power Loss

Transient Response with 0.5A to 1A to 0.5A Output Load Step

100

90

80

70

60

50

40

30

20

3.2

2.8

2.4

2

V

OUT

500mV/DIV

AC COUPLED

I

+ I

L1 L2

1A/DIV

1.6

1.2

0.8

0.4

0

I

LOAD

1A/DIV

3579 TA16

100μs/DIV

0

0.25

0.5

0.75

1

1.25

LOAD CURRENT (A)

3579 TA15

35791f

33

LT3579/LT3579-1

TYPICAL APPLICATION

VFD (Vacuum Flourescent Display) Power Supply Switches at 1MHz

Danger High Voltage! Operation by High Voltage Trained Personnel Only

V

100V

OUT2

D6

330mA*

C6

2.2μF

s2

D5

D4

C4

2.2μF

s2

V

67V

500mA*

OUT1

C5

2.2μF

s2

D3

C3

2.2μF

s2

D2

D1

L1

10μH

M1**

V

IN

9V TO 16V

C1

2.2μF

s3

D9**

D8**

8.2V

C2

383k

6.5k**

2.2μF

s3

SW1 SW2

V

FB

IN

D7**

100k

536k

V

IN

FAULT

GATE

LT3579

SHDN

CLKOUT

C

10μF

IN

V

C

RT

SYNC GND

SS

34k

470pF

27pF

86.6k

2.2μF

3579 TA17

*MAX TOTAL

OUTPUT POWER

C

: 10μF, 25V, X7R, 1210

IN

C1-C6: 2.2μF, 50V, X7R, 1210

D1-D6: DIODES INC SBR2A40P1

D7: CENTRAL SEMI CMDSH-3TR

D8: CENTRAL SEMI CMDZ5237B-LTZ

D9: DIODES INC MBRM360

L1: WÜRTH WE-PD 7447710

M1: SILICONIX SI7461DP

22W (V = 9V)

IN

27W (V = 12V)

IN

33W (V = 16V)

IN

**OPTIONAL FOR OUTPUT

SHORT CIRCUIT PROTECTION

Efﬁciency and Power Loss (V_IN= 12V)

Cycle-to-Cycle

90

5

4

3

2

1

0

V

OUT1

2V/DIV

AC COUPLED

V

85

80

75

70

65

OUT2

2V/DIV

AC COUPLED

I

L

1A/DIV

SW1

20V/DIV

3579 TA19

1μs/DIV

0

5

10

15

20

25

30

TOTAL OUTPUT POWER (W)

3579 TA18

35791f

34

LT3579/LT3579-1

TYPICAL APPLICATION

1MHz, 5V to 12V Converter

C2

4.7μF

D5

V

–12V

0.8A*

OUT2

C

10μF

s2

OUT2

D4

R1**

1.2k

C1

4.7μF

L1

4.7μH

D1

D3

V

OUT1

V

5V

IN

12V

0.8A*

D2

130k

SW1

IN

SW2

C

OUT1

10μF

V

FB

SHDN

GATE

s2

LT3579

100k

FAULT

CLKOUT

C

10μF

V

C

RT

IN

SYNC GND

SS

27pF

34k

1nF

86.6k

0.1μF

3579 TA20

C

: 10μF, 16V, X7R, 1206

*MAX TOTAL OUTPUT POWER = 9.6W

IN

C1, C2: 4.7μF, 25V, X7R, 1206

, C : 10μF, 25V, X7R, 1210

C

OUT1 OUT2

D1-D5: DIODES INC SBR2A40P1

L1: VISHAY IHLP-2525CZ-01-4R7

R1: 1.2k, 2W

**IF DRIVING ASYMMETRICAL LOADS, PLACE A 1.2k, 2W

RESISTOR FROM THE +12V OUTPUT TO THE –12V OUTPUT FOR

IMPROVED LOAD REGULATION OF THE –12V OUTPUT.

Efﬁciency and Power Loss

Transient Response with 0.15A to 0.35A to 0.15A

Symmetrical Output Load Step

90

85

3

V

2.7

OUT1

500mV/DIV

2.4

2.1

1.8

1.5

1.2

80

75

AC COUPLED

V

OUT2

500mV/DIV

70

65

AC COUPLED

I

L

60

55

1A/DIV

0.9

0.6

50

45

40

0.3

0

3579 TA22

100μs/DIV

0

100

200

300

400

500

LOAD CURRENT (mA)

3579 TA21

35791f

35

LT3579/LT3579-1

TYPICAL APPLICATION

1MHz, 2-Phase Converter Generates a 24V Output from a 8V to 16V Input and Uses Small Components

L2

4.7μH

D2

C

4.7μF

s2

OUT1S

C

10μF

PWR2

SW1 SW2

V

CLKOUT

IN

FAULT

FB

LT3579-1

SLAVE

C

4.7μF

VIN2

SHDN

GATE

RT

V

C

SYNC GND SS

0.22μF

86.6k

V

24V

M1**

V

OUT1

OUT

L1

4.7μH

5.1A*

D1

V

PWR

6.4k**

8V TO 16V

C

4.7μF

s2

C

OUT

OUT1M

C

10μF

PWR1

4.7μF

s2

SW1 SW2

V

IN

137k

V

IN

CLKOUT

3.3V TO V

PWR

V

100k

OUT1

FAULT

FB

D3**

LT3579-1

MASTER

V

500k

21.5k

5k

PWR

SHDN GATE

RT

V

C

4.7μF

VIN1

47pF

7k

SYNC GND SS

86.6k

0.22μF

2.2nF

3579 F23

*MAX OUTPUT CURRENT

C

: 10μF, 25V, X7R, 1210

: 4.7μF, 25V, X7R, 1206

PWR1, PWR2

C

VIN1, VIN2

V

PWR

= 8V

V

= 12V

V

= 16V

PWR

C

: 4.7μF, 50V, X5R, 1210

OUT1M, OUT1S, OUT

D1, D2: CENTRAL SEMI CTLSH5-40M833

D3: CENTRAL SEMI CTLSH1-40M563

L1, L2: VISHAY IHLP-2525CZ-01-4R7

M1: SILICONIX SI7461DP

V

= 3.3V TO 5V

2.4A

2.2A

**OPTIONAL FOR OUTPUT SHORT CIRCUIT PROTECTION

3.7A

5.1A

3.9A

IN

V

= V

PWR

3.1A

IN

Efﬁciency and Power Loss (V_PWR= 12V)

Transient Response with 1.5A to 3.25A to 1.5A

Output Load Step (V_PWR= 12V and V_IN= 3.3V)

100

90

80

70

60

50

40

30

20

8

7

6

5

4

3

2

1

0

V

OUT

1V/DIV

AC COUPLED

V

= 12V

IN

I

+ I

L1 L2

5A/DIV

V

= 3.3V

IN

I

LOAD

1A/DIV

3579 TA25

100μs/DIV

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

LOAD CURRENT (A)

3579 TA24

35791f

36

LT3579/LT3579-1

TYPICAL APPLICATION

2MHz, Boost Converter with Output Disconnect Generates a 5V Output from 2.8V to 4.2V Input

L1

0.47μH

D1

V

5V

2A

M1

OUT

V

IN

2.8V TO 4.2V

C

22μF

OUT1

43.5k

10k

SW1 SW2

V

FB

GATE

IN

SHDN

LT3579

100k

C

22μF

OUT

FAULT

RT

CLKOUT

C

IN

V

C

10μF

SYNC GND

SS

47pF

6.34k

2.2nF

43.2k

22nF

3579 TA26

C

: 10μF, 16V, X7R, 1206

, C : 22μF, 16V, X7R, 1210

IN

OUT1 OUT

D1: CENTRAL SEMI CTLSH3-30M833

L1: VISHAY IHLP-2020BZ-01-R47

M1: SILICONIX SI7123DN

Efﬁciency and Power Loss

Transient Response with 0.8A to 1.8A to 0.8A

Output Load Step (V_IN= 3.3V)

100

90

80

70

60

50

40

30

20

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0

V

OUT

200mV/DIV

AC COUPLED

I

L

1A/DIV

V

= 3.3V

IN

I

LOAD

1A/DIV

3579 TA28

100μs/DIV

0

0.5

1

1.5

2

2.5

LOAD CURRENT (A)

3579 TA27

35791f

37

LT3579/LT3579-1

PACKAGE DESCRIPTION

FE Package

20-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation CB

6.40 – 6.60*

(.252 – .260)

3.86

(.152)

3.86

(.152)

20 1918 17 16 15 14 1312 11

6.60 0.10

2.74

(.108)

4.50 0.10

6.40

(.252)

BSC

2.74

(.108)

SEE NOTE 4

0.45 0.05

1.05 0.10

0.65 BSC

5

7

8

1

2

3

4

6

9 10

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

FE20 (CB) TSSOP 0204

0.195 – 0.30

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

35791f

38

LT3579/LT3579-1

PACKAGE DESCRIPTION

UFD Package

20-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1711 Rev B)

0.70 0.05

2.65 0.05

4.50 0.05

3.10 0.05

1.50 REF

3.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

2.50 REF

4.10 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR

C = 0.35

0.75 0.05

1.50 REF

4.00 0.10

(2 SIDES)

R = 0.05 TYP

19

20

0.40 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 0.10

(2 SIDES)

2.50 REF

3.65 0.10

2.65 0.10

(UFD20) QFN 0506 REV B

0.25 0.05

0.50 BSC

0.200 REF

R = 0.115

TYP

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

35791f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

39

LT3579/LT3579-1

TYPICAL APPLICATION

1MHz SEPIC Converter Generates a 12V Output from

a 9V to 16V Input

Efﬁciency and Power Loss

100

90

80

70

60

50

40

30

20

3.2

2.8

2.4

2

C1

4.7μF

L1

6.8μH

D1

V

OUT

PWR

•

12V

9V TO 16V

1.9A*

C

PWR

4.7μF

L

130k

2

6.8μH

1.6

1.2

0.8

0.4

0

•

V

= 12V

PWR

IN

SW1 SW2

V

IN

= 5V

C

OUT

V

3.3V TO V

FB

IN

PWR

10μF

s3

SHDN

GATE

LT3579

100k

FAULT

RT

CLKOUT

VC

SYNC GND SS

C

VIN

4.7μF

0

0.25 0.5 0.75

1

1.25 1.5 1.75

LOAD CURRENT (A)

2

47pF

9.53k

86.6k

0.22μF

3579 TA08

2.2nF

3579 TA29

*MAX OUTPUT CURRENT

= 9V

C

: 4.7μF, 25V, X7R, 1206

PWR

VIN

V

PWR

V

= 12V

PWR

C1: 4.7μF, 25V, X7R, 1206

: 10μF, 25V, X7R, 1210

C

V

IN

= 3.3V TO 5V

1.6A

1.4A

1.9A

1.4A

OUT

D1: DIODES INC MBRM360

L1, L2: COOPER BUSSMANN DRQ125-6R8-R

V

= V

PWR

LINE REGULATION (V = 5V, I

= 1A) = 0.017%/V

OUT

IN

LOAD REGULATION (V

= 12V, V = 5V) = –0.23%/A

PWR

IN

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LT3581

LT3580

LT3479

3.3A (I ), 42V, 2.5MHz, High Efﬁciency

V : 2.5V to 22V, V

= 42V, I = 1.9mA, I = < 1μA, 4mm × 3mm DFN-14,

Q SD

SW

IN

OUT(MAX)

Step-Up DC/DC Converter

MSOP-16E

2A (I ), 42V, 2.5MHz, High Efﬁciency Step-Up

V : 2.5V to 32V, V

= 42V, I = 1mA, I = < 1μA, 3mm × 3mm DFN-8,

Q SD

SW

IN

DC/DC Converter

MSOP-8E

3A (I ), 40V, 3.5MHz, High Efﬁciency Step-Up

V : 2.5V to 24V, V

= 40V, I = 5mA, I = < 1μA, 4mm × 3mm DFN-14,

Q SD

SW

IN

DC/DC Converter

TSSOP-16E

35791f

LT 0410 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

40

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3579IFE-1-PBF
厂家：	Linear
描述：	6A Boost/Inverting DC/DC Converter with Fault Protection 6A升压/负输出DC / DC转换器故障保护转换器
文件：	总40页 (文件大小：512K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3579IFE-1-PBF [Linear]

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