LT3050EDDB-5#TRPBF_技术文档

LT3050 Series

100mA, Linear Regulator

with Precision Current Limit

and Diagnostic Outputs

DESCRIPTION

FEATURES

th

The LT^®3050 series are micro-power, low noise, low

dropout voltage (LDO) linear regulators. The devices

supply 100mA of output current with a dropout voltage of

340mV. A 10nF bypass capacitor reduces output noise to

n

Output Current Monitor: 1/100 of I

OUT

n

Fault Indicator: Current Limit, Minimum I

or

OUT

Thermal Limit

n

Output Current: 100mA

Dropout Voltage: 340mV

30μV

in a 10Hz to 100kHz bandwidth and soft-starts

RMS

Input Voltage Range: 1.6V to 45V

the reference. The LT3050’s 45V input voltage rating

combined with its precision current limit and diagnostic

functions make the IC an ideal choice for robust, high

reliability applications.

Programmable Precision Current Limit: 5ꢀ

Programmable Minimum I

Monitor

(10Hz to 100kHz)

OUT

Low Noise: 30μV

RMS

Adjustable Output (V = V

= 0.6V)

REF

OUT(MIN)

AsingleresistorprogramstheLT3050’scurrentlimit,accurate

to 5ꢀ over a wide input voltage and temperature range.

A single resistor programs the LT3050’s minimum output

currentmonitor,usefulfordetectingopen-circuitconditions.

The current monitor function sources a current equal to

1/100th of output current. A logic FAULT pin asserts low if

the LT3050 is in current limit, operating below its minimum

output current (open-circuit) or is in thermal shutdown.

Fixed Output Voltages: 3.3V, 5V

Output Tolerance: 2ꢀ Over Line, Load and Temperature

Stable with Low ESR, Ceramic Output Capacitors

(2.2μF minimum)

n

Shutdown Current: <1μA

Reverse-Battery, Reverse-Output and

Reverse-Current Protection

Thermal Limit Protection

12-Lead 3mm × 2mm DFN and MSOP Packages

n

The LT3050 optimizes stability and transient response

with low ESR ceramic capacitors, requiring a minimum of

2.2μF. The LT3050 is available in ﬁxed output voltages of

3.3V and 5V, and as an adjustable version with an output

voltage range down to the 0.6V reference.The LT3050 is

available in the thermally-enhanced 12-Lead 3mm × 2mm

DFN and MSOP packages.

APPLICATIONS

n

Protected Antenna Supplies

n

Automotive Telematics

n

Industrial Applications (Trucks, Forklifts, etc.)

High Reliability Applications

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

TYPICAL APPLICATION

External Current Limit R_IMAX= 1.15k

105

5V Supply with 100mA Precision Current Limit, 10mA I_MIN

V

OUT

= 5V

104

103

102

101

100

99

IN

OUT

5V

12V

IN

SHDN

2.2ꢁF

V

= 15V

1ꢁF

120k

IN

V

FAULT

V

= 12V

LT3050-5

IN

I

MAX

I

TO ꢁP ADC

0.1ꢁF

MON

1.15k

10nF

= 5.6V

98

3k

(THRESHOLD = 100mA)

(ADC FULL SCALE = 3V)

97

I

REF/BYP

96

MIN

11.3k

0.1ꢁF

GND

95

10nF

(THRESHOLD = 10mA)

–75 –50 –25

0

–25 50 75 100 125 150 175

3050 TA01

TEMPERATURE (°C)

3050 TA01a

3050fa

1

LT3050 Series

(Note 1)

ABSOLUTE MAXIMUM RATINGS

IN Pin Voltage ........................................................ 50V

OUT Pin Voltage..................................................... 50V

Input-to-Output Differential Voltage....................... 50V

ADJ Pin Voltage (Note 16) ..................................... 50V

REF/BYP Pin Voltage........................................–0.3V, 1V

SHDN Pin Voltage ................................................... 50V

FAULT Pin Voltage..........................................–0.3V, 50V

Output Short-Circuit Duration .......................... Indeﬁnite

Operating Junction Temperature Range (Notes 2, 3)

E, I Grades.........................................–40°C to 125°C

MP Grade...........................................–55°C to 125°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature: Soldering, 10 sec.................... 300°C

(MSOP Package Only)

I

Pin Voltage ..............................................–0.3V, 7V

Pin Voltage ...............................................–0.3V, 7V

Pin Voltage...............................................–0.3V, 7V

MON

MIN

MAX

PIN CONFIGURATION

TOP VIEW

1

2

3

4

5

6

REF/BYP

12 I

11 I

MON

1

2

3

4

5

6

REF/BYP

12

11

10 GND

9

8

7

I

MON

MAX

I

MIN

MAX

I

MIN

13

GND

FAULT

SHDN

IN

10 GND

FAULT

SHDN

IN

13

GND

ADJ

OUT

9

8

7

ADJ

OUT

IN

MSE PACKAGE

DDB PACKAGE

12-LEAD PLASTIC MSOP

12-LEAD (3mm s 2mm) PLASTIC DFN

T

= 125°C, θ = 45°C/W, θ = 5°C/W TO 10°C/W

JA JC

EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB

JMAX

T

= 125°C, θ = 49°C/W, θ = 13.5°C/W

JMAX

JA

JC

EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LT3050EMSE#PBF

LT3050IMSE#PBF

TAPE AND REEL

PART MARKING*

3050

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT3050EMSE#TRPBF

LT3050IMSE#TRPBF

LT3050MPMSE#TRPBF

LT3050EMSE-3.3#TRPBF

LT3050IMSE-3.3#TRPBF

12-Lead Plastic MSOP

–40°C to 125°C

–55°C to 125°C

–40°C to 125°C

–55°C to 125°C

–40°C to 125°C

–55°C to 125°C

–40°C to 125°C

3050

12-Lead Plastic MSOP

LT3050MPMSE#PBF

LT3050EMSE-3.3#PBF

LT3050IMSE-3.3#PBF

3050

12-Lead Plastic MSOP

305033

12-Lead Plastic MSOP

LT3050MPMSE-3.3#PBF LT3050MPMSE-3.3#TRPBF 305033

12-Lead Plastic MSOP

LT3050EMSE-5#PBF

LT3050IMSE-5#PBF

LT3050MPMSE-5#PBF

LT3050EDDB#PBF

LT3050EMSE-5#TRPBF

LT3050IMSE-5#TRPBF

LT3050MPMSE-5#TRPBF

LT3050EDDB#TRPBF

30505

LFGC

12-Lead Plastic MSOP

12-Lead (3mm × 2mm) Plastic DFN

LT3050IDDB#PBF

LT3050IDDB#TRPBF

LFGC

LT3050EDDB-3.3#PBF

LT3050IDDB-3.3#PBF

LT3050EDDB-3.3#TRPBF

LT3050IDDB-3.3#TRPBF

LFWR

3050fa

2

LT3050 Series

ORDER INFORMATION

LEAD FREE FINISH

LT3050EDDB-5#PBF

LT3050IDDB-5#PBF

LEAD BASED FINISH

LT3050EMSE

TAPE AND REEL

PART MARKING*

LFWS

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

TEMPERATURE RANGE

–40°C to 125°C

–55°C to 125°C

–40°C to 125°C

–55°C to 125°C

–40°C to 125°C

–55°C to 125°C

–40°C to 125°C

LT3050EDDB-5#TRPBF

LT3050IDDB-5#TRPBF

TAPE AND REEL

12-Lead (3mm × 2mm) Plastic DFN

PACKAGE DESCRIPTION

LFWS

PART MARKING*

3050

LT3050EMSE#TR

12-Lead Plastic MSOP

LT3050IMSE

LT3050IMSE#TR

3050

12-Lead Plastic MSOP

LT3050MPMSE

LT3050EMSE-3.3

LT3050IMSE-3.3

LT3050MPMSE-3.3

LT3050EMSE-5

LT3050IMSE-5

LT3050MPMSE#TR

LT3050EMSE-3.3#TR

LT3050IMSE-3.3#TR

LT3050MPMSE-3.3#TR

LT3050EMSE-5#TR

LT3050IMSE-5#TR

LT3050MPMSE-5#TR

LT3050EDDB#TR

3050

12-Lead Plastic MSOP

305033

30505

12-Lead Plastic MSOP

30505

12-Lead Plastic MSOP

LT3050MPMSE-5

LT3050EDDB

30505

12-Lead Plastic MSOP

LFGC

12-Lead (3mm × 2mm) Plastic DFN

LT3050IDDB

LT3050IDDB#TR

LFGC

LT3050EDDB-3.3

LT3050IDDB-3.3

LT3050EDDB-5

LT3050IDDB-5

LT3050EDDB-3.3#TR

LT3050IDDB-3.3#TR

LT3050EDDB-5#TR

LT3050IDDB-5#TR

LFWR

LFWS

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 2)

PARAMETER

CONDITIONS

= 100mA

MIN

TYP

MAX

UNITS

l

Minimum Input Voltage (Notes 3, 11)

Regulated Output Voltage

I

1.6

2.2

V

LOAD

LT3050-3.3: V = 3.9V, I

= 1mA

LOAD

3.267

3.234

3.3

3.333

3.366

V

IN

3.9V < V < 15V, 1mA < I

< 100mA (Note 15)

IN

LT3050-5: V = 5.6V, I

= 1mA

LOAD

< 100mA (Note 15)

LOAD

4.95

4.9

5

5.05

5.1

V

IN

5.6V < V 15V, 1mA < I

IN

ADJ Pin Voltage (Notes 3, 4)

Line Regulation (Note 3)

V

= 2.2V, I

= 1mA

LOAD

594

588

600

606

612

mV

IN

2.2V < V < 15V, 1mA < I

< 100mA (Note 15)

LOAD

IN

l

LT3050-3.3: ΔV = 3.9V to 45V, I

= 1mA

LOAD

2.2

3.3

0.4

16.5

25

3

mV

IN

LT3050-5: ΔV = 5.6V to 45V, I

= 1mA

LOAD

IN

LT3050: ΔV = 2.2V to 45V, I

= 1mA

LOAD

IN

l

Load Regulation (Note 3)

LT3050-3.3: V = 3.9V, I

= 1mA to 100mA

LOAD

7.2

8.4

0.2

33

50

4

mV

IN

LT3050-5: V = 5.6V, I

= 1mA to 100mA

LOAD

IN

LT3050: V = 2.2V, I

= 1mA to 100mA

LOAD

IN

3050fa

3

LT3050 Series

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Dropout Voltage

IN

I

= 1mA

110

150

220

mV

LOAD

l

V

= V

(Notes 5, 6)

OUT(NOMINAL)

I

= 10mA

195

280

340

240

340

mV

LOAD

I

= 50mA

330

450

mV

LOAD

I

= 100mA

400

550

mV

LOAD

l

GND Pin Current

= V

I

= 0mA

45

60

175

0.85

2.2

90

160

370

2

ꢁA

LOAD

V

+ 0.6V (Notes 6, 7, 11)

OUT(NOMINAL)

= 1mA

IN

= 10mA

= 50mA

= 100mA

ꢁA

mA

5.2

Quiescent Current in Shutdown

ADJ Pin Bias Current (Notes 3, 12)

Output Voltage Noise

V

C

= 12V, V

= 0V

0.17

12.5

90

1

ꢁA

nA

IN

SHDN

l

= 12V

60

IN

= 10μF, I

= 100mA, V

= 600mV,

ꢁV

OUT

LOAD

OUT

RMS

BW = 10Hz to 100kHz

Output Voltage Noise

Shutdown Threshold

SHDN Pin Current (Note 13)

Ripple Rejection

C

OUT

= 10μF, C = 0.01μF, I

= 100mA, V = 600mV

OUT

30

BYP

LOAD

RMS

BW = 10Hz to 100kHz

l

V

= Off to On

= On to Off

0.7

0.6

1.5

V

OUT

0.3

l

V

SHDN

V

SHDN

= 0V

= 45V

1

3

ꢁA

0.9

V

– V

= 2V, V

= 0.5V

,

IN

OUT

RIPPLE

= 100mA

LOAD

P-P

f

= 120Hz, I

RIPPLE

LT3050

70

55

51

85

70

66

dB

LT3050-3.3

LT3050-5

l

FAULT Pin Logic Low Voltage

FAULT Pin Leakage Current

V

= 2.2V, FAULT Asserted, I

= 100μA

140

250

1

mV

ꢁA

mA

IN

FAULT

FAULT = 5V, FAULT Not Asserted

0.01

Input Reverse Leakage Current

Reverse Output Current (Note 14)

Internal Current Limit (Note 3)

V

= –45V, V

= 0

300

10

IN

OUT

= 1.2V, V = 0

0.2

OUT

IN

V

IN

V

IN

= 2.2Vor V

+ 0.6V, V

+ 0.6V, ΔV

= 0V, I = 0V

MAX

= –5ꢀ

240

OUT(NOMINAL)

OUT

l

110

OUT

External Programmed Current Limit

(Notes 6, 8)

LT3050-3.3

3.9V < V < 13.3V, R

= 2.26k

IMAX

FAULT

= 1.5k

IMAX

IN

l

FAULT Pin Threshold (I

)

48.8

73.6

96

51.4

77.5

101

54

mA

3.9V < V < 13.3V, R

IN

FAULT Pin Threshold (I

)

81.4

106

FAULT

3.9V < V < 13.3V, R

= 1.15k

IMAX

IN

FAULT Pin Threshold (I

)

FAULT

LT3050, LT3050-5

5.6V < V < 15V, R

= 2.26k

IMAX

IN

l

FAULT Pin Threshold (I

)

47.8

72.1

94.4

50.4

75.9

99.3

52.9

79.7

mA

FAULT

5.6V < V < 15V, R

= 1.5k

IN

IMAX

FAULT Pin Threshold (I

FAULT

= 1.15k

FAULT

5.6V < V < 15V, R

IN

IMAX

FAULT Pin Threshold (I

104.3

3050fa

4

LT3050 Series

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 2)

PARAMETER

Minimum I

CONDITIONS

LT3050-3.3: 3.9V < V < 13.3V, R = 110K

IMIN

MIN

TYP

MAX

UNITS

l

Threshold Accuracy

0.92

0.9

1.03

1

1.13

1.1

mA

MIN

IN

(Notes 6, 9)

LT3050, LT3050-5: 5.6V < V < 15V, R

= 110K

IN

IMIN

l

I

Threshold Accuracy (Notes 6, 9)

LT3050-3.3: 3.9V < V < 13.3V, R = 11.3K

IMIN

9.2

9

10.3

10

11.3

11

mA

MIN

IN

LT3050, LT3050-5: 5.6V < V < 15V, R

= 11.3K

IMIN

IN

Current Monitor Ratio (Notes 6, 10)

I

= 5mA, 25mA, 50mA, 75mA, 100mA

LOAD

l

Ratio = I /I

95

100

105

LT3050-3.3: V

= V , 3.9V < V < 13.3V

OUT MON

IMON

OUT IN

LT3050, LT3050-5: V

= V , 5.6V < V < 15V

OUT IN

IMON

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime. Absolute maximum input-to-output differential

voltage is not achievable with all combinations of rated IN pin and OUT pin

voltages. With the IN pin at 50V, the OUT pin may not be pulled below 0V.

The total differential voltage from IN to OUT must not exceed 50V.

10ꢁA to GND pin current. See the GND Pin Current curves in the Typical

Performance Characteristics section.

Note 8: Current limit varies inversely with the external resistor value tied

from the I

pin to GND. For detailed information on how to set the

MAX

I

pin resistor value, please see the Operation section. If a programmed

MAX

current limit is not needed, the I

pin must be tied to GND and internal

MAX

protection circuitry implements short-circuit protection as speciﬁed.

Note 2: The LT3050 is tested and speciﬁed under pulse load conditions

Note 9: The I fault condition asserts if the output current falls below the

MIN

such that T ~ T . The LT3050E is 100ꢀ production tested at T = 25°C.

J

A

I

threshold deﬁned by an external resistor from the I

pin to GND.

MIN

Performance at –40°C and 125°C is assured by design, characterization

and correlation with statistical process controls. The LT3050I is

guaranteed over the full –40°C to 125°C operating junction temperature

range. The LT3050MP is 100ꢀ tested over the –55°C to 125°C operating

junction temperature range.

For detailed information on how to set the I

pin resistor value, please

MIN

see the Operation section. I

settings below the Minimum I

Accuracy

MIN

speciﬁcation in the Electrical Characteristics section are not guaranteed

to 10ꢀ tolerance. If the I fault condition is not needed, the I pin

MIN

must be left ﬂoating (unconnected).

Note 3: The LT3050 adjustable version is tested and speciﬁed for these

conditions with ADJ pin connected to the OUT pin.

Note 10: The current monitor ratio varies slightly when V

detailed information on how to calculate the output current from the I

≠ V . For

OUT

IMON

MON

Note 4: Maximum junction temperature limits operating conditions.

Regulated output voltage speciﬁcations do not apply for all possible

combinations of input voltage and output current. If operating at the

maximum input voltage, limit the output current range. If operating at the

maximum output current, limit the input voltage range.

Note 5: Dropout voltage is the minimum differential IN-to-OUT voltage

needed to maintain regulation at a speciﬁed output current. In dropout,

pin, please see the Operation section. If the current monitor function is not

needed, the I pin must be tied to GND.

MON

Note 11: To satisfy requirements for minimum input voltage, current limit

is tested at V = V +1V or V = 2.2V, whichever is greater.

IN

OUT(NOMINAL)

IN

Note 12: ADJ pin bias current ﬂows out of the ADJ pin:

Note 13: SHDN pin current ﬂows into the SHDN pin.

Note 14: Reverse output current is tested with the IN pin grounded and the

OUT pin forced to the speciﬁed voltage. This current ﬂows into the OUT pin

and out of the GND pin.

Note 15: 100mA of output current does not apply to the full range of input

voltage due to the internal current limit foldback.

Note 16: The ADJ pin cannot be externally driven for ﬁxed output voltage

options. LTC allows the use of a small feedforward capacitor from OUT

to ADJ to reduce noise and improve transient response. See the Bypass

Capacitance section of the Applications Information.

the output voltage equals (V - V

). For some output voltages,

DROPOUT

IN

minimum input voltage requirements limit dropout voltage.

Note 6: To satisfy minimum input voltage requirements, the LT3050

adjustable version is tested and speciﬁed for these conditions with an

external resistor divider (60k bottom, 440k top) which sets V

to 5V.

OUT

The external resistor divider adds 10μA of DC load on the output. This

external current is not factored into GND pin current.

Note 7: GND pin current is tested with V = V

+ 0.6V and

IN

OUT(NOMINAL)

a current source load. GND pin current increases in dropout. For the

ﬁxed output voltage versions, an internal resistor divider adds about

3050fa

5

LT3050 Series

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

Guaranteed Dropout Voltage

Dropout Voltage

Typical Dropout Voltage

600

550

500

450

400

350

300

250

200

150

100

50

600

550

500

450

400

350

300

250

200

150

100

50

600

550

500

450

400

350

300

250

200

150

100

50

=TEST POINTS

I

= 100mA

= 50mA

L

I

T = 125°C

J

T ≤ 125°C

J

L

I

= 10mA

T = 25°C

J

L

T ≤ 25°C

J

I

= 1mA

L

0

–75 –50 –25

0

25 50 75 100 125 150 175

0

10 20 30 40 50 60 70 80 90 100

0

10 20 30 40 50 60 70 80 90 100

OUTPUT CURRENT (mA)

TEMPERATURE (°C)

3050 G01

3050 G02

3050 G03

Adjustable Quiescent Current

ADJ Pin Voltage

Output Voltage LT3050-3.3

80

70

60

50

40

30

20

10

0

612

610

608

606

604

602

600

598

596

594

592

590

588

3.366

3.355

3.344

3.333

3.322

3.311

3.300

3.289

3.278

3.267

3.256

3.245

3.234

I

= 1mA

I

= 1mA

LOAD

V

L

= V

= 5V

= 5ꢁA

= 12V

SHDN

IN

OUT

I

V

= 12V

IN

ALL OTHER PINS = 0V

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

3050 G04

3050 G05

3050 G05a

Output Voltage LT3050-5

GND Pin Current LT3050-3.3

Quiescent Current

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

5.100

5.075

5.050

5.025

5.000

4.975

100

90

80

70

60

50

40

30

20

10

0

I

= 1mA

T = 25°C

J

LOAD

I

= 10ꢁA

R

= 33Ω, I = 100mA

L

LT3050-5

L

R

L

= 66Ω, I = 50mA

L

LT3050-3.3

R

L

= 3.3k, I = 1mA

L

4.950

4.925

R

= 330Ω, I = 10mA

L

V

SHDN

= 0V, R = 0

L

4.900

0

1

2

3

4

5

6

7

8

9

10 11 12

–75 –50 –25

0

25 50 75 100 125 150 175

0

5

10 15 20 25 30 35 40 45

(V)

INPUT VOLTAGE (V)

TEMPERATURE (°C)

V

IN

3050 G07a

3050 G06

3050 G05b

3050fa

6

LT3050 Series

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

GND Pin Current LT3050-5

GND Pin Current vs I_LOAD

SHDN Pin Threshold

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V

= 5.6V

OUT

I = 1mA

L

IN

= 5V

R

= 50Ω, I = 100mA

L

R

= 100Ω, I = 50mA

L

OFF TO ON

L

ON TO OFF

R

= 5k, I = 1mA

L

R

= 500Ω, I = 10mA

L

0

1

2

3

4

5

6

7

8

9

10 11 12

0

10 20 30 40 50 60 70 80 90 100

(mA)

–75 –50 –25

0

25 50 75 100 125 150 175

INPUT VOLTAGE (V)

I

TEMPERATURE (°C)

LOAD

3050 G07

3050 G08

3050 G09

SHDN Pin Input Current

ADJ Pin Bias Current

3.0

2.5

2.0

1.5

1.0

0.5

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

50

45

40

35

30

25

20

15

10

5

V

= 45V

SHDN

0

–75 –50 –25

0

25 50 75 100 125 150 175

0

10

20

30

40

50

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

SHDN PIN VOLTAGE (V)

TEMPERATURE (°C)

3050 G10

3050 G11

3050 G12

Internal Current Limit

vs Output Voltage

Internal Current Limit

350

300

250

200

150

100

50

250

225

200

175

150

125

100

75

225

200

175

150

125

100

75

V

= 12V

= 0V

V

– V

= 1V

OUT(NOMINAL)

IN

OUT

IN

T = 125°C

J

T = 125°C

J

50

T = 25°C

J

T = 25°C

J

CURRENT LIMIT

AT FAULT

THRESHOLD

CURRENT LIMIT

AT FAULT

THRESHOLD

T = –40°C

J

T = –40°C

J

25

T = –55°C

J

T = –55°C

J

0

–75 –50 –25

0

25 50 75 100 125 150 175

0

5

10 15 20 25 30 35 40 45

0

5

10 15 20 25 30 35 40 45

TEMPERATURE (°C)

INPUT/OUTPUT DIFFERENTIAL (V)

OUTPUT VOLTAGE (V)

3050 G13

3050 G14

3050 G15

3050fa

7

LT3050 Series

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

Reverse Output Current

Input Ripple Rejection

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

50

45

40

35

30

25

20

15

10

5

90

80

70

60

50

40

30

20

10

0

V

= V

= 1.2V

ADJ

ALL PINS GROUNDED EXCEPT FOR OUT

C

= 10nF

= 100pF

= 0

OUT

IN

REF/BYP

= 0

C

REF/BYP

I

ADJ

I

= 100mA

L

C

V

= 10ꢁF

= 5V

OUT

I

OUT

= 5.8V + 50mV

RIPPLE

IN

RMS

0

10

20

V

30

(V)

40

50

–75 –50 –25

0

25 50 75 100 125 150 175

10

100

1K

10K 100K 1M

10M

TEMPERATURE (°C)

FREQUENCY (Hz)

OUT

3050 G16

3050 G17

3050 G18

Input Ripple Rejection

Ripple Rejection vs Temperature

Minimum Input Voltage

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

I

=100mA

C

= 10ꢁF

C

= 10µF

L

OUT

REF/BYP

= 2.2ꢁF

= 10nF

I

= 100mA

L

I

V

= 100mA

= 5V

IN

C

V

= 100pF

L

OUT

REF/BYP

= 5V

OUT

= 5.8V + 0.5V RIPPLE AT f = 120Hz

= 5.8V + 50mV

RIPPLE

P-P

IN

RMS

–75 –50 –25

0

25 50 75 100 125 150 175

10

100

1K

10K 100K 1M

10M

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

FREQUENCY (Hz)

TEMPERATURE (°C)

3050 G19a

3050 G19

3050 G20

Load Regulation

–0

–5

–0

–3

4

3

ΔI = 1mA TO 100mA

L

OUT

IN

V

= 0.6V

= 2.2V

–6

–10

–15

–20

2

–9

–12

1

–15

–18

–21

–24

–27

–30

–33

–25

–30

–35

–40

–45

0

–1

–2

–3

–4

ΔI = 1mA TO 100mA

L

ΔI = 1mA TO 100mA

L

V

= 5V

V

= 3.3V

OUT

= 5.6V

= 3.9V

IN

–50

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

3050 G21b

3050 G21a

3050 G21

3050fa

8

LT3050 Series

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

Output Noise Spectral Density

C_REF/BYP= 0, C_FF= 0

Output Noise Spectral Density

vs C_REF/BYP, C_FF= 0

Output Noise Spectral Density

vs C_FF, C_REF/BYP= 10nF

10

1

10

1

10

1

C

= 100pF

REF/BYP

V

= 5V

OUT

C

FF

= 0

V

= 0.6V

OUT

C

= 10nF

= 5V

FF

V

= 5V

OUT

= 3.3V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

= 0.6V

0.1

0.01

0.1

0.01

0.1

0.01

C

= 10nF

REF/BYP

C

= 1nF

C

= 1nF

1k

REF/BYP

FF

V

C

I

OUT

C

I

= 10ꢁF

= 100mA

C

FF

= 100pF

10k

C

I

= 10ꢁF

OUT

L

= 10ꢁF

OUT

= 100mA

L

10

100

1k

FREQUENCY (Hz)

10k

100k

10

100

1K

FREQUENCY (Hz)

10K

100k

10

100

100k

FREQUENCY (Hz)

3050 G22

3050 G23

3050 G23a

RMS Output Noise vs Load

Current vs C_REF/BYP

RMS Output Noise vs Load

Current C_REF/BYP= 10nF

RMS Output Noise

vs Feedforward Capacitor (C_FF

)

110

100

90

80

70

60

50

40

30

20

10

0

120

110

100

90

80

70

60

50

40

30

20

10

0

170

160

150

140

130

120

110

100

90

f = 10Hz TO 100kHz

V

C

= 0.6V

= 10ꢁF

f

= 10Hz TO 100kHz

= 10ꢁF

OUT

V

= 5V

V

= 5V

OUT

C

I

= 10nF

C

= 0

REF/BYP

OUT

REF/BYP

V

= 3.3V

= 10ꢁF

OUT

= 5ꢁA

V

= 2.5V

FB-DIVIDER

L

OUT

V

= 2.5V

OUT

I

= 100mA

C

= 10pF

V

= 3.3V

REF/BYP

OUT

V

= 1.8V

OUT

V

= 1.5V

OUT

C

= 100pF

REF/BYP

80

70

60

C

= 1nF

50

REF/BYP

40

V

= 1.2V

= 0.6V

OUT

C

= 10nF

30

REF/BYP

V

= 1.8V

V

= 1.2V

V

OUT

= 0.6V

OUT

20

C

1

= 100nF

REF/BYP

= 1.5V

10

OUT

0

0.01

0.1

10

100

10p

100p

1n

10n

0.01

0.1

1

10

100

LOAD CURRENT (mA)

FEEDFORWARD CAPACITOR, C (F)

LOAD CURRENT (mA)

FF

3050 G24

3050 G25a

3050 G25

5V 10Hz to 100kHz Output Noise

C_REF/BYP= 10nF, C_FF= 10nF

Startup Time

5V 10Hz to 100kHz Output Noise

vs REF/BYP Capacitor

C

_REF/BYP= 10nF, C_FF= 0

60

50

40

30

20

10

0

V

OUT

100ꢁV/DIV

3050 G27

3050 G26

C

LOAD

= 10ꢁF

= 100mA

1ms/DIV

C

I

= 10ꢁF

= 100mA

1ms/DIV

OUT

LOAD

I

0

10 20 30 40 50 60 70 80 90 100

REF/BYP CAPACITOR (nF)

3050 G33

3050fa

9

LT3050 Series

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

5V Transient Response

C_FF= 0, I_OUT= 10mA to 100mA

5V Transient Response

Transient Response (Load Dump)

C

_FF= 10nF, I_OUT= 10mA to 100mA

V

OUT

V

= 5V

V

= 5V

OUT

20mV/DIV

50mV/DIV

45V

12V

I

V

I

= 5V

= 50mA

= 2.2ꢁF

I

OUT

V

50mA/DIV

IN

50mA/DIV

10V/DIV

C

3050 G29

3050 G28b

3050 G28a

1ms/DIV

V

C

= 6V

IN

OUT

100ꢁs/DIV

V

C

= 6V

OUT

IN

= C = 10ꢁF

IN

I

= 10ꢁA

I

= 10ꢁA

FB-DIVIDER

SHDN Transient Response

_REF/BYP=0

SHDN Transient Response

_REF/BYP= 10nF

External Current Limit

R_IMAX= 2.26k

C

54.0

V

= 3.3V

OUT

53.6

53.2

52.8

52.4

OUT

5V/DIV

I =100mA

I

= 100mA

V

= 13.3V

L

IN

52.0

51.6

51.2

50.8

50.4

50.0

49.6

49.2

48.8

REF/BYP

500mV/DIV

V

= 3.9V

IN

SHDN

1V/DIV

SHDN

1V/DIV

3050 G30

3050 G31

2ms/DIV

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

3050 G34a

External Current Limit

R_IMAX= 1.5k

External Current Limit

R_IMAX= 1.15k

External Current Limit

R_IMAX= 2.26k

106

105

104

103

102

101

81.10

80.35

79.60

78.85

78.10

77.35

52.8

52.3

51.8

51.3

50.8

50.3

49.8

49.3

48.8

48.3

47.8

V

= 3.3V

V

= 5V

V

= 3.3V

OUT

V = 13.3V

IN

V

= 13.3V

IN

V

= 15V

IN

V

= 12V

V

= 3.9V

V

= 3.9V

IN

100

99

98

97

96

76.60

75.85

75.10

74.35

73.60

= 5.6V

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

3050 G36a

3050 G35a

3050 G34

3050fa

10

LT3050 Series

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

External Current Limit

R_IMAX= 1.5k

Minimum Output Current

Threshold R_IMIN= 11.3k

External Current Limit

R_IMAX= 1.15k

79.50

78.75

78.00

77.25

76.50

75.75

75.00

74.25

73.50

72.75

72.00

11.3

11.0

10.7

105

104

103

102

101

100

99

V

= 5V

V

= 5V

V

= 3.3V

OUT

V

= 15V

IN

V

= 15V

IN

V

= 13.3V

IN

10.4

10.1

V

= 12V

IN

V

= 12V

IN

V

= 3.9V

IN

= 5.6V

98

9.8

9.5

9.2

97

96

95

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

–25 50 75 100 125 150 175

TEMPERATURE (°C)

3050 G35

3050 G38a

3050 G36

Minimum Output Current

Threshold R_IMIN= 110k

Minimum Output Current

Threshold R_IMIN= 110k

Minimum Output Current

Threshold R_IMIN= 11.3k

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

1.13

1.10

1.07

11.00

10.75

10.50

V

= 5V

V

= 5V

V

= 3.3V

OUT

V

= 13.3V

IN

V

= 15V

10.25

10.00

IN

V

= 15V

IN

1.04

1.01

V

= 12V

IN

V

= 12V

IN

= 5.6V

V

= 3.9V

= 5.6V

IN

9.75

9.50

9.25

0.98

0.95

0.92

9.00

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25 50 75 100 125 150 175

TEMPERATURE (°C)

3050 G37

3050 G37a

3050 G38

I_OUT/I_MONCurrent Ratio

V_OUT= 3.3V, V_IN= 12V

I_OUT/I_MONCurrent Ratio

V_OUT= 3.3V, V_IN= 3.9V

I_OUT/I_MONCurrent Ratio

V_OUT= 3.3V, V_IN= 3.9V

103

102

101

100

99

102

101

100

99

102

101

100

99

V

IMON

= 3.3V

98

97

96

V

IMON

= 0V

96

95

V

= 0V

V

= 0V

IMON

95

94

V

= 1V

V

= 1V

125°C

25°C

–55°C

= 2V

= 3.3V

= 2V

= 3.3V

94

93

92

0

25

50

75

(mA)

100

125

0

25

50

75

(mA)

100

125

0

25

50

75

(mA)

100

125

I

OUT

3050 G39a

3050 G40a

3050 G41a

3050fa

11

LT3050 Series

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

I_OUT/I_MONCurrent Ratio

V_OUT= 3.3V, V_IN= 12V

I_OUT/I_MONCurrent Ratio

V_OUT= 5V, V_IN= 12V

I_OUT/I_MONCurrent Ratio

V_OUT= 5, V_IN= 5.6V

103

102

101

100

99

102

101

100

99

102

101

100

99

V

= 3.3V

IMON

V

= 5V

= 4V

IMON

98

97

V

= 3V

= 2V

= 1V

= 0V

IMON

V

= 0V

IMON

97

96

V

= 5V

= 4V

= 3V

= 2V

= 1V

= 0V

IMON

96

95

IMON

95

94

125°C

25°C

94

93

–55°C

93

92

0

25

50

75

(mA)

100

125

0

25

50

75

(mA)

100

125

0

25

50

I

75

(mA)

100

125

I

OUT

3050 G42a

3050 G39

3050 G40

I

_OUT/I_MONCurrent Ratio

I_OUT/I_MONCurrent Ratio

V_OUT= 5V, V_IN= 12V

I_OUTCalculated From I_MON

V_OUT= 5V

V_OUT= 5V, V_IN= 5.6V

102

100

99

98

97

96

95

94

93

92

91

103

102

101

100

9

5

4

V

70 + V – V

IN OUT

IMON

I

= I

OUT MONR •

•

R

70 + V – V

IN OUT

IMON

V

= 5V

IMON

V

= 5V

3

IMON

(SEE OPERATION SECTION FOR DETAILS)

2

125°C

25°C

1

125°C

25°C

–55°C

98

0

–55°C

97

–1

–2

–3

–4

–5

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

=5.6V, R

=1k

=2k

=3k

=1k

=2k

=3k

V

= 0V

IMON

96

V

= 0V

IMON

95

=12V, R

IMON

94

93

0

25

50

75

(mA)

100

125

0

25

50

75

(mA)

100

125

0

25

50

75

(mA)

100

125

I

OUT

3050 G41

3050 G42

3050 G43

3050fa

12

LT3050 Series

PIN FUNCTIONS

REF/BYP (Pin 1): Bypass/Soft-Start. Connecting a single

capacitor from this pin to GND bypasses the LT3050’s

reference noise and soft-starts the reference. A 10nF by-

pass capacitor typically reduces output voltage noise to

IN. The LT3050 does not function if the SHDN pin is not

connected. The SHDN pin cannot be driven below GND

unless tied to the IN pin. If the SHDN pin is driven below

GND while IN is powered, the output may turn on. SHDN

pin logic cannot be referenced to a negative rail.

30μV

in a 10Hz to 100kHz bandwidth. Soft-start time

RMS

is directly proportional to the REF/BYP capacitor value.

If the LT3050 is placed in shutdown, REF/BYP is actively

pulled low by an internal device to reset soft-start. If low

noise or soft-start performance is not required, this pin

must be left ﬂoating (unconnected). Do not drive this pin

with any active circuitry. Because the REF/BYP pin is the

reference input to the error ampliﬁer, stray capacitance at

this point should be minimized. Special attention should

begiventoanystraycapacitancesthatcancoupleexternal

signalsontotheREF/BYPpinproducingundesirableoutput

transients or ripple. A minimum REF/BYP capacitance of

100pF is recommended.

IN (Pin 5,6):Input. These pinssupply powertothe device.

The LT3050 requires a local IN bypass capacitor if it is

located more than six inches from the main input ﬁlter

capacitor. In general, battery output impedance rises

with frequency, so adding a bypass capacitor in battery

powered circuits is advisable. A minimum input of 1ꢁF

generally sufﬁces.

OUT (Pin 7,8): Output. These pins supply power to the

load. Stability requirements demand a minimum 2.2μF

ceramic output capacitor to prevent oscillations. Large

load transient applications require larger output capaci-

tors to limit peak voltage transients. See the Applications

Information section for details on transient response and

reverseoutputcharacteristics. Permissibleoutputvoltage

rangefortheadjustablevoltageversionis600mVto44.5V.

The top of the resistor divider setting output voltage in

the ﬁxed 3.3V and 5V versions connects directly to OUT

on the IC.

I

(Pin 2): Minimum Output Current Programming

MIN

Pin. This pin is the collector of a PNP current mirror that

outputs 1/200th of the power PNP load current. This pin

is also the input to the minimum output current fault com-

parator. Connecting a resistorbetween I

the minimum output current fault threshold. For detailed

information on how to set the I

please see the Operation section.

and GND sets

MIN

pin resistor value,

MIN

ADJ(Pin9):Adjust.Thispinistheerrorampliﬁer’sinverting

terminal. Its typical bias of 16nA current ﬂows out of the

pin (see curve of ADJ Pin Bias Current vs. Temperature

in the Typical Performance Characteristics section). The

typical ADJ pin voltage is 600mV referenced to GND.

A small external decoupling capacitor (10nF minimum)

is required to improve I PSRR. If minimum output

MIN

current programming is not required, the I

be left ﬂoating (unconnected).

pin must

MIN

GND (PIN 10, Exposed Pad Pin 13): Ground. The exposed

pad of the DFN and MSOP packages is an electrical con-

nection to GND. To ensure proper electrical and thermal

performance, solder Pin 13 to the PCB ground and tie

directly to Pin 10. Connect the bottom of the output volt-

age setting resistor divider directly to GND (Pin 10) for

optimum load regulation performance.

FAULT (Pin 3): Fault Pin. This is an open collector logic

pin which asserts during current limit, thermal limit or

a minimum current fault condition. The maximum low

logic output level is deﬁned for sinking 100μA of current.

Off state logic may be as high as 45V without damaging

internal circuitry regardless of the V used.

IN

SHDN (Pin 4): Shutdown. Pulling the SHDN pin low puts

the LT3050 into a low power state and turns the output

off. Drive the SHDN pin with either logic or an open collec-

tor/drain with a pull-up resistor. The resistor supplies the

pull-up current to the open collector/drain logic, normally

several microamperes, and the SHDN pin current, typi-

cally less than 2μA. If unused, connect the SHDN pin to

I

(Pin 11): Precision Current Limit Programming

MAX

Pin. This pin is the collector of a current mirror PNP that

th

is 1/200 the size of the output power PNP. This pin is

also the input to the current limit ampliﬁer. Current limit

threshold is set by connecting a resistor between the I

pin and GND.

MAX

3050fa

13

LT3050 Series

PIN FUNCTIONS

FordetailedinformationonhowtosettheI

value, please see the Operation section.

pinresistor

of the power PNP current. When OUT = I

current exactly equals 1/100 that of the output current.

For detailed information on how to calculate the output

, the pin

MAX

MON

th

The I

pin requires a 10nF decoupling capacitor to

MAX

currentfromtheI

pin,pleaseseetheOperationsection.

MON

ground. If not used, tie I

to GND.

MAX

The I

pin requires a small (22nF minimum) external

MON

I

(Pin 12): Output Current Monitor. This pin is the

decoupling capacitor. If the I

be tied to GND.

pin is not used, it must

MON

th

collector of a PNP current mirror that outputs 1/100

BLOCK DIAGRAM

IN

5, 6

R1

D1

OUT

R2

QI

MAX

1/200

MIN

MON

1/200

1/100

QPOWER

1

THERMAL/

CURRENT LIMITS

30k

R4

ADJ

–

+

9

OUT

7, 8

Q3

CURRENT

LIMIT

Q2

100k

R3

R1

AMPLIFIER

ERROR

AMPLIFIER

I

MAX

11

12

+

–

D2

I

IDEAL

DIODE

D3

MON

I

MIN

COMPARATOR

100k

R2

+

–

I

MIN

600mV

REFERENCE

SHDN

2

3

+

4

–

FAULT

U1

QFAULT

GND

10, 13

REF/BYP

1

3050 BD01

FIXED V

3.3V

R1

60k

R2

OUT

270k

440k

5V

3050fa

14

LT3050 Series

OPERATION

I

Pin Operation (Current Monitor)

A small decoupling capacitor (22nF minimum) from I

MON

to GND is required to improve I

pin power supply

MON

The I

pin is the collector of a PNP which mirrors the

MON

rejection. If the current monitor is not needed, it must be

tied to GND.

LT3050 output PNP at a ratio of 1:100 (see block diagram

on page 11). The current sourced by the I

pin is

MON

th

~1/100 of the current sourced by the OUT pin when the

Open Circuit Detection (I

Pin)

MIN

I

and OUT pin voltages are equal and the device is not

MON

The I

pin is the collector of a PNP which mirrors the

operating in dropout. If the I

and OUT pin voltages

MIN

MON

LT3050 output at a ratio of approximately 1:200 (see block

diagram on page 11). The I fault comparator asserts

are not the same, the ratio deviates from 1/100 due to

the Early voltages of the I

to the equation:

and OUT PNPs according

MIN

MON

the FAULT pin if the I

pin voltage is below 0.6V. This

MIN

low output current fault threshold voltage (I

) is set

OPEN

¥

´

I

70ꢁ V ꢂ V

1

by attaching a resistor from I

to GND.

IMON

IN

¦

^IMONµ

MIN

ꢀ

v

I_OUTI_MONR

70ꢁ V ꢂ V

IN OUT

§

¶

119.85–(1.68 – 36.8 •I_OPEN)• V_OUT

I_OPEN

144424443

R_IMIN

=

Early Voltage Compensation

where the Early voltage of the PNPs is 70V and I

is

MONR

current ratio.

This equation is empirically derived and partially

compensates for early voltage effects in the I current

a variable which represents the I

to I

OUT

MON

I

varies with V to V

voltage according to the

MIN

MONR

IN

OUT

mirror. It is valid for an input voltage range from 0.6V

above the output to 10V above the output. It is valid for

output voltages up to 12V. The accuracy of this equation

for setting the resistor value is approximately 2ꢀ. Unit

values are Amps, Volts, and Ohms.

empirically derived equation:

= 97 + 5 • log (1+V – V ) for (V – V )

OUT

I

MONR

≥0.5

10

IN

OUT

IN

I

= 96 + 2 • (V – V ) for (V – V ) < 0.5

IN OUT IN OUT

MONR

The I

pin current can be converted into a voltage for

Iftheopencircuitdetectionfunctionisnotneeded,theI

MIN

MON

use by monitoring circuitry simply by connecting the I

pin to a resistor.

pinmustbeleftﬂoating(unconnected).Asmalldecoupling

capacitor (10nF minimum) from I to GND is required

MON

MIN

to improve I

pin power supply rejection and to prevent

MIN

Connecting a resistor from I

to GND converts the

MON

FAULT pin glitches.

I

pin current into a voltage that can be monitored by

MON

circuitry such as an ADC.

See the Typical Performance Characteristics section for

additional information.

For example, a 1.2k resistor results in a I

pin voltage

MON

of 1.2V for an output current of 100mA and an output

voltage of 1.2V.

The output current of the device can be calculated from

the I

pin voltage by the following equation:

MON

¥

´

V

70ꢁ V ꢂ V_OUT

IMON

IN

I_OUTꢀ I_MONR

v

¦

µ

{

OUT

R_IMON

70ꢁ V ꢂ V

§

¶

IN

IMON

123

144424443

I

Ratio

I

Early VoltageCompensation

IMON

I

MON

3050fa

15

LT3050 Series

OPERATION

External Programmable Current Limit (I

See the Typical Performance Characteristics section for

additional information.

Pin)

MAX

The I

pin is the collector of a PNP which mirrors the

MAX

LT3050outputataratioofapproximately1:200(seeBlock

Diagram). The I pin is also the input to the precision

FAULT Pin Operation

MAX

The FAULT pin is an open collector logic pin which asserts

during internal current limit, precision current limit, ther-

mal limit, or a minimum current fault. There is no internal

pull-up on the FAULT pin; an external pull-up resistor is

required. The FAULT pin provides drive for up to 100μA

of pull-down current. Off state logic may be as high as

45V, regardless of the input voltage used. When asserted,

the FAULT pin drive circuitry adds 50μA (nominal) of GND

pin current.

current limit ampliﬁer. If the output load increases to the

point where it causes the I pin voltage to reach 0.6V,

MAX

the current limit ampliﬁer takes control of output regula-

tion so that the I pin clamps at 0.6V, regardless of the

MAX

output voltage. The current limit threshold (I

by attaching a resistor (R

) is set

LIMIT

to GND:

) from I

IMAX

MAX

119.22− 0.894• V_OUT

R_IMAX

=

I_LIMIT

Depending on the I

capacitance, BYP capacitance,

This equation is empirically derived and partially compen-

sates for early voltage effects in the I current mirror.

It is valid for an input voltage range from 0.6V above the

output to 10V above the output. It is valid for output volt-

ages up to 12V. The accuracy of this equation for setting

the resistor value is approximately 1ꢀ. Unit values are

Amps, Volts, and Ohms.

MIN

and OUT capacitance, the FAULT pin may assert during

startup. Consideration should be given to masking the

FAULT signal during startup. The FAULT pin circuitry is

inactive (not asserted) during shutdown and when the

OUT pin is pulled above the IN pin.

MAX

Operation in Dropout

In cases where the IN to OUT voltage exceeds 10V, fold-

back current limit will lower the internal current level limit,

possibly causing it to preempt the external programmable

The LT3050 contains circuitry which prevents the PNP

output power device from saturating in dropout. This also

keepstheI

, I , andI

MON MIN

currentmirrorsfunctioning

current limit. See the Internal Current Limit vs V – V

MAX

IN

OUT

accurately, even in dropout. However, this anti-saturation

circuitry becomes less active at lower output currents, so

there is some degradation of current mirror function for

output currents less than 10mA.

graph in the Typical Performance Characteristics section.

If the external programmable current limit is not needed,

the I

pin must be connected to GND. The I

MAX

requires a 10nF decoupling capacitor.

3050fa

16

LT3050 Series

APPLICATIONS INFORMATION

The LT3050 is a micropower, low noise and low dropout

voltage,100mAlinearregulatorwithmicropowershutdown,

programmablecurrentlimit,anddiagnosticfunctions.The

device supplies up to 100mA at a typical dropout voltage

of 340mV and operates over a 2.2V to 45V input range.

referenced to ground. The current in R1 is then equal to

0.6V/R1, and the current in R2 is the current in R1 minus

the ADJ pin bias current.

V

IN

OUT

LT3050

OUT

Asingleexternalcapacitorcanprovidelownoisereference

performance and output soft-start functionality. For

example,connectinga10nFcapacitorfromtheREF/BYPpin

V

R2

R1

IN

SHDN ADJ

GND

to GND lowers output noise to 30μV

over a 10Hz to

RMS

3050 F01

100kHz bandwidth. This capacitor also soft-starts the

reference and prevents output voltage overshoot at turn-on.

R2

R1

V

_OUT= 0.6V 1+

– I

(

•R2

ADJ

)

The LT3050’s quiescent current is merely 45μA but

provides fast transient response with a minimum low ESR

2.2μF ceramic output capacitor. In shutdown, quiescent

current is less than 1μA and the reference soft-start

capacitor is reset.

V

_ADJ= 0.6V

_ADJ= 16nA at 25°C

OUTPUT RANGE = 0.6V to 44.5V

I

Figure 1. Adjustable Operation

The LT3050 optimizes stability and transient response

with low ESR, ceramic output capacitors. The regulator

does not require the addition of ESR as is common with

other regulators. The LT3050 typically provides 0.1ꢀ line

regulation and 0.1ꢀ load regulation. Internal protection

circuitry includes reverse-battery protection, reverse-

outputprotection,reverse-currentprotection,currentlimit

with fold-back and thermal shutdown.

The ADJ pin bias current, 16nA at 25°C, ﬂows from the

ADJ pin through R1 to GND. Calculate the output voltage

using the formula in Figure 1. The value of R1 should be

no greater than 124k to provide a minimum 5μA load

current so that output voltage errors, caused by the ADJ

pin bias current, are minimized. Note that in shutdown,

the output is turned off and the divider current is zero.

CurvesofADJPinVoltagevsTemperatureandADJPinBias

CurrentvsTemperatureappearintheTypicalPerformance

Characteristics Section.

This “bullet-proof” protection set makes it ideal for use in

battery-powered, automotive and industrial systems.

In battery backup applications where the output is held

up by a backup battery and the input is pulled to ground,

the LT3050 acts like it has a diode in series with its output

and prevents reverse current ﬂow.

The LT3050 is tested and speciﬁed with the ADJ pin tied

to the OUT pin, yielding V

= 0.6V. Speciﬁcations for

OUT

output voltages greater than 0.6V are proportional to the

Adjustable Operation

ratio of the desired output voltage to 0.6V: V /0.6V. For

OUT

example, load regulation for an output current change

The adjustable LT3050 has an output voltage range of

0.6V to 44.5V. The output voltage is set by the ratio of

two external resistors, as shown in Figure 1. The device

servos the output to maintain the ADJ pin voltage at 0.6V

of 1mA to 100mA is –0.2mV (typical) at V

= 0.6V.

OUT

at V

= 12V, load regulation is:

OUT

12V

0.6V

• –0.2mV = – 4mV

(

)

3050fa

17

LT3050 Series

APPLICATIONS INFORMATION

Table1shows1ꢀresistordividervaluesforsomecommon

output voltages with a resistor divider current of 5ꢁA.

Using a feedforward capacitor (C ) from V

to the ADJ

OUT

FF

pin has the added beneﬁt of improving transient response

foroutputvoltagesgreaterthan0.6V. Withnofeedforward

capacitor, the settling time will increase as the output

voltage is raised above 0.6V. Use the equation in Figure 2

Table 1. Output Voltage Resistor Divider Valves

V

(V)

R1 (kΩ)

118

R2 (kΩ)

118

OUT

1.2

to determine the minimum value of C to achieve a

FF

1.5

1.8

2.5

3

121

182

transient response that is similar to 0.6V output voltage

performance regardless of the chosen output voltage

(See Figure 3 and Transient Response in the Typical Perf-

ormance Characteristics section).

124

249

115

365

124

499

3.3

5

124

562

During start-up, the internal reference will soft-start if a

reference bypass capacitor is present. Regulator start-

up time is directly proportional to the size of the bypass

capacitor, slowing to 6ms with a 10nF bypass capacitor

(See Start-up Time vs REF/BYP Capacitor in the Typical

Performance Characteristics section). The reference by-

pass capacitor is actively pulled low during shutdown to

reset the internal reference.

115

845

Bypass Capacitance, Output Voltage Noise and

Transient Response

The LT3050 regulator provides low output voltage noise

over the 10Hz to 100kHz bandwidth while operating at

full load with the addition of a reference bypass capacitor

(C

) from the REF/BYP pin to GND. A good quality,

REF/BYP

lowleakagecapacitorisrecommended. Thiscapacitorwill

bypass the internal reference of the regulator, providing a

IN

OUT

V

OUT

lowfrequencynoisepole.Withtheuseof10nFforC

REF/BYP,

C

OUT

V

FF

LT3050-5

IN

the output voltage noise decreases to as low as 30ꢁV

RMS

SHDN

ADJ

when the output voltage is set for 0.6V. For higher output

voltages (generated by using a feedback resistor divider),

the output voltage noise gains up accordingly when using

GND REF/BYP

10nF

10ꢁA

C_FF

I_FB

• I

FB DIVIDER

(

)

C

REF/BYP

V_OUT

=

10ꢁA FOR FIXED V

(

)

DIVIDER

OUT

R1+R2

C

by itself.

3050 F02

REF/BYP

Figure 2. Feedforward Capacitor for Fast Transient Response

Tolowertheoutputvoltagenoiseforhigheroutputvoltages,

include a feedforward capacitor (C ) from V to the

FF

OUT

ADJ pin. A good quality, low leakage capacitor is recom-

mended. This capacitor will bypass the error ampliﬁer of

the regulator, providing a low frequency noise pole. With

V

C

= 5V

OUT

= 10ꢁF

I

= 10ꢁA

FB-DIVIDER

0

the use of 10nF for both C and C

, output voltage

FF

RMS

REF/BYP

when the output voltage is

noise decreases to 30ꢁV

100pF

1nF

set to 5V by a 5ꢁA feedback resistor divider. If the current

in the feedback resistor divider is doubled, C must also

FF

10nF

be doubled to achieve equivalent noise performance.

LOAD CURRENT

100mA/DIV

Highervaluesofoutputvoltagenoiseareoftenmeasuredif

care is not exercised with regard to circuit layout and test-

ing. Crosstalkfromnearbytracesinducesunwantednoise

onto the LT3050’s output. Power supply ripple rejection

must also be considered. The LT3050 regulator does not

have unlimited power supply rejection and passes a small

portion of the input noise through to the output.

3050 F03

100ꢁs/DIV

Figure 3. Transient Response vs Feedforward Capacitor

3050fa

18

LT3050 Series

APPLICATIONS INFORMATION

Start-up time is also affected by the presence of a feed-

forward capacitor. Start-up time is directly proportional to

the size of the feedforward capacitor and the output volt-

age, and is inversely proportional to the feedback resistor

divider current, slowing to 15ms with a 4.7nF feedforward

capacitoranda10ꢁFoutputcapacitorforanoutputvoltage

set to 5V by a 5ꢁA feedback resistor divider.

Give extra consideration to the use of ceramic capacitors.

Manufacturers make ceramic capacitors with a variety of

dielectrics, each with different behavior across tempera-

ture and applied voltage. The most common dielectrics

are speciﬁed with EIA temperature characteristic codes

of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics

provide high C-V products in a small package at low cost,

butexhibitstrongvoltageandtemperaturecoefﬁcients, as

shown in Figures 4 and 5. When used with a 5V regulator,

a 16V 10μF Y5V capacitor can exhibit an effective value

as low as 1μF to 2μF for the DC bias voltage applied, and

over the operating temperature range. The X5R and X7R

dielectrics yield much more stable characteristics and are

more suitable for use as the output capacitor.

Output Capacitance

The LT3050 regulator is stable with a wide range of output

capacitors.TheESRoftheoutputcapacitoraffectsstability,

mostnotablywithsmallcapacitors.Useaminimumoutput

capacitor of 2.2ꢁF with an ESR of 3Ω or less to prevent

oscillations. If a feedforward capacitor is used with output

voltages set for greater than 24V, use a minimum output

capacitor of 4.7ꢁF. The LT3050 is a micropower device

and output load transient response is a function of output

capacitance. Larger values of output capacitance decrease

the peak deviations and provide improved transient re-

sponseforlargerloadcurrentchanges. Bypasscapacitors,

used to decouple individual components powered by the

LT3050, increase the effective output capacitor value. For

applications with large load current transients, a low ESR

ceramic capacitor in parallel with a bulk tantalum capacitor

often provides an optimally damped response.

The X7R type works over a wider temperature range and

has better temperature stability, while the X5R is less

expensive and is available in higher values. Care still must

beexercisedwhenusingX5RandX7Rcapacitors;theX5R

and X7R codes only specify operating temperature range

and maximum capacitance change over temperature.

Capacitance change due to DC bias with X5R and X7R

capacitors is better than Y5V and Z5U capacitors, but can

still be signiﬁcant enough to drop capacitor values below

appropriate levels. Capacitor DC bias characteristics tend

toimproveascomponentcasesizeincreases,butexpected

capacitance at operating voltage should be veriﬁed.

20

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10ꢁF

0

40

20

X5R

–20

X5R

0

–20

–40

–60

–40

Y5V

–60

–80

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10ꢁF

–100

0

8

12 14

2

4

6

10

16

DC BIAS VOLTAGE (V)

–100

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

3050 F04

3050 F05

Figure 4. Ceramic Capacitor DC Bias Characteristics

Figure 5. Ceramic Capacitor Temperature Characteristics

3050fa

19

LT3050 Series

APPLICATIONS INFORMATION

a heavy output load when the input voltage is high and the

outputvoltageislow.Commonsituationsare:immediately

after the removal of a short-circuit or if the shutdown pin

is pulled high after the input voltage is already turned on.

The load line for such a load intersects the output cur-

rent curve at two points. If this happens, there are two

stable output operating points for the regulator. With this

double intersection, the input power supply needs to be

cycled down to zero and brought up again to make the

output recover.

V

C

= 5V

OUT

= 10ꢁF

= 10nF

REF/BYP

V

OUT

1mV/DIV

3050 F06

10ms/DIV

Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor

Thermal Considerations

Voltage and temperature coefﬁcients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress,

similar to the way a piezoelectric accelerometer or micro-

phoneworks.Foraceramiccapacitor,thestressisinduced

by vibrations in the system or thermal transients. The

resulting voltages produced cause appreciable amounts

of noise. A ceramic capacitor produced the trace in

Figure 6 in response to light tapping from a pencil. Similar

vibration induced behavior can masquerade as increased

output voltage noise.

The LT3050’s maximum rated junction temperature of

125°Climitsitspowerhandlingcapability.Twocomponents

comprise the power dissipated by the device:

1. Output current multiplied by the input/output

voltage differential: I

• (V – V ), and

OUT

IN OUT

2. GND pin current multiplied by the input voltage:

• V

I

GND

IN

GND pin current is determined using the GND Pin Current

curvesintheTypicalPerformanceCharacteristicssection.

Power dissipation equals the sum of the two components

listed above.

Overload Recovery

The LT3050 regulator has internal thermal limiting that

protects the device during overload conditions. For con-

tinuous normal conditions, do not exceed the maximum

junction temperature of 125°C. Carefully consider all

sources of thermal resistance from junction-to-ambient

including other heat sources mounted in proximity to the

LT3050.

Like many IC power regulators, the LT3050 has safe oper-

ating area protection. The safe area protection decreases

current limit as input-to-output voltage increases, and

keeps the power transistor inside a safe operating region

for all values of input-to-output voltage. The LT3050 pro-

vides some output current at all values of input-to-output

voltage up to the device breakdown.

The undersides of the LT3050 DFN and MSOP packages

have exposed metal from the lead frame to the die attach-

ment. These packages allow heat to directly transfer from

thediejunctiontotheprintedcircuitboardmetaltocontrol

maximumoperatingjunctiontemperature.Thedual-in-line

pin arrangement allows metal to extend beyond the ends

of the package on the topside (component side) of a PCB.

Connect this metal to GND on the PCB. The multiple IN

and OUT pins of the LT3050 also assist in spreading heat

to the PCB.

Whenpowerisﬁrstapplied, theinputvoltagerisesandthe

output follows the input; allowing the regulator to start-up

intoveryheavyloads. Duringstart-up, astheinputvoltage

is rising, the input-to-output voltage differential is small,

allowing the regulator to supply large output currents.

With a high input voltage, a problem can occur wherein

the removal of an output short will not allow the output

to recover. Other regulators, such as the LT1083/LT1084/

LT1085familyandLT1764Aalsoexhibitthisphenomenon,

so it is not unique to the LT3050. The problem occurs with

3050fa

20

LT3050 Series

APPLICATIONS INFORMATION

For surface mount devices, heat sinking is accomplished

by using the heat spreading capabilities of the PC board

and its copper traces. Copper board stiffeners and plated

through-holes also can spread the heat generated by

power devices. The following tables list thermal resis-

tance as a function of copper area in a ﬁxed board size.

All measurements were taken in still air on a four-layer

FR-4 board with one ounce solid internal planes and two

ounce external trace planes with a total board thickness

of 1.6mm. For further information on thermal resistance

and using thermal information, refer to JEDEC standard

JESD51, notably JESD51-12.

The power dissipated by the device equals:

* (V – V ) + I * V

IN(MAX)

I

OUT(MAX)

IN(MAX)

OUT

GND

where,

I

= 75mA

= 12.6V

OUT(MAX)

V

IN(MAX)

I

at (I = 75mA, V = 12V) = 1.5mA

OUT IN

GND

So,

P = 75mA • (12.6V - 5V) + 1.5mA • 12.6V = 0.589W

Using a DFN package, the thermal resistance ranges from

44°C/W to 49°C/W depending on the copper area. So the

junction temperature rise above ambient approximately

equals:

Table 1. MSOP Measured Thermal Resistance

COPPER AREA

BOARD

AREA

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

TOPSIDE

BACKSIDE

2500 sq mm 2500 sq mm 2500 sq mm

1000 sq mm 2500 sq mm 2500 sq mm

225 sq mm 2500 sq mm 2500 sq mm

100 sq mm 2500 sq mm 2500 sq mm

40°C/W

41°C/W

43°C/W

45°C/W

0.589W • 49°C/W = 28.86°C

The maximum junction temperature equals the maximum

ambienttemperatureplusthemaximumjunctiontempera-

ture rise above ambient or:

Table 2. DFN Measured Thermal Resistance

T

= 85°C + 28.86°C = 113.86°C

JMAX

COPPER AREA

TOPSIDE

THERMAL RESISTANCE

(JUNCTION-TO-AMBIENT)

BOARD AREA

2500 sq mm

Protection Features

2500 sq mm

1000 sq mm

225 sq mm

100 sq mm

44°C/W

The LT3050 incorporates several protection features that

make it ideal for use in battery-powered circuits. In ad-

dition to the normal protection features associated with

monolithicregulators,suchascurrentlimitingandthermal

limiting, the device also protects against reverse-input

voltages, reverse-output voltages and reverse output-to-

input voltages.

45°C/W

47°C/W

49°C/W

Calculating Junction Temperature

Example: Given an output voltage of 5V, an input voltage

range of 12V 5ꢀ, a maximum output current range of

75mAandamaximumambienttemperatureof85°C, what

will the maximum junction temperature be?

Current limit protection and thermal overload protection

protect the device against current overload conditions at

the output of the device. For normal operation, do not

exceed a junction temperature of 125°C.

3050fa

21

LT3050 Series

APPLICATIONS INFORMATION

TheLT3050INpinwithstandsreversevoltagesof50V. The

devicelimitscurrentﬂowtolessthan300μA(typicallyless

than 10μA) and no negative voltage appears at OUT. The

device protects both itself and the load against batteries

that are plugged in backwards.

the output can be pulled below ground by 50V. No cur-

rent ﬂows through the pass transistor from the output.

However, current ﬂows in (but is limited by) the resistor

divider that sets the output voltage. Current ﬂows from

the bottom resistor in the divider and from the ADJ pin’s

internal clamp through the top resistor in the divider to

the external circuitry pulling OUT below ground. If the

input is powered by a voltage source, the output sources

current equal to its current limit capability and the LT3050

protects itself by thermal limiting. In this case, grounding

the SHDN pin turns off the device and stops the output

from sourcing current.

The SHDN pin cannot be driven below GND unless tied

to the IN pin. If the SHDN pin is driven below GND while

IN is powered, the output may turn on. SHDN pin logic

cannot be referenced to a negative rail.

The LT3050 incurs no damage if its output is pulled be-

low ground. If the input is left open-circuit or grounded,

1.0

ALL PINS GROUNDED EXCEPT FOR OUT

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

10

20

V

30

(V)

40

50

OUT

3050 F07

Figure 7. Reverse Output Current

3050fa

22

LT3050 Series

PACKAGE DESCRIPTION

DDB Package

12-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1723 Rev Ø)

0.64 0.05

(2 SIDES)

R = 0.115

TYP

7

0.40 0.10

12

3.00 0.10

(2 SIDES)

R = 0.05

TYP

0.70 0.05

2.55 0.05

1.15 0.05

2.00 0.10

PIN 1 BAR

(2 SIDES)

TOP MARK

PIN 1

R = 0.20 OR

(SEE NOTE 6)

0.25 s 45°

PACKAGE

OUTLINE

0.64 0.10

(2 SIDES)

0.23 0.05

CHAMFER

6

1

(DDB12) DFN 0106 REV Ø

0.25 0.05

0.45 BSC

0.75 0.05

0.200 REF

0.45 BSC

2.39 0.05

(2 SIDES)

2.39 0.10

(2 SIDES)

0 – 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3050fa

23

LT3050 Series

PACKAGE DESCRIPTION

MSE Package

12-Lead Plastic MSOP Exposed Die Pad

(Reference LTC DWG # 05-08-1666 Rev B)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 p 0.102

(.112 p .004)

2.845 p 0.102

(.112 p .004)

0.889 p 0.127

(.035 p .005)

1

6

0.35

REF

5.23

(.206)

MIN

1.651 p 0.102

(.065 p .004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

12

4.039 p 0.102

(.159 p .004)

(NOTE 3)

7

NO MEASUREMENT PURPOSE

0.65

(.0256)

BSC

0.42 p 0.038

(.0165 p .0015)

TYP

0.406 p 0.076

RECOMMENDED SOLDER PAD LAYOUT

(.016 p .003)

12 11 10 9 8 7

REF

DETAIL “A”

0.254

(.010)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

0o – 6o TYP

4.90 p 0.152

(.193 p .006)

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1

2 3 4 5 6

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MSE12) 0608 REV B

0.650

(.0256)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3050fa

24

LT3050 Series

REVISION HISTORY

REV

DATE DESCRIPTION

PAGE NUMBER

A

6/10 Updated data sheet to include ﬁxed voltage options.

1-14, 17-26

3050fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

25

LT3050 Series

TYPICAL APPLICATION

5V Protected Antenna Supply with 100mA Current Limit, 10mA I_MIN

IN

OUT

5V

C

FF

12V

IN

1ꢁF

10ꢁF

SHDN

FAULT

120k

10nF

V

ADJ

LT3050-5

I

MAX

1.15k

I

10nF

TO ꢁP ADC

MON

(THRESHOLD = 100mA)

3k

0.1ꢁF

(ADC FULL SCALE = 3V)

I

MIN

REF/BYP

GND

11.3k

0.1ꢁF

10nF

(THRESHOLD = 10mA)

3050 TA02

RELATED PARTS

PART

DESCRIPTION

NUMBER

COMMENTS

LT1761

LT1762

LT1763

LT1962

100mA, Low Noise LDO

150mA, Low Noise LDO

500mA, Low Noise LDO

300mA, Low Noise LDO

300mV Dropout Voltage, Low Noise: 20μV

, V = 1.8V to 20V, ThinSOT Package

RMS IN

300mV Dropout Voltage, Low Noise: 20μV

, V = 1.8V to 20V, MS8 Package

RMS IN

, V = 1.8V to 20V, SO-8 Package

RMS IN

270mV Dropout Voltage, Low Noise: 20μV

340mV Dropout Voltage, Low Noise: 40μV

Ceramic Capacitors, TO-220, DD-PAK, SOT-223 and SO-8 Packages

, V = 1.8V to 20V, MS8 Package

RMS IN

LT1963/A 1.5A Low Noise, Fast Transient

Response LDO

, V = 2.5V to 20V, “A” Version Stable with

RMS IN

LT1965

1.1A, Low Noise, Low Dropout Linear

Regulator

290mV Dropout Voltage, Low Noise: 40μV , V : 1.8V to 20V, V : 1.2V to 19.5V, Stable

RMS IN

OUT

with Ceramic Capacitors, TO-220, DD-PAK, MSOP and 3 × 3 DFN Packages

LT3008

20mA, 45V, 3ꢁA I Micropower LDO

300mV Dropout Voltage, Low I : 3μA, V = 2.0V to 45V, V = 0.6V to 39.5V; ThinSOT and

Q

IN

OUT

2mm × 2mm DFN-6 Packages

LT3009

LT3010

20mA, 3ꢁA I Micropower LDO

Q

280mV Dropout Voltage, Low I : 3μA, V = 1.6V to 20V, ThinSOT and SC-70 Packages

Q

IN

50mA, High Voltage, Micropower LDO V : 3V to 80V, V : 1.275V to 60V, VDO = 0.3V, I = 30μA, ISD < 1μA, Low Noise: <100μV

,

IN

OUT

Q

RMS

Stable with 1μF Output Capacitor, Exposed MS8 Package

LT3011

LT3012

LT3013

50mA, High Voltage, Micropower LDO V : 3V to 80V, V : 1.275V to 60V, VDO = 0.3V, I = 46μA, ISD < 1μA, Low Noise: <100μV

,

IN

OUT

Q

RMS

with PWRGD

Power Good, Stable with 1μF Output Capacitor, 3 × 3 DFN-10 and Exposed MS12E Packages

250mA, 4V to 80V, Low Dropout

Micropower Linear Regulator

V : 4V to 80V, V : 1.24V to 60V, VDO = 0.4V, I = 40μA, ISD < 1μA, TSSOP-16E and

IN

OUT

Q

4mm × 3mm DFN-12 Packages

250mA, 4V to 80V, Low Dropout

Micropower Linear Regulator with

PWRGD

V : 4V to 80V, V : 1.24V to 60V, VDO = 0.4V, I = 65μA, ISD < 1μA, Power Good feature;

IN

OUT

Q

TSSOP-16E and 4mm × 3mm DFN-12 Packages

LT3014/HV 20mA, 3V to 80V, Low Dropout

Micropower Linear Regulator

V : 3V to 80V (100V for 2ms, “HV” version), V : 1.22V to 60V, VDO = 0.35V, I = 7μA, ISD <

IN

OUT

Q

1μA, ThinSOT and 3mm × 3mm DFN-8 Packages

LT3060

100mA, Low Noise LDO with Soft Start 300mV Dropout Voltage, Low Noise: 20μV

, V = 1.8V to 45V, DFN Package

RMS IN

LT3080/-1 1.1A, Parallelable, Low Noise, Low

Dropout Linear Regulator

300mV Dropout Voltage (2-supply operation), Low Noise: 40μV

, V : 1.2V to 36V, V : 0V

RMS IN OUT

to 35.7V, Current-Based Reference with 1-Resistor V

set; Directly Parallelable (no op amp

OUT

required), Stable with Ceramic Caps, TO-220, SOT-223, MSOP and 3mm × 3mm DFN Packages;

“–1” Version has Integrated Internal Ballast Resistor

LT3085

500mA, Parallelable. Low Noise, Low

Dropout Linear Regulator

275mV Dropout Voltage (2-supply operation), Low Noise: 40ꢁV

, V : 1.2V to 36V, V : 0V

RMS IN OUT

to 35.7V, Current-Based Reference with 1-Resistor V

set; Directly Parallelable (no op amp

OUT

required), Stable with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN Packages

3050fa

LT 0610 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

26

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3050EDDB-5#TRPBF
厂家：	Linear
描述：	LT3050 - 100mA, Linear Regulator with Precision Current Limit and Diagnostic Outputs; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C 线性稳压器IC 调节器电源电路光电二极管输出元件
文件：	总26页 (文件大小：394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3050EDDB-5#TRPBF [Linear]

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