LT3028EFE#TR [Linear]
LT3028 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulators with Independent Inputs; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LT3028EFE#TR |
厂家: | Linear |
描述: | LT3028 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulators with Independent Inputs; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 稳压器 |
文件: | 总16页 (文件大小:205K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT1965
1.1A, Low Noise,
Low Dropout Linear Regulator
FEATURES
DESCRIPTION
The LT®1965 is a low noise, low dropout linear regulator.
The device supplies 1.1A of output current with a 290mV
typical dropout voltage. Operating quiescent current is
500μA, reducing to <1μA in shutdown. Quiescent current
is well controlled; it does not rise in dropout as with many
other regulators. The LT1965 regulator has very low out-
put noise which makes it ideal for sensitive RF and DSP
supply applications.
■
Output Current: 1.1A
■
Dropout Voltage: 290mV
■
Low Noise: 40μV
500μA Quiescent Current
(10Hz to 100kHz)
RMS
■
■
■
■
■
■
■
■
Wide Input Voltage Range: 1.8V to 20V
No Protection Diodes Needed
Controlled Quiescent Current in Dropout
Adjustable Output from 1.20V to 19.5V
< 1μA Quiescent Current in Shutdown
Stable with 10μF Output Capacitor
Stable with Ceramic, Tantalum or Aluminum
Electrolytic Capacitors
Reverse Battery Protection
No Reverse Current
Current Limit with Foldback Protection
Thermal Limiting
5-Lead TO-220, DD-PAK, Thermally Enhanced 8-Lead
Output voltage ranges from 1.20V to 19.5V. The LT1965
regulator is stable with output capacitors as low as 10μF.
Internal protection circuitry includes reverse battery pro-
tection, current limiting with foldback, thermal limiting
and reverse current protection. The LT1965 is available
as an adjustable device with a 1.20V reference voltage.
The package offering includes the 5-lead TO-220, 5-lead
DD-PAK as well as the thermally enhanced 8-lead MSOP
■
■
■
■
■
and 8-lead 3mm × 3mm DFN.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
MSOP and 8-Lead 3mm × 3mm DFN Packages
APPLICATIONS
■
Logic Power Supplies
■
Post Regulator for Switching Supplies
■
Low Noise Instrumentation
TYPICAL APPLICATION
Dropout Voltage
3.3V to 2.5V Regulator
400
T
= 25°C
J
350
300
250
200
150
100
50
2.5V
1.1A
IN
OUT
ADJ
+
> 3V
+
V
IN
5.11k
1%
10μF*
10μF*
TO 20V
LT1965
SHDN
GND
4.75k
1%
*CERAMIC, TANTALUM OR
ALUMINUM ELECTROLYTIC
1965 TA01
0
0
0.2
0.6
0.8
1
1.2
0.4
OUTPUT CURRENT (A)
1965 TA01b
1965f
1
LT1965
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Operating Junction Temperature Range (E, I Grade)
(Notes 2, 13)......................................–40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
IN Pin Voltage ......................................................... 22V
OUT Pin Voltage...................................................... 22V
Input to Output Differential Voltage (Note 2) ......... 22V
ADJ Pin Voltage ........................................................ 9V
SHDN Pin Voltage ................................................... 22V
Output Short-Circuit Duration .......................... Indefinite
(Only for MSOP, TO-220, DD-PAK Packages) ... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
OUT
OUT
ADJ
GND
1
2
3
4
8
7
6
5
IN
OUT
OUT
ADJ
GND
1
2
3
4
8 IN
7 IN
6 SHDN
5 GND
IN
9
9
SHDN
GND
MS8E PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
= 125°C, θ = 60°C/W
JA
JMAX
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 65°C/W
JA
JMAX
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
FRONT VIEW
FRONT VIEW
5
4
3
2
1
ADJ
OUT
GND
IN
5
4
3
2
1
ADJ
OUT
GND
IN
TAB IS
GND
TAB IS
GND
SHDN
SHDN
T PACKAGE
5-LEAD PLASTIC TO-220
Q PACKAGE
5-LEAD PLASTIC DD-PAK
T
= 125°C, θ = 30°C/W
JA
T
= 125°C, θ = 50°C/W
JMAX
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LT1965EDD#PBF
LT1965EMS8E#PBF
LT1965EQ#PBF
LT1965ET#PBF
TAPE AND REEL
PART MARKING*
LCXW
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LT1965EDD#TRPBF
LT1965EMS8E#TRPBF
LT1965EQ#TRPBF
LT1965ET#TRPBF
LT1965IDD#TRPBF
LT1965IMS8E#TRPBF
LT1965IQ#TRPBF
LT1965IT#TRPBF
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LTCXX
LT1965Q
LT1965T
LCXW
5-Lead Plastic DD-PAK
5-Lead Plastic TO-220
LT1965IDD#PBF
LT1965IMS8E#PBF
LT1965IQ#PBF
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LTCXX
LT1965Q
LT1965T
5-Lead Plastic DD-PAK
LT1965IT#PBF
5-Lead Plastic TO-220
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1965f
2
LT1965
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Input Voltage (Notes 4, 12)
I
I
= 0.5A
= 1.1A
1.65
1.8
V
V
LOAD
LOAD
●
2.3
ADJ Pin Voltage (Notes 4, 5)
V
= 2.1V, I
= 1mA
LOAD
1.182
1.164
1.20
1.20
1.218
1.236
V
V
IN
●
●
2.3V < V < 20V, 1mA < I
< 1.1A
LOAD
IN
Line Regulation (Note 4)
Load Regulation
ΔV = 2.1V to 20V, I
= 1mA
3
8
mV
IN
LOAD
V
V
= 2.3V, ΔI
= 2.3V, ΔI
= 1mA to 1.1A
= 1mA to 1.1A
4.25
8
16
mV
mV
IN
IN
LOAD
LOAD
●
●
●
●
●
Dropout Voltage
I
I
= 1mA
= 1mA
0.05
0.10
0.19
0.29
0.08
0.14
V
V
LOAD
LOAD
V
= V
OUT(NOMINAL)
IN
(Notes 6, 7, 12)
I
I
= 100mA
= 100mA
0.175
0.28
V
V
LOAD
LOAD
I
I
= 500mA
= 500mA
0.25
0.36
V
V
LOAD
LOAD
I
I
= 1.1A
= 1.1A
0.36
0.49
V
V
LOAD
LOAD
●
●
●
●
●
GND Pin Current
I
I
I
I
I
= 0mA
0.5
0.6
2.2
8.2
21
1.1
1.5
5.5
20
mA
mA
mA
mA
mA
LOAD
LOAD
LOAD
LOAD
LOAD
V
= V
+ 1V
OUT(NOMINAL)
= 1mA
IN
(Notes 6, 8)
= 100mA
= 500mA
= 1.1A
40
Output Voltage Noise
C
= 10μF, I
= 1.1A, BW = 10Hz to 100kHz
40
μV
RMS
OUT
LOAD
ADJ Pin Bias Current (Notes 4, 9)
Shutdown Threshold
1.3
4.5
2
μA
●
●
V
OUT
V
OUT
= Off to On
= On to Off
0.85
0.45
V
V
0.2
SHDN Pin Current (Note 10)
V
V
= 0V
= 20V
0.01
5.5
1
10
μA
μA
SHDN
SHDN
Quiescent Current in Shutdown
Ripple Rejection
V
= 6V, V
= 0V
SHDN
0.01
75
1
μA
dB
IN
V
– V
= 1.5V (AVG), V
= 0.5V ,
P-P
57
IN
OUT
= 120Hz, I
RIPPLE
f
= 0.75A
LOAD
RIPPLE
Current Limit
V
IN
V
IN
= 7V, V
= V
= 0
2
A
A
OUT
OUT(NOMINAL)
●
1.2
+ 1V, ΔV
= -0.1V (Note 6)
OUT
Input Reverse Leakage Current
Reverse Output Current (Note 11)
V
= –20V, V
= 0
OUT
1
mA
μA
IN
V
= 1.2V, V < 1.2V (Note 4)
175
400
OUT
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Absolute maximum input to output differential voltage is not
achievable with all combinations of rated IN pin and OUT pin voltages.
With the IN pin at 22V, the OUT pin may not be pulled below 0V. The total
measured voltage from IN to OUT must not exceed 22V.
Note 5: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of input voltage and output current. Limit the output current
range if operating at the maximum input voltage. Limit the input-to-output
voltage differential if operating at the maximum output current.
Note 6: To satisfy minimum input voltage requirements, the LT1965 is
tested and specified for these conditions with an external resistor divider
(bottom 4.02k, top 4.32k) for an output voltage of 2.5V. The external
resistor divider adds 300μA of output DC load current.
Note 3: The LT1965 is tested and specified under pulse load conditions
such that T ≅ T . The LT1965E is 100% tested at T = 25°C. Performance
Note 7: Dropout voltage is the minimum input-to-output voltage
differential needed to maintain regulation at a specified output current. In
J
A
A
at –40°C and 125°C is assured by design, characterization, and correlation
with statistical process controls. The LT1965I is guaranteed over the full
–40°C to 125°C operating junction temperature range.
dropout, the output voltage equals: (V – V
)
IN
DROPOUT
Note 8: GND pin current is tested with V = V
+ 1V and a
IN
OUT(NOMINAL)
Note 4: The LT1965 is tested and specified for these conditions with the
ADJ connected to the OUT pin.
current source load. GND pin current increases slightly in dropout. See
GND pin current curves in the Typical Performance Characteristics section.
1965f
3
LT1965
ELECTRICAL CHARACTERISTICS
Note 9: ADJ pin bias current flows into the ADJ pin.
Note 10: SHDN pin current flows into the SHDN pin.
Note 13: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 11: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out of the GND pin.
Note 12: For the LT1965, the minimum input voltage specification limits
the dropout voltage under some output voltage/load conditions.
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Dropout Voltage
Guaranteed Dropout Voltage
Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINTS
T
= 125°C
= 25°C
J
I
= 1.1A
L
T
= 125°C
= 25°C
J
T
J
I
I
= 500mA
= 100mA
L
T
J
L
I
= 1mA
L
0
0
0
–50 –25
0
25
50
75 100 125
0
0.2
0.6
0.8
1
1.2
0
0.2
0.6
0.8
1
1.2
0.4
0.4
TEMPERATURE (°C)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
1965 G03
1965 G01
1965 G02
Quiescent Current
ADJ Pin Voltage
Quiescent Current
1.218
1.214
1.210
1.206
1.202
1.198
1.194
1.190
1.186
1.182
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
= 1mA
V
= 6V
T
= 25°C
J
L
IN
L
R
=
, I = 0
IN
R
= 4.02k
∞
L
L
V
= V
V
= V
SHDN
SHDN
IN
–50 –25
0
25
50
75 100 125
0
2
4
6
8
10 12 14 16 18 20
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
1965 G05
1965 G04
1965 G06
1965f
4
LT1965
TYPICAL PERFORMANCE CHARACTERISTICS
GND Pin Current
GND Pin Current
GND Pin Current vs ILOAD
25.0
22.5
20.0
17.5
15.0
12.5
10.0
7.50
5.00
2.50
0
25
20
15
10
5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= V
+ 1V
OUT(NOMINAL)
T
= 25°C
SHDN
T
= 25°C
SHDN
IN
J
V
J
= V
V
= V
IN
= 1.2V
IN
*FOR V
*FOR V
= 1.2V
OUT
OUT
R
= 24Ω, I = 50mA*
L
L
R
= 1.091Ω, I = 1.1A*
L
L
R
R
= 120Ω, I = 10mA*
L
L
L
R
= 2.4Ω, I = 500mA*
L
L
= 1.2k, I = 1mA*
L
R
= 12Ω, I = 100mA*
L
L
0
0
0.2
0.6
0.8
1.0
1.2
0
1
2
3
4
5
6
7
8
9
10
0.4
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1965 G09
1965 G08
1965 G07
SHDN Pin Threshold
SHDN Pin Input Current
SHDN Pin Input Current
6
5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
V
= 20V
SHDN
OFF TO ON
4
3
ON TO OFF
2
1
0
0
2
4
6
8
10 12 14 16 18 20
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
SHDN PIN VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1965 G11
1965 G10
1965 G12
ADJ Pin Bias Current
Current Limit vs VIN–VOUT
Current Limit vs Temperature
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 7V
ΔV
= –100mV
IN
OUT
OUT
= 0V
T
= –50°C
J
T
= 125°C
J
T
= 25°C
J
0
2
4
6
8
10 12 14 16 18 20
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
INPUT/OUTPUT DIFFERENTIAL (V)
TEMPERATURE (°C)
1965 G13
1965 G14
1965 G15
1965f
5
LT1965
TYPICAL PERFORMANCE CHARACTERISTICS
Reverse Output Current
Reverse Output Current
Ripple Rejection vs Frequency
6
5
90
80
70
60
50
40
30
20
10
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
T
= 25°C
IN
J
V
V
= 0V
IN
OUT
V
= 0V
= 1.2V
CURRENT FLOWS INTO
OUTPUT PIN
ꢀ
V
= V
OUT
ADJ
4
3
2
1
0
I
= 0.75A
OUT
L
C
= 10μF CERAMIC
V
= V
IN
OUT(NOMINAL)
+ 1V + 50mV
RIPPLE
RMS
0
2
4
6
8
10
10
100
1k
10k
100k
1M
–50 –25
0
25
50
75 100 125
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
TEMPERATURE (°C)
1965 G16
1965 G18
1965 G17
Ripple Rejection vs Temperature
Minimum Input Voltage
Load Regulation
100
90
2.5
2.0
1.5
1.0
0.5
0
0
–2
V
= 2.3V
IN
L
ΔI = 1mA TO 1.1A
–4
I
I
= 1.1A
L
= 500mA
L
–6
80
–8
I
L
= 100mA
–10
–12
–14
–16
70
60
I
= 0.75A
L
V
= V
+ 1V + 0.5
IN
OUT(NOMINAL) P-P
RIPPLE AT f = 120Hz
–50 –25 25
TEMPERATURE (°C)
0
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
1965 G19
1965 G20
1965 G21
RMS Output Noise vs Load
Current (10Hz to 100kHz)
1.8V 10Hz to 100kHz
Output Noise
Output Noise Spectral Density
1.00
0.10
0.01
80
70
60
50
40
30
20
10
0
C
I
= 10μF
C
I
= 10μF
OUT
L
OUT
L
= 1.1A
= 1.1A
V
V
V
= 3.3V
= 2.5V
= 1.8V
OUT
OUT
OUT
V
OUT
V
V
= 3.3V
= 1.2V
V
OUT
OUT
OUT
= 2.5V
100μV/DIV
V
= 1.8V
OUT
V
= 1.5V
OUT
V
= 1.2V
OUT
1
1965 G24
400μs/DIV
V
= 1.5V
0.1
OUT
10
100
1k
FREQUENCY (Hz)
10k
100k
0.0001 0.001
0.01
10
LOAD CURRENT (A)
1965 G22
1965 G23
1965f
6
LT1965
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response
SHDN Transient Response
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
50
V
= 3.3V
OUT
SHDN
0
–50
–100
1.5
V
C
C
= 4.3V
IN
IN
OUT
= 10μF CERAMIC
OUTPUT
1.0
0.5
0.0
= 10μF CERAMIC
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80
TIME (μs)
TIME (μs)
1965 G26
V
C
= 3.3V
OUT
= 2.5k, I = 1mA FOR V
1965 G25
IN
= 10μF CERAMIC
R
= 2.5V
OUT
L
L
PIN FUNCTIONS (DFN/MSOP/DD-PAK/TO-220)
OUT (Pins 1, 2 / 1, 2 / 4 / 4): Output. This pin supplies
power to the load. Use a minimum output capacitor of
10μF to prevent oscillations. Large load transient applica-
tions require larger output capacitors to limit peak volt-
age transients. See the Applications Information section
for more information on output capacitance and reverse
output characteristics.
be driven below GND unless it is tied to the IN pin. If the
SHDN pin is driven below GND while IN is powered, the
output will turn on. SHDN pin logic cannot be referenced
to a negative supply rail.
IN (Pins 7, 8 / 7, 8 / 2 / 2): Input. This pin supplies power
tothedevice.TheLT1965requiresabypasscapacitoratIN
if located more than six inches from the main input filter
capacitor. Include a bypass capacitor in battery-powered
circuits as a battery’s output impedance generally rises
with frequency. A bypass capacitor in the range of 1μF to
10μF suffices. The LT1965’s design withstands reverse
voltages on the IN pin with respect to ground and the
OUT pin. In the case of a reversed input, which occurs if
a battery is plugged in backwards, the LT1965 behaves
as if a diode is in series with its input. No reverse current
flows into the LT1965 and no reverse voltage appears at
the load. The device protects itself and the load.
ADJ (Pins 3 / 3 / 5 / 5): Adjust. This pin is the input to the
error amplifier. It has a typical bias current of 1.3μA that
flows into the pin. The ADJ pin voltage is 1.20V referenced
to ground.
GND (Pins 4, 5 / 4, 5 / 3 / 3): Ground. For the adjustable
LT1965, connect the bottom of the resistor divider, setting
output voltage, directly to GND for optimum regulation.
SHDN (Pin 6 / 6 / 1 / 1): Shutdown. Pulling the SHDN pin
low puts the LT1965 into a low power state and turns the
output off. Drive the SHDN pin with either logic or an open
collector/drain with a pull-up resistor. The resistor sup-
plies the pull-up current to the open collector/drain logic,
normallyseveralmicroamperesandtheSHDNpincurrent,
typically less than 6μA. If unused, connect the SHDN pin
Exposed Pad (Pin 9 / 9, DFN and MSOP Packages Only):
Ground. Tie this pin directly to Pins 4 and 5 and the PCB
ground. This pin provides enhanced thermal performance
with its connection to the PCB ground. See the Applica-
tions Information section for thermal considerations and
to V . The LT1965 will be in its low power shutdown state
IN
if the SHDN pin is not connected. The SHDN pin cannot
calculating junction temperature.
1965f
7
LT1965
APPLICATIONS INFORMATION
The LT1965 is a 1.1A low dropout regulator with shut-
down. The device is capable of supplying 1.1A at a typical
dropout voltage of 290mV. The low operating quiescent
current (500μA) drops to less than 1μA in shutdown. In
addition to its low quiescent current, the LT1965 regulator
incorporates several protection features that make it ideal
for use in battery-powered systems. The device protects
itself against both reverse input and reverse output volt-
ages. In battery backup applications, if a backup battery
holds up the output when the input is pulled to ground,
the LT1965 performs like it has a diode in series with its
output, preventing reverse current flow. Also, in dual sup-
ply applications where the regulator load is returned to a
negative supply, the output can be pulled below ground
by as much as 20V. The LT1965 still starts and operates
normally in this situation.
The adjustable device is tested and specified with the ADJ
pin tied to the OUT pin for an output voltage of 1.20V.
Specifications for output voltages greater than 1.20V are
proportional to the ratio of the desired output voltage to
1.20V: V /1.20V. For example, load regulation for an
OUT
outputcurrentchangeof1mAto1.1Aistypically–4.25mV
at V
= 1.20V. At V
= 5V, load regulation is:
OUT
OUT
5V
1.20V
• –4.25mV = –17.71mV
Output Capacitance
The LT1965’s design is stable with a wide range of out-
put capacitors. The ESR of the output capacitor affects
stability, most notably with small capacitors. A minimum
output capacitor of 10μF with an ESR of 3Ω or less is
recommended to prevent oscillations. The LT1965 is a
low quiescent current device and output load transient
responseisafunctionofoutputcapacitance.Largervalues
of output capacitance decrease the peak deviations and
provide improved transient response for larger current
changes.
Adjustable Operation
The LT1965 has an output voltage range of 1.20V to 20V.
Figure 1 illustrates that the ratio of two external resistors
sets the output voltage. The device servos the output to
maintaintheADJpinvoltageat1.20Vreferencedtoground.
R1’s current equals 1.20V/R1. R2’s current equals R1’s
current plus the ADJ pin bias current. The ADJ pin bias
current, 1.3μA at 25°C, flows through R2 into the ADJ pin.
Use the formula in Figure 1 to calculate output voltage.
Linear Technology recommends that R1’s value be less
than 12.1k to minimize output voltage errors due to the
ADJ pin bias current. In shutdown, the output turns off
and the divider current is zero. For curves depicting ADJ
Pin Voltage vs Temperature and ADJ Pin Bias Current vs
Temperature, see the Typical Performance Characteristics
section.
Ceramic capacitors require extra consideration. Manufac-
turersmakeceramiccapacitorswithavarietyofdielectrics,
eachwithdifferentbehavioracrosstemperatureandapplied
voltage. The most common dielectrics used are specified
with EIA temperature characteristic codes of Z5U, Y5V,
X5R and X7R. The Z5U and Y5V dielectrics provide high
C-V products in a small package at low cost, but exhibit
strong voltage and temperature coefficients as shown in
Figures 2 and 3. When used with a 5V regulator, a 16V
10μF Y5V capacitor can exhibit an effective value as low
as 1μF to 2μF for the DC bias applied and over the operat-
ing temperature range. The X5R and X7R dielectrics yield
much more stable characteristics and are more suitable
for use as the output capacitor. The X7R type works over
a wider temperature range and has better temperature
stability whereas X5R is less expensive and is available in
highervalues.CarestillmustbeexercisedwhenusingX5R
and X7R capacitors; the X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
R2
⎠
R1
⎛
⎝
⎞
IN
OUT
LT1965
V
VOUT = 1.20V 1+
+IADJ •R2
⎟
OUT
⎜
+
V
R2
R1
IN
V
ADJ = 1.20V
ADJ = 1.3µA AT 25ºC
OUTPUT RANGE = 1.20V TO 19.5V
ADJ
I
GND
1965 F01
Figure 1. Adjustable Operation
Z5U capacitors, but can still be significant enough to drop
1965f
8
LT1965
APPLICATIONS INFORMATION
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltages should be verified.
Overload Recovery
Like many IC power regulators, the LT1965 has safe oper-
ating area protection. The safe area protection decreases
currentlimitasinput-to-outputvoltageincreasesandkeeps
the power transistor inside a safe operating region for all
values of input-to-output voltage. The protective design
provides some output current at all values of input-to-
output voltage up to the device breakdown.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise. A ceramic capacitor produced the trace
in Figure 4 in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
When power is first applied, as input voltage rises, the
output follows the input, allowing the regulator to start up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowingtheregulatortosupplylargeoutputcurrents.With
ahighinputvoltage, aproblemcanoccurwhereinremoval
of an output short will not allow the output to recover.
20
40
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
X5R
X5R
0
–20
–20
–40
–40
Y5V
–60
–60
Y5V
–80
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
–100
0
8
12 14
2
4
6
10
16
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
DC BIAS VOLTAGE (V)
1965 F02
1965 F03
Figure 2. Ceramic Capacitor DC Bias Characteristics
Figure 3. Ceramic Capacitor Temperature Characteristics
1mV/DIV
1965 F04
1ms/DIV
V
C
LOAD
= 1.3V
= 10μF
= 0
OUT
OUT
I
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
1965f
9
LT1965
APPLICATIONS INFORMATION
Other regulators, such as the LT1083/LT1084/LT1085
family, also exhibit this phenomenon, so it is not unique
to the LT1965.
Thermal Considerations
The LT1965’s maximum rated junction temperature of
125°C limits its power handling capability. Two compon-
ents comprise the power dissipated by the device:
The problem occurs with a heavy output load when the
input voltage is high and the output voltage is low. Com-
mon situations include immediately after the removal of a
short-circuit or if the shutdown pin is pulled high after the
input voltage has already been turned on. The load line for
such a load may intersect the output current curve at two
points.Ifthishappens,therearetwostableoutputoperating
points for the regulator. With this double intersection, the
input power supply may need to be cycled down to zero
and brought up again to make the output recover.
1. Output current multiplied by the input/output voltage
differential: I
• (V – V ), and
OUT
IN OUT
2. GND pin current multiplied by the input voltage:
• V
I
GND
IN
GND pin current is determined using the GND Pin Current
curvesintheTypicalPerformanceCharacteristicssection.
Power dissipation equals the sum of the two components
listed.
The LT1965 regulator has internal thermal limiting that
protects the device during overload conditions. For con-
tinuous normal conditions, do not exceed the maximum
junction temperature rating of 125°C. Carefully consider
all sources of thermal resistance from junction to ambi-
ent including other heat sources mounted in proximity to
the LT1965.
Output Voltage Noise
TheLT1965regulator’sdesignprovideslowoutputvoltage
noise over the 10Hz to 100kHz bandwidth while operating
atfullload.Outputvoltagenoiseisapproximately80nV/√Hz
over this frequency bandwidth for the LT1965. For higher
output voltages (generated by using a resistor divider),
the output voltage noise gains up accordingly.
The underside of the LT1965 DFN package has exposed
Higher values of output voltage noise may be measured
if care is not exercised with regard to circuit layout and
testing.Crosstalkfromnearbytracescaninduceunwanted
noiseontotheLT1965’soutput. Powersupplyripplerejec-
tion must also be considered; the LT1965 regulator does
not have unlimited power supply rejection and will pass a
small portion of the input noise through to the output.
2
metal (4mm ) from the lead frame to the die attachment.
The underside of the LT1965 MSOP package also has ex-
2
posed metal (2mm ). Both packages allow heat to directly
transfer from the die junction to the printed circuit board
metaltocontrolmaximumoperatingjunctiontemperature.
The dual-in-line pin arrangement allows metal to extend
beyondtheendsofthepackageonthetopside(component
side) of a PCB. Connect this metal to GND on the PCB.
The multiple IN and OUT pins of the LT1965 also assist
in spreading heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
1965f
10
LT1965
APPLICATIONS INFORMATION
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 1/16" FR-4 board with one ounce
copper.
Calculating Junction Temperature
Example:Givenanoutputvoltageof2.5V, aninputvoltage
range of 3.3V 5%, an output current range of 0mA to
500mA and a maximum ambient temperature of 85°C,
what will the maximum junction temperature be?
Table 1. Measured Thermal Resistance for DFN Package
Copper Area
Topside* Backside
Thermal Resistance
The power dissipated by the device equals:
Board Area (Junction-to-Ambient)
2
2
2
2
2
2
2
2500mm
1000mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
60°C/W
62°C/W
65°C/W
68°C/W
70°C/W
I
• (V
– V ) + I
• V
OUT(MAX)
IN(MAX)
OUT
GND IN(MAX)
2
2
2
2
2
2
where:
225mm
100mm
2
I
= 500mA
= 3.465V
OUT(MAX)
2
50mm
V
*Device is mounted on topside
IN(MAX)
I
at (I = 500mA, V = 3.465V) = 8.2mA
OUT IN
GND
Table 2. Measured Thermal Resistance for MSOP Package
Copper Area
Topside* Backside
Thermal Resistance
So,
Board Area (Junction-to-Ambient)
P = 500mA(3.465V – 2.5V) + 8.2mA(3.465V) = 0.511W
2
2
2
2
2
2
2
2500mm
1000mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
55°C/W
57°C/W
60°C/W
65°C/W
68°C/W
2
2
2
2
2
Using a DFN package, the thermal resistance will be in
the range of 60°C/W to 70°C/W depending on the cop-
per area. So the junction temperature rise above ambient
approximately equals:
2
225mm
100mm
2
2
50mm
*Device is mounted on topside
0.511W • 65°C/W = 33.22°C
Table 3. Measured Thermal Resistance for DD-PAK Package
The maximum junction temperature equals the maximum
ambienttemperatureplusthemaximumjunctiontempera-
ture rise above ambient or:
Copper Area
Topside* Backside
Thermal Resistance
Board Area (Junction-to-Ambient)
2
2
2
2
2
2500mm
1000mm
125mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
25°C/W
30°C/W
35°C/W
2
2
2
T
= 85°C + 33.22°C = 118.22°C
JMAX
2
*Device is mounted on topside
Measured Thermal Resistance for TO-220 Package
Thermal Resistance (Junction-to-Case) = 3°C/W
1965f
11
LT1965
APPLICATIONS INFORMATION
Protection Features
TheLT1965incursnodamageiftheADJpinispulledabove
or below ground by 9V. If the input is left open circuit or
grounded, the ADJ pin performs like an open circuit when
pulled below ground and like a large resistor (typically 5k
up to 3V on the ADJ pin and then 1.5k up to 9V) in series
with a diode when pulled above ground.
The LT1965 incorporates several protection features
that make it ideal for use in battery-powered circuits.
In addition to the normal protection features associated
with monolithic regulators, such as current limiting and
thermal limiting, the device also protects against reverse
input voltages, reverse output voltages and reverse out-
put-to-input voltages.
In situations where the ADJ pin connects to a resistor
dividerthatwouldpulltheADJpinaboveits9Vclampvolt-
age if the output is pulled high, the ADJ pin input current
must be limited to less than 5mA. For example, a resistor
divider is used to provide a regulated 1.5V output from the
1.20V reference when the output is forced to 20V. The top
resistor of the resistor divider must be chosen to limit the
current into the ADJ pin to less than 5mA when the ADJ
pin is at 9V. The 11V difference between the OUT and ADJ
pins divided by the 5mA maximum current into the ADJ
pin yields a minimum top resistor value of 2.2k.
Current limit protection and thermal overload protection
protect the device against current overload conditions
at its output. For normal operation, do not exceed the
maximum rated junction temperature of 125°C.
Theinputofthedevicewithstandsreversevoltagesof22V.
The LT1965 limits current flow to less than 1mA (typically
less than 200μA) and no negative voltage appears at the
output.Thedeviceprotectsbothitselfandtheloadagainst
batteries that are plugged in backwards.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled
to ground, pulled to some intermediate voltage, or is left
open circuit. Current flow back into the output follows the
curve shown in Figure 5.
The LT1965 incurs no damage if its output is pulled below
ground. If the input is left open circuit or grounded, the
output can be pulled below ground by 22V. For the adjust-
able version, the output acts like an open circuit and no
current flows from the output. However, current flows in
(but is limited by) the resistor divider that sets the output
voltage. If the input is powered by a voltage source, the
output sources current equal to its current limit capability
and the LT1965 protects itself by thermal limiting. In this
case, grounding the SHDN pin turns off the device and
stops the output from sourcing current.
If the LT1965’s IN pin is forced below the OUT pin or the
OUT pin is pulled above the IN pin, input current typically
drops to less than 2μA. This occurs if the LT1965 input is
connected to a discharged (low voltage) battery and either
abackupbatteryorasecondregulatorholdsuptheoutput.
The state of the SHDN pin has no effect on the reverse
output current if the output is pulled above the input.
6
T
= 25°C
IN
J
V
= 0V
5
CURRENT FLOWS INTO
OUTPUT PIN
V
= V
OUT
ADJ
4
3
2
1
0
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
1965 F05
Figure 5. Reverse Output Current
1965f
12
LT1965
TYPICAL APPLICATIONS
Paralleling of Regulators for Higher Output Current
R1
0.01Ωꢀ
3.3V
2.2A
IN
OUT
ADJ
R8
6.98k
1%
+
+
C1
100μF
LT1965
SHDN
GND
C2
V
> 3.7V
IN
22μF
R9
4.02k
1%
R2
0.01Ωꢀ
IN
OUT
ADJ
R6
6.65k
1%
LT1965
SHDN
SHDN
R7
4.02k
1%
GND
R3
2.2k
R4
2.2k
R5
10k
8
3
2
+
–
1
1/2
LT1366
C3
0.01μF
4
1965 TA03
1965f
13
LT1965
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 ± 0.10
TYP
5
8
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1203
4
1
0.25 ± 0.05
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
MS8E Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1662)
BOTTOM VIEW OF
EXPOSED PAD OPTION
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.0205)
REF
2.06 ± 0.102
(.081 ± .004)
0.889 ± 0.127
(.035 ± .005)
2.794 ± 0.102
(.110 ± .004)
1
8
7 6 5
1.83 ± 0.102
(.072 ± .004)
5.23
(.206)
MIN
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
3.20 – 3.45
(.126 – .136)
4.90 ± 0.152
(.193 ± .006)
2.083 ± 0.102
(.082 ± .004)
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
8
1
2
3
4
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
DETAIL “A”
0.254
0.18
(.007)
(.010)
0° – 6° TYP
SEATING
PLANE
GAUGE
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.65
(.0256)
BSC
0.53 ± 0.152
(.021 ± .006)
MSOP (MS8E) 0603
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR
GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.152mm (.006") PER SIDE
1965f
14
LT1965
PACKAGE DESCRIPTION
Q Package
5-Lead Plastic DD Pak
(Reference LTC DWG # 05-08-1461)
.390 – .415
(9.906 – 10.541)
.060
.256
.165 – .180
(4.191 – 4.572)
(1.524)
(6.502)
.045 – .055
(1.143 – 1.397)
15° TYP
+.008
.004
.060
(1.524)
TYP
–.004
.060
.059
(1.499)
TYP
.183
(1.524)
(4.648)
+0.203
–0.102
.330 – .370
0.102
(
)
(8.382 – 9.398)
.095 – .115
(2.413 – 2.921)
.075
(1.905)
.067
(1.702)
BSC
.050 ± .012
(1.270 ± 0.305)
.300
(7.620)
.013 – .023
(0.330 – 0.584)
+.012
.143
–.020
.028 – .038
(0.711 – 0.965)
TYP
+0.305
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
3.632
Q(DD5) 0502
(
)
–0.508
.080
.420
.276
.420
.350
.090
.325
.205
.565
.565
.320
.090
.042
.067
.042
RECOMMENDED SOLDER PAD LAYOUT
.067
NOTE:
1. DIMENSIONS IN INCH/
(MILLIMETER)
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
2. DRAWING NOT TO SCALE
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1420)
.165 – .180
(4.191 – 4.572)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.045 – .055
(1.143 – 1.397)
.230 – .270
(5.842 – 6.858)
.570 – .620
(14.478 – 15.748)
.620
(15.75)
TYP
.460 – .500
(11.684 – 12.700)
.330 – .370
(8.382 – 9.398)
.700 – .728
(17.78 – 18.491)
.095 – .115
(2.413 – 2.921)
SEATING PLANE
.152 – .202
(3.861 – 5.131)
.155 – .195*
(3.937 – 4.953)
.260 – .320
(6.60 – 8.13)
.013 – .023
(0.330 – 0.584)
.067
BSC
.135 – .165
(3.429 – 4.191)
.028 – .038
(0.711 – 0.965)
(1.70)
* MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801
1965f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT1965
TYPICAL APPLICATION
Adjustable Current Source
R5, 0.01Ω
LT1965
LOAD
IN
OUT
R1
1k
+
+
C1
10μF
C4
10μF
SHDN
GND
ADJ
V
> 2.7V
IN
LT1004-1.2
R4
R6
R8
100k
R2
80.6k
C3
1μF
2.2k 2.2k
R3
2k
R7
470Ω
2
8
–
1
1/2
LT1366
1965 TA04
3
+
4
C2
3.3μF
NOTE: ADJUST R1 FOR
0A TO 1.1A CONSTANT-CURRENT
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1129
700mA, Micropower, LDO
V : 4.2V to 30V, V
= 3.8V, V = 0.40V, I = 50μA, I = 16μA;
IN
OUT(MIN) DO Q SD
DD, SOT-223, S8, TO220-5 and TSSOP20 Packages
LT1761
LT1762
LT1763
100mA, Low Noise Micropower, LDO
150mA, Low Noise Micropower, LDO
500mA, Low Noise Micropower, LDO
V : 1.8V to 20V, V = 1.22V, V = 0.30V, I = 20μA, I = < 1μA,
IN
OUT(MIN)
DO
Q
SD
Low Noise < 20μV
, Stable with 1μF Ceramic Capacitors, ThinSOT™ Package
RMS
V : 1.8V to 20V, V
= 1.22V, V = 0.30V, I = 25μA, I = < 1μA,
DO Q SD
IN
OUT(MIN)
Low Noise < 20μV
, MS8 Package
RMS
V : 1.8V to 20V, V
= 1.22V, V = 0.30V, I = 30μA, I = < 1μA,
DO Q SD
IN
OUT(MIN)
Low Noise < 20μV
, S8 Package
RMS
LT1764/LT1764A 3A, Low Noise, Fast Transient Response,
LDO
V : 2.7V to 20V, V
= 1.21V, V = 0.34V, I = 1mA, I = < 1μA, Low Noise
IN
OUT(MIN) DO Q SD
< 40μV
, “A” Version Stable with Ceramic Capacitors, DD and TO220-5 Packages
RMS
LTC1844
150mA, Very Low Drop-Out LDO
V : 1.6V to 6.5V, V
= 1.25V, V = 0.08V, I = 35μA, I = < 1μA,
IN
OUT(MIN) DO Q SD
Low Noise < 60μV
, ThinSOT™ Package
RMS
LT1962
300mA, Low Noise Micropower, LDO
V : 1.8V to 20V, V
= 1.22V, V = 0.27V, I = 30μA, I = < 1μA,
IN
OUT(MIN) DO Q SD
Low Noise < 20μV
, MS8 Package
RMS
LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, V : 2.1V to 20V, V
= 1.21V, V = 0.34V, I = 1mA, I = < 1μA,
DO Q SD
IN
OUT(MIN)
LDO
Low Noise < 40μV
, “A” Version Stable with Ceramic Capacitors;
RMS
DD, TO220-5, SOT-223 and S8 Packages
LT3020
LT3021
LT3023
LT3024
LT3027
LT3028
100mA, Low Voltage V , V
= 0.9V, V : 0.9V to 10V, V
= 0.20V, V = 0.15V, I = 120μA, I = 3μA, DFN and
DO Q SD
DO IN(MIN)
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
LDO
MS8 Packages
500mA, Low Voltage V , V
= 0.9V, V : 0.9V to 10V, V
= 0.20V, V = 0.16V, I = 120μA, I = 3μA, DFN and
DO Q SD
DO IN(MIN)
IN
LDO
S8 Packages
Dual, 2x 100mA, Low Noise Micropower,
LDO
V : 1.8V to 20V, V
= 1.22V, V = 0.30V, I = 40μA, I = < 1μA, DFN and
DO Q SD
IN
MS10 Packages
Dual, 100mA/500mA, Low Noise
Micropower, LDO
V : 1.8V to 20V, V
= 1.22V, V = 0.30V, I = 60μA, I = < 1μA, DFN and
DO Q SD
IN
TSSOP Packages
Dual, 2x 100mA, Low Noise Micropower,
LDO with Independent Inputs
V : 1.8V to 20V, V
= 1.22V, V = 0.30V, I = 25μA, I = < 1μA,
DO Q SD
, DFN and MS10 Packages
IN
Low Noise < 20μV
RMS
Dual, 100mA/500mA, Low Noise
Micropower, LDO with Independent Inputs Low Noise < 20μV
V : 1.8V to 20V, V
= 1.22V, V = 0.30V, I = 30μA, I = < 1μA,
, DFN and TSSOP Packages
IN
OUT(MIN) DO Q SD
RMS
ThinSOT is a trademark of Linear Technology Corporation
1965f
LT 0807 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
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(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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