LT1766EGN-5-TR_技术文档

LT1766/LT1766-5

5.5V to 60V 1.5A, 200kHz

Step-Down Switching Regulator

FEATURES

DESCRIPTION

TheLT^®1766/LT1766-5are200kHzmonolithicbuckswitch-

ing regulators that accept input voltages up to 60V. A high

efﬁciency 1.5A, 0.2Ω switch is included on the die along

withallthenecessaryoscillator, controlandlogiccircuitry.

A current mode control architecture delivers fast transient

response and excellent loop stability.

n

Wide Input Range: 5.5V to 60V

n

1.5A Peak Switch Current

n

Constant 200kHz Switching Frequency

n

Saturating Switch Design: 0.2Ω

n

Peak Switch Current Rating Maintained Over

Full Duty Cycle Range

n

Low Effective Supply Current: 2.5mA

Special design techniques and a new high voltage process

achieve high efﬁciency over a wide input range. Efﬁciency

ismaintainedoverawideoutputcurrentrangebyusingthe

output to bias the circuitry and by utilizing a supply boost

capacitor to saturate the power switch. Patented circuitry

maintainspeakswitchcurrentoverthefulldutycyclerange.

A shutdown pin reduces supply current to 25μA and the

device can be externally synchronized from 228kHz to

700kHz with logic-level inputs.

n

Low Shutdown Current: 25μA

n

1.2V Feedback Reference Voltage (LT1766)

n

5V Fixed Output (LT1766-5)

n

Easily Synchronizable

n

Cycle-by-Cycle Current Limiting

n

Small 16-Pin SSOP and Thermally Enhanced

TSSOP Packages

APPLICATIONS

The LT1766/LT1766-5 are available in a 16-pin fused-lead

SSOPpackageoraTSSOPpackagewithexposedbackside

for improved thermal performance.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 6498466, 6531909.

n

High Voltage, Industrial and Automotive

n

Portable Computers

n

Battery-Powered Systems

n

Battery Chargers

n

Distributed Power Systems

TYPICAL APPLICATION

5V Buck Converter

1N4148W

Efﬁciency vs Load Current

6

0.33μF

100

90

80

70

60

50

BOOST

47μH

V

= 5V

V

5V

1A

OUT

4

2

V

*

IN

L = 47μH

V

SW

V

= 12V

= 42V

IN

2.2μF^†

5.5V TO 60V

10MQ060N

100V

LT1766

+

100μF 10V

SOLID

TANTALUM

CERAMIC

15

14

10

12

SHDN

BIAS

FB

OFF ON

15.4k

4.99k

SYNC

GND

V

C

1, 8, 9, 16 11

220pF

2.2k

0.022μF

0

0.25

0.50

0.75

1.00

1.25

LOAD CURRENT (A)

1766 TA01

1766 TA02

*FOR INPUT VOLTAGES BELOW 7.5V, SOME RESTRICTIONS MAY APPLY

^†TDK C4532X7R2A225K

1766fc

1

LT1766/LT1766-5

ABSOLUTE MAXIMUM RATINGS

(Note 1)

Operating Junction Temperature Range

Input Voltage (V ) .................................................. 60V

IN

LT1766EFE/LT1766EFE-5/LT1766EGN/

BOOST Pin Above SW.............................................. 35V

BOOST Pin Voltage ................................................. 68V

SYNC, SENSE Voltage (LT1766-5) ............................. 7V

SHDN Voltage ............................................................ 6V

BIAS Pin Voltage ..................................................... 30V

FB Pin Voltage/Current (LT1766) ................... 3.5V/2mA

LT1766EGN-5 (Note 8,10)....................–40°C to 125°C

LT1766IFE/LT1766IFE-5/

LT1766IGN/LT1766IGN-5 (Note 8,10)..–40°C to 125°C

LT1766HFE ..........................................–40°C to 140°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

PIN CONFIGURATION

TOP VIEW

GND

SW

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

SW

NC

1

2

3

4

5

6

7

8

16 GND

SHDN

SYNC

NC

15 SHDN

14 SYNC

13 NC

V

IN

V

IN

17

GND

NC

BOOST

NC

FB/SENSE

NC

BOOST

NC

12 FB/SENSE

V

C

11

10 BIAS

GND

V

C

BIAS

GND

9

FE PACKAGE

16-LEAD PLASTIC TSSOP

GN PACKAGE

16-LEAD PLASTIC SSOP

θ

= 45°C, θ (PIN 17) = 10°C/W

θ

= 85°C, θ (PIN 8) = 25°C/W

JA JC

JA

JC

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

FOUR CORNER PINS SOLDERED TO GROUND PIN

1766fc

2

LT1766/LT1766-5

ORDER INFORMATION

LEAD FREE FINISH

LT1766EFE#PBF

LT1766IFE#PBF

LT1766HFE#PBF

LT1766EFE-5#PBF

LT1766IFE-5#PBF

LT1766EGN#PBF

LT1766IGN#PBF

LT1766EGN-5#PBF

LT1766IGN-5#PBF

LEAD BASED FINISH

LT1766EFE

TAPE AND REEL

LT1766EFE#TRPBF

LT1766IFE#TRPBF

LT1766HFE#TRPBF

LT1766EFE-5#TRPBF

LT1766IFE-5#TRPBF

LT1766EGN#TRPBF

LT1766IGN#TRPBF

LT1766EGN-5#TRPBF

LT1766IGN-5#TRPBF

TAPE AND REEL

LT1766EFE#TR

PART MARKING

1766EFE

1766IFE

1766HFE

1766EFE-5

1766IFE-5

1766

PACKAGE DESCRIPTION

16-Lead Plastic TSSOP

16-Lead Plastic SSOP

PACKAGE DESCRIPTION

16-Lead Plastic TSSOP

16-Lead Plastic SSOP

TEMPERATURE RANGE

0°C to 125°C

–40°C to 125°C

–40°C to 140°C

0°C to 125°C

–40°C to 125°C

0°C to 125°C

1766I

–40°C to 125°C

0°C to 125°C

17665

1766I5

–40°C to 125°C

TEMPERATURE RANGE

0°C to 125°C

PART MARKING

1766EFE

1766IFE

1766HFE

1766EFE-5

1766IFE-5

1766

LT1766IFE

LT1766IFE#TR

–40°C to 85°C

–40°C to 140°C

0°C to 125°C

LT1766HFE

LT1766HFE#TR

LT1766EFE-5

LT1766EFE-5#TR

LT1766IFE-5#TR

LT1766EGN#TR

LT1766IFE-5

–40°C to 125°C

0°C to 125°C

LT1766EGN

LT1766IGN

LT1766IGN#TR

1766I

–40°C to 125°C

0°C to 125°C

LT1766EGN-5

LT1766EGN-5#TR

LT1766IGN-5#TR

17665

LT1766IGN-5

1766I5

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^{(LT1766E/LT1766I Grade)}

The l denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_J= 25°C.

V_IN= 15V, VC = 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER

CONDITIONS

5.5V ≤ V ≤ 60V

MIN

TYP

MAX

UNITS

Reference Voltage (V ) (LT1766)

1.204

1.195

1.219

1.234

1.243

V

REF

IN

l

V

+ 0.2 ≤ V ≤ V – 0.2

C OH

OL

SENSE Voltage (LT1766-5)

5.5V ≤ V ≤ 60V

4.94

4.90

5

5.06

5.10

V

IN

V

OL

+ 0.2V ≤ V ≤ V – 0.2V

C OH

SENSE Pin Resistance (LT1766-5)

FB Input Bias Current (LT1766)

Error Amp Voltage Gain

9.5

13.8

–0.5

400

19

kΩ

μA

l

–1.5

(Notes 2, 9)

dl (V ) = 10μA (Note 9)

200

V/V

Error Amp g

1500

1000

2000

3000

4200

μMho

m

C

V to Switch g

1.7

225

0.9

2.1

2

A/V

μA

V

C

m

l

EA Source Current

EA Sink Current

FB = 1V or V

= 4.1V

125

100

400

450

SENSE

FB = 1.4V or V

Duty Cycle = 0

SHDN = 1V

= 5.7V

SENSE

V Switching Threshold

C

V High Clamp

C

V

l

Switch Current Limit

V Open, Boost = V + 5V, FB = 1V or V = 4.1V

C SENSE

1.5

3

A

IN

1766fc

3

LT1766/LT1766-5

ELECTRICAL CHARACTERISTICS ^{(LT1766E/LT1766I Grade)}

The l denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_J= 25°C.

V_IN= 15V, V_C= 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER

CONDITIONS

= 1.5A, Boost = V + 5V (Note 7)

MIN

TYP

MAX

UNITS

Switch On-Resistance

I

SW

0.2

0.3

0.4

Ω

IN

l

Maximum Switch Duty Cycle

Switch Frequency

FB = 1V or V

= 4.1V

93

90

96

%

SENSE

V Set to Give DC = 50%

C

184

172

200

216

228

kHz

l

f

Line Regulation

5.5V ≤ V ≤ 60V

0.05

0.8

4.6

1.8

0.15

%/V

V

SW

IN

Frequency Shifting Threshold

Df = 10kHz

(Note 3)

SW

l

Minimum Input Voltage

Minimum Boost Voltage

Boost Current (Note 5)

5.5

3

V

(Note 4) I ≤ 1.5A

V

SW

l

Boost = V + 5V, I = 0.5A

12

45

25

70

mA

IN

SW

Boost = V + 5V, I = 1.5A

IN

SW

Input Supply Current (I

)

(Note 6) V

= 5V

1.4

2.9

25

2.2

4.2

mA

VIN

BIAS

Bias Supply Current (I

(Note 6) V

= 5V

BIAS

Shutdown Supply Current

SHDN = 0V, V ≤ 60V, SW = 0V, V Open

75

200

μA

IN

C

l

Lockout Threshold

V Open

C

2.3

2.42

2.53

V

l

Shutdown Thresholds

V Open, Shutting Down

C

0.15

0.25

0.37

0.45

0.6

V

C

V Open, Starting Up

l

Minimum SYNC Amplitude

SYNC Frequency Range

SYNC Input Resistance

1.5

2.2

V

kHz

kΩ

228

700

20

(LT1766H Grade)

The l denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_J= 25°C.

V_IN= 15V, V_C= 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER

CONDITIONS

5.5V ≤ V ≤ 60V

MIN

TYP

MAX

UNITS

Reference Voltage (V

)

REF

1.204

1.175

1.219

1.234

1.265

V

IN

l

V

+ 0.2 ≤ V ≤ V – 0.2

C OH

OL

FB Input Bias Current

–0.5

400

–1.5

μA

Error Amp Voltage Gain

(Notes 2, 9)

dl (V ) = 10μA (Note 9)

200

V/V

Error Amp g

1500

900

2000

3000

4200

μMho

m

C

l

V to Switch g

1.7

225

0.9

2.1

2

A/V

μA

V

C

m

l

EA Source Current

EA Sink Current

FB = 1V or V

= 4.1V

125

100

400

450

SENSE

FB = 1.4V or V

Duty Cycle = 0

SHDN = 1V

= 5.7V

SENSE

V Switching Threshold

C

V High Clamp

C

V

l

Switch Current Limit

Switch On Resistance

V Open, Boost = V + 5V, FB = 1V or V

C

= 4.1V

0.75

3

A

IN

SENSE

I

SW

= 0.75A, Boost = V + 5V (Note 7)

0.2

0.3

0.8

Ω

IN

Maximum Switch Duty Cycle

Switch Frequency

FB = 1V or V

= 4.1V

93

90

96

%

SENSE

V Set to Give DC = 50%

C

184

135

200

216

228

kHz

1766fc

4

LT1766/LT1766-5

ELECTRICAL CHARACTERISTICS ^{(LT1766H Grade)}

The ^ldenotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_J= 25°C.

V_IN= 15V, V_C= 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

0.05

0.8

MAX

UNITS

l

f

SW

f

SW

Line Regulation

5.5V ≤ V ≤ 60V

0.15

%/V

V

IN

Frequency Shifting Threshold

Df = 10kHz

(Note 3)

l

Minimum Input Voltage

Minimum Boost Voltage

Boost Current (Note 5)

4.6

5.5

3

V

(Note 4) I ≤ 0.75A

1.8

V

SW

l

Boost = V + 5V, I = 0.5A

12

45

40

100

mA

IN

SW

Boost = V + 5V, I = 0.75A

IN

Input Supply Current (I

)

(Note 6) V

= 5V

1.4

2.9

25

2.2

4.2

mA

VIN

BIAS

Bias Supply Current (I

(Note 6) V

= 5V

BIAS

Shutdown Supply Current

SHDN = 0V, V ≤ 60V, SW = 0V, V Open

120

500

μA

IN

C

l

Lockout Threshold

V Open

C

2.3

2.42

2.68

V

l

Shutdown Thresholds

V Open, Shutting Down

C

0.15

0.25

0.37

0.45

0.9

V

C

V Open, Starting Up

l

Minimum SYNC Amplitude

SYNC Frequency Range

SYNC Input Resistance

1.5

2.2

V

kHz

kΩ

228

700

20

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 7: Switch on-resistance is calculated by dividing V to SW voltage

by the forced current. See Typical Performance Characteristics for the

graph of switch voltage at other currents.

IN

Note 8: The LT1766EGN, LT1766EGN-5, LT1766EFE and LT1766EFE-5

are guaranteed to meet performance speciﬁcations from 0°C to 125°C

junction temperature. Speciﬁcations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LT1766IGN, LT1766IGN-5,

LT1766IFE and LT1766IFE-5 are guaranteed over the full –40°C to 125°C

operating junction temperature range. The LT1766HGN and LT1766HFE are

guaranteed over the full –40°C to 140°C operating junction temperature

range.

Note 2: Gain is measured with a V swing equal to 200mV above the low

C

clamp level to 200mV below the upper clamp level.

Note 3: Minimum input voltage is not measured directly, but is guaranteed

by other tests. It is deﬁned as the voltage where internal bias lines are still

regulated so that the reference voltage and oscillator remain constant.

Actual minimum input voltage to maintain a regulated output will depend

upon output voltage and load current. See Applications Information.

Note 4: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 5: Boost current is the current ﬂowing into the BOOST pin with the

pin held 5V above input voltage. It ﬂows only during switch on time.

Note 6: Input supply current is the quiescent current drawn by the input

pin when the BIAS pin is held at 5V with switching disabled. Bias supply

current is the current drawn by the BIAS pin when the BIAS pin is held

at 5V. Total input referred supply current is calculated by summing input

Note 9: Transconductance and voltage gain refer to the internal ampliﬁer

exclusive of the voltage divider. To calculate gain and transconductance,

refer to the SENSE pin on ﬁxed voltage parts. Divide the values shown by

the ratio V /1.219.

OUT

Note 10: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 140°C when overtemperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

Note 11: High junction temperatures degrade operating lifetimes.

Operating lifetime at junction temperatures between 125°C and 140°C is

derated to 1000 hours.

supply current (I ) with a fraction of bias supply current (I

):

BIAS

VIN

I

= I + (I

)(V /V )

BIAS OUT IN

TOTAL

VIN

with V = 15V, V

= 5V, I = 1.4mA, I

= 2.9mA, I

= 2.4mA.

IN

OUT

VIN

BIAS

TOTAL

1766fc

5

LT1766/LT1766-5

TYPICAL PERFORMANCE CHARACTERISTICS

Switch Peak Current Limit

FB Pin Voltage and Current

SHDN Pin Bias Current

1.234

1.229

1.224

1.219

2.0

1.5

250

200

150

100

12

2.5

2.0

1.5

1.0

T

= 25°C

A

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

CURRENT DROPS TO A FEW μA

TYPICAL

VOLTAGE

CURRENT

1.0

0.5

0

GUARANTEED MINIMUM

1.214

1.209

1.204

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

6

0

20

40

60

80

100

50

100 125 150

50

100 125 150

75

–50 –25

0

25

75

–50 –25

0

25

DUTY CYCLE (%)

JUNCTION TEMPERATURE (°C)

1766 G01

1766 G02

1766 G03

Lockout and Shutdown

Thresholds

Shutdown Supply Current

300

250

2.4

40

35

30

25

20

15

10

5

T

= 25°C

A

V

A

= 0V

SHDN

T

= 25°C

LOCKOUT

2.0

1.6

1.2

0.8

0.4

0

V

= 60V

IN

200

150

V

IN

= 15V

100

50

0

START-UP

SHUTDOWN

0

–25

0

25

50

75

100

125 150

0

10

20

30

40

50

60

0

0.1

0.2

0.3

0.4

0.5

–50

SHUTDOWN VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

INPUT VOLTAGE (V)

1766 G06

1766 G04

1766 G05

Error Ampliﬁer Transconductance

Frequency Foldback

3000

2500

2000

1500

1000

500

200

150

100

50

600

500

2500

2000

1500

1000

500

T

A

= 25°C

T

= 25°C

A

PHASE

400

300

200

100

GAIN

V

C

SWITCHING

FREQUENCY

C

OUT

12pF

R

OUT

200k

–3

V

2 • 10

(

)

FB

ERROR AMPLIFIER EQUIVALENT CIRCUIT

= 50Ω

0

FB PIN

CURRENT

R

LOAD

–50

0

100

1k

10k

100k

1M

10M

–50

–25

0

25

50

75

100

125 150

0

0.5

1.0

1.5

FREQUENCY (Hz)

JUNCTION TEMPERATURE (°C)

V

FB

(V)

1766 G08

1766 G07

1766 G09

1766fc

6

LT1766/LT1766-5

TYPICAL PERFORMANCE CHARACTERISTICS

Minimum Input Voltage with 5V

Output

Switching Frequency

BOOST Pin Current

230

220

210

200

190

180

170

7.5

7.0

6.5

6.0

5.5

5.0

45

T

= 25°C

T

= 25°C

A

40

35

30

25

20

15

10

5

MINIMUM INPUT

VOLTAGE TO START

MINIMUM INPUT

VOLTAGE TO RUN

0

–50

–25

0

25

50

75

100 125 150

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

LOAD CURRENT (A)

1

0

0.5

1

1.5

JUNCTION TEMPERATURE (°C)

SWITCH CURRENT (A)

1766 G10

1766 G11

1766 G12

Switch Minimum On-Time

vs Temperature

V_CPin Shutdown Threshold

Switch Voltage Drop

2.1

1.9

600

500

400

300

450

400

350

300

250

200

150

100

50

T

= 150°C

J

1.7

1.5

1.3

1.1

0.9

T

J

= 125°C

T

J

= 25°C

200

100

0

T

J

= –40°C

0.7

0

50

100 125 150

–50 –25

0

25

75

0

0.5

1

1.5

50

100 125 150

–50 –25

0

25

75

JUNCTION TEMPERATURE (°C)

SWITCH CURRENT (A)

JUNCTION TEMPERATURE (°C)

1766 G13

1766 G14

1766 G15

PIN FUNCTIONS

GND (Pins 1, 8, 9, 16, 17): The GND pin connections act

as the reference for the regulated output, so load regula-

tion will suffer if the ground end of the load is not at the

same voltage as the GND pins of the IC. This condition will

occur when load current or other currents ﬂow through

metal paths between the GND pins and the load ground.

Keep the paths between the GND pins and the load ground

short and use a ground plane when possible. The GND

pin also acts as a heat sink and should be soldered to a

large copper plane to reduce thermal resistance. For the

FE package, the exposed pad should be soldered to the

coppergroundplaneunderneaththedevice. (SeeApplica-

tions Information—Layout Considerations.)

SW (Pin 2): The switch pin is the emitter of the on-chip

power NPN switch. This pin is driven up to the input pin

voltage during switch on-time. Inductor current drives the

switch pin negative during switch off-time. Negative volt-

age is clamped with the external catch diode. Maximum

negative switch voltage allowed is –0.8V.

NC (Pins 3, 5, 7, 13): No Connection.

1766fc

7

LT1766/LT1766-5

PIN FUNCTIONS

V (Pin 4): This is the collector of the on-chip power NPN

FB/SENSE (Pin 12): The feedback pin is used to set the

outputvoltageusinganexternalvoltagedividerthatgener-

ates 1.22V at the pin for the desired output voltage. The

5V ﬁxed output voltage parts have the divider included on

the chip and the FB pin is used as a SENSE pin, connected

directly to the 5V output. Three additional functions are

performedbytheFBpin.Whenthepinvoltagedropsbelow

0.6V, switchcurrentlimitisreducedandtheexternalSYNC

function is disabled. Below 0.8V, switching frequency is

also reduced. See Feedback Pin Functions in Applications

Information for details.

IN

switch. V powers the internal control circuitry when a

IN

voltage on the BIAS pin is not present. High dI/dt edges

occur on this pin during switch turn on and off. Keep

the path short from the V pin through the input bypass

IN

capacitor, through the catch diode back to SW. All trace

inductanceonthispathwillcreateavoltagespikeatswitch

off, adding to the V voltage across the internal NPN.

CE

BOOST (Pin 6): The BOOST pin is used to provide a drive

voltage,higherthantheinputvoltage,totheinternalbipolar

NPN power switch. Without this added voltage, the typical

switch voltage loss would be about 1.5V. The additional

BOOST voltage allows the switch to saturate and voltage

loss approximates that of a 0.2Ω FET structure, but with

much smaller die area.

SYNC (Pin 14): The SYNC pin is used to synchronize the

internal oscillator to an external signal. It is directly logic

compatibleandcanbedrivenwithanysignalbetween10%

and 90% duty cycle. The synchronizing range is equal to

initial operating frequency up to 700kHz. See Synchroniz-

ing in Applications Information for details.

BIAS (Pin 10): The BIAS pin is used to improve efﬁciency

when operating at higher input voltages and light load cur-

rent. Connecting this pin to the regulated output voltage

forces most of the internal circuitry to draw its operating

currentfromtheoutputvoltageratherthantheinputsupply.

This architecture increases efﬁciency especially when the

input voltage is much higher than the output. Minimum

output voltage setting for this mode of operation is 3V.

SHDN (Pin 15): The SHDN pin is used to turn off the

regulator and to reduce input drain current to a few mi-

croamperes. This pin has two thresholds: one at 2.38V to

disable switching and a second at 0.4V to force complete

micropower shutdown. The 2.38V threshold functions

as an accurate undervoltage lockout (UVLO); sometimes

used to prevent the regulator from delivering power until

the input voltage has reached a predetermined level.

V (Pin 11) The V pin is the output of the error ampliﬁer

C

and the input of the peak switch current comparator. It is

normally used for frequency compensation, but can also

If the SHDN pin functions are not required, the pin can

either be left open (to allow an internal bias current to lift

the pin to a default high state) or be forced high to a level

not to exceed 6V.

serve as a current clamp or control loop override. V sits

C

at about 0.9V for light loads and 2.1V at maximum load.

It can be driven to ground to shut off the regulator, but if

driven high, current must be limited to 4mA.

BLOCK DIAGRAM

The LT1766 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

twofeedbackloopsthatcontrolthedutycycleofthepower

switch. In addition to the normal error ampliﬁer, there is a

current sense ampliﬁer that monitors switch current on a

cycle-by-cyclebasis.Aswitchcyclestartswithanoscillator

the comparator, the ﬂip-ﬂop is reset and the switch turns

off. Output voltage control is obtained by using the output

of the error ampliﬁer to set the switch current trip point.

This technique means that the error ampliﬁer commands

current to be delivered to the output rather than voltage.

A voltage fed system will have low phase shift up to the

resonant frequency of the inductor and output capacitor,

thenanabrupt180°shiftwilloccur.Thecurrentfedsystem

pulsewhichsetstheR ﬂip-ﬂoptoturntheswitchon.When

S

switch current reaches a level set by the inverting input of

1766fc

8

LT1766/LT1766-5

BLOCK DIAGRAM

will have 90° phase shift at a much lower frequency, but

will not have the additional 90° shift until well beyond

the LC resonant frequency. This makes it much easier to

frequency compensate the feedback loop and also gives

much quicker transient response.

output voltage). This will improve efﬁciency if the BIAS

pin voltage is lower than regulator input voltage.

High switch efﬁciency is attained by using the BOOST

pin to provide a voltage to the switch driver which is

higher than the input voltage, allowing switch to be satu-

rated. This boosted voltage is generated with an external

capacitoranddiode.Twocomparatorsareconnectedtothe

shutdownpin.Onehasa2.38Vthresholdforundervoltage

lockout and the second has a 0.4V threshold for complete

shutdown.

MostofthecircuitryoftheLT1766operatesfromaninternal

2.9V bias line. The bias regulator normally draws power

fromtheregulatorinputpin,butiftheBIASpinisconnected

to an external voltage higher than 3V, bias power will be

drawn from the external source (typically the regulated

V

4

IN

R

SENSE

LIMIT

–

+

2.9V BIAS

REGULATOR

INTERNAL

CC

BIAS

10

V

CURRENT

COMPARATOR

SLOPE COMP

∑

SYNC 14

BOOST

6

ANTISLOPE COMP

SHUTDOWN

COMPARATOR

200kHz

OSCILLATOR

–

+

S

Q1

POWER

SWITCH

R

DRIVER

CIRCUITRY

S

FLIP-FLOP

R

0.4V

5.5μA

2

SW

SHDN 15

+

–

FREQUENCY

FOLDBACK

LOCKOUT

COMPARATOR

×1

Q2

FOLDBACK

CURRENT

LIMIT

V

C(MAX)

Q3

CLAMP

ERROR

AMPLIFIER

= 2000μMho

CLAMP

–

+

12

FB

g

m

11

1.22V

2.38V

V

C

GND

1, 8, 9, 16, 17

1766 F01

Figure 1. LT1766 Block Diagram

1766fc

9

LT1766/LT1766-5

APPLICATIONS INFORMATION

FEEDBACK PIN FUNCTIONS

regulator to operate at very low duty cycles, and the

average current through the diode and inductor is equal

totheshort-circuitcurrentlimitoftheswitch(typically2A

for the LT1766, folding back to less than 1A). Minimum

switch on-time limitations would prevent the switcher

from attaining a sufﬁciently low duty cycle if switching

frequency were maintained at 200kHz, so frequency is

reducedbyabout5:1whenthefeedbackpinvoltagedrops

below 0.8V (see Frequency Foldback graph). This does

not affect operation with normal load conditions; one

simply sees a gear shift in switching frequency during

start-up as the output voltage rises.

The feedback (FB) pin on the LT1766 is used to set output

voltage and provide several overload protection features.

The ﬁrst part of this section deals with selecting resistors

to set output voltage and the remaining part talks about

foldback frequency and current limiting created by the FB

pin. Please read both parts before committing to a ﬁnal

design. The 5V ﬁxed output voltage part (LT1766-5) has

internaldividerresistorsandtheFBpinisrenamedSENSE,

connected directly to the output.

The suggested value for the output divider resistor (see

Figure 2) from FB to ground (R2) is 5k or less, and a

formula for R1 is shown below. The output voltage error

caused by ignoring the input bias current on the FB pin

is less than 0.25% with R2 = 5k. A table of standard 1%

values is shown in Table 1 for common output voltages.

Please read the following if divider resistors are increased

above the suggested values.

In addition to lower switching frequency, the LT1766 also

operates at lower switch current limit when the feedback

pin voltage drops below 0.6V. Q2 in Figure 2 performs

this function by clamping the V pin to a voltage less than

C

its normal 2.1V upper clamp level. This foldback current

limit greatly reduces power dissipation in the IC, diode

andinductorduringshort-circuitconditions.Externalsyn-

chronization is also disabled to prevent interference with

foldbackoperation.Again,itisnearlytransparenttotheuser

under normal load conditions. The only loads that may be

affected are current source loads which maintain full load

current with output voltage less than 50% of ﬁnal value.

In these rare situations the feedback pin can be clamped

above 0.6V with an external diode to defeat foldback cur-

rent limit. Caution: clamping the feedback pin means that

frequency shifting will also be defeated, so a combination

of high input voltage and dead shorted output may cause

the LT1766 to lose control of current limit.

R2 V

−1.22

1.22

(

)

OUT

R1=

Table 1

OUTPUT

VOLTAGE

(V)

R1

% ERROR AT OUTPUT

R2

(NEAREST 1%) DUE TO DISCREET 1%

(kΩ)

7.32

8.45

15.4

18.7

24.9

30.9

36.5

46.4

RESISTOR STEPS

+0.32

3

3.3

5

4.99

4.75

4.47

4.32

4.12

–0.43

–0.30

6

+0.38

8

+0.20

The internal circuitry which forces reduced switching

frequency also causes current to ﬂow out of the feedback

pin when output voltage is low. The equivalent circuitry is

shown in Figure 2. Q1 is completely off during normal op-

eration. If the FB pin falls below 0.8V, Q1 begins to conduct

currentandreducesfrequencyattherateofapproximately

1.4kHz/μA. Toensureadequatefrequencyfoldback(under

worst-case short-circuit conditions), the external divider

Thevinin resistance must be low enough to pull 115μA out

10

12

15

–0.54

+0.24

–0.27

More Than Just Voltage Feedback

Thefeedbackpinisusedformorethanjustoutputvoltage

sensing. It also reduces switching frequency and current

limit when output voltage is very low (see the Frequency

Foldback graph in Typical Performance Characteristics).

This is done to control power dissipation in both the IC

and in the external diode and inductor during short-cir-

cuit conditions. A shorted output requires the switching

of the FB pin with 0.44V on the pin (R ≤ 3.8k). The net

DIV

result is that reductions in frequency and current limit are

affected by output voltage divider impedance. Although

1766fc

10

LT1766/LT1766-5

APPLICATIONS INFORMATION

V

SW

LT1766

L1

TO FREQUENCY

OUTPUT

5V

SHIFTING

1.4V

Q1

ERROR

AMPLIFIER

R1

1.2V

+

–

R4

2k

R3

1k

FB

+

C1

BUFFER

Q2

R2

5k

TO SYNC CIRCUIT

V

GND

C

1766 F02

Figure 2. Frequency and Current Limit Foldback

divider impedance is not critical, caution should be used if

resistors are increased beyond the suggested values and

short-circuitconditionsoccurwithhighinputvoltage.High

frequencypickupwillincreaseandtheprotectionaccorded

by frequency and current foldback will decrease.

V

AT I

= 1A

OUT

40mV/DIV

0.5A/DIV

= 0.1A

INDUCTOR CURRENT

AT I = 1A

CHOOSING THE INDUCTOR

OUT

For most applications, the output inductor will fall into

the range of 15μH to 100μH. Lower values are chosen to

reduce physical size of the inductor. Higher values allow

more output current because they reduce peak current

seen by the LT1766 switch, which has a 1.5A limit. Higher

values also reduce output ripple voltage.

INDUCTOR CURRENT

AT I = 0.1A

OUT

V

= 40V

OUT

L = 47μH

2.5μs/DIV

1766 F03

IN

= 5V

C = 100μF, 10V, 0.1Ω

Figure 3. LT1766 Ripple Voltage Waveform

When choosing an inductor you will need to consider

output ripple voltage, maximum load current, peak induc-

tor current and fault current in the inductor. In addition,

other factors such as core and copper losses, allowable

component height, EMI, saturation and cost should also

be considered. The following procedure is suggested

as a way of handling these somewhat complicated and

conﬂicting requirements.

inductor value to achieve a desirable output ripple volt-

age level. If output ripple voltage is of less importance,

the subsequent suggestions in Peak Inductor and Fault

Current and EMI will additionally help in the selection of

the inductor value.

Peak-to-peak output ripple voltage is the sum of a triwave

(created by peak-to-peak ripple current (I

) times ESR)

LP-P

and a square wave (created by parasitic inductance (ESL)

and ripple current slew rate). Capacitive reactance is as-

sumed to be small compared to ESR or ESL.

Output Ripple Voltage

Figure 3 shows a typical output ripple voltage wave-

form for the LT1766. Ripple voltage is determined by

dI

dt

V_RIPPLE= I

ESR + ESL

_LP-P)( ) (

(

)

ripple current (I

) through the inductor and the high

LP-P

frequency impedance of the output capacitor. The fol-

lowing equations will help in choosing the required

1766fc

11

LT1766/LT1766-5

APPLICATIONS INFORMATION

where:

If maximum load current is 0.5A, for instance, a 0.5A

inductor may not survive a continuous 2A overload con-

dition. Dead shorts will actually be more gentle on the

inductor because the LT1766 has frequency and current

limit foldback.

ESR = equivalent series resistance of the output

capacitor

ESL = equivalent series inductance of the output

capacitor

Peakswitchandinductorcurrentcanbesigniﬁcantlyhigher

than output current, especially with smaller inductors

and lighter loads, so don’t omit this step. Powdered iron

cores are forgiving because they saturate softly, whereas

ferrite cores saturate abruptly. Other core materials fall

somewhere in between. The following formula assumes

continuous mode of operation, but errs only slightly on

dI/dt = slew rate of inductor ripple current = V /L

IN

Peak-to-peak ripple current (I

) through the inductor

LP-P

and into the output capacitor is typically chosen to be

between 20% and 40% of the maximum load current. It

is approximated by:

V

V – V

IN OUT

(

=

_OUT)(

)

Table 2

I_LP-P

V

f L

_IN)( )( )

(

VENDOR/

PART NO.

VALUE

(μH)

I

DCR

(OHMS)

HEIGHT

(mm)

DC

(AMPS)

Example: with V = 40V, V

= 5V, L = 47μH, ESR = 0.1Ω

Coiltronics

IN

OUT

andESL=10nH,outputripplevoltagecanbeapproximated

CTX15-1P

15

1.4

1.1

1.3

1.4

2.4

1.9

1.7

1.4

0.087

0.08

4.2

6

as follows:

CTX15-1

5 40 − 5

( )(

)

CTX33-2P

33

47

0.126

0.106

0.099

0.146

0.19

I_P-P

=

= 0.465A

40 47 •10⁻⁶200 •10³

CTX33-2

6

( )

(

)(

)

UP2-330

5.9

dI

40

UP2-470

=

= 10⁶• 0.85

47 •10⁻⁶

dt

UP2-680

68

100

V_RIPPLE= 0.465A 0.1 + 10 •10⁻⁹10⁶0.85

UP2-101

0.277

(

)(

)

(

)

(

)(

)

Sumida

= 0.0465 + 0.0085 = 55mV_P-P

CDRH6D28-150M

CDRH6D38-150M

CDRH6D28-330M

CDRH104R-330M

CDRH125-330M

CDRH104R-470M

CDRH125-470M

CDRH6D38-680M

CDRH104R-680M

CDRH125-680M

CDRH104R-101M

CDRH125-101M

Coilcraft

15

1.4

1.6

0.076

0.062

0.122

0.069

0.044

0.095

0.058

0.173

0.158

0.093

0.225

0.120

3

4

Toreduceoutputripplevoltagefurtherrequiresanincrease

in the inductor value or a reduction in the capacitor ESR.

The latter can effect loop stability since the ESR forms

a useful zero in the overall loop response. Typically the

inductor value is adjusted with the trade-off being a

physically larger inductor with the possibility of increased

component height and cost. Choosing a smaller inductor

with lighter loads may result in discontinuous operation

buttheLT1766isdesignedtoworkwellinbothcontinuous

or discontinuous mode.

33

47

0.97

2.1

3

3.8

6

2.1

3.8

6

47

1.8

68

100

0.75

1.5

4

3.8

6

1.5

1.35

1.3

3.8

6

Peak Inductor Current and Fault Current

To ensure that the inductor will not saturate, the peak

inductor current should be calculated knowing the

maximum load current. An appropriate inductor should

then be chosen. In addition, a decision should be made

whether or not the inductor must withstand continuous

fault conditions.

DT3316P-153

DT3316P-333

DT3316P-473

15

33

47

1.8

1.3

1

0.06

0.09

0.11

5

1766fc

12

LT1766/LT1766-5

APPLICATIONS INFORMATION

the high side for discontinuous mode, so it can be used

for all conditions.

Maximumloadcurrentwouldbeequaltomaximumswitch

current for an inﬁnitely large inductor, but with ﬁnite

inductor size, maximum load current is reduced by one-

V_OUTV – V_OUT

(

)( ^IN

)

(I_LP-P

2

)

half peak-to-peak inductor current (I

). The following

LP-P

I_PEAK= I_OUT

+

= I_OUT+

formula assumes continuous mode operation, implying

that the term on the right is less than one-half of I .

2 V f L

( )( ^IN)( )( )

P

EMI

I

=

OUT(MAX)

Continuous Mode

Decideifthedesigncantolerateanopencoregeometrylike

a rod or barrel, which have high magnetic ﬁeld radiation,

or whether it needs a closed core like a toroid to prevent

EMI problems. This is a tough decision because the rods

or barrels are temptingly cheap and small and there are

no helpful guidelines to calculate when the magnetic ﬁeld

radiation will be a problem.

V

+ V V − V

– V

I_LP-P

2

(

_F)(

)

OUT

IN

OUT F

I_P–

=I_P−

2 L f V

( )( )(

)

IN

For V

= 5V, V = 8V, V = 0.63V, f = 200kHz and

OUT

L = 20μH:

IN

F(D1)

5 + 0.63 8 − 5 – 0.63

(

)(

)

I_{OUT MAX}₎= 1.5 −

(

2 20 •10⁻⁶200•10³

8

( )

)(

)

Additional Considerations

=1.5 − 0.21= 1.29A

After making an initial choice, consider additional factors

such as core losses and second sourcing, etc. Use the

experts in Linear Technology’s Applications department

if you feel uncertain about the ﬁnal choice. They have

experience with a wide range of inductor types and can tell

you about the latest developments in low proﬁle, surface

mounting, etc.

Note that there is less load current available at the higher

input voltage because inductor ripple current increases.

At V = 15V, duty cycle is 33% and for the same set of

IN

conditions:

5 + 0.63 15 − 5 – 0.63

(

)(

)

I_OUT(MAX)= 1.5 −

2 20 •10⁻⁶200•10³15

( )

)(

)

Maximum Output Load Current

= 1.5 − 0.44 = 1.06A

Maximum load current for a buck converter is limited

To calculate actual peak switch current with a given set

of conditions, use:

by the maximum switch current rating (I ). The current

P

rating for the LT1766 is 1.5A. Unlike most current mode

converters, the LT1766 maximum switch current limit

does not fall off at high duty cycles. Most current mode

converters suffer a drop off of peak switch current for

duty cycles above 50%. This is due to the effects of slope

compensation required to prevent subharmonic oscilla-

tions in current mode converters. (For detailed analysis,

see Application Note 19.)

I_LP-P

2

I_{SW PEAK}= I_OUT

+

(

)

(V_OUT+ V ) V − V

– V

F

(

)

F

IN

OUT

= I_OUT

2 L f V

( )( )(

)

IN

Reduced Inductor Value and Discontinuous Mode

If the smallest inductor value is of most importance to a

converter design, in order to reduce inductor size/cost,

discontinuous mode may yield the smallest inductor solu-

tion. The maximum output load current in discontinuous

mode, however, must be calculated and is deﬁned later

in this section.

The LT1766 is able to maintain peak switch current limit

over the full duty cycle range by using patented circuitry*

tocanceltheeffectsofslopecompensationonpeakswitch

current without affecting the frequency compensation it

provides.

*Patent # 6, 498, 466

1766fc

13

LT1766/LT1766-5

APPLICATIONS INFORMATION

Discontinuous mode is entered when the output load

Short-Circuit Considerations

current is less than one-half of the inductor ripple current

The LT1766 is a current mode controller. It uses the V

C

(I ). In this mode, inductor current falls to zero before

LP-P

node voltage as an input to a current comparator which

the next switch turn on (see Figure 8). Buck converters

will be in discontinuous mode for output load current

given by:

turns off the output switch on a cycle-by-cycle basis as

this peak current is reached. The internal clamp on the V

C

node, nominally 2V, then acts as an output switch peak

current limit. This action becomes the switch current limit

speciﬁcation.Themaximumavailableoutputpoweristhen

determined by the switch current limit.

(V_OUT+ V )(V – V_OUT– V )

F

IN

F

I

OUT

<

(2)(V )(f)(L)

Discontinuous Mode

The inductor value in a buck converter is usually chosen

large enough to keep inductor ripple current (I ) low;

IN

A potential controllability problem could occur under

short-circuit conditions. If the power supply output is

short circuited, the feedback ampliﬁer responds to the

LP-P

thisisdonetominimizeoutputripplevoltageandmaximize

output load current. In the case of large inductor values,

as seen in the equation above, discontinuous mode will

be associated with light loads.

low output voltage by raising the control voltage, V ,

C

to its peak current limit value. Ideally, the output switch

would be turned on, and then turned off as its current

exceededthevalueindicatedbyV . However, thereisﬁnite

C

When choosing small inductor values, however, discon-

tinuous mode will occur at much higher output load cur-

rents. The limit to the smallest inductor value that can be

chosen is set by the LT1766 peak switch current (I ) and

the maximum output load current required, given by:

responsetimeinvolvedinboththecurrentcomparatorand

turn-off of the output switch. These result in a minimum

on-time, t

. When combined with the large ratio of

ON(MIN)

P

V to (V + I • R), the diode forward voltage plus inductor

IN

F

I • R voltage drop, the potential exists for a loss of control.

Expressed mathematically the requirement to maintain

control is:

2

I

I_P

OUT(MAX)

Discontinuous Mode

=

(2)(I_LP-P

)

2

V_F+I•R

I

(f)(L)(V )

IN

(_P) (

)

f • t_ON≤

V

IN

2(V_OUT+ V )(V – V_OUT– V )

F

IN

F

where:

f = Switching frequency

= Switch minimum on-time

Example: For V = 15V, V

= 5V, V = 0.63V, f = 200kHz

F

IN

OUT

and L = 10μH.

t

ON

V = Diode forward voltage

(1.5)²•(200•10³)(10^–5)(15)

F

I

OUT(MAX)

Discontinuous

=

V = Input voltage

IN

2(5 + 0.63)(15 – 5 – 0.63)

I • R = Inductor I • R voltage drop

Mode

If this condition is not observed, the current will not be

I

= 0.639A

OUT(MAX)

Discontinuous Mode

limited at I , but will cycle-by-cycle ratchet up to some

PK

higher value. Using the nominal LT1766 clock frequency

What has been shown here is that if high inductor ripple

currentanddiscontinuousmodeoperationcanbetolerated,

small inductor values can be used. If a higher output load

current is required, the inductor value must be increased.

of 200KHz, a V of 40V and a (V + I • R) of say 0.7V, the

IN

F

maximum t to maintain control would be approximately

ON

90ns, an unacceptably short time.

The solution to this dilemma is to slow down the oscil-

lator when the FB pin voltage is abnormally low thereby

indicating some sort of short-circuit condition. Oscillator

frequency is unaffected until FB voltage drops to about

2/3 of its normal value. Below this point the oscillator

1766fc

If I

no longer meets the discontinuous mode

OUT(MAX)

criteria, use the I

equation for continuous mode;

OUT(MAX)

the LT1766 is designed to operate well in both modes of

operation, allowing a large range of inductor values to

be used.

14

LT1766/LT1766-5

APPLICATIONS INFORMATION

capacitors fail during very high turn-on surges, which

do not occur at the output of regulators. High discharge

surges,suchaswhentheregulatoroutputisdeadshorted,

do not harm the capacitors.

frequency decreases roughly linearly down to a limit

of about 40kHz. This lower oscillator frequency during

short-circuit conditions can then maintain control with

the effective minimum on time.

It is recommended that for [V /(V

+ V )] ratios > 10,

Unliketheinputcapacitor,RMSripplecurrentintheoutput

capacitor is normally low enough that ripple current rating

is not an issue. The current waveform is triangular with

IN OUT

F

a soft-start circuit should be used to control the output

capacitor charge rate during start-up or during recovery

from an output short circuit, thereby adding additional

control over peak inductor current. See Buck Converter

with Adjustable Soft-Start later in this data sheet.

a typical value of 125mA

this is:

. The formula to calculate

RMS

Output capacitor ripple current (RMS):

0.29 V

_OUT)(

=

V − V

IN OUT

(

)

OUTPUT CAPACITOR

I_{RIPPLE RMS}

(

)

L f V

( )( )(

)

IN

The output capacitor is normally chosen by its effective

series resistance (ESR), because this is what determines

output ripple voltage. To get low ESR takes volume, so

physically smaller capacitors have high ESR. The ESR

range for typical LT1766 applications is 0.05Ω to 0.2Ω.

A typical output capacitor is an AVX type TPS, 100μF at

10V, with a guaranteed ESR less than 0.1Ω. This is a “D”

size surface mount solid tantalum capacitor. TPS capaci-

tors are specially constructed and tested for low ESR, so

they give the lowest ESR for a given volume. The value

in microfarads is not particularly critical, and values from

22μF to greater than 500μF work well, but you cannot

cheat mother nature on ESR. If you ﬁnd a tiny 22μF solid

tantalum capacitor, it will have high ESR, and output ripple

voltage will be terrible. Table 2 shows some typical solid

tantalum surface mount capacitors.

Ceramic Capacitors

Higher value, lower cost ceramic capacitors are now

becoming available. They are generally chosen for their

good high frequency operation, small size and very low

ESR (effective series resistance). Their low ESR reduces

output ripple voltage but also removes a useful zero in the

loop frequency response, common to tantalum capaci-

tors. To compensate for this, a resistor R_Ccan be placed

in series with the V_Ccompensation capacitor, C_C. Care

must be taken however, since this resistor sets the high

frequency gain of the error ampliﬁer, including the gain at

the switching frequency. If the gain of the error ampliﬁer

is high enough at the switching frequency, output ripple

voltage (although smaller for a ceramic output capacitor)

may still affect the proper operation of the regulator. A

ﬁlter capacitor, C_F, in parallel with the R_C/C_Cnetwork is

suggested to control possible ripple at the V_Cpin. An All

Ceramic solution is possible for the LT1766 by choos-

ing the correct compensation components for the given

application.

Table 3. Surface Mount Solid Tantalum Capacitor ESR

and Ripple Current

E Case Size

ESR (MAX, Ω)

RIPPLE CURRENT (A)

AVX TPS, Sprague 593D

D Case Size

0.1 to 0.3

0.7 to 1.1

AVX TPS, Sprague 593D

C Case Size

0.1 to 0.3

0.2 (typ)

0.7 to 1.1

0.5 (typ)

Example: For V_IN= 8V to 40V, V_OUT= 3.3V at 1A, the

LT1766canbestabilized,providegoodtransientresponse

and maintain very low output ripple voltage using the

following component values: (refer to the ﬁrst page of

this data sheet for component references) C3 = 2.2μF,

R_C= 4.7k, C_C= 15nF, C_F= 220pF and C1 = 47μF. See

Application Note 19 for further detail on techniques for

proper loop compensation.

AVX TPS

Many engineers have heard that solid tantalum capacitors

arepronetofailureiftheyundergohighsurgecurrents.This

is historically true, and type TPS capacitors are specially

tested for surge capability, but surge ruggedness is not

a critical issue with the output capacitor. Solid tantalum

1766fc

15

LT1766/LT1766-5

APPLICATIONS INFORMATION

INPUT CAPACITOR

recommends derating capacitor operating voltage by 2:1

for high surge applications.

Step-downregulatorsdrawcurrentfromtheinputsupplyin

pulses. Theriseandfalltimesofthesepulsesareveryfast.

Theinputcapacitorisrequiredtoreducethevoltageripple

this causes at the input of LT1766 and force the switching

current into a tight local loop, thereby minimizing EMI.

The RMS ripple current can be calculated from:

CATCH DIODE

HighestefﬁciencyoperationrequirestheuseofaSchottky

type diode. DC switching losses are minimized due to its

low forward voltage drop, and AC behavior is benign due

to its lack of a signiﬁcant reverse-recovery time. Schottky

diodesaregenerallyavailablewithreverse-voltageratings

of up to 60V and even 100V, and are price competitive

with other types.

2

I_{RIPPLE RMS}= I_OUTV_OUTV – V

/ V

IN

(

)

IN

OUT

(

)

Ceramiccapacitorsareidealforinputbypassing.At200kHz

switchingfrequency,theenergystoragerequirementofthe

input capacitor suggests that values in the range of 2.2μF

to 20μF are suitable for most applications. If operation is

requiredclosetotheminimuminputrequiredbytheoutput

of the LT1766, a larger value may be required. This is to

prevent excessive ripple causing dips below the minimum

operating voltage resulting in erratic operation.

The use of so-called ultrafast recovery diodes is generally

not recommended. When operating in continuous mode,

thereverse-recoverytimeexhibitedbyultrafastdiodeswill

result in a slingshot type effect. The power internal switch

will ramp up V current into the diode in an attempt to

IN

get it to recover. Then, when the diode has ﬁnally turned

off, some tens of nanoseconds later, the V node volt-

SW

Depending on how the LT1766 circuit is powered up you

may need to check for input voltage transients.

age ramps up at an extremely high dV/dt, perhaps 5 to

even 10V/ns! With real world lead inductances, the V

SW

node can easily overshoot the V rail. This can result in

IN

The input voltage transients may be caused by input volt-

age steps or by connecting the LT1766 converter to an

already powered up source such as a wall adapter. The

suddenapplicationofinputvoltagewillcausealargesurge

of current in the input leads that will store energy in the

parasiticinductanceoftheleads.Thisenergywillcausethe

input voltage to swing above the DC level of input power

source and it may exceed the maximum voltage rating of

input capacitor and LT1766.

poor RFI behavior and if the overshoot is severe enough,

damage the IC itself.

Thesuggestedcatchdiode(D1)isanInternationalRectiﬁer

10MQ060N Schottky. It is rated at 1.5A average forward

current and 60V reverse voltage. Typical forward voltage

is 0.63V at 1A. The diode conducts current only during

switch off time. Peak reverse voltage is equal to regulator

inputvoltage.Averageforwardcurrentinnormaloperation

can be calculated from:

The easiest way to suppress input voltage transients is

to add a small aluminum electrolytic capacitor in parallel

with the low ESR input capacitor. The selected capacitor

needs to have the right amount of ESR in order to criti-

cally dampen the resonant circuit formed by the input lead

inductance and the input capacitor. The typical values of

ESR will fall in the range of 0.5Ω to 2Ω and capacitance

will fall in the range of 5μF to 50μF.

I_OUTV – V

(

)

IN

OUT

I_D(AVG)

=

V

IN

This formula will not yield values higher than 1.5A with

maximum load current of 1.5A. The only reason to

consider a larger diode is the worst-case condition of a

high input voltage and shorted output. With a shorted

condition, diode current will increase to a typical value

of 2A, determined by peak switch current limit. This is

safe for short periods of time, but it would be prudent to

checkwiththediodemanufacturerifcontinuousoperation

under these conditions must be tolerated.

Iftantalumcapacitorsareused,valuesinthe22μFto470μF

range are generally needed to minimize ESR and meet

ripple current and surge ratings. Care should be taken to

ensure the ripple and surge ratings are not exceeded. The

AVX TPS and Kemet T495 series are surge rated. AVX

1766fc

16

LT1766/LT1766-5

APPLICATIONS INFORMATION

BOOST PIN

SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

Formostapplications, theboostcomponentsarea0.33μF

capacitor and a 1N4148W diode. The anode is typically

connected to the regulated output voltage to generate a

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT1766. Typically, UVLO is used in situations where

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

loadtothesourceandcancausethesourcetocurrentlimit

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

voltage approximately V

above V to drive the output

OUT

IN

stage. However, the output stage discharges the boost ca-

pacitor during the on time of the switch. The output driver

requires at least 3V of headroom throughout this period

to keep the switch fully saturated. If the output voltage is

less than 3.3V, it is recommended that an alternate boost

supply is used. The boost diode can be connected to the

input, although, care must be taken to prevent the 2× V

IN

boost voltage from exceeding the BOOST pin absolute

maximum rating. The additional voltage across the switch

driver also increases power loss, reducing efﬁciency. If

available, and independent supply can be used with a local

bypass capacitor.

Threshold voltage for lockout is about 2.38V. A 5.5μA

bias current ﬂows out of the pin at this threshold. The

internally generated current is used to force a default high

state on the shutdown pin if the pin is left open. When

low shutdown current is not an issue, the error due to this

current can be minimized by making R 10k or less. If

A 0.33μF boost capacitor is recommended for most ap-

plications. Almost any type of ﬁlm or ceramic capacitor

is suitable, but the ESR should be <1Ω to ensure it can

be fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

4700ns on time, 42mA boost current and 0.7V discharge

ripple. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve cir-

cuit operation or efﬁciency. Under low input voltage and

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start-up operation.

LO

shutdown current is an issue, R can be raised to 100k,

LO

but the error due to initial bias current and changes with

temperature should be considered.

R_LO= 10k to 100k 25k suggested

(

)

R_LOV − 2.38V

(

)

IN

R_HI=

2.38V −R_LO5.5μA

(

)

V = Minimum input voltage

IN

R

FB

L1

LT1766

OUTPUT

V

SW

2.38V

+

–

IN

INPUT

STANDBY

R

HI

5.5μA

+

SHDN

C1

+

–

TOTAL

SHUTDOWN

C2

LO

0.4V

GND

1766 F04

Figure 4. Undervoltage Lockout

1766fc

17

LT1766/LT1766-5

APPLICATIONS INFORMATION

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface ca-

pacitance to the switching nodes are minimized. If high

resistor values are used, the shutdown pin should be

bypassed with a 1000pF capacitor to prevent coupling

problems from the switch node. If hysteresis is desired

in the undervoltage lockout point, a resistor, R_FB, can

be added to the output node. Resistor values can be

calculated from:

compensation used to prevent subharmonic switching is

reduced. This type of subharmonic switching only occurs

at input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufﬁcient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

At power-up, when V is being clamped by the FB pin (see

C

R_LOV − 2.38 ΔV/V

+ 1 + ΔV

(

)

[

IN

OUT

]

Figure 2, Q2), the sync function is disabled. This allows

the frequency foldback to operate in the shorted output

condition.Duringnormaloperation,switchingfrequencyis

controlledbytheinternaloscillatoruntiltheFBpinreaches

0.6V, after which the SYNC pin becomes operational. If no

synchronization is required, this pin should be connected

to ground.

R_HI=

2.38 −R_LO5.5μA

(

)

R = R V /ΔV

(

)

(

)

FB

HI

OUT

25k suggested for R

LO

V = Input voltage at which switching stops as input

voltage descends to trip level

ΔV = Hysteresis in input voltage level

IN

LAYOUT CONSIDERATIONS

Example: output voltage is 5V, switching is to stop if input

voltagedropsbelow12Vandshouldnotrestartunlessinput

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maxi-

mum efﬁciency, switch rise and fall times are typically

in the nanosecond range. To prevent noise both radiated

and conducted, the high speed switching current path,

shown in Figure 5, must be kept as short as possible.

This is implemented in the suggested layout of Figure 6.

Shortening this path will also reduce the parasitic trace

inductance of approximately 25nH/inch. At switch off, this

parasitic inductance produces a ﬂyback spike across the

LT1766 switch. When operating at higher currents and

input voltages, with poor layout, this spike can generate

voltages across the LT1766 that may exceed its absolute

rises back to 13.5V. ΔV is therefore 1.5V and V = 12V.

IN

Let R = 25k.

LO

25k 12 − 2.38 1.5/5 + 1 + 1.5

(

)

[

]

R_HI=

2.38 – 25k 5.5μA

(

)

25k 10.41

(

)

=

= 116k

2.24

R_FB= 116k 5/1.5 = 387k

(

)

SYNCHRONIZING

The SYNC input must pass from a logic level low, through

the maximum synchronization threshold with a duty cycle

between 10% and 90%. The input can be driven directly

from a logic level output. The synchronizing range is equal

to initial operating frequency up to 700kHz. This means

that minimum practical sync frequency is equal to the

worst-case high self-oscillating frequency (228kHz), not

the typical operating frequency of 200kHz. Caution should

be used when synchronizing above 265kHz because at

highersyncfrequenciestheamplitudeoftheinternalslope

LT1766

L1

5V

HIGH

FREQUENCY

CIRCULATING

PATH

V

IN

C3

D1 C1

LOAD

1766 F05

Figure 5. High Speed Switching Path

1766fc

18

LT1766/LT1766-5

APPLICATIONS INFORMATION

CONNECT TO

GROUND PLANE

GND

L1

FOR THE FE PACKAGE, THE

EXPOSED PAD (PIN 17) SHOULD

BE PROPERLY SOLDERED TO

THE GROUND PLANE.

NOTE: BOOST AND BIAS

COPPER TRACES ARE ON

A SEPARATE LAYER FROM

THE GROUND PLANE

C1

MINIMIZE LT1766

C3-D1 LOOP

D2

V

OUT

D1

C3

C2

GND

1

2

3

4

5

6

7

8

GND

SW

GND 16

SHDN

SYNC

KELVIN SENSE

15

14

13

V

OUT

V

IN

LT1766

FB

12

11

R2

V

C

BOOST

GND

R1

C

FB

BIAS 10

GND

C

F

9

V

IN

R

C

KEEP FB AND V COMPONENTS

C

AWAY FROM HIGH FREQUENCY,

HIGH CURRENT COMPONENTS

C

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

1766 F06

Figure 6. Suggested Layout

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

willreduceanyadditionalheatingeffects. FortheFEpack-

age, the exposed pad (Pin 17) should be soldered to the

copper ground plane underneath the device.

The V and FB components should be kept as far away as

C

PARASITIC RESONANCE

possible from the switch and boost nodes. The LT1766

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability

or subharmonic like oscillation.

Resonance or ringing may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

followingswitchrisetimeiscausedbyswitch/diode/input

capacitorleadinductanceanddiodecapacitance.Schottky

diodes have very high “Q” junction capacitance that can

ring for many cycles when excited at high frequency. If

total lead length for the input capacitor, diode and switch

path is 1 inch, the inductance will be approximately 25nH.

At switch off, this will produce a spike across the NPN

output device in addition to the input voltage. At higher

currents this spike can be in the order of 10V to 20V

or higher with a poor layout, potentially exceeding the

absolute max switch voltage. The path around switch,

catch diode and input capacitor must be kept as short as

possibletoensurereliableoperation.Whenlookingatthis,

Board layout also has a signiﬁcant effect on thermal

resistance. Pins 1, 8, 9 and 16, GND, are a continuous

copper plate that runs under the LT1766 die. This is the

best thermal path for heat out of the package. Reducing

the thermal resistance from Pins 1, 8, 9 and 16 onto the

board will reduce die temperature and increase the power

capability of the LT1766. This is achieved by providing as

much copper area as possible around these pins. Add-

ing multiple solder ﬁlled feedthroughs under and around

these four corner pins to the ground plane will also help.

Similar treatment to the catch diode and coil terminations

1766fc

19

LT1766/LT1766-5

APPLICATIONS INFORMATION

SW RISE

SW FALL

SWITCH NODE

VOLTAGE

10V/DIV

0.2A/DIV

2V/DIV

INDUCTOR

CURRENT

AT I

= 0.1A

OUT

1766 F08

V

= 40V

OUT

L = 47μH

1μs/DIV

50ns/DIV

1766 F07

IN

= 5V

Figure 7. Switch Node Resonance

Figure 8. Discontinuous Mode Ringing

a >100MHz oscilloscope must be used, and waveforms

should be observed on the leads of the package. This

switch off spike will also cause the SW node to go below

ground. The LT1766 has special circuitry inside which

mitigates this problem, but negative voltages over 0.8V

lasting longer than 10ns should be avoided. Note that

100MHz oscilloscopes are barely fast enough to see the

details of the falling edge overshoot in Figure 7.

Boost current loss:

2

V_OUT

I

/36

OUT

(

)

P_BOOST

=

V

IN

Quiescent current loss:

P = V 0.0015 + V 0.003

OUT

(

)

(

)

Q

IN

R

EFF

= Switch resistance (≈0.3) hot

SW

A second, much lower frequency ringing is seen during

switch off-time if load current is low enough to allow the

inductor current to fall to zero during part of the switch

off-time (see Figure 8). Switch and diode capacitance

resonatewiththeinductortoformdampedringingat1MHz

to 10 MHz. This ringing is not harmful to the regulator

and it has not been shown to contribute signiﬁcantly to

EMI. Any attempt to damp it with a resistive snubber will

degrade efﬁciency.

t

= Effective switch current/voltage overlap time

= (t + t + t + t )

r

f

Ir

If

t = (V /1.2)ns

r

IN

t = (V /1.7)ns

f

t = t = (I /0.05)ns

Ir

If

OUT

f = Switch frequency

Example: with V = 40V, V

= 5V and I

= 1A:

IN

OUT

0.3 1 ²5

(

)( ) ( )

P_SW

=

+ 97•10⁻⁹1/2 1 40 200 •10³

(

)

( )( )

(

)

40

THERMAL CALCULATIONS

= 0.04 + 0.388 = 0.43W

Power dissipation in the LT1766 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit cur-

rent, and input quiescent current. The following formulas

showhowtocalculateeachoftheselosses.Theseformulas

assume continuous mode operation, so they should not

be used for calculating efﬁciency at light load currents.

2

5 1/36

( )

(

)

= 0.02W

P_BOOST

=

40

P_Q= 40(0.0015)+ 5(0.003) = 0.08W

Total power dissipation in the IC is given by:

= P + P + P

P

TOT

SW

BOOST

Q

Switch loss:

2

= 0.43W + 0.02W + 0.08W = 0.53W

R_SWI_OUTV_OUT

(

) (

)

P_SW

=

+ t_EFF(1/2) I_OUT

V

f

(

)(

^IN

)( )

V

IN

1766fc

20

LT1766/LT1766-5

APPLICATIONS INFORMATION

Thermal resistance for the LT1766 packages is inﬂuenced

by the presence of internal or backside planes.

DietemperaturecanpeakforcertaincombinationsofV_IN,

V_OUTand load current. While higher V_INgives greater

switch AC losses, quiescent and catch diode losses, a

lower V_INmay generate greater losses due to switch DC

losses. In general, the maximum and minimum V_INlevels

should be checked with maximum typical load current

for calculation of the LT1766 die temperature. If a more

accurate die temperature is required, a measurement of

the SYNC pin resistance (to GND) can be used. The SYNC

pin resistance can be measured by forcing a voltage no

greater than 0.5V at the pin and monitoring the pin cur-

rent over temperature in an oven. This should be done

with minimal device power (low V_INand no switching

(V_C= 0V)) in order to calibrate SYNC pin resistance with

ambient (oven) temperature.

SSOP (GN16) package: With a full plane under the GN16

package, thermal resistance will be about 85°C/W.

TSSOP (exposed pad) package: With a full plane under

the TSSOP package, thermal resistance will be about

45°C/W.

To calculate die temperature, use the proper thermal

resistance number for the desired package and add in

worst-case ambient temperature:

T = T + (θ • P )

TOT

J

A

JA

When estimating ambient, remember the nearby catch

diode and inductor will also be dissipating power:

Note: Some of the internal power dissipation in the IC,

due to BOOST pin voltage, can be transferred outside

of the IC to reduce junction temperature, by increasing

the voltage drop in the path of the boost diode D2 (see

Figure 9). This reduction of junction temperature inside

the IC will allow higher ambient temperature operation for

a given set of conditions. BOOST pin circuitry dissipates

power given by:

(V )(V – V_OUT)(I_LOAD

)

F

IN

P_DIODE

=

V

IN

V = Forward voltage of diode (assume 0.63V at 1A)

F

(0.63)(40 – 5)(1)

P_DIODE

=

= 0.55W

40

2

P

= (I

) (R )

INDUCTOR

LOAD L

R = Inductor DC resistance (assume 0.1Ω)

V_OUT• (I_SW/ 36) • V_C2

L

P_DISS(BOOST)

=

2

V

IN

P

(1) (0.1) = 0.1W

INDUCTOR

Onlyaportionofthetemperatureriseintheexternalinductor

and diode is coupled to the junction of the LT1766. Based

on empirical measurements the thermal effect on LT1766

junctiontemperatureduetopowerdissipationintheexternal

inductor and catch diode can be calculated as:

Typically V (the boost voltage across the capacitor C2)

C2

equals Vout. This is because diodes D1 and D2 can be

considered almost equal, where:

V

C2

= V – V – (–V ) = V

OUT FD2 FD1 OUT

Hence the equation used for boost circuitry power dissi-

pation given in the previous Thermal Calculations section

is stated as:

ΔT (LT1766) ≈ (P

+ P

)(10°C/W)

J

DIODE

INDUCTOR

UsingtheexamplecalculationsforLT1766dissipation,the

LT1766 die temperature will be estimated as:

V_OUT•(I_SW/36)•V_OUT

P_DISS(BOOST)

=

T = T + (θ • P ) + [10 • (P

+ P

)]

J

A

JA

TOT

DIODE

INDUCTOR

V

IN

With the GN16 package (θ = 85°C/W), at an ambient

temperature of 60°C:

JA

Here it can be seen that boost power dissipation increases

asthesquareofV .Itispossible,however,toreduceV

OUT

C2

T = 60 + (85 • 0.53) + (10 • 0.65) = 112°C

J

below V

to save power dissipation by increasing the

OUT

With the TSSOP package (θ = 45°C/W), at an ambient

temperature of 60°C:

voltage drop in the path of D2. Care should be taken that

JA

V

C2

does not fall below the minimum 3.3V boost voltage

required for full saturation of the internal power switch.

T = 60 + (45 • 0.53) + (10 • 0.65) = 90°C

J

1766fc

21

LT1766/LT1766-5

APPLICATIONS INFORMATION

is approximately 5V. During

For an FE package with thermal resistance of 45°C/W,

ambienttemperaturesavingswouldbe,T(ambient)savings

= 0.116W • 45°C/W = 5c. For a GN Package with thermal

resistanceof85°C/W, ambienttemperaturesavingswould

be T/(ambient) savings = 0.116 • 85°C/W = 10c. The 7V

zenershouldbesizedforexcessof0.116Woperation. The

tolerances of the zener should be considered to ensure

For output voltages of 5V, V

C2

switch turn on, V will fall as the boost capacitor C2 is

C2

dicharged by the BOOST pin. In the previous BOOST Pin

section, the value of C2 was designed for a 0.7V droop in

V =V

.Hence,anoutputvoltageaslowas4Vwould

C2

DROOP

still allow the minimum 3.3V for the boost function using

the C2 capacitor calculated. If a target output voltage of

12V is required, however, an excess of 8V is placed across

the boost capacitor which is not required for the boost

function but still dissipates additional power.

minimum V exceeds 3.3V + V

.

C2

DROOP

Input Voltage vs Operating Frequency Considerations

The absolute maximum input supply voltage for the

LT1766 is speciﬁed at 60V. This is based solely on internal

semiconductorjunctionbreakdowneffects.Duetointernal

What is required is a voltage drop in the path of D2 to

achieve minimal power dissipation while still maintaining

minimum boost voltage across C2. A zener, D4, placed in

series with D2 (see Figure 9), drops voltage to C2.

power dissipation, the actual maximum V achievable in

IN

a particular application may be less than this.

Example:theBOOSTpinpowerdissipationfora20Vinput

to 12V output conversion at 1A is given by:

A detailed theoretical basis for estimating internal power

loss is given in the section, Thermal Considerations. Note

that AC switching loss is proportional to both operating

frequencyandoutputcurrent.ThemajorityofACswitching

loss is also proportional to the square of input voltage.

12•(1/36)•12

P_BOOST

=

= 0.2W

20

If a 7V zener D4 is placed in series with D2, then power

dissipation becomes :

For example, while the combination of V = 40V, V

IN

OUT

= 5V at 1A and f

= 200kHz may be easily achievable,

OSC

simultaneously raising V to 60V and f

to 700kHz is

12•(1/36)•5

IN

OSC

P_BOOST

=

= 0.084W

not possible. Nevertheless, input voltage transients up to

60V can usually be accommodated, assuming the result-

ing increase in internal dissipation is of insufﬁcient time

duration to raise die temperature signiﬁcantly.

20

D2

D4

Asecondconsiderationiscontrollability.Apotentiallimita-

D2

tion occurs with a high step-down ratio of V to V , as

IN

OUT

this requires a correspondingly narrow minimum switch

on time. An approximate expression for this (assuming

continuous mode operation) is given as follows:

C2

BOOST

LT1766

L1

V

OUT

V

IN

SW

IN

C3

D1

V_OUT+ V_F

Min t_ON

=

SHDN

BIAS

FB

V_IN(f_OSC

)

R1

+

SYNC

GND

C1

where:

V = Input voltage

R2

V

C

IN

OUT

V

= Output voltage

C

R

F

C

V = Schottky diode forward drop

F

OSC

C

f

= Switching frequency

1766 F09

A potential controllability problem arises if the LT1766 is

called upon to produce an on time shorter than it is able

Figure 9. Boost Pin, Diode Selection

to produce. Feedback loop action will lower then reduce

1766fc

22

LT1766/LT1766-5

APPLICATIONS INFORMATION

the V control voltage to the point where some sort of

LT1766

CURRENT MODE

C

cycle-skipping or odd/even cycle behavior is exhibited.

V

SW

OUTPUT

POWER STAGE

= 2mho

ERROR

g

m

In summary:

AMPLIFIER

C

FB

R1

FB

–

CERAMIC

ESL

TANTALUM

1. Be aware that the simultaneous requirements of high

g

=

m

2000μmho

ESR

C1

+

V , high I

and high f

may not be achievable in

IN

OUT

OSC

R

1.22V

O

200k

+

R

practice due to internal dissipation. The Thermal Con-

siderations section offers a basis to estimate internal

power. Inquestionablecasesaprototypesupplyshould

be built and exercised to verify acceptable operation.

LOAD

C1

GND

V

C

R2

R

C

F

C

1766 F10

2. ThesimultaneousrequirementsofhighV ,lowV and

IN

OUT

high f

can result in an unacceptably short minimum

OSC

Figure 10. Model for Loop Response

switch on-time. Cycle skipping and/or odd/even cycle

behavior will result although correct output voltage is

usually maintained.

80

180

150

120

90

60

GAIN

FREQUENCY COMPENSATION

40

20

Before starting on the theoretical analysis of frequency

response, the following should be remembered—the

worse the board layout, the more difﬁcult the circuit will

be to stabilize. This is true of almost all high frequency

analog circuits, read the Layout Considerations section

ﬁrst. Common layout errors that appear as stability prob-

lems are distant placement of input decoupling capacitor

PHASE

0

60

–20

–40

30

0

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

R

1766 F11

V

= 42V

= 5V

= 500mA

= 100μF, 10V, 0.1Ω

= 2.2k

= 22nF

= 220pF

IN

OUT

LOAD

C

F

V

C

and/or catch diode, and connecting the V compensation

I

C

OUT

to a ground track carrying signiﬁcant switch current. In

addition, thetheoreticalanalysisconsidersonlyﬁrstorder

non-ideal component behavior. For these reasons, it is

important that a ﬁnal stability check is made with produc-

tion layout and components.

Figure 11. Overall Loop Response

stability. This ESR, however, contributes signiﬁcantly to

the ripple voltage at the output (see Output Ripple Volt-

age in the Applications Section). It is possible to reduce

capacitor size and output ripple voltage by replacing the

tantalum output capacitor with a ceramic output capaci-

tor because of its very low ESR. The zero provided by the

tantalum output capacitor must now be reinserted back

into the loop. Alternatively there may be cases where,

even with the tantalum output capacitor, an additional

zero is required in the loop to increase phase margin for

improved transient response.

The LT1766 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 10.

The LT1766 can be considered as two g blocks, the error

m

ampliﬁer and the power stage.

Figure 11 shows the overall loop response. At the V

C

pin, the frequency compensation components used are:

R = 2.2k, C = 0.022μF and C = 220pF. The output

C

F

capacitor used is a 100μF, 10V tantalum capacitor with

typical ESR of 100mΩ.

A zero can be added into the loop by placing a resistor,

R at the V pin in series with the compensation capaci-

C,

C

The ESR of the tantalum output capacitor provides a use-

ful zero in the loop frequency response for maintaining

tor, C or by placing a capacitor, C , between the output

C

FB

and the FB pin.

1766fc

23

LT1766/LT1766-5

APPLICATIONS INFORMATION

When using R , the maximum value has two limitations.

CONVERTER WITH BACKUP OUTPUT REGULATOR

C

First, the combination of output capacitor ESR and R

C

Insystemswithaprimaryandbackupsupply,forexample,

a battery-powered device with a wall adapter input, the

output of the LT1766 can be held up by the backup supply

with the LT1766 input disconnected. In this condition, the

may stop the loop rolling off altogether. Second, if the

loop gain is not rolled off sufﬁciently at the switching

frequency, output ripple will peturb the V pin enough to

C

causeunstabledutycycleswitchingsimilartosubharmonic

SW pin will source current into the V pin. If the SHDN pin

IN

oscillations. If needed, an additional capacitor, C , can be

F

is held at ground, only the shut down current of 25μA will

be pulled via the SW pin from the second supply. With the

SHDN pin ﬂoating, the LT1766 will consume its quiescent

addedacrosstheR /C networkfromtheV pintoground

C

to further suppress V ripple voltage.

C

With a tantalum output capacitor, the LT1766 already in-

cludes a resistor, R and ﬁlter capacitor, C , at the V pin

operating current of 1.5mA. The V pin will also source

IN

current to any other components connected to the input

line. If this load is greater than 10mA or the input could

be shorted to ground, a series Schottky diode must be

added, as shown in Figure 12. With these safeguards,

C

F

C

(see Figures 10 and 11) to compensate the loop over the

entire V range (to allow for stable pulse skipping for high

IN

V -to-V

ratios ≥10). A ceramic output capacitor can

IN

OUT

still be used with a simple adjustment to the resistor R

the output can be held at voltages up to the V absolute

C

IN

for stable operation. (See Ceramic Capacitors section for

maximum rating.

stabilizingLT1766). Ifadditionalphasemarginisrequired,

acapacitor,C ,canbeinsertedbetweentheoutputandFB

FB

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

pin but care must be taken for high output voltage applica-

tions.Suddenshortstotheoutputcancreateunacceptably

large negative transients on the FB pin.

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 13 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

For V -to-V

ratios <10, higher loop bandwidths are

OUT

IN

possible by readjusting the frequency compensation

conﬁguration with the addition of R3, R4, C and Q1.

SS

components at the V pin.

C

As the output starts to rise, Q1 turns on, regulating switch

current via the V pin to maintain a constant dv/dt at the

When checking loop stability, the circuit should be op-

erated over the applications’s full voltage, current and

temperature range. Proper loop compensation may be

obtained by emperical methods as described in detail in

Application Notes 19 and 76.

C

output.Outputrisetimeiscontrolledbythecurrentthrough

C

deﬁned by R4 and Q1’s V . Once the output is in

SS

BE

regulation, Q1 turns off and the circuit operates normally.

R3 is transient protection for the base of Q1.

D2

1N4148W

C2

0.33μF

D3

L1

47μH

10MQ060N

BOOST

REMOVABLE

INPUT

V

LT1766 SW

IN

5V, 1A

R3

ALTERNATE

SUPPLY

BIAS

54k

R1

SHDN

15.4k

SYNC

FB

+

C1

100μF

10V

R2

4.99k

GND

V

C

D1

10MQ060N

R4

25k

R

C

2.2k

C3

2.2μF

C

F

220pF

C

0.022μF

1766 F12

Figure 12. Dual Source Supply with 25μA Reverse Leakage

1766fc

24

LT1766/LT1766-5

APPLICATIONS INFORMATION

is transferred by magnetic coupling into L1B, powering

the –5V rail. C4 pulls L1B positive during switch on-time,

causing current to ﬂow, and energy to build in L1B and

C4. At switch off, the energy stored in both L1B and C4

supply the –5V rail. This reduces the current in L1A and

changes L1B current waveform from square to triangular.

For details on this circuit, including maximum output cur-

rents, see Design Note 100.

R4 C_SSV_OUT

( )( )(

)

RiseTime =

V_BE

Using the values shown in Figure 10,

47 •10³15•10^–9

5

( )

(

)(

)

Rise Time =

= 5ms

0.7

The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

output current is unchanged. Variants of this circuit can

be used for sequencing multiple regulator outputs.

D2

1N4148W

C2

0.33μF

L1A*

50μH

BOOST

LT1766

V

OUT1

V

IN

5V

7.5V

V

SW

FB

IN

(SEE DN100

FOR MAX I

TO 60V

)

OUT

R1

SHDN

SYNC

GND

C1

15.4k

C3

2.2μF

100V

CER

D2

+

100μF

10V

1N4148W

OUTPUT

R2

V

C

TANT

5V

INPUT

40V

C2

4.99k

1A

L1

0.33μF

BOOST

BIAS

SW

R

C

2.2k

47μH

C

F

220pF

D1

V

IN

C

C3

C

+

C1

100μF

D1

0.022μF

2.2μF

50V

CER

LT1766

R1

GND

15.4k

C4

C5

+

SHDN

SYNC GND

100μF

FB

C

100μF

10V

L1B*

D3

10V

R2

4.99k

V

TANT

V

OUT2

–5V^†

C

SS

15nF

1766 F14

* L1 IS A SINGLE CORE WITH TWO WINDINGS

COILTRONICS #CTX50-3A

C

F

R3

2k

Q1

220pF

R

C

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL

2.2k

1766 F13

PRELOAD OF 1k TO 5k MAY BE USED TO

IMPROVE LOAD REGULATION

D1, D3: 10MQ060N

C

R4

47k

0.022μF

Figure 14. Dual Output SEPIC Converter

Figure 13. Buck Converter with Adjustable Soft-Start

POSITIVE-TO-NEGATIVE CONVERTER

DUAL OUTPUT SEPIC CONVERTER

The circuit in Figure 15 is a positive-to-negative topology

using a grounded inductor. It differs from the standard

approach in the way the IC chip derives its feedback signal

becausetheLT1766acceptsonlypositivefeedbacksignals.

The ground pin must be tied to the regulated negative

output. A resistor divider to the FB pin then provides the

proper feedback voltage for the chip.

The circuit in Figure 14 generates both positive and nega-

tive 5V outputs with a single piece of magnetics. The two

inductors shown are actually just two windings on a stan-

dard Coiltronics inductor. The topology for the 5V output

is a standard buck converter. The –5V topology would be

a simple ﬂyback winding coupled to the buck converter

if C4 were not present. C4 creates a SEPIC (single-ended

primary inductance converter) topology which improves

regulation and reduces ripple current in L1. Without C4,

the voltage swing on L1B compared to L1A would vary

due to relative loading and coupling losses. C4 provides a

low impedance path to maintain an equal voltage swing in

L1B, improving regulation. In a ﬂyback converter, during

switch on-time, all the converter’s energy is stored in L1A

only, since no current ﬂows in L1B. At switch off, energy

Thefollowingequationcanbeusedtocalculatemaximum

load current for the positive-to-negative converter:

⎡

⎤

(V )(V_OUT

)

IN

I_P–

(V_OUT)(V – 0.3)

IN

⎢

⎥

2(V_OUT+ V )(f)(L)

IN

⎣

⎦

I_MAX

=

(V_OUT+ V – 0.3)(V_OUT+ V )

IN

F

1766fc

25

LT1766/LT1766-5

APPLICATIONS INFORMATION

I = Maximum rated switch current

mode formula to calculate minimum inductor needed. If

load current is higher, use the continuous mode formula.

P

V = Minimum input voltage

IN

OUT

V

= Output voltage

Output current where continuous mode is needed:

V = Catch diode forward voltage

F

(V )²(I_P)²

0.3 = Switch voltage drop at 1.5A

IN

I_CONT

>

4(V + V_OUT)(V + V_OUT+ V )

Example: with V

= 5.5V, V

MAX

= 12V, L = 18μH,

OUT

IN

F

IN(MIN)

V = 0.63V, I = 1.5A: I = 0.280A.

F

P

Minimum inductor discontinuous mode:

2(V_OUT)(I_OUT

(f)(I_P)²

)

OUTPUT DIVIDER

L_MIN

=

Refer to Applications Information Feedback Pin Functions

to calculate R1 and R2 for the (negative) output voltage

(from Table 1).

Minimum inductor continuous mode:

(V )(V_OUT

)

IN

†

D2

L_MIN

=

1N4148W

⎡

⎤

⎛

⎝

(V_OUT+ V )⎞

F

2(f)(V + V_OUT) I_P–I_OUT1+

⎜

⎟

IN

⎢

⎣

⎥

⎦

C2

L1*

V

IN

⎠

0.33μF

†

18μH

INPUT

BOOST

LT1766

V

5.5V TO

48V

V

SW

FB

IN

For a 40V to –12V converter using the LT1766 with peak

switch current of 1.5A and a catch diode of 0.63V:

R1

44.2k

GND

V

C

C1

C3

+

D1

100μF

25V

2.2μF

100V

CER

(40)²(1.5)²

4(40 + 12)(40 + 12 + 0.63)

10MQO60N

C

TANT

I_CONT

>

= 0.573A

R2

4.99k

C

R

F

OUTPUT**

–12V, 0.25A

1766 F15

For a load current of 0.25A, this says that discontinuous

mode can be used and the minimum inductor needed is

found from:

* INCREASE L1 TO 30μH OR 60μH FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

†

FOR V > 44V AND V

= –12V, ADDITIONAL VOLTAGE DROP IN THE

IN

OUT

PATH OF D2 IS REQUIRED TO ENSURE BOOST PIN MAXIMUM RATING IS

2(12)(0.25)

NOT EXCEEDED. SEE APPLICATIONS INFORMATION (BOOST PIN VOLTAGE)

L_MIN

=

= 13.3μH

(200 •10³)(1.5)²

Figure 15. Positive-to-Negative Converter

In practice, the inductor should be increased by about

30% over the calculated minimum to handle losses and

variations in value. This suggests a minimum inductor of

18μH for this application.

Inductor Value

The criteria for choosing the inductor is typically based on

ensuring that peak switch current rating is not exceeded.

This gives the lowest value of inductance that can be

used, but in some cases (lower output load currents) it

may give a value that creates unnecessarily high output

ripple voltage.

Ripple Current in the Input and Output Capacitors

Positive-to-negative converters have high ripple current

in the input capacitor. For long capacitor lifetime, the RMS

value of this current must be less than the high frequency

ripplecurrentratingofthecapacitor.Thefollowingformula

willgiveanapproximatevalueforRMSripplecurrent. This

formula assumes continuous mode and large inductor

value. Small inductors will give somewhat higher ripple

current, especially in discontinuous mode. The exact

formulas are very complex and appear in Application

The difﬁculty in calculating the minimum inductor size

needed is that you must ﬁrst decide whether the switcher

will be in continuous or discontinuous mode at the critical

point where switch current reaches 1.5A. The ﬁrst step is

to use the following formula to calculate the load current

above which the switcher must use continuous mode. If

your load current is less than this, use the discontinuous

1766fc

26

LT1766/LT1766-5

APPLICATIONS INFORMATION

Note 44, pages 29 and 30. For our purposes here a fudge

factor (ff) is used. The value for ff is about 1.2 for higher

load currents and L ≥15μH. It increases to about 2.0 for

smaller inductors at lower load currents.

Keep in mind that during start-up and output overloads,

average diode current may be much higher than with nor-

mal loads. Care should be used if diodes rated less than

1A are used, especially if continuous overload conditions

must be tolerated.

V_OUT

Input Capacitor I_RMS= (ff)(I_OUT

)

BOOST Pin Voltage

V

IN

ff = 1.2 to 2.0

To ensure that the BOOST pin voltage does not exceed its

absolute maximum rating of 68V with respect to device

GND pin voltage, care should be taken in the generation of

boost voltage. For the conventional method of generating

boostvoltage, showninFigure1, thevoltageattheBOOST

pin during switch on time is approximately given by:

The output capacitor ripple current for the positive-to-

negative converter is similar to that for a typical buck

regulator—it is a triangular waveform with peak-to-peak

value equal to the peak-to-peak triangular waveform of the

inductor. The low output ripple design in Figure 15 places

the input capacitor between V and the regulated negative

IN

V

(GND pin) = (V – V

) + V

GNDPIN C2

BOOST

IN

output. This placement of the input capacitor signiﬁcantly

reduces the size required for the output capacitor (versus

where:

placing the input capacitor between V and ground).

IN

V

= (D2+) – V – (D1+) + V

C2 D2 D1

= voltage across the boost capacitor

The peak-to-peak ripple current in both the inductor and

output capacitor (assuming continuous mode) is:

For the positive-to-negative converter shown in Figure 15,

the conventional Buck output node is grounded (D2+) = 0V

and the catch diode (D1+) is connected to the negative

DC • V

IN

I_P-P

=

f •L

output = V

= –12V. Absolute maximum ratings should

OUT

V_OUT+ V

V_OUT+ V + V

F

DC = Duty Cycle =

also be observed with the GND pin now at –12V. It can be

seen that for V = V :

IN

F

D1

D2

I_P-P

12

I_COUT(RMS) =

V

= (D2+) – (D1+) = |V | = 12V

OUT

C2

The maximum V voltage allowed for the device (GND

IN

The output ripple voltage for this conﬁguration is as low

as the typical buck regulator based predominantly on the

inductor’s triangular peak-to-peak ripple current and the

ESR of the chosen capacitor (see Output Ripple Voltage

in Applications Information).

pin at –12V) is 48V.

The maximum V voltage allowed without exceeding the

IN

BOOST pin voltage absolute maximum rating is given by:

V

= Boost (Max) + (V

) – V

IN(MAX)

GNDPIN C2

= 68 + (–12) – 12 = 44V

Diode Current

To increase usable V voltage, V must be reduced. This

IN

C2

Average diode current is equal to load current. Peak diode

current will be considerably higher.

can be achieved by placing a zener diode V (anode at

Z1

C2+) in series with D2.

Peak diode current:

Note: A maximum limit on V_Z1must be observed to

ensure a minimum V_C2is maintained on the boost

capacitor; referred to as V_BOOST(MIN)in the Electrical

Characteristics.

ContinuousMode =

(V + V_OUT

)

(V )(V_OUT)

IN

2(L)(f)(V + V_OUT)

IN

I_OUT

+

V

IN

2(I_OUT)(V_OUT

(L)(f)

)

DiscontinuousMode =

1766fc

27

LT1766/LT1766-5

PACKAGE DESCRIPTION

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BB

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

1.10

(.0433)

MAX

16 1514 13 12 1110

9

4.30 – 4.50*

(.169 – .177)

0.25

REF

6.60 p0.10

0o – 8o

2.94

(.116)

4.50 p0.10

SEE NOTE 4

0.65

(.0256)

BSC

6.40

(.252)

BSC

2.94

(.116)

0.09 – 0.20

0.50 – 0.75

0.05 – 0.15

(.002 – .006)

0.45 p0.05

(.0035 – .0079)

(.020 – .030)

0.195 – 0.30

(.0077 – .0118)

TYP

1.05 p0.10

NOTE:

0.65 BSC

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

RECOMMENDED SOLDER PAD LAYOUT

2. DIMENSIONS ARE IN

FE16 (BB) TSSOP 0204

5

7

8

1

2

3

4

6

3. DRAWING NOT TO SCALE

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 p.005

.009

(0.229)

REF

.015 p .004

(0.38 p 0.10)

16 15 14 13 12 11 10 9

s 45o

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0o – 8o TYP

.254 MIN

.150 – .165

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

(0.203 – 0.305)

TYP

NOTE:

.0165 p.0015

.0250 BSC

1. CONTROLLING DIMENSION: INCHES

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

GN16 (SSOP) 0204

RECOMMENDED SOLDER PAD LAYOUT

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

1

2

3

4

5

6

7

8

3. DRAWING NOT TO SCALE

1766fc

28

LT1766/LT1766-5

REVISION HISTORY ^{(Revision history begins at Rev C)}

REV

DATE

DESCRIPTION

PAGE NUMBER

C

03/10 Removed LT1766HGN from Order Information

2

1766fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

LT1766/LT1766-5

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

V : 7.3V to 45V/64V, V

LT1074/LT1074HV

4.4A (I ), 100kHz, High Efﬁciency Step-Down DC/DC Converters

: 2.21V, I : 8.5mA,

Q

OUT

IN

OUT(MIN)

I

: 10μA, DD-5/7, TO220-5/7

SD

LT1076/LT1076HV

LT1616

1.6A (I ), 100kHz, High Efﬁciency Step-Down DC/DC Converters

V : 7.3V to 45V/64V, V

SD

: 2.21V, I : 8.5mA,

Q

OUT

IN

OUT(MIN)

I

: 10μA, DD-5/7, TO220-5/7

500mA (I ), 1.4MHz, High Efﬁciency

V : 3.6V to 25V, V

SD

: 1.25V, I : 1.9mA,

Q

OUT

IN

OUT(MIN)

Step-Down DC/DC Converter

I

: <1μA, ThinSOT™

LT1676

60V, 440mA (I ), 100kHz, High Efﬁciency

V : 7.4V to 60V, V

: 1.24V, I : 3.2mA,

OUT(MIN) Q

OUT

IN

Step-Down DC/DC Converter

I : 2.5μA, S8

SD

LT1765

25V, 2.75A (I ), 1.25MHz, High Efﬁciency

V : 3V to 25V, V

: 1.20V, I : 1mA,

OUT

IN

OUT(MIN) Q

Step-Down DC/DC Converter

I : 15μA, S8, TSSOP16E

SD

LT1766

60V, 1.2A (I ), 200kHz, High Efﬁciency

V : 5.5V to 60V, V

: 1.20V, I : 2.5mA,

OUT(MIN) Q

OUT

IN

Step-Down DC/DC Converter

I : 25μA, TSSOP16/E

SD

LT1767

25V, 1.2A (I ), 1.25MHz, High Efﬁciency

V : 3V to 25V, V

: 1.20V, I : 1mA,

OUT(MIN) Q

OUT

IN

Step-Down DC/DC Converter

I : 6μA, MS8/E

SD

LT1776

40V, 550mA (I ), 200kHz, High Efﬁciency

V : 7.4V to 40V, V

: 1.24V, I : 3.2mA,

OUT(MIN) Q

OUT

IN

Step-Down DC/DC Converter

I : 30μA, N8,S8

SD

LT1940

Dual Output 1.4A (I ) Constant 1.1MHz, High Efﬁciency

V : 3V to 25V, V

: 1.20V, I : 2.5mA,

OUT(MIN) Q

OUT ,

IN

Step-Down DC/DC Converter

I : <1μA, TSSOP-16E

SD

LT1956

60V, 1.2A (I ), 500kHz, High Efﬁciency

V : 5.5V to 60V, V

SD

: 1.20V, I : 2.5mA,

Q

OUT

IN

OUT(MIN)

Step-Down DC/DC Converter

I

: 25μA, TSSOP16/E

LT1976

60V, 1.2A (I ), 200kHz, Micropower (I = 100μA), High Efﬁciency

V : 3.3V to 60V, V

: 1.20V, I : 100μA,

Q

OUT

Q

IN

SD

Step-Down DC/DC Converter

I

: <1μA, TSSOP16/E

LT3010

80V, 50mA, Low Noise Linear Regulator

V : 1.5V to 80V, V

: 1.28V, I : 30μA,

Q

IN

SD

I

: <1μA, MS8E

LTC3412

LTC3414

LT3430/LT3431

LT3433

2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter

V : 2.5V to 5.5V, V

SD

: 0.8V, I : 60μA,

Q

OUT

IN

OUT(MIN)

I

: <1μA, TSSOP16E

4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter

V : 2.3V to 5.5V, V

: 0.8V, I : 64μA,

Q

OUT

IN

SD

I

: <1μA, TSSOP20E

60V, 2.75A (I ), 200kHz/500kHz, High Efﬁciency

V : 5.5V to 60V, V

: 1.20V, I : 2.5mA,

OUT

IN

OUT(MIN) Q

Step-Down DC/DC Converters

I : 30μA, TSSOP16E

SD

High Voltage, Micropower (I = 100μA), Buck-Boost DC/DC Converter

V : 4V to 60V, I : 100μA, 500mA Switch Current,

Q

IN

Q

TSSOP16E

LTC3727/LTC3727-1 36V, 500kHz, High Efﬁciency Step-Down DC/DC Controllers

V : 4V to 36V, V

SD

: 0.8V, I : 670μA,

IN

OUT(MIN) Q

I

: 20μA, QFN-32, SSOP-28

1766fc

LT/TP 0310 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1766EGN-5-TR
厂家：	Linear
描述：	5.5V to 60V 1.5A, 200kHz Step-Down Switching Regulator 5.5V至60V 1.5A ， 200kHz的降压型开关稳压器稳压器开关
文件：	总30页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1766EGN-5-TR [Linear]

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