LT1715CMS [Linear]
4ns, 150MHz Dual Comparator with Independent Input/Output Supplies; 为4ns ， 150MHz的双通道比较器，带有独立的输入/输出电源
| 型号： | LT1715CMS |
| 厂家： | 
Linear |
| 描述： | 4ns, 150MHz Dual Comparator with Independent Input/Output Supplies |
| 文件： | 总16页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1715
4ns, 150MHz
Dual Comparator with
Independent Input/Output Supplies
U
FEATURES
DESCRIPTIO
The LT®1715 is an UltraFastTM dual comparator optimized
for low voltage operation. Separate supplies allow inde-
■
UltraFast: 4ns at 20mV Overdrive
■
150MHz Toggle Frequency
■
Separate Input and Output Power Supplies
Low Power: 4.6mA per Comparator at 3V
Pinout Optimized for High Speed Use
Output Optimized for 3V and 5V Supplies
TTL/CMOS Compatible Rail-to-Rail Output
Input Voltage Range Extends 100mV
Below Negative Rail
pendent analog input ranges and output logic levels with
no loss of performance. The input voltage range extends
from100mVbelowVEE to1.2VbelowVCC. Internalhyster-
esis makes the LT1715 easy to use even with slow moving
input signals. The rail-to-rail outputs directly interface to
TTL and CMOS. The symmetric output drive results in
similar rise and fall times that can be harnessed for analog
applications or for easy translation to other single supply
logic levels.
■
■
■
■
■
■
Internal Hysteresis with Specified Limits
U
The LT1715 is available in the 10-pin MSOP package. The
pinout of the LT1715 minimizes parasitic effects by plac-
ing the most sensitive inputs away from the outputs,
shielded by the power rails.
APPLICATIO S
■
High Speed Differential Line Receivers
■
Level Translators
■
Window Comparators
Crystal Oscillator Circuits
Threshold Detectors/Discriminators
High Speed Sampling Circuits
Delay Lines
For a dual/quad single supply comparator with similar
propagation delay, see the LT1720/LT1721. For a single
comparatorwithsimilarpropagationdelay,seetheLT1719.
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
■
U
TYPICAL APPLICATIO
100MHz Dual Differential Line Receiver
Line Receiver Response to 100MHz Clock,
50MHz Data Both with 25mVP-P Inputs
5V
3V
3V
+
–
CLOCK OUT
1V/DIV
OUT A
OUT B
IN A
IN B
0V
3V
DATA OUT
0V
1V/DIV
+
–
FET PROBES
5ns/DIV
1715 TA02
1715 TA01
–5V
1
LT1715
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
Supply Voltage
+VS to GND .......................................................... 7V
V
CC to VEE........................................................ 13.2V
TOP VIEW
LT1715CMS
LT1715IMS
+IN A
–IN A
–IN B
+IN B
1
2
3
4
5
10
9
V
CC
S
OUT A
OUT B
GND
+VS to VEE ....................................................... 13.2V
VEE to GND ....................................... –13.2V to 0.3V
Input Current (+IN, –IN) ................................... ±10mA
Output Current (Continuous) ............................ ±20mA
Operating Temperature Range ................ –40°C to 85°C
Specified Temperature Range (Note 2)... –40°C to 85°C
Junction Temperature.......................................... 150°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
A
+V
8
7
6
B
V
EE
MS10 PACKAGE
10-LEAD PLASTIC MSOP
MS10 PART MARKING
TJMAX = 150°C, θJA = 120°C/ W (NOTE 3)
LTVQ
LTVV
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV,
unless otherwise specified.
SYMBOL
– V
PARAMETER
CONDITIONS
MIN
2.7
TYP
MAX
12
UNITS
V
Input Supply Voltage
Output Supply Voltage
Input Voltage Range
Input Trip Points
●
●
●
V
V
V
CC
EE
+V
2.7
6
S
V
(Note 4)
(Note 5)
V
– 0.1
V
– 1.2
CC
CMR
EE
+
V
V
●
●
–1.5
–5.5
5.5
1.5
mV
mV
TRIP
TRIP
–
V
Input Offset Voltage
(Note 5)
(Note 5)
0.4
2.5
3.5
mV
mV
OS
●
●
●
●
●
●
●
V
Input Hysteresis Voltage
Input Offset Voltage Drift
Input Bias Current
2
3.5
10
6
mV
µV/°C
µA
HYST
∆V /∆T
OS
I
I
–6
–2.5
0.2
70
0
B
Input Offset Current
0.6
µA
OS
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Gain
(Note 6)
(Note 7)
(Note 8)
60
65
dB
80
dB
A
V
V
∞
V
+
Output High Voltage
I
I
= 4mA, V = V
+ 20mV
●
●
+V – 0.4
V
V
OH
SOURCE
IN
TRIP
–
S
Output Low Voltage
= 10mA, V = V
– 20mV
0.4
OL
SINK
IN
TRIP
f
t
Maximum Toggle Frequency
Propagation Delay
(Note 9)
150
4
MHz
MAX
PD20
V
V
= 20mV (Note 10),
EE
2.8
2.8
6
7
ns
ns
OVERDRIVE
CC
= 5V, V = –5V
●
●
V
V
= 20mV, V = 5V, V = 0V
4.4
4.8
ns
OVERDRIVE
OVERDRIVE
CC
EE
= 20mV, V = 3V, V = 0V
3
3
6.5
7.5
ns
ns
CC
EE
t
t
Propagation Delay
V
= 5mV, V = 0V (Notes 10, 11)
6
9
12
ns
ns
PD5
OVERDRIVE
EE
●
●
+
–
Propagation Delay Skew
(Note 12) Between t /t , V = 0V
0.5
1.5
ns
SKEW
PD PD
EE
2
LT1715
ELECTRICAL CHARACTERISTICS
unless otherwise specified.
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = –5V, +VS = 5V, VCM = 1V, COUT = 10pF, VOVERDRIVE = 20mV,
SYMBOL
∆t
PARAMETER
CONDITIONS
MIN
TYP
0.3
2
MAX
UNITS
ns
Differential Propagation Delay
Output Rise Time
(Note 13) Between Channels
10% to 90%
●
1
PD
t
t
t
ns
r
f
Output Fall Time
90% to 10%
2
ns
+
–
Output Timing Jitter
V
= 1.2V (6dBm), Z = 50Ω
t
15
11
ps
RMS
ps
RMS
JITTER
IN
P-P
IN
PD
PD
f = 20MHz (Note 14)
t
I
I
I
Positive Input Stage Supply Current
(per Comparator)
+V = V = 5V, V = –5V
●
●
●
●
●
●
1
2
mA
mA
mA
mA
mA
mA
CC
S
CC
EE
+V = V = 3V, V = 0V
0.9
1.6
S
CC
EE
Negative Input Stage Supply Current
(per Comparator)
+V = V = 5V, V = –5V
–4.8
–3.8
–2.9
–2.4
4.6
EE
S
S
CC
EE
+V = V = 3V, V = 0V
S
CC
EE
Positive Output Stage Supply Current
(per Comparator)
+V = V = 5V, V = –5V
7.5
6
S
CC
EE
V = V = 3V, V = 0V
3.7
S
CC
EE
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 8: Because of internal hysteresis, there is no small-signal region in
which to measure gain. Proper operation of internal circuity is ensured by
measuring V and V with only 20mV of overdrive.
OH
OL
Note 2: The LT1715C is guaranteed to meet specified performance from
0°C to 70°C. The LT1715C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LT1715I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 9: Maximum toggle rate is defined as the highest frequency at which
a 100mV sinusoidal input results in an error free output toggling to greater
than 4V when high and to less than 1V when low on a 5V output supply.
Note 10: Propagation delay measurements made with 100mV steps.
±
Note 3: Thermal resistances vary depending upon the amount of PC board
Overdrive is measured relative to V
.
TRIP
2
metal attached to Pin 5 of the device. θ is specified for a 2500mm 3/32"
JA
Note 11: t cannot be measured in automatic handling equipment with
PD
2
FR-4 board covered with 2oz copper on both sides and with 100mm of
low values of overdrive. The LT1715 is 100% tested with a 100mV step
and 20mV overdrive. Correlation tests have shown that t limits can be
guaranteed with this test.
Note 12: Propagation Delay Skew is defined as:
copper attached to Pin 5. Thermal performance can be improved beyond
the given specification by using a 4-layer board or by attaching more metal
area to Pin 5.
Note 4: If one input is within these common mode limits, the other input
can go outside the common mode limits and the output will be valid.
PD
t
= |t
– t
|
PDHL
SKEW
PDLH
Note 13: Differential propagation delay is defined as the larger of the two:
Note 5: The LT1715 comparator includes internal hysteresis. The trip
∆t
PDLH
∆t
PDHL
= |t
= |t
– t
PDLHB
– t
PDHLB
|
|
PDLHA
PDHLA
points are the input voltage needed to change the output state in each
+
–
direction. The offset voltage is defined as the average of V
while the hysteresis voltage is the difference of these two.
and V
,
TRIP
TRIP
Note 14: Package inductances combined with asynchronous activity on
the other channel can increase the output jitter. See Channel Interactions
in Applications Information. Specification above is with one channel active
only.
Note 6: The common mode rejection ratio is measured with V = 5V,
CC
V
V
= –5V and is defined as the change in offset voltage measured from
EE
= –5.1V to V = 3.8V, divided by 8.9V.
CM
CM
Note 7: The power supply rejection ratio is measured with V = 1V and is
CM
defined as the worst of: the change in offset voltage from V = +V =
CC
S
2.7V to V = +V = 6V (with V = 0V) divided by 3.3V or the change in
CC
S
EE
offset voltage from V = 0V to V = –6V (with V = +V = 6V) divided
EE
EE
CC
S
by 6V.
3
LT1715
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Input Offset and Trip Voltages
vs Supply Voltage
Input Offset and Trip Voltages
vs Temperature
Input Common Mode Limits
vs Temperature
3
2
3
2
4.2
4.0
+V = V = 5V
+
S CC
= 1V
CM
= –5V
EE
+V = V = 5V
S
EE
CC
= –5V
V
TRIP
V
V
V
+
–
V
TRIP
3.8
3.6
1
0
1
V
OS
V
OS
0
–4.8
–5.0
–5.2
–1
–2
–3
–1
–2
–3
–
V
TRIP
V
TRIP
T
V
V
= 25°C
A
= 1V
CM
= GND
EE
–5.4
–60 –40 –20
0
20 40 60 80 100 120 140
4.5
5.5 6.0
50
TEMPERATURE (°C)
100 125
2.5 3.0
3.5 4.0
5.0
–50 –25
0
25
75
TEMPERATURE (°C)
SUPPLY VOLTAGE, V = +V (V)
CC
S
1715 G02
1715 G01
1715 G03
Input Current
vs Differential Input Voltage
Quiescent Supply Current
vs Temperature
Quiescent Supply Current
vs Supply Voltage
2
1
6
5
8
6
V
CC
V
EE
= +V = 5V
S
= –5V
T
= 25°C
EE
T
V
V
= 25°C
A
A
I , OUTPUT HIGH
S
V
= GND
= +V = 5V
CC
S
= –5V
EE
4
0
I
S
4
3
I , OUTPUT LOW
S
–1
–2
–3
–4
–5
–6
–7
2
2
I
CC
1
I
CC
0
0
–1
–2
–3
–4
–2
–4
–6
I
, OUTPUT LOW
EE
I
EE
I
EE
, OUTPUT HIGH
–25
0
50
75 100 125
4
7
–5 –4 –3 –2 –1
0
5
–50
25
0
2
3
5
6
1
2
3
4
1
DIFFERENTIAL INPUT VOLTAGE (V)
SUPPLY VOLTAGE, V = +V (V)
TEMPERATURE (°C)
CC
S
1715 G04
1715 G05
1715 G06
Output Low Voltage
vs Load Current
Output High Voltage
vs Load Current
Supply Current
vs Toggle Frequency
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0.5
0.4
0.3
0.2
0.1
0
30
25
VALID
TOGGLING
INCOMPLETE
OUTPUT TOGGLING
V
= +V = 5V, UNLESS
V
= +V = 5V, UNLESS
CC S
CC
S
125°C
OTHERWISE NOTED
OTHERWISE NOTED
+V = 2.7V
S
V
= –10mV
V
= 10mV
IN
IN
125°C
C
LOAD
= 20pF
C
= 10pF
LOAD
–55°C
20
–55°C
25°C
15
10
25°C
C
LOAD
= 0pF
125°C
T
= 25°C
IN
A
V
= ±50mV SINUSOID
5
0
125°C
+V = 2.7V
+V = V = 5V
V
S
EE
CC
= GND
S
0
4
8
12
16
20
0
4
8
12
16
20
175
200 225
0
25 50 75 100 125 150
OUTPUT SOURCE CURRENT (mA)
TOGGLE FREQUENCY (MHz)
OUTPUT SINK CURRENT (mA)
1715 G08
1715 G07
1715 G09
4
LT1715
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Propagation Delay
vs Overdrive
Propagation Delay
vs Temperature
Propagation Delay
vs Supply Voltage
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
5.5
5.0
4.5
4.0
3.5
8
7
6
5
4
3
t
C
= 10pF
T
V
C
= 25°C
PDLH
STEP
LOAD
T
= 25°C
STEP
A
A
V
V
= 100mV
= 100mV
= 100mV
STEP
LOAD
= 10pF
OVERDRIVE = 20mV
C
= 10pF
LOAD
V
V
= +V = 3V
S
CC
EE
= 0V
V
CC
V
= +V = 3V
EE
OVERDRIVE = 5mV
S
t
PDLH
= 0V
V
= GND
EE
t
PDHL
t
t
PDLH
t
PDLH
PDHL
t
PDLH
t
PDHL
V
EE
= –5V
V
CC
V
= +V = 5V
EE
V
= +V = 5V
S
S
CC
OVERDRIVE = 20mV
= –5V
V
= –5V
t
EE
PDHL
10
20
OVERDRIVE (mV)
40
–25
0
50
75 100 125
4.5
5.5
+
6.0
0
50
–50
25
2.5 3.0
3.5 4.0
5.0
30
TEMPERATURE (°C)
SUPPLY VOLTAGE, +V = V OR V (V)
S
CC
1715 G10
1715 G11
1715 G12
Maximum Toggle Rate
vs Input Amplitude
Maximum Toggle Rate
vs Temperature
Maximum Toggle Rate
vs Supply Voltage
250
230
210
190
170
150
130
110
90
180
250
225
200
175
150
125
100
75
T
= 25°C
T
= 25°C
A
A
TOGGLING FROM
+V = V = 5V
V = ±50mV SINUSOID
160
140
120
100
80
S
EE
CC
IN
1V TO +V – 1V
V
C
= GND
+V = V = 5V
S
S
EE
LOAD
LOAD
CC
= 10pF
V
C
R
= –5V
LOAD
= 10pF
= 500Ω
TOGGLING FROM
20% TO 80% OF +V
S
60
T
= 25°C
40
A
V
= ±50mV SINUSOID
IN
EE
20
V
C
= GND
= 10pF
70
LOAD
0
50
50
1
10
INPUT SINUSOID AMPLITUDE (mV)
100
–50
0
25
50
75
125
–25
100
4
2
3
5
6
TEMPERATURE (°C)
+V = V SUPPLY VOLTAGE (V)
S
CC
1715 G13
1715 G14
1715 G15
Maximum Toggle Rate
vs Load Capacitance
Propagation Delay
Response to 150MHz 25mVP-P
Sine Wave Driving 10pF
vs Load Capacitance
250
225
200
175
150
125
100
75
8
7
6
5
4
3
NA
T
= 25°C
IN
T
= 25°C
STEP
A
A
25mVP-P
20mV/DIV
1V/DIV
V
= ±50mV SINUSOID
V
= 100mV
+V = V = 5V
V
OVERDRIVE = 20mV
+V = V = 5V
S
EE
CC
= GND
5V
S
EE
CC
= –5V
V
OUT A
0V
RISING EDGE
(t
)
PDLH
FALLING EDGE
(t
)
PDHL
FET PROBES
VCC = 5V
2.5ns/DIV
1715 G18
V
EE = –5V
50
+VS = 5V
VCM = 0V
10
20
40
0
5
10 15 20 25 30 35 40 45 50
OUTPUT CAPACITANCE (pF)
1715 G16
0
50
30
OUTPUT LOAD CAPACITANCE (pF)
1715 G17
5
LT1715
U
U
U
PI FU CTIO S
+IN A (Pin 1): Noninverting Input of Comparator A.
–IN A (Pin 2): Inverting Input of Comparator A.
–IN B (Pin 3): Inverting Input of Comparator B.
+IN B (Pin 4): Noninverting Input of Comparator B.
GND (Pin 6): Ground for Output Stage.
OUT B (Pin 7): Output of Comparator B.
OUT A (Pin 8): Output of Comparator A.
+VS (Pin 9): Positive Supply Voltage for Output Stage.
V
EE (Pin 5): Negative Supply Voltage for Input Stage and
V
CC (Pin 10): Positive Supply Voltage for Input Stage.
Substrate.
TEST CIRCUITS
±VTRIP Test Circuit
LTC203
BANDWIDTH-LIMITED TRIANGLE WAVE
1kHz, V ±7.5V
~
CM
14
15
3
2
V
CC
+
0.1µF
1000 × V
TRIP
50k
1µF
10nF
10k
+
16
9
1
8
DUT
50Ω
1/2 LT1715
–
50Ω
1/2 LT1112
200k
1000 × V
HYST
+
–
V
CM
11
10
6
7
1000 × V
OS
10k
LTC203
3
2
14
15
–
1/2 LT1638
+
1000 × V
TRIP
100k
100k
1µF
10nF
–
1
8
16
9
+
–
2.4k
100k
100k
1/2 LT1638
1/2 LT1112
+
–
0.15µF
6
7
11
10
1715 TC01
NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V.
200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS
WHEN DUT IS NOT POWERED
6
LT1715
TEST CIRCUITS
Response Time Test Circuit
+V – V
s
CM
0V
0.01µF
0.01µF
V
– V
CM
CC
–100mV
25Ω
+
DUT
1/2 LT1715
10× SCOPE PROBE
25Ω
(C ≈ 10pF)
50k
IN
–
0.1µF
130Ω
50Ω
V1*
PULSE
IN
2N3866
0V
V
– V
1N5711
EE
CM
–3V
–V
+
CM
50Ω
400Ω
750Ω
*V1 = –1000 • (OVERDRIVE + V
)
TRIP
NOTE: RISING EDGE TEST SHOWN.
1715 TC02
FOR FALLING EDGE, REVERSE LT1719 INPUTS
–5V
W U U
U
APPLICATIO S I FOR ATIO
2.7V TO 6V
Power Supply Configurations
5V
The LT1715 has separate supply pins for the input and
output stages that allow flexible operation, accommodat-
ing separate voltage ranges for the analog input and the
outputlogic.Ofcourse,asingle3V/5Vsupplymaybeused
by tying +VS and VCC together as well as GND and VEE.
V
V
CC
CC
EE
3V
+V
+
–
+
–
+V
S
S
GND
GND
V
V
EE
–5V
Theminimumvoltagerequirementcanbesimplystatedas
boththeoutputandtheinputstagesneedatleast2.7Vand
the VEE pin must be equal to or less than ground.
Single Supply
±5V Input, 3V Output Supplies
12V
The following rules must be adhered to in any
configuration:
V
V
CC
CC
5V
+V
3V
+V
+
–
+
–
S
S
2.7V ≤ (VCC – VEE) ≤ 12V
2.7V ≤ (+VS – GND) ≤ 6V
(+VS – VEE) ≤ 12V
GND
GND
V
V
EE
EE
–5.2V
1715 F01
V
EE ≤ Ground
12V Input, 5V Output Supplies Front End Entirely Negative
Although the ground pin need not be tied to system
ground, most applications will use it that way. Figure 1
shows three common configurations. The final one is
uncommon, but it will work and may be useful as a level
translator; the input stage is run from –5.2V and ground
while the output stage is run from 3V and ground. In this
case the common mode input voltage range does not
include ground, so it may be helpful to tie VCC to 3V.
Conversely, VCC may also be tied below ground, as long as
the above rules are not violated.
Figure 1. Variety of Power Supply Configurations
Input Voltage Considerations
The LT1715 is specified for a common mode range of
–100mV to 3.8V when used with a single 5V supply. A
more general consideration is that the common mode
rangeis100mVbelowVEE to1.2VbelowVCC.Thecriterion
for this common mode limit is that the output still
7
LT1715
W U U
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APPLICATIO S I FOR ATIO
responds correctly to a small differential input signal. If
oneinputiswithinthecommonmodelimit, theotherinput
signal can go outside the common mode limits, up to the
absolute maximum limits, and the output will retain the
correct polarity.
equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection cir-
cuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltages are at the absolute
maximum ratings.
When either input signal falls below the negative common
mode limit, the internal PN diode formed with the sub-
strate can turn on, resulting in significant current flow
through the die. An external Schottky clamp diode
between the input and the negative rail can speed up
recovery from negative overdrive by preventing the sub-
strate diode from turning on.
The LT1715 input stage has general purpose internal ESD
protection for the human body model. For use as a line
receiver, additional external protection may be required.
As with most integrated circuits, the level of immunity to
ESD is much greater when residing on a printed circuit
boardwherethepowersupplydecouplingcapacitancewill
limit the voltage rise caused by an ESD pulse.
When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least –400mV common mode.
However, the offset and hysteresis in this mode will
increasedramatically,toasmuchas15mVeach.Theinput
bias currents will also increase.
Input Bias Current
Inputbiascurrentismeasuredwithbothinputsheldat1V.
As with any PNP differential input stage, the LT1715 bias
current flows out of the device. It will go to zero on the
higherofthetwoinputsanddoubleonthelowerofthetwo
inputs. With more than two diode drops of differential
input voltage, the LT1715’s input protection circuitry
activates, and current out of the lower input will increase
an additional 30% and there will be a small bias current
intothehigherofthetwoinputpins, of4µAorless. Seethe
Typical Performance curve “Input Current vs Differential
Input Voltage.”
When one input signal goes above the common mode
range without exceeding a diode drop above the input
supply rail, the input stage will remain biased and the
comparator will maintain correct output polarity. Above
this voltage, the input stage current source will saturate
completely and the ESD protection diode will forward
conduct. Once the aberrant input falls back into the com-
monmoderange,thecomparatorwillrespondcorrectlyto
valid input signals within less than 10ns.
High Speed Design Considerations
When both input signals are above the positive common
modelimit,theinputstagewillgetdebiasedandtheoutput
polarity will be random. However, the internal hysteresis
will hold the output to a valid logic level. When at least one
of the inputs returns to within the common mode limits,
recovery from this state will take as long as 1µs.
Applicationofhighspeedcomparatorsisoftenplaguedby
oscillations. The LT1715 has 4mV of internal hysteresis,
which will prevent oscillations as long as parasitic output
to input feedback is kept below 4mV. However, with the
2V/ns slew rate of the LT1715 outputs, a 4mV step can be
created at a 100Ω input source with only 0.02pF of output
to input coupling. The LT1715’s pinout has been arranged
tominimizeproblemsbyplacingthesensitiveinputsaway
from the outputs, shielded by the power rails. The input
and output traces of the circuit board should also be
separated, and the requisite level of isolation is readily
achieved if a topside ground plane runs between the
output and the inputs. For multilayer boards where the
ground plane is internal, a topside ground or supply trace
should be run between the inputs and the output.
The propagation delay does not increase significantly
when driven with large differential voltages, but with low
levels of overdrive, an apparent increase may be seen with
large source resistances due to an RC delay caused by the
2pF typical input capacitance.
Input Protection
The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
8
LT1715
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APPLICATIONS INFORMATION
ThegroundpinoftheLT1715candisturbthegroundplane
potential while toggling due to the extremely fast on and
offtimesoftheoutputstage. Therefore, usingagroundfor
input termination or filtering that is separate from the
LT1715 Pin 6 ground can be highly beneficial. For ex-
ample, a ground plane tied to Pin 6 and directly adjacent
to a 1" long input trace can capacitively couple 4mV of
disturbance into the input. In this scenario, cutting the
ground plane between the GND pin and the inputs will cut
the capacitance and the disturbance down substantially.
maintain signal integrity. The LT1715 can drive DC termi-
nations of 200Ω or more, but lower characteristic imped-
ance traces can be used with series termination or AC
termination topologies.
Channel Interactions
The LT1715’s two channels are designed to be entirely
independent. However, at frequencies approaching and
exceeding 100MHz, bond wire inductance begins to inter-
fere with overlapping switching edges on the two chan-
nels. Figure 3 shows one channel of the comparator
toggling at 100MHz with the other channel driven low with
the scope set to display infinite persistence. Jitter is
almost nonexistent. Figure 4 displays the same channel at
100MHz with infinite persistence, but the other channel of
the comparator is toggling as well at frequencies swept
from 60MHz to 160MHz. Jitter will occur as rising and
fallingedgesalignforanynonharmonicornonfundamen-
tal frequency of the high frequency signal.
Figure 2 shows a typical topside layout of the LT1715 on
such a multilayer board. Shown is the topside metal etch
including traces, pin escape vias, and the land pads for an
MS10 LT1715 and its adjacent X7R 10nF bypass capaci-
tors in the 0805 case.
The ground trace from Pin 6 runs under the device up to
the bypass capacitor, shielding the inputs from the
outputs. Note the use of a common via for the LT1715 and
the bypass capacitors, which minimizes interference from
highfrequencyenergyrunningaroundthegroundplaneor
power distribution traces.
–5V
The supply bypass should include an adjacent 10nF
ceramic capacitor and a 2.2µF tantalum capacitor no
farther than 5cm away; use more capacitance on +VS if
driving more than 4mA loads. To prevent oscillations, it is
helpful to balance the impedance at the inverting and
noninverting inputs; source impedances should be kept
low, preferably 1kΩ or less.
OUT A
1V/DIV
0V
5ns/DIV
1715 F03
The outputs of the LT1715 are capable of very high slew
rates. To prevent overshoot, ringing and other problems
with transmission line effects, keep the output traces
shorter than 10cm, or be sure to terminate the lines to
Figure 3. Clean 100MHz Toggling
–5V
OUT A
1V/DIV
0V
1715 F02
5ns/DIV
1715 F04
Figure 2. Typical Topside Metal for Multilayer PCB Layouts
Figure 4. 100MHz Jitter with Both Channels Driven
9
LT1715
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APPLICATIO S I FOR ATIO
At frequencies well beyond 100MHz, the toggling of one
channel may be impaired by toggling on the other. This is
arathercomplexinteractionofsupplybypassingandbond
inductance, and it cannot be entirely prevented. However,
good bypassing and board layout techniques will effec-
tively minimize it.
V
OH
V
HYST
+
–
(= V
– V
)
TRIP
TRIP
V
/2
HYST
Power Supply Sequencing
V
OL
+
–
∆V = V – V
IN
IN
IN
The LT1715 is designed to tolerate any power supply
sequencing at system turn-on and power down. In any of
the previously shown power supply configurations, the
various supplies can activate in any order without exces-
sive current drain by the LT1715.
0
–
+
V
V
TRIP
V
TRIP
+
–
V
+ V
2
TRIP
TRIP
=
OS
1715 F05
Figure 5. Hysteresis I/O Characteristics
As always, the Absolute Maximum Ratings must not be
exceeded, either on the power supply terminals or the
input terminals. Power supply sequencing problems can
occur when input signals are powered from supplies that
are independent of the LT1715’s supplies. No problems
should occur if the input signals are powered from the
same VCC and VEE supplies as the LT1715.
LT1715 is the significant reduction in these effects, which
is important whenever an LT1715 is used to detect a
threshold crossing in one direction only. In such a case,
the relevant trip point will be all that matters, and a stable
offset voltage with an unpredictable level of hysteresis, as
seenincompetingcomparators, isuseless. TheLT1715is
many times better than prior generation comparators in
these regards. In fact, the CMRR and PSRR tests are
performed by checking for changes in either trip point to
the limits indicated in the specifications table. Because the
offset voltage is the average of the trip points, the CMRR
and PSRR of the offset voltage is therefore guaranteed to
beatleastasgoodasthoselimits. Thismorestringenttest
also puts a limit on the common mode and power supply
dependence of the hysteresis voltage.
Unused Comparators
Ifacomparatorisunused, itsoutputshouldbeleftfloating
tominimizeloadcurrent. Theunusedinputscanbetiedoff
to the rails and power consumption can be further mini-
mized if the inputs are connected to the power rails to
induce an output low. Connecting the inverting input to
VCC and the noninverting input to VEE will likely be the
easiest method.
Additionalhysteresismaybeaddedexternally. Therail-to-
railoutputsoftheLT1715makethismorepredictablethan
with TTL output comparators due to the LT1715’s small
variability of VOH (output high voltage).
Hysteresis
The LT1715 includes internal hysteresis, which makes it
easier to use than many other similar speed comparators.
The input-output transfer characteristic is illustrated in
Figure 5 showing the definitions of VOS and VHYST based
upon the two measurable trip points. The hysteresis band
makes the LT1715 well behaved, even with slowly moving
inputs.
To add additional hysteresis, set up positive feedback by
adding additional external resistor R3 as shown in Fig-
ure 6. Resistor R3 adds a portion of the output to the
threshold set by the resistor string. The LT1715 pulls the
outputs to +VS and ground to within 200mV of the rails
withlightloads,andtowithin400mVwithheavyloads.For
the load of most circuits, a good model for the voltage on
the right side of R3 is 300mV or +VS – 300mV, for a total
voltageswingof(+VS–300mV)–(300mV)=+VS–600mV.
The exact amount of hysteresis will vary from part to part
as indicated in the specifications table. The hysteresis
level will also vary slightly with changes in supply voltage
and common mode voltage. A key advantage of the
10
LT1715
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APPLICATIONS INFORMATION
V
REF
R1mayalsoberequired.Notethatthecurrentsthroughthe
R1/R2biasstringshouldbemanytimestheinputcurrents
oftheLT1715.For5%accuracy,thecurrentmustbeatleast
20 times the input current, more for higher accuracy.
R3
R2
+
1/2 LT1715
R1
–
Interfacing the LT1715 to ECL
The LT1715’s comparators can be used in high speed
applications where Emitter-Coupled Logic (ECL) is de-
ployed. To interface the output of the LT1715 to ECL logic
inputs, standard TTL/CMOS to ECL level translators such
as the 10H124, 10H424 and 100124 can be used. These
components come at a cost of a few nanoseconds addi-
tional delay as well as supply currents of 50mA or more,
andareonlyavailableinquads. Afaster, simplerandlower
power translator can be constructed with resistors as
shown in Figure 8.
INPUT
1715 F06
Figure 6. Additional External Hysteresis
Withthisinmind, calculationoftheresistorvaluesneeded
isatwo-stepprocess.First,calculatethevalueofR3based
on the additional hysteresis desired, the output voltage
swing and the impedance of the primary bias string:
R3 = (R1 R2)(+VS – 0.6V)/(additional hysteresis)
Additional hysteresis is the desired overall hysteresis less
the internal 4mV hysteresis.
Figure 8a shows the standard TTL to Positive ECL (PECL)
resistiveleveltranslator.Thistranslatorcannotbeusedfor
theLT1715,orwithCMOSlogic,becauseitdependsonthe
820Ωresistortolimittheoutputswing(VOH)oftheall-NPN
TTL gate with its so-called totem-pole output. The LT1715
is fabricated in a complementary bipolar process and the
output stage has a PNP driver that pulls the output nearly
all the way to the supply rail, even when sourcing 10mA.
The second step is to recalculate R2 to set the same
averagethresholdasbefore. Theaveragethresholdbefore
was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is
calculated based on the average output voltage (+VS/2)
and the simplified circuit model in Figure 7. To assure that
the comparator’s noninverting input is, on average, the
same VTH as before:
Figure 8b shows a three resistor level translator for inter-
facing the LT1715 to ECL running off the same supply rail.
No pull-down on the output of the LT1715 is needed, but
pull-down R3 limits the VIH seen by the PECL gate. This is
needed because ECL inputs have both a minimum and
maximum VIH specification for proper operation. Resistor
valuesaregivenforbothECLinterfacetypes;inbothcases
it is assumed that the LT1715 operates from the same
supply rail.
R2′ = (VREF – VTH)/(VTH/R1 + (VTH – VS/2)/R3)
For additional hysteresis of 10mV or less, it is not uncom-
mon for R2′ to be the same as R2 within 1% resistor
tolerances.
This method will work for additional hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3
is low enough to effect the bias string, and adjustment of
V
REF
Figure 8c shows the case of translating to PECL from an
LT1715poweredbya3Vsupplyrail.Again,resistorvalues
are given for both ECL interface types. This time four re-
sistorsareneeded,althoughwith10KH/E,R3isnotneeded.
In that case, the circuit resembles the standard TTL trans-
lator of Figure 8a, but the function of the new resistor, R4,
is much different. R4 loads the LT1715 output when high
so that the current flowing through R1 doesn’t forward
biastheLT1715’sinternalESDclampdiode. Althoughthis
diode can handle 20mA without damage, normal
R2′
V
TH
R3
+V
2
S
V
=
AVERAGE
R1
+
1/2 LT1715
–
1715 F07
Figure 7. Model for Additional Hysteresis Calculations
11
LT1715
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APPLICATIONS INFORMATION
5V
5V
180Ω
270Ω
820Ω
DO NOT USE FOR LT1715
LEVEL TRANSLATION. SEE TEXT
LSTTL
10KH/E
(a) STANDARD TTL TO PECL TRANSLATOR
+V
S
V
CC
R2
R1
+V
R1
R2
R3
S
1/2 LT1715
10KH/E 5V OR 5.2V 510Ω 180Ω 750Ω
100K/E
4.5V
620Ω 180Ω 510Ω
R3
V
EE
(b) LT1715 OUTPUT TO PECL TRANSLATOR
V
ECL
V
3V
CC
R2
R1
R4
V
R1
R2
R3
R4
ECL
1/2 LT1715
10KH/E 5V OR 5.2V 300Ω 180Ω OMIT 560Ω
100K/E
4.5V
330Ω 180Ω 1500Ω 1000Ω
R3
V
EE
(c) 3V LT1715 OUTPUT TO PECL TRANSLATOR
V
+V
S
CC
R4
ECL FAMILY
V
+V
R1
R2
R3
R4
ECL
S
R1
5V
3V
5V
3V
560Ω 270Ω 330Ω 1200Ω
270Ω 510Ω 300Ω 330Ω
680Ω 270Ω 300Ω 1500Ω
330Ω 390Ω 270Ω 430Ω
1715 F08
1/2 LT1715
10KH/E
–5.2V
–4.5V
R2
R3
100K/E
V
EE
V
ECL
(d) LT1715 OUTPUT TO STANDARD ECL TRANSLATOR
Figure 8
operation and performance of the output stage can be
impaired above 100µA of forward current. R4 prevents
this with the minimum additional power dissipation.
Of course, if the VEE of the LT1715 is the same as the ECL
negative supply, the GND pin can be tied to it as well and
+VS grounded. Then the output stage has the same power
rails as the ECL and the circuits of Figure 8b can be used.
Finally, Figure 8d shows the case of driving standard,
negative-rail, ECL with the LT1715. Resistor values are
givenforbothECLinterfacetypesandforbotha5Vand3V
LT1715 supply rail. Again, a fourth resistor, R4 is needed
to prevent the low state current from flowing out of the
LT1715, turning on the internal ESD/substrate diodes.
Resistor R4 again prevents this with the minimum addi-
tional power dissipation.
For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond,
with most layouts. Avoid the temptation to use speedup
capacitors. Not only can they foul up the operation of the
ECL gate because of overshoots, they can damage the
ECL inputs, particularly during power-up of separate
supply configurations.
12
LT1715
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U
The level translator designs assume one gate load. Mul-
tiple gates can have significant IIH loading, and the trans-
missionlineroutingandterminationissuesalsomakethis
case difficult.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single 2.7V
supply, the LT1715 still has a respectable 1.6V of input
common mode range. The differential input voltage range
is rail-to-rail, without the large input currents found in
competing devices. The input stage also features phase
reversal protection to prevent false outputs when the
inputs are driven below the –100mV common mode
voltage limit.
ECL, and particularly PECL, is valuable technology for
high speed system design, but it must be used with care.
With less than a volt of swing, the noise margins need to
be evaluated carefully. Note that there is some degrada-
tion of noise margin due to the ±5% resistor selections
shown. With 10KH/E, there is no temperature compensa-
tion of the logic levels, whereas the LT1715 and the
circuits shown give levels that are stable with tempera-
ture. This will lower the noise margin over temperature.
Insomeconfigurationsitispossibletoaddcompensation
with diode or transistor junctions in series with the
resistors of these networks.
Theinternalhysteresisisimplementedbypositive,nonlin-
ear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
lower output transistors. The output transistors are con-
nected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mVfromtherail, notquitethe50mVor15mVofLinear
Technology’s rail-to-rail amplifiers and other products.
But the output of a comparator is digital, and this output
stagecandriveTTLorCMOSdirectly.ItcanalsodriveECL,
as described earlier, or analog loads.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola,
now ON Semiconductor.
Circuit Description
The block diagram of the LT1715 is shown in Figure 9. The
circuit topology consists of a differential input stage, a
gain stage with hysteresis and a complementary com-
mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.
The bias conditions and signal swings in the output stage
are designed to turn their respective output transistors off
faster than on. This helps minimize the surge of current
from +VS to ground that occurs at transitions, to minimize
+V
S
NONLINEAR STAGE
+
–
V
CC
+
Σ
+IN
–IN
+
–
+
–
A
A
OUT
V1
V2
+
Σ
+
–
V
EE
GND
1715 F09
Figure 9. LT1715 Block Diagram
13
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thefrequency-dependentincreaseinpowerconsumption.
The frequency dependence of the supply current is shown
in the Typical Performance Characteristics.
will easily leave this undesired operating mode no worse
for the wear provided there is adequate heat sinking to
prevent thermal overload. At frequencies well beyond the
maximumtogglerate,thepartwilltogglewithlimitedoutput
swing and well controlled power consumption.
Speed Limits
The LT1715 comparator is intended for high speed appli-
cations, where it is important to understand a few limita-
tions. These limitations can roughly be divided into three
categories: input speed limits, output speed limits, and
internal speed limits.
The internal speed limits manifest themselves as disper-
sion. All comparators have some degree of dispersion,
defined as a change in propagation delay versus input
overdrive. The propagation delay of the LT1715 will vary
with overdrive, from a typical of 4ns at 20mV overdrive to
6ns at 5mV overdrive (typical). The LT1715’s primary
source of dispersion is the hysteresis stage. As a change
of polarity arrives at the gain stage, the positive feedback
of the hysteresis stage subtracts from the overdrive avail-
able. Only when enough time has elapsed for a signal to
propagate forward through the gain stage, backwards
through the hysteresis path and forward through the gain
stage again, will the output stage receive the same level of
overdrive that it would have received in the absence of
hysteresis.
There are no significant input speed limits except the
shunt capacitance of the input nodes. If the 2pF typical
input nodes are driven, the LT1715 will respond.
Theoutputspeedisconstrainedbythreemechanisms,the
firstofwhichistheslewcurrentsavailablefromtheoutput
transistors. To maintain low power quiescent operation,
the LT1715 output transistors are sized to deliver 35mA to
60mAtypicalslewcurrents.Thisissufficienttodrivesmall
capacitive loads and logic gate inputs at extremely high
speeds. But the slew rate will slow dramatically with heavy
capacitive loads. Because the propagation delay (tPD)
definition ends at the time the output voltage is halfway
between the supplies, the fixed slew current makes the
LT1715fasterat3Vthan5Vwithlargecapacitiveloadsand
sufficient input overdrive.
The LT1715 is several hundred picoseconds faster when
VEE = –5V, relative to single supply operation. This is due
totheinternalspeedlimit;thegainstageoperatesbetween
VEE and +VS, and it is faster with higher reverse voltage
bias due to reduced silicon junction capacitances.
Inmanyapplications, asshowninthefollowingexamples,
there is plenty of input overdrive. Even in applications
providing low levels of overdrive, the LT1715 is fast
enough that the absolute dispersion of 2ns (= 6 – 4) is
often small enough to ignore.
Another manifestation of this output speed limit is skew,
the difference between tPD+ and tPD–. The slew currents of
the LT1715 vary with the process variations of the PNP
and NPN transistors, for rising edges and falling edges
respectively. The typical 0.5ns skew can have either polar-
ity, rising edge or falling edge faster. Again, the skew will
increase dramatically with heavy capacitive loads.
The gain and hysteresis stage of the LT1715 is simple,
short and high speed to help prevent parasitic oscilla-
tions while adding minimum dispersion. This internal
“self-latch” can be usefully exploited in many applica-
tions because it occurs early in the signal chain, in a low
power, fully differential stage. It is therefore highly im-
mune to disturbances from other parts of the circuit,
such as the output, or on the supply lines. Once a high
speedsignaltripsthehysteresis, theoutputwillrespond,
after some propagation delay, without regard to these
externalinfluencesthatcancausetroubleinnonhysteretic
comparators.
Afinallimittooutputspeedistheturn-onandturn-offtime
of the output devices. Each device has substantial base
charge that requires one nanosecond or more of active
chargingordischargingbythebiascurrentoftheDarlington
driverstage.Whentoggleratesarehighenoughthatinsuf-
ficient time is allowed for this turn-on or turn-off, glitches
mayoccurleadingtodropoutorruntpulses. Furthermore,
power consumption may increase nonlinearly if devices
are not turned off before the opposing cycle. However,
oncethetogglefrequencyincreasesordecreases, thepart
14
LT1715
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U
±VTRIP Test Circuit
Becausethetrianglewaveisattenuated1000:1andfedto
the LT1715’s differential input, the sampled voltages are
therefore 1000 times the input trip voltages. The hyster-
esisandoffsetarecomputedfromthetrippointsasshown.
Theinputtrippointstestcircuitusesa1kHztrianglewave
torepeatedlytripthecomparatorbeingtested.TheLT1715
output is used to trigger switched capacitor sampling of
the triangle wave, with a sampler for each direction.
W
W
SI PLIFIED SCHE ATIC
V
+V
S
CC
150Ω
–IN
OUTPUT
150Ω
+IN
GND
V
EE
1715 SS
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS10 Package
10-Lead Plastic MSOP
(LTC DWG # 05-08-1661)
0.118 ± 0.004*
(3.00 ± 0.102)
0.034
(0.86)
REF
0.043
(1.10)
MAX
10 9
8
7 6
0.007
(0.18)
0° – 6° TYP
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
SEATING
PLANE
0.007 – 0.011
(0.17 – 0.27)
0.021 ± 0.006
(0.53 ± 0.015)
0.005 ± 0.002
(0.13 ± 0.05)
0.0197
(0.50)
BSC
MSOP (MS10) 1100
1
2
3
4 5
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
15
LT1715
U
TYPICAL APPLICATIO
High Performance Sine Wave
to Square Wave Converter
Similar delay performance is achieved with input frequen-
ciesashighas50MHz.Thereis,however,someadditional
encroachment into the central flat zone by both the small
amplitude and large amplitude variations.
Propagationdelayofcomparatorsistypicallyspecifiedfor
a 100mV step with some fraction of that for overdrive. But
in many signal processing applications, such as in com-
munications, the goal is to convert a sine wave, such as a
carrier, to a square wave for use as a timing clock. The
desired behavior is for the output timing to be dependent
on the input timing only. No phase shift should occur as a
function of the input amplitude, which would result in AM
to FM conversion.
With small input signals, the hysteresis and dispersion
make the LT1715 act like a comparator with a 12mV
hysteresis span. In other words, a 12mVP-P sine wave at
10MHzwillbarelytoggletheLT1715,with90°ofphaselag
or 25ns additional delay.
Above 5VP-P at 10MHz, the LT1715 delay starts to de-
crease due to internal capacitive feed-forward in the input
stage. Unlike some comparators, the LT1715 will not
falsely anticipate a change in input polarity, but the feed-
forward is enough to make a transition propagate through
the LT1715 faster once the input polarity does change.
The circuit of Figure 12a is a simple LT1715-based sine
wave to square wave converter. The ±5V supplies on the
input allow very large swing inputs, while the 3V logic
supply keeps the output swing small to minimize cross
talk. Figure 12b shows the time delay vs input amplitude
with a 10MHz sine wave. The LT1715 delay changes just
0.65ns over the 26dB amplitude range; 2.33° at 10MHz.
ThedelayisparticularlyflatyieldingexcellentAMrejection
from 0dBm to 15dBm. If a 2:1 transformer is used to drive
the input differentially, this exceptionally flat zone spans
–5dBm to 10dBm, a common range for RF signal levels.
5
4
25°C
V
V
= 5V
CC
EE
= –5V
3
2
+V = 3V
S
10MHz
5V
3V
SINE WAVE
INPUT
SQUARE WAVE
OUTPUT
+
1
0
632mV
0
2V
6.32V
P-P
P-P
P-P
50Ω
1/2 LT1715
–
–5
5
10
15
20
25
INPUT AMPLITUDE (dBm)
–5V
1715 F12a
1715 F12b
Figure 12a. LT1715-Based Sine Wave to Square Wave Converter
Figure 12b. Time Delay vs Sine Wave Input Amplitude
RELATED PARTS
PART NUMBER
LT1016
DESCRIPTION
COMMENTS
UltraFast Precision Comparator
Industry Standard 10ns Comparator
Single Supply Version of LT1016
6mA Single Supply Comparator
UltraFast Rail-to-Rail Input and Output Comparator
LT1116
12ns Single Supply Ground-Sensing Comparator
7ns, UltraFast, Single Supply Comparator
4.5ns, 3V/5V/±5V Single/Dual Rail-to-Rail Comparators
LT1394
LT1711/LT1712
LT1713/LT1714
LT1719
7ns, Low Power, 3V/5V/±5V Single/Dual Rail-to-Rail Comparators
4.5ns Single Supply 3V/5V Comparator
Rail-to-Rail Input and Output Comparator
Single Comparator Similar to the LT1715
Dual/Quad Comparator Similar to the LT1715
LT1720/LT1721
Dual/Quad 4.5ns, Single Supply 3V/5V Comparator
1715f LT/TP 0401 4K • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2001
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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