LT1010CDD#PBF [Linear]
LT1010 - Fast 150mA Power Buffer; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LT1010CDD#PBF |
| 厂家： | 
Linear |
| 描述： | LT1010 - Fast 150mA Power Buffer; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1010
Fast 1ꢀ0ꢁm ꢂPowe ꢃBuuwe
FTEATURES
DESCRIPTION
The LT®1010 is a fast, unity-gain buffer that can increase
the output capability of existing IC op amps by more than
an order of magnitude. This easy-to-use part makes fast
amplifiers less sensitive to capacitive loading and reduces
thermal feedback in precision DC amplifiers.
n
20MHz Bandwidth
n
75V/µs Slew Rate
n
Drives 10V Into 75ꢀ
5mA Quiescent Current
Drives Capacitive Loads > 1µF
Current and Thermal Limit
n
n
n
Designed to be incorporated within the feedback loop, the
buffer can isolate almost any reactive load. Speed can be
improvedwithasingleexternalresistor. Internaloperating
currents are essentially unaffected by the supply voltage
range. Single supply operation is also practical.
n
Operates from Single Supply ≥ 4.5V
n
Very Low Distortion Operation
n
Available in 8-Pin miniDIP, Plastic TO-220
and Tiny 3mm × 3mm × 0.75mm 8-Pin DFN Packages
This monolithic IC is supplied in 8-pin miniDIP, plastic
TO-220 and 8-pin DFN packages. The low thermal re-
sistance power package is an aid in reducing operating
junction temperatures.
APPLICATIONS
n
Boost Op Amp Output
n
Isolate Capacitive Loads
n
Drive Long Cables
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Audio Amplifiers
n
Video Amplifiers
n
Power Small Motors
n
Operational Power Supply
n
FET Driver
TYPICAL APPLICATION
Very Low Distortion Buffered Preamplifier
+
V
0.4
18V
C2
22pF
V
R
= 10V
OUT
L
P-P
R7
50Ω
= 400Ω
R1
1k
+
0.3
0.2
0.1
0
V
3
2
7
R6
R8
100Ω
+
BOOST
100Ω
IN
OUT
6
OUTPUT
LT1056CN8
LT1010CT
C1
22pF
R2
1M
–
–
4
R3
1k
R4
10k
V
+
V
LM334
= 2mA
NOTE 1: ALL RESISTORS 1% METAL FILM
NOTE 2: SUPPLIES WELL BYPASSED AND LOW Z
R
SET
33.2Ω
1%
O
–
I
V
SET
10
100
1k
10k
100k
+
FREQUENCY (Hz)
V
1010 TA01
–18V
1010 TA02
1010fe
1
LT1010
ABSOLUTE MAXIMUM RATINGS
PRECONDITIONING
100% Thermal Limit Burn In–LT1010CT
(Note 1)
Total Supply Voltage ............................................. 22V
Continuous Output Current (Note 2)................. 150mA
Input Current (Note 3)......................................... 40mA
Junction Temperature Range
LT1010C................................................ 0°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
PIN CONFIGURATION
TOP VIEW
FRONT VIEW
5
TOP VIEW
+
V
1
2
3
4
8
7
6
5
INPUT
NC
+
OUTPUT
V
1
2
3
4
8
7
6
5
INPUT
NC
BIAS
OUT
NC
4
3
2
1
BIAS
–
9
BIAS
OUT
NC
–
–
V
V
V
V
(TAB)
–
V
+
NC
NC
INPUT
DD PACKAGE
N8 PACKAGE
8-LEAD PDIP
T PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5-LEAD PLASTIC TO-220
T
= 150°C, θ = 43°C/W, θ = 7.5°C/W
JA JC
JMAX
T
= 150°C, θ = 100°C/W, θ = 45°C/W
JA JC
T
= 125°C, θ = 50°C/W, θ = 3°C/W
JMAX
JMAX
JA
JC
–
EXPOSED PAD (PIN 9) V CAN BE SOLDERED TO PCB
TO REDUCE THERMAL RESISTANCE (NOTE 7)
ORDER INFORMATION
LEAD FREE FINISH
LT1010CDD#PBF
LT1010CN8#PBF
LT1010CT#PBF
LEAD BASED FINISH
LT1010CDD
TAPE AND REEL
LT1010CDD#TRPBF
LT1010CN8#TRPBF
LT1010CT#TRPBF
TAPE AND REEL
LT1010CDD#TR
LT1010CN8#TR
LT1010CT#TR
PART MARKING
LBWZ
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 100°C
8-Lead (3mm × 3mm) Plastic DFN
8-Lead PDIP
LTC1010CN8
LTC1010CT
PART MARKING
LBWZ
0°C to 100°C
5-Lead Plastic TO-220
PACKAGE DESCRIPTION
8-Lead (3mm × 3mm) Plastic DFN
8-Lead PDIP
0°C to 100°C
TEMPERATURE RANGE
0°C to 100°C
LT1010CN8
LTC1010CN8
LTC1010CT
0°C to 100°C
LT1010CT
5-Lead Plastic TO-220
0°C to 100°C
OBSOLETE PACKAGE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1010fe
2
LT1010
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (See Note 4. Typical values in curves.)
SYMBOL PARAMETER
CONDITIONS (Note 4)
MIN
TYP
MAX
UNITS
V
OS
Output Offset Voltage
(Note 4)
0
–20
150
220
mV
mV
l
V = 15V, V = 0V
20
100
mV
S
IN
I
Input Bias Current
I
I
= 0mA
0
0
0
250
500
800
µA
µA
µA
B
OUT
OUT
≤ 150mA
l
l
A
Large-Signal Voltage Gain
Output Resistance
0.995
1.00
V/V
V
R
I
I
=
=
1mA
150mA
5
5
10
10
12
ꢀ
ꢀ
ꢀ
OUT
OUT
OUT
l
Slew Rate
V = 15V, V
S
=
10V, V
=
8V, R = 100ꢀ
75
V/µs
IN
OUT
L
+
V
V
Positive Saturation Offset
I
I
I
= 0 (Note 5)
1.0
1.1
V
V
SOS
OUT
OUT
OUT
l
l
l
l
l
–
Negative Saturation Offset
Saturation Resistance
Bias Terminal Voltage
Supply Current
= 0 (Note 5)
0.2
0.3
V
V
SOS
R
=
150mA (Note 5)
= 20ꢀ (Note 6)
22
28
ꢀ
ꢀ
SAT
V
R
700
560
840
880
mV
mV
BIAS
BIAS
I
S
I
= 0, I = 0
BIAS
9
10
mA
mA
OUT
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: The output saturation characteristics are measured with 100mV
output clipping. See Applications Information for determining available
output swing and input drive requirements for a given load.
Note 6: The output stage quiescent current can be increased by connecting
+
Note 2: Dissipation must be based on a thermal resistance. See
a resistor between the BIAS pin and V . The increase is equal to the bias
Application Information for power dissipation.
terminal voltage divided by this resistance.
Note 3: In current limit or thermal limit, input current increases sharply
Note 7: Thermal resistance varies depending upon the amount of PC board
with input-output differentials greater than 8V; so input current must be
metal attached to the pin (Pin 9) of the device. θ is specified for a certain
JA
+
limited. Input current also rises rapidly for input voltages 8V above V or
amount of 1oz copper metal trace connecting to Pin 9 as described in the
thermal resistance tables in the Applications Information section.
–
0.5V below V .
Note 4: Specifications apply for 4.5V ≤ V ≤ 40V,
S
–
+
V + 0.5V ≤ V ≤ V – 1.5V and I
= 0, unless otherwise stated.
IN
OUT
Temperature range is 0°C ≤ T ≤ 100°C.
C
1010fe
3
LT1010
TYPICAL PERFORMANCE CHARACTERISTICS
Bandwidth
Phase Lag
Phase Lag
50
40
30
20
10
0
50
50
R
= 200Ω
= 50Ω
L
R
20
10
5
20
10
5
L
R
= 50Ω
L
R
= 50Ω
R = 200Ω
L
L
R
= 200Ω
L
V
C
A
= 100mV
100pF
C
= 100pF
= 50Ω
C
L
= 100pF
= 50Ω
IN
L
V
P-P
L
S
R
R
S
BIAS
= –3dB
I
= 0
R
= 20Ω
BIAS
T = 25°C
J
T = 25°C
T = 25°C
J
J
0
20
30
2
5
10
20
2
5
10
20
10
40
FREQUENCY (MHz)
FREQUENCY (MHz)
QUIESCENT CURRENT (mA)
1010 G02
1010 G03
1010 G01
Small-Step Response
Output Impedance
Capacitive Loading
100
10
1
150
100
50
10
0
R
J
= 100Ω
I
= 0
R
I
J
= 50Ω
= 0
L
BIAS
J
S
BIAS
T = 25°C
T = 25°C
T = 25°C
INPUT
OUTPUT
3nF
100pF
0
–50
–100
–150
–10
–20
0.1µF
0
10
20
30
0.1
1
10
100
0.1
1
10
100
TIME (ns)
FREQUENCY (MHz)
FREQUENCY (MHz)
1010 G05
1010 G04
1010 G06
Slew Response
Negative Slew Rate
Supply Current
80
60
40
20
0
20
15
10
5
400
300
200
100
0
V
V
=
IN
= 0
15V
10V
V
= 1ꢀV
S
S
=
0 ≥ V ≥ –10V
IN
I
L
POSITIVE
15V
R
= 200Ω
= 100Ω
T
= 25°C
L
C
R
L
V
=
S
R
= 100Ω
L
T = 25°C
J
0
I
= 0
BIAS
R
= ꢀ0Ω
L
f ≤ 1MHz
–5
NEGATIVE
–10
–15
–20
R
= 20Ω
100
BIAS
0
50
150
20
–50
200
250
0
10
30
40
0
1
2
3
4
5
TIME (ns)
QUIESCENT CURRENT (mA)
FREQUENCY (MHz)
1010 G07
1010 G08
1010 G09
1010fe
4
LT1010
TYPICAL PERFORMANCE CHARACTERISTICS
Output Offset Voltage
Input Bias Current
Input Bias Current
200
150
100
50
200
150
100
50
200
150
100
50
V
S
= 15V
= 75Ω
V
= 0
V
= 0
IN
IN
R
L
T = 125°C
J
+
–
V
V
= 38V
= –2V
+
–
V
V
= 38V
= –2V
T = 25°C
J
+
–
V
V
= 2V
= –38V
+
–
T = –55°C
J
V
V
= 2V
= –38V
0
0
0
50
50
–100 –50
50
–50
0
100
150
–50
0
100
150
–150
100
150
0
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
1010 G10
1010 G11
1010 G12
Voltage Gain
Output Resistance
Output Noise Voltage
200
150
100
50
12
10
8
1.000
0.999
0.998
T = 25°C
J
I
≤ 150mA
I
= 0
OUT
OUT
V
= 40V
S
6
V
= 4.5V
S
4
R
= 1k
S
R
S
= 50Ω
2
0
0.997
0
100
TEMPERATURE (°C)
10
100
1k
10k
–50
0
50
150
100
TEMPERATURE (°C)
–50
0
50
150
FREQUENCY (Hz)
1010 G15
1010 G14
1010 G13
Positive Saturation Voltage
Negative Saturation Voltage
Supply Current
7
6
5
4
3
4
3
2
1
0
4
3
2
1
0
V
= 0
= 0
= 0
IN
I
I
OUT
BIAS
T = –55°C
J
I
= 150mA
I
= –150mA
L
L
T = 25°C
J
I
= 50mA
= 5mA
I
= –50mA
= –5mA
L
L
T = 125°C
J
I
I
L
L
20
0
10
30
40
50
50
–50
0
100
150
–50
0
100
150
TOTAL SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1010 G18
1010 G16
1010 G17
1010fe
5
LT1010
TYPICAL PERFORMANCE CHARACTERISTICS
Bias Terminal Voltage
Total Harmonic Distortion
Total Harmonic Distortion
0.4
0.3
0.2
0.1
0
0.8
0.6
0.4
0.2
0
1.0
0.9
0.8
0.7
0.6
0.5
V
= ±±0V
R
= 50Ω
I
= 0
BIAS
S
L
f = 10kHz
V
V
=
1ꢀV
10V
= 2ꢀ°C
S
V
=
15V
=
S
C
OUT
T
= 25°C
T
C
R
BIAS
= 100Ω
R
= ±0Ω
I
= 0
R
= 50Ω
BIAS
BIAS
BIAS
R
R
= ꢀ0Ω
L
L
= 100Ω
0.1
1
10
100
1
10
100
1000
–50
50
100
0
150
TEMPERATURE (°C)
OUTPUT VOLTAGE (V
)
FREQUENCY (kHz)
P-P
1010 G20
1010 G21
1010 G19
Shorted Input Characteristics
Peak Power Capability
Peak Output Current
0.5
0.4
0.3
0.2
0.1
0
10
8
50
25
T
= 85°C
V
V
=
S
OUT
15V
= 0
V
V
J
=
OUT
T = 25°C
15V
= 0
C
S
SINK
6
SOURCE
0
TO-220
4
–25
2
0
–50
–10
–5
5
1
10
PULSE WIDTH (ms)
100
–50
0
50
100
150
–15
10
15
0
TEMPERATURE (°C)
INPUT VOLTAGE (V)
1010 G23
1010 G24
1010 G22
1010fe
6
LT1010
APPLICATIONS INFORMATION
General
idealized buffer with the unloaded gain specified for the
LT1010. Otherwise, it has zero offset voltage, bias current
and output resistance. Its output also saturates to the
These notes briefly describe the LT1010 and how it is
1
used;adetailedexplanationisgivenelsewhere. Emphasis
2
internal supply terminals.
here will be on practical suggestions that have resulted
from working extensively with the part over a wide range
of conditions. A number of applications are also outlined
that demonstrate the usefulness of the buffer beyond that
of driving a heavy load.
+
V
+
V
SOS
I
B
R′
V
OS
+
R
OUT
Design Concept
INPUT
A1
OUTPUT
The schematic below describes the basic elements of the
bufferdesign.Theopampdrivestheoutputsinktransistor,
Q3, such that the collector current of the output follower,
Q2, never dropsbelowthe quiescentvalue (determined by
R′ R′ = R
– R
OUT
SAT
–
V
SOS
–
V
1010 AI02
I and the area ratio of D1 and D2). As a result, the high
1
frequency response is essentially that of a simple follower
even when Q3 is supplying the load current. The internal
feedback loop is isolated from the effects of capacitive
loading by a small resistor in the output lead.
Loaded voltage gain can be determined from the unloaded
gain, A , the output resistance, R , and the load resis-
V
OUT
tance, R , using:
L
AVRL
ROUT + RL
AVL
=
+
V
D1
D2
BIAS
Maximum positive output swing is given by:
I
–
+
2
(V+ – VSOS )RL
+
+
Q2
VOUT
=
A1
RSAT + RL
INPUT
Q1
R1
I
1
OUTPUT
The input swing required for this output is:
Q3
ROUT
RL
–
+
+
V
V
= VOUT 1+
– VOS + ∆VOS
1010 AI01
IN
The scheme is not perfect in that the rate of rise of sink
current is noticeably less than for source current. This
can be mitigated by connecting a resistor between the
where ∆V is the 100mV clipping specified for the satu-
OS
ration measurements. Negative output swing and input
drive requirements are similarly determined.
+
bias terminal and V , raising quiescent current. A feature
of the final design is that the output resistance is largely
independentofthefollowerquiescentcurrentortheoutput
loadcurrent.Theoutputwillalsoswingtothenegativerail,
which is particularly useful with single supply operation.
Supply Bypass
The buffer is no more sensitive to supply bypassing than
slower op amps as far as stability is concerned. The
0.1µF disc ceramic capacitors usually recommended for
op amps are certainly adequate for low frequency work.
As always, keeping the capacitor leads short and using
Equivalent Circuit
Below 1MHz, the LT1010 is quite accurately represented
by the equivalent circuit shown here for both small- and
large-signal operation. The internal element, A1, is an
1
R. J. Widlar, “Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,”
Linear Technology Corp. TP-1, April, 1984.
2
See electrical characteristics section for guaranteed limits.
1010fe
7
LT1010
APPLICATIONS INFORMATION
a ground plane is prudent, especially when operating at
high frequencies.
Normally, thermal overload protection will limit dissipa-
tion and prevent damage. However, with more than 30V
across the conducting output transistor, thermal limiting
is not quick enough to ensure protection in current limit.
The thermal protection is effective with 40V across the
conducting output transistor as long as the load current
is otherwise limited to 150mA.
The buffer slew rate can be reduced by inadequate sup-
ply bypass. With output current changes much above
100mA/µs, using 10µF solid tantalum capacitors on both
supplies is good practice, although bypassing from the
positive to the negative supply may suffice.
When used in conjunction with an op amp and heavily
loaded (resistive or capacitive), the buffer can couple into
supply leads common to the op amp causing stability
problems with the overall loop and extended settling time.
Adequatebypassingcanusuallybeprovidedby10µFsolid
tantalum capacitors. Alternately, smaller capacitors could
beusedwithdecouplingresistors. Sometimestheopamp
has much better high frequency rejection on one supply,
so bypass requirements are less on this supply.
Drive Impedance
Whendrivingcapacitiveloads,theLT1010likestobedriven
from a low source impedance at high frequencies. Certain
low power op amps (e.g., the LM10) are marginal in this
respect. Some care may be required to avoid oscillations,
especially at low temperatures.
Bypassingthebufferinputwithmorethan200pFwillsolve
the problem. Raising the operating current also works.
Parallel Operation
Power Dissipation
Parallel operation provides reduced output impedance,
more drive capability and increased frequency response
under load. Any number of buffers can be directly paral-
leled as long as the increased dissipation in individual
units caused by mismatches of output resistance and
offset voltage is taken into account.
InmanyapplicationstheLT1010willrequireheatsinking.
Thermal resistance, junction to still air is 50°C/W for the
TO-220 package and 100°C/W for the miniDIP package.
Circulating air, a heat sink or mounting the package to
a printed circuit board will reduce thermal resistance.
In DC circuits, buffer dissipation is easily computed. In
AC circuits, signal waveshape and the nature of the load
determine dissipation. Peak dissipation can be several
times average with reactive loads. It is particularly im-
portant to determine dissipation when driving large load
capacitance.
When the inputs and outputs of two buffers are connected
, flows between the outputs:
together, a current, ∆I
OUT
VOS1 – VOS2
ROUT1 + ROUT2
∆IOUT
=
With AC loading, power is divided between the two output
transistors. This reduces the effective thermal resistance,
junction to case is 3°C/W for the TO-220 package as long
as the peak rating of neither output transistor is exceeded.
Thetypicalcurvesindicatethepeakdissipationcapabilities
of one output transistor.
where V and R
are the offset voltage and output
OS
OUT
resistance of the respective buffers.
Normally, the negative supply current of one unit will
increase and the other decrease, with the positive supply
+
current staying the same. The worst-case (V → V )
IN
increase in standby dissipation can be assumed to be
∆I V , where V is the total supply voltage.
OUT T
T
Overload Protection
Offset voltage is specified worst case over a range of sup-
ply voltages, input voltage and temperature. It would be
unrealistictousetheseworst-casenumbersabovebecause
paralleled units are operating under identical conditions.
The LT1010 has both instantaneous current limit and
thermaloverloadprotection.Foldbackcurrentlimitinghas
not been used, enabling the buffer to drive complex loads
without limiting. Because of this, it is capable of power
dissipation in excess of its continuous ratings.
1010fe
8
LT1010
APPLICATIONS INFORMATION
The offset voltage specified for V = 15V, V = 0V and
Atlowerfrequencies, thebufferiswithinthefeedbackloop
so that its offset voltage and gain errors are negligible. At
S
IN
T = 25°C will suffice for a worst-case condition.
A
higher frequencies, feedback is through C , so that phase
F
+
V
shift from the load capacitance acting against the buffer
output resistance does not cause loop instability.
I
S
I
Stability depends upon the R C time constant or the
S
F F
A1
LT1010
closed-loop bandwidth. With an 80kHz bandwidth, ring-
V
IN
V
OUT
ing is negligible for C = 0.068µF and damps rapidly for
L
C = 0.33µF. The pulse response is shown in the graph.
L
∆I
OUT
Pulse Response
A2
LT1010
C
= 0.068µF
L
5
0
I
– ∆I
I + ∆I
S OUT
S
OUT
1010 AI03
–5
–
V
C
= 0.33µF
L
Output load current will be divided based on the output
resistance of the individual buffers. Therefore, the avail-
ableoutputcurrentwillnotquitebedoubledunlessoutput
resistances are matched. As for offset voltage, the 25°C
limits should be used for worst-case calculations.
5
0
–5
100
0
50
150
200
TIME (µs)
Parallel operation is not thermally unstable. Should one
unit get hotter than its mates, its share of the output and
its standby dissipation will decrease.
1010 AI05
Small-signalbandwidthisreducedbyC ,butconsiderable
F
isolation can be obtained without reducing it below the
powerbandwidth.Often,abandwidthreductionisdesirable
to filter high frequency noise or unwanted signals.
As a practical matter, parallel connection needs only some
increased attention to heat sinking. In some applications,
a few ohms equalization resistance in each output may be
wise.Onlythemostdemandingapplicationsshouldrequire
matching, and then just of output resistance at 25°C.
R
F
2k
C
F
1nF
Isolating Capacitive Loads
–
A1
LT118A
A2
LT1010
R
S
V
OUT
The inverting amplifier below shows the recommended
method of isolating capacitive loads. Noninverting ampli-
fiers are handled similarly.
2k
V
+
IN
C
L
1010 AI06
R
F
R
The follower configuration is unique in that capacitive
load isolation is obtained without a reduction in small-
signal bandwidth, although the output impedance of the
buffer comes into play at high frequencies. The precision
unity-gain buffer above has a 10MHz bandwidth without
capacitive loading, yet it is stable for all load capacitance
20k
S
V
IN
C
F
100pF
–
A1
LT1007
A2
LT1010
V
OUT
+
C
L
1010 AI04
to over 0.3µF, again determined by R C .
F F
1010fe
9
LT1010
APPLICATIONS INFORMATION
This is a good example of how fast op amps can be made
quite easy to use by employing an output buffer.
stage. Feedback is arranged in the conventional manner,
although the 68µF-0.01µF combination limits DC gain to
unity for all gain settings. For applications sensitive to
NTSC requirements, dropping the 25ꢀ output stage bias
value will aid performance.
Integrator
A lowpass amplifier can be formed just by using large C
F
in the inverter described earlier, as long as the increasing
closed-loop output impedance above the cutoff frequency
is not a problem and the op amp is capable of supplying
the required current at the summing junction.
R2
800Ω
C1
15pF
–
A1
A2
LT1010
V
C
I
OUT
HA2625
1010 AI09
V
IN
+
I
IN
R
F
20k
R1
100Ω
–
A1
LT1012
A2
LT1010
V
OUT
1010 AI07
This shows the buffer being used with a wideband ampli-
fier that is not unity-gain stable. In this case, C1 cannot
be used to isolate large capacitive loads. Instead, it has an
optimum value for a limited range of load capacitances.
+
C
F
500pF
If the integrating capacitor must be driven from the buffer
output, the circuit above can be used to provide capacitive
load isolation. As before, the stability with large capacitive
Thebuffercancausestabilityproblemsincircuitslikethis.
With the TO-220 packages, behavior can be improved by
raising the quiescent current with a 20ꢀ resistor from the
loads is determined by R C .
+
F F
bias terminal to V . Alternately, devices in the miniDIP can
be operated in parallel.
Wideband Amplifiers
It is possible to improve capacitive load stability by oper-
ating the buffer class A at high frequencies. This is done
by using quiescent current boost and bypassing the bias
This simple circuit provides an adjustable gain video
amplifier that will drive 1V into 75ꢀ. The differential
P-P
pair provides gain with the LT1010 serving as an output
–
terminal to V with more than 0.02µF.
15V
TYPICAL SPECIFICATIONS
R2
1.6k
1V INTO 75Ω
P-P
AT A = 2
0.5dB TO 10MHz
3dB DOWN AT 16MHz
AT A = 10
0.5dB TO 4MHz
–3dB = 8MHz
8.2k
25Ω
BIAS
–
+
A1
A2
LT1010
+
22µF
OUTPUT
HA2625
+
22µF
1010 AI10
INPUT
OUTPUT
(75Ω)
LT1010
R1
400Ω
–15V
PEAKING
5pF to 25pF
900Ω
1k
Putting the buffer outside the feedback loop as shown
here will give capacitive load isolation, with large output
capacitorsonlyreducingbandwidth.Bufferoffset,referred
to the op amp input, is divided by the gain. If the load re-
sistance is known, gain error is determined by the output
resistance tolerance. Distortion is low.
INPUT
Q1 Q2
Q1, Q2: 2N3866
GAIN SET
5.1k
–15V
+
0.01µF
68µF
1010 AI08
1010fe
10
LT1010
APPLICATIONS INFORMATION
R3
current boost. The appearance is always worse with fast
rise signal generators than in practical applications.
800Ω
C1
20pF
R4
39Ω
–
Track and Hold
A2
LT1010
A1
HA2625
OUTPUT 1
OUTPUT 2
INPUT
The 5MHz track and hold shown here has a 400kHz power
bandwidth driving 10V. A buffered input follower drives
the hold capacitor, C4, through Q1, a low resistance FET
switch. The positive hold command is supplied by TTL
logic with Q3 level shifting to the switch driver, Q2. The
output is buffered by A3.
+
R1
R2
50Ω 200Ω
R5
39Ω
A3
LT1010
1010 AI11
–
When the gate is driven to V for HOLD, it pulls charge
OTHER
SLAVES
out of the hold capacitor. A compensating charge is put
into the hold capacitor through C3. The step into hold is
made independent of the input level with R7 and adjusted
to zero with R10.
The 50ꢀ video line splitter here puts feedback on one
buffer with the others slaved. Offset and gain accuracy of
slaves depend on their matching with master.
When driving long cables, including a resistor in series
with the output should be considered. Although it reduces
gain, it does isolate the feedback amplifier from the effects
of unterminated lines which present a resonant load.
Since internal dissipation can be quite high when driving
fastsignalsintoacapacitiveload, usingabufferinapower
packageisrecommended.Raisingbufferquiescentcurrent
to 40mA with R3 improves frequency response.
When working with wideband amplifiers, special attention
should always be paid to supply bypassing, stray capaci-
tance and keeping leads short. Direct grounding of test
probes, rather than the usual ground lead, is absolutely
necessary for reasonable results.
This circuit is equally useful as a fast acquisition sample
and hold. An LT1056 might be used for A3 to reduce drift
inholdbecauseitslowerslewrateisnotusuallyaproblem
in this application.
Current Sources
The LT1010 has slew limitations that are not obvious
from standard specifications. Negative slew is subject
to glitching, but this can be minimized with quiescent
A standard op amp voltage to current converter with a
buffer to increase output current is shown here. As usual,
+
V
R3
20Ω
R1
2k
–
Q1
A3
LT118A
INPUT
+
OUTPUT
2N5432
A1
LT118A
A2
LT1010
S
D
+
–
C1
C3
+
50pF
R2
2k
100pF
D2*
6V
A4
LT118A
C2
–
D1
HP2810
R4
2k
C4
1nF
150pF
R8
5k
R5
1k
Q3
2N2907
R9
10k
C5
10pF
Q2
2N2222
HOLD
R6
1k
R10
50k
R7
200k
R11
6.2k
1010 AI12
–
V
*2N2369 EMITTER BASE JUNCTION
1010fe
11
LT1010
APPLICATIONS INFORMATION
excellent matching of the feedback resistors is required to
get high output resistance. Output is bidirectional.
R2
2k
C1
1nF
–
R3
2Ω
A1
LT118A
A2
OUTPUT
R1
100k
0.01%
R2
100k
0.01%
R2(V2 – V1)
R1R4
LT1010
I
=
OUT
+
R4
2k
0.1%
R5
V1
2k
–
+
D1
1N457
0.1%
R4
A3
LT118A
10Ω
0.1%
–
A1
LT1012
A2
LT1010
I
C2
10pF
D2
1N457
OUT
R1
2k
R6
99.8k
0.1%
+
R3
100k
0.01%
R7
99.8k
0.1%
V
V
I
1010 AI13
V
V2
1V/V
10mA/V
R4
1010 AI15
100k
0.01%
enables the current regulator to get control of the output
current from the buffer current limit within a microsecond
for an instantaneous short.
This circuit uses an instrumentation amplifier to eliminate
the matched resistors. The input is not high impedance
and must be driven from a low impedance source like
an op amp. Reversal of output sense can be obtained by
grounding Pin 7 of the LM163 and driving Pin 5.
In the voltage regulation mode, A1 and A2 act as a fast
voltage follower using the capacitive load isolation tech-
nique described earlier. Load transient recovery as well as
capacitive load stability are determined by C1. Recovery
from short circuit is clean.
A2
LT1010
V
10R1
IN
I
=
OUT
Bidirectionalcurrentlimitcanbeobtainedbyaddinganother
op amp connected as a complement to A3.
R1
10Ω
0.1%
V
IN
–
2
7
I
OUT
A1
6
Supply Splitter
LM163
×10
+ 3
Dual supply op amps and comparators can be operated
from a single supply by creating an artificial ground at
half the supply voltage. The supply splitter shown here
can source or sink 150mA.
5
1010AI14
Output resistances of several megohms can be obtained
with both circuits. This is impressive considering the
150mA output capability. High frequency output charac-
teristics will depend on the bandwidth and slew rate of the
amplifiers. Both these circuits have an equivalent output
capacitance of about 30nF.
The output capacitor, C2, can be made as large as neces-
sary to absorb current transients. An input capacitor is
also used on the buffer to avoid high frequency instability
that can be caused by high source impedance.
+
V
C3
Voltage/Current Regulator
R1
0.1µF
10k
ThiscircuitregulatestheoutputvoltageatV untiltheload
V
I
A1
LT1010
+
V /2
current reaches a value programmed by V . For heavier
R2
10k
C1
1nF
C2
0.01µF
loads, it is a precision current regulator.
With output currents below the current limit, the current
regulator is disconnected from the loop by D1 with D2
keeping its output out of saturation. This output clamp
1010 AI16
1010fe
12
LT1010
APPLICATIONS INFORMATION
High Current Booster
5V
Q1
The circuit below uses a discrete stage to get 3A output
capacity. The configuration shown provides a clean, quick
way to increase LT1010 output power. It is useful for high
current loads such as linear actuator coils in disk drives.
INPUT
2N5486
A
B
A2
LT1010
OUTPUT
10M
–5V
0.1µF
4
3
2
+
The 33ꢀ resistors sense the LT1010’s supply current
with the grounded 100ꢀ resistor supplying a load for
the LT1010. The voltage drop across the 33ꢀ resistors
biases Q1 and Q2. Another 100ꢀ value closes a local
feedback loop, stabilizing the output stage. Feedback
to the LT1056 control amplifier is via the 10k value. Q3
and Q4, sensing across the 0.18ꢀ units, furnish current
limiting at about 3.3A.
10k
A1
LTC1050
6
Q2
2N2222
–
0.01µF
7
100Ω
10M
2000pF
0.1µF
1k
5V
–5V
1010 AI18
similarly filtered version of the input signal. The amplified
difference between these signals is used to set Q2’s bias,
and hence, Q1’s channel current. This forces Q1’s V to
15pF
GS
whatever voltage is required to match the circuit’s input
andoutputpotentials.The2000pFcapacitoratA1provides
stable loop compensation. The RC network in A1’s output
preventsitfromseeinghighspeededgescoupledthrough
Q2’scollector-basejunction.A2’soutputisalsofedbackto
theshieldaroundQ1’sgatelead,bootstrappingthecircuit’s
effective input capacitance down to less than 1pF.
10k
15V
0.18Ω
+
1k
Q3
22µF
33Ω
68pF
2N3906
10k
Q1
MJE2955
INPUT
–
+
OUTPUT
LT1056
LT1010
100Ω
Gain-Trimmable Wideband FET Amplifier
100Ω
Q2
A potential difficulty with the previous circuit is that the
gain is not quite unity. The figure labeled A on the next
page maintains high speed and low bias while achieving
a true unity-gain transfer function.
MJE3055
1k
Q4
2N3904
33Ω
1010 AI17
–15V
0.18Ω
22µF
+
This circuit is somewhat similar except that the Q2-Q3
stagetakesgain.A2DCstabilizestheinput-outputpathand
A1 provides drive capability. Feedback is to Q2’s emitter
from A1’s output. The 1k adjustment allows the gain to be
precisely set to unity. With the LT1010, output stage slew
HEAT SINK OUTPUT TRANSISTORS
Wideband FET Input Stabilized Buffer
The figure below shows a highly stable unity-gain buffer
with good speed and high input impedance. Q1 and Q2
constitute a simple, high speed FET input buffer. Q1 func-
tions as a source follower with the Q2 current source load
settingthedrain-sourcechannelcurrent.TheLT1010buffer
provides output drive capability for cables or whatever
load is required. Normally, this open-loop configuration
would be quite drifty because there is no DC feedback. The
LTC®1050 contributes this function to stabilize the circuit.
It does this by comparing the filtered circuit output to a
and full power bandwidth (1V ) are 100V/µs and 10MHz
P-P
respectively. –3dB bandwidth exceeds 35MHz. At A = 10
(e.g., 1k adjustment set at 50ꢀ), full power bandwidth
stays at 10MHz while the –3dB point falls to 22MHz.
With the optional discrete stage, slew exceeds 1000V/µs
and full power bandwidth (1V ) is 18MHz. –3dB band-
P-P
widthis58MHz.AtA=10,fullpowerisavailableto10MHz,
with the –3dB point at 36MHz.
1010fe
13
LT1010
APPLICATIONS INFORMATION
Figures A and B show response with both output stages.
The LT1010 is used in Figure A (Trace A = input, Trace B
= output). Figure B uses the discrete stage and is slightly
faster. Either stage provides more than adequate perfor-
mance for driving video cable or data converters and the
LT1012 maintains DC stability under all conditions.
Thermal Considerations for the MiniDIP Package
The miniDIP package requires special thermal consider-
ations since it is not designed to dissipate much power. Be
awarethatforapplicationsrequiringlargeoutputcurrents,
another package should be used.
Gain-Trimmable Wideband FET Amplifier
15V
10pF
1k
470Ω
Q3
2N3906
Q1
2N5486
INPUT
15V
Q2
2N3904
A
B
A2
LT1010
OUTPUT
0.01µF
3k
1k
2N3904
1k
GAIN
ADJ
3Ω
B
A
10M
10k
2k
300Ω 50Ω 5.6k
3k
10M
3Ω
2N3906
0.1µF
0.1µF
+
–15V
3k
A1
LT1012
1k
–
–15V
0.002µF
1010 AI19
(A)
(B)
A = 0.2V/DIV
B = 0.2V/DIV
A = 0.2V/DIV
B = 0.2V/DIV
1010 AI20
1010 AI21
10ns/DIV
10ns/DIV
Figure A. Waveforms Using LT1010
Figure B. Waveforms Using Discrete Stage
1010fe
14
LT1010
APPLICATIONS INFORMATION
Typical thermal calculations for the miniDIP package are
detailed in the following paragraphs.
Thermal Resistance of DFN Package
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
For 4.8mA supply current (typical at 50°C, 30V supply
voltage—see supply current graphs) to the LT1010 at
15V, P = power dissipated in the part is equal to:
D
(30V)(0.0048A) = 0.144W
The rise in junction is then:
The following table lists thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
(0.144W)(100°C/W—This is θ for the N package)
JA
= 14.4°C.
Table 1. DFN Measured Thermal Resistance
This means that the junction temperature in 50°C ambient
air without driving any current into a load is:
COPPER AREA
THERMAL RESISTANCE
TOPSIDE
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
14.4°C + 50°C = 64.4°C
2500 sq mm 2500 sq mm 2500 sq mm
1000 sq mm 2500 sq mm 2500 sq mm
225 sq mm 2500 sq mm 2500 sq mm
100 sq mm 2500 sq mm 2500 sq mm
40°C/W
45°C/W
50°C/W
62°C/W
Using the LT1010 to drive 8V DC into a 200ꢀ load using
15V power supplies dissipates P in the LT1010 where:
D
V+ – V
V
OUT
(
)
(
(
)
OUT
PD =
For the DFN package, the thermal resistance junction-to-
RL
case (θ ), measured at the Exposed Pad on the back of
JC
15V –8V 8V
)(
)
= 0.280W
the die, is 7.5°C/W.
=
200Ω
Continuous operation at the maximum supply voltage
and maximum load current is not practical due to thermal
limitations. Transient operation at the maximum supply
is possible. The approximate thermal time constant for a
2500sq mm 3/32" FR-4 board with maximum topside and
backside area for one ounce copper is 3 seconds. This
timeconstantwillincreaseasmorethermalmassisadded
(i.e., vias, larger board and other components).
ThiscausestheLT1010junctiontemperaturetoriseanother
(0.280W)(100°C/W) = 28°C.
This heats the junction to 64.4°C + 28°C = 92.4°C.
An example of 1MHz operation further shows the limita-
tions of the N (or miniDIP) package. For 15V operation:
PD at I = 0 at 1MHz* = (10mA)(30V) = 0.30W
L
Foranapplicationwithtransienthighpowerpeaks,average
power dissipation can be used for junction temperature
calculationsaslongasthepulseperiodissignificantlyless
than the thermal time constant of the device and board.
*See Supply Current vs Frequency graph.
This power dissipation causes the junction to heat from
50°C(ambientinthisexample)to50°C+(0.3W)(100°C/W)
= 80°C. Driving 2V
of 1MHz signal into a 200ꢀ load
RMS
causes an additional
2V
200Ω
P =
• 15–2 = 0.130W
(
)
D
to be dissipated, resulting in another (0.130W)(100°C/W)
= 13°C risein junctiontemperatureto80°C +13°C= 93°C.
1010fe
15
LT1010
(Excluding protection circuits)
SCHEMATIC DIAGRAM
R6
15Ω
+
V
R10
200Ω
R7
300Ω
Q11
Q18
R5
1.5k
BIAS
Q17
Q19
R2
1k
R3
R4
R11
Q5
Q2
1k
1k
200Ω
C1
Q20
R14
30pF
Q6
Q7
R12
3k
Q8
Q21
7Ω
OUTPUT
INPUT
Q3
Q12
R8
1k
Q15
R13
200Ω
Q4
Q13
Q22
R1
4k
R9
4k
Q1
Q9
Q10
Q14
Q16
–
V
1010 SD
DEFINITION OF TERMS
Output Offset Voltage: The output voltage measured with
the input grounded (split supply operation).
Saturation Resistance: The ratio of the change in output
saturation voltage to the change in current producing it,
going from no load to full load.*
Input Bias Current: The current out of the input terminal.
Slew Rate: The average time rate of change of output
voltage over the specified output range with an input step
between the specified limits.
Large-Signal Voltage Gain: The ratio of the output volt-
age change to the input voltage change over the specified
input voltage range.*
Bias Terminal Voltage: The voltage between the bias
Output Resistance: The ratio of the change in output volt-
age to the change in load current producing it.*
+
terminal and V .
Supply Current: The current at either supply terminal with
no output loading.
Output Saturation Voltage: The voltage between the
output and the supply rail at the limit of the output swing
toward that rail.
*Pulse measurements (~1ms) as required to minimize thermal effects.
Saturation Offset Voltage: The output saturation voltage
with no load.
1010fe
16
LT1010
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
2.10 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.125
0.40 ± 0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
1010fe
17
LT1010
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
.130 ± .005
.300 – .325
.045 – .065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
8
1
7
6
5
4
.065
(1.651)
TYP
.255 ± .015*
(6.477 ± 0.381)
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
–.015
2
3
.325
.018 ± .003
(0.457 ± 0.076)
.100
(2.54)
BSC
N8 1002
+0.889
8.255
(
)
–0.381
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
.165 – .180
(4.191 – 4.572)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.045 – .055
(1.143 – 1.397)
.230 – .270
(5.842 – 6.858)
.570 – .620
(14.478 – 15.748)
.620
(15.75)
TYP
.460 – .500
(11.684 – 12.700)
.330 – .370
(8.382 – 9.398)
.700 – .728
(17.78 – 18.491)
.095 – .115
(2.413 – 2.921)
SEATING PLANE
.152 – .202
(3.861 – 5.131)
.155 – .195*
(3.937 – 4.953)
.260 – .320
(6.60 – 8.13)
.013 – .023
(0.330 – 0.584)
.067
BSC
.135 – .165
(3.429 – 4.191)
.028 – .038
(0.711 – 0.965)
(1.70)
* MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801
1010fe
18
LT1010
REVISION HISTORY (Revision history begins at Rev E)
REV
DATE
DESCRIPTION
PAGE NUMBER
E
5/11
Revised temperature ranges and values in Absolute Maximum Ratings and Pin Configuration sections
Revised Notes 2 and 4 in Electrical Characteristics section
2
3
Updated temperature values in Power Dissipation, Thermal Considerations for the MiniDIP Package, and Thermal
Resistance of DFN Package sections of the Applications Information section
8, 15
1010fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1010
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1206
250mA, 60MHz Current Feedback Amplifier
1.1A, 35MHz Current Feedback Amplifier
Dual 500mA, 50MHz CFA
900V/µs, Excellent Video Characteristics
900V/µs Slew Rate, Stable with Large Capacitive Loads
LT1210
LT1795
500mA I
ADSL Driver
OUT
LT1886
Dual 700MHz, 200mA Op Amp
DSL Driver
1010fe
LT 0511 REV E • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 1991
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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Linear
LT1010CT#PBF
LT1010 - Fast 150mA Power Buffer; Package: TO-220; Pins: 5; Temperature Range: 0°C to 70°C
Linear
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