LS3N166 [Linear]
Small Signal Field-Effect Transistor, 0.05A I(D), 30V, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HERMETIC SEALED, TO-78, 6 PIN;
| 型号： | LS3N166 |
| 厂家： | 
Linear |
| 描述： | Small Signal Field-Effect Transistor, 0.05A I(D), 30V, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HERMETIC SEALED, TO-78, 6 PIN 晶体管 |
| 文件： | 总2页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LS/3N165, LS/3N166
MONOLITHIC DUAL P-CHANNEL
ENHANCEMENT MODE MOSFET
FEATURES
VERY HIGH INPUT IMPEDANCE
HIGH GATE BREAKDOWN
ULTRA LOW LEAKAGE
LOW CAPACITANCE
LS3N165, LS3N166
3N165, 3N166
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
(TA=25°C unless otherwise noted)
Drain-Source or Drain-Gate Voltage (NOTE 2)
3N165
40 V
3N166
30 V
Gate-Gate Voltage
±80 V
Drain Current (NOTE 2)
Storage Temperature
50 mA
TO-99
TOP VIEW
SOIC
TOP VIEW
-55ºC to +150ºC
-55ºC to +150ºC
+300ºC
Operating Temperature
Lead Temperature (Soldering, 10 sec.)
Power Dissipation (One Side)
Total Derating above 25ºC
300 mW
4.2 mW/ºC
ELECTRICAL CHARACTERISTICS (TA=25°C and VBS=0 unless otherwise noted)
3N165 &
3N166
LS3N165 &
LS3N166
SYMBOL
IGSSR
CHARACTERISTIC
Gate Reverse Leakage Current
Gate Forward Leakage Current
MIN MAX MIN MAX UNITS
CONDITIONS
--
--
10
-10
-25
-200
-400
-30
-5
--
--
--
100
-100
--
VGS=40V
IGSSF
VGS=-40V
TA=+125ºC
--
pA
IDSS
Drain to Source Leakage Current
Source to Drain Leakage Current
On Drain Current
--
-200
-400
-30
-5
VDS=-20 V, VGS=VBS=0V
ISDS
--
--
-5
-2
-2
--
VSD=-20 V, VGD=VDB=0V
ID(on)
VGS(th)
VGS(th)
rDS(on)
gfs
-5
-2
-2
--
mA
V
VDS=-15V VGS=-10 V VSB=0V
Gate Source Threshold Voltage
Gate Source Threshold Voltage
Drain Source ON Resistance
Forward Transconductance
Output Admittance
VDS=-15V ID=-10µA
VDS=VGS ID=-10µA
VSB=0V
VSB=0V
-5
-5
V
300
300 ohms VGS=-20V ID=-100µA VSB=0V
1500 3000 1500 3000 µS
VDS=-15V ID=-10mA
VSB=0V
f=1kHz
gos
--
--
300
3.0
0.7
3.0
--
--
--
--
--
300
3.0
1.0
3.0
µS
pF
µS
Clss
Input Capacitance
Crss
Reverse Transfer Capacitance
Output Capacitance
--
VDS=-15V ID=-10mA
(NOTE 3) VSB=0V
VDS=-15V ID=-10mA
(NOTE 3) VSB=0V
f=1MHz
Coss
RE(Yls)
--
1200
f=100MHz
Common Source Forward
Transconductance
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201138 06/26/2013 Rev#A6 ECN# 3N165 3N166
MATCHING CHARACTERISTICS 3N165
LIMITS
SYMBOL
Gfs1/Gfs2
VGS1-2
CHARACTERISTIC
MIN. MAX. UNITS
CONDITIONS
Forward Transconductance Ratio
Gate Source Threshold Voltage Differential
0.90
--
1.0
VDS=-15V ID=-500 µA f=1kHz VSB=0V
VDS=-15V ID=-500 µA VSB=0V
100
mV
ΔVGS1-2/ΔT Gate Source Threshold Voltage Differential
--
100 µV/ºC VDS=-15V ID=-500 µA VSB=0V
TA=-55ºC to = +125ºC
Change with Temperature
TYPICAL SWITCHING WAVEFORM
INPUT PULSE
Rise Time≤2ns
Pulse Width≥200ns
SAMPLING SCOPE
Tr≤0.2ns
CIN≤2pF
RIN≥10M
Typical Switching Time Test Circuit
NOTES:
1. MOS field effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static charge. To
avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures:
To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when being tested
or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove devices from circuits
with the power on, as transient voltages may cause permanent damage to the devices.
2. Per transistor.
3. For design reference only, not 100% tested.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing
high-quality discrete components. Expertise brought to LIS is based on processes and products developed
at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall,
a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide,
co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems.
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201138 06/26/2013 Rev#A6 ECN# 3N165 3N166
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