1725I [Linear]
General Purpose Isolated Flyback Controller; 通用隔离反激式控制器
| 型号： | 1725I |
| 厂家： | 
Linear |
| 描述： | General Purpose Isolated Flyback Controller |
| 文件： | 总28页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1725
General Purpose
Isolated Flyback Controller
U
FEATURES
DESCRIPTIO
The LT®1725 is a monolithic switching regulator control-
ler specifically designed for the isolated flyback topology.
It drives the gate of an external MOSFET and is generally
poweredfromathirdtransformerwinding. Thesefeatures
allow for an application input voltage limited only by
external power path components. The third transformer
winding also provides output voltage feedback informa-
tion, such that an optoisolator is not required. Its gate
drive capability coupled with a suitable external MOSFET
can deliver load power up to tens of watts.
■
Drives External Power MOSFET with External
I
SENSE Resistor
■
■
Application Input Voltage Limited Only by
External Power Components
Senses Output Voltage Directly from Primary Side
Winding—No Optoisolator Required
Accurate Regulation Without User Trims
Regulation Maintained Well into Discontinuous Mode
Switching Frequency from 50kHz to 250kHz with
External Capacitor
Optional Load Compensation
Optional Undervoltage Lockout
Available in 16-Pin SO and SSOP Packages
■
■
■
■
■
■
The LT1725 has a number of features not found on most
other switching regulator ICs. By utilizing current mode
switchingtechniques, itprovidesexcellentACandDCline
regulation. Its unique control circuitry can maintain regu-
lation well into discontinuous mode in most applications.
Optionalloadcompensationcircuitryallowsforimproved
load regulation. An optional undervoltage lockout pin
halts operation when the application input voltage is too
low. An optional external capacitor implements a soft-
start function. A 3V output is available at up to several mA
for powering primary side application circuitry.
U
APPLICATIO S
■
Telecom Isolated Converters
■
Offline Isolated Power Supplies
■
Instrumentation Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
48V to Isolated 5V Converter
CTX02-14989
6
Output Load Regulation
470pF
5.25
LT1725
18Ω
V
36V TO 72V
IN
35.7k
1%
BAS16
3V
FB
OUT
1
V
IN
= 48V
V
V
= 36V
= 72V
IN
22Ω
47k
V
I
= 5V
= 0 to 2A
3.01k
1%
OUT
OUT
V
CC
SFST
VC
IN
2
9
1nF
47pF
+
12CWQ06
15µF
1µF
5.00
4.75
51Ω
1W
68Ω
OSCAP
11
150pF
820k
33k
UVLO
t
ON
10
+
51k
1.5µF
100pF
150µF
ENDLY
51k
51k
2.7k
4
12
MENAB
0
0.5
1.0
1.5
2.0
I
(A)
LOAD
GATE
R
IRF620
OCMP
1725 F10b
I
R
SENSE
CMPC
SGND
PGND
0.1µF
0.18Ω
1725 TA01a
1725f
1
LT1725
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC Supply Voltage................................................. 22V
UVLO Pin Voltage .................................................... VCC
ISENSE Pin Voltage .................................................... 2V
FB Pin Current ..................................................... ±2mA
Operating Junction
TOP VIEW
ORDER PART
NUMBER
PGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GATE
I
V
CC
SENSE
LT1725CGN
LT1725CS
LT1725IGN
LT1725IS
SFST
t
ON
R
OCMP
ENDLY
MINENAB
SGND
R
Temperature Range
CMPC
OSCAP
LT1725C.............................................. 0°C to 100°C
LT1725I ........................................... –40°C TO 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
V
C
UVLO
GN PART
MARKING
FB
3V
OUT
GN PACKAGE
S PACKAGE
1725
1725I
16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 110°C/W (GN)
TJMAX = 125°C, θJA = 100°C/W (SO)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
V
CC
V
V
V
Turn-On Voltage
Turn-Off Voltage
Hysteresis (Note 3)
●
●
●
14.0
8
4.0
15.1
9.7
5.4
16.0
11
6.5
V
V
V
CC
CC
CC
(V
– V
)
TURN-ON
TURN-OFF
I
Supply Current
Start-Up Current
V = Open
C
●
●
6
10
120
15
280
mA
µA
CC
Feedback Amplifier
V
FB
Feedback Voltage
1.230
1.220
1.245
1.260
1.270
V
V
●
I
Feedback Pin Input Current
500
1000
50
nA
µmho
µA
FB
g
Feedback Amplifier Transconductance
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
Reference Voltage/Current Line Regulation
Voltage Gain
∆l = ±10µA
●
●
400
30
1800
80
m
C
I
, I
SRC SNK
V
2.5
V
CL
12V ≤ V ≤ 18V
●
0.01
2000
40
0.05
50
%/V
V/V
µA
IN
V = 1V to 2V
C
Soft-Start Charging Current
V
V
= 0V
25
SFST
SFST
Soft-Start Discharge Current
= 1.5V, V
= 0V
0.8
1.5
mA
UVLO
Gate Output
V
GATE
Output High Level
Output Low Level
I
I
= 100mA
= 500mA
●
●
11.5
11.0
12.1
11.8
V
V
GATE
GATE
I
I
= 100mA
= 500mA
●
●
0.3
0.6
0.45
1.0
V
V
GATE
GATE
I
t
t
Output Sink Current in Shutdown, V
= 0V
V = 2V
GATE
●
1.2
2.5
30
30
mA
ns
GATE
UVLO
Rise Time
Fall Time
C = 1000pF
L
r
f
C = 1000pF
L
ns
1725f
2
LT1725
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, GATE open, VC = 1.4V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Amplifier
V
V
Control Pin Threshold
Switch Current Limit
Duty Cycle = Min
0.90
0.80
1.12
250
1.25
1.35
V
V
C
●
●
Duty Cycle ≤ 30%
Duty Cycle ≤ 30%
Duty Cycle = 80%
220
200
270
280
mV
mV
mV
ISENSE
220
∆V
ISENSE
/∆V
0.30
mV
C
Timing
f
Switching Frequency
C
= 100pF
90
80
100
115
125
kHz
kHz
OSCAP
●
C
Oscillator Capacitor Value
Minimum Switch On Time
Flyback Enable Delay Time
Minimum Flyback Enable Time
Timing Resistor Value
(Note 2)
33
200
pF
ns
ns
ns
kΩ
%
OSCAP
t
t
t
R
R
R
= 50k
tON
200
200
200
ON
= 50k
= 50k
ED
EN
ENDLY
MENAB
R
(Note 2)
24
85
200
t
Maximum Switch Duty Cycle
●
●
90
Load Compensation
Sense Offset Voltage
Current Gain Factor
UVLO Function
2
5
mV
mV
0.80
1.21
0.95
1.05
V
UVLO Pin Threshold
1.25
1.29
V
UVLO
UVLO
I
UVLO Pin Bias Current
V
V
= 1.2V
= 1.3V
–0.25
–4.50
+0.1
–3.5
+0.25
–2.50
µA
µA
UVLO
UVLO
3V Output Function
V
REF
Reference Output Voltage
Output Impedance
Current Limit
I
= 1mA
●
●
2.8
8
3.0
10
15
3.2
V
Ω
LOAD
mA
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: Component value range guaranteed by design.
Note 3: The V turn-on/turn-off voltages and hysteresis voltage are
CC
proportional in magnitude to each other-guaranteed by design.
1725f
3
LT1725
TYPICAL PERFOR A CE CHARACTERISTICS
U W
VCC Hysteresis Voltage vs
Temperature
VCC Turn-On Voltage vs
Temperature
Start-Up Current vs Temperature
250
200
150
100
50
6.50
6.25
6.00
5.75
5.50
5.25
5.00
4.75
16.00
15.75
15.50
15.25
15.00
14.75
14.50
14.25
0
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
1725 G03
1725 G02
1725 G01
UVLO Pin Input Current vs
Temperature
Oscillator Frequency vs
Temperature
Supply Current vs Temperature
13
12
11
10
9
115
110
105
100
95
1
0
V
= 1.2V
UVLO
–1
–2
–3
–4
–5
–6
V
= 1.3V
UVLO
90
8
–50
85
50
TEMPERATURE (°C)
100 125
0
25
50
75 100 125
–50 –25
0
25
75
–25
50
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
1725 G06
1725 G04
1725 G05
VC Clamp Voltage, Switching
Threshold vs Temperature
VCC-VGATE vs ISOURCE
VGATE vs ISINK
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
1.0
0.8
0.6
0.4
0.2
0
CLAMP VOLTAGE
T
= 125°C
A
T
= 125°C
A
T
= 25°C
A
T = 25°C
A
SWITCHING THRESHOLD
T
= –55°C
A
T
= –55°C
A
50
TEMPERATURE (°C)
100 125
1725 G09
–50 –25
0
25
75
1
10
I
100
(mA)
1000
1
10
100
1000
I
(mA)
SOURCE
SINK
1725 G07
1725 G08
1725f
4
LT1725
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Enable Delay Time vs
Temperature
Minimum Switch-On Time vs
Temperature
Minimum Enable Time vs
Temperature
275
250
225
200
175
150
125
275
250
225
200
175
150
125
275
250
225
200
175
150
125
R
TON
= 50k
R
= 50k
MINENAB
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
1725 G10
1725 G12
1725 G11
Feedback Amplifier
Transconductance vs Temperature
Feedback Amplifier Output Current
vs FB Pin Voltage
80
60
1600
1400
1200
1000
800
40
T
= –55°C
A
T
= 25°C
A
20
0
–20
–40
–60
–80
T
= 125°C
A
600
400
200
–50 –25
50
TEMPERATURE (°C)
100 125
1.10 1.15 1.20 1.25 1.30
FB PIN VOLTAGE (V)
1.40
0
25
75
1.05
1.35
1725 G14
1725 G13
Soft-Start Charging Current vs
Temperature
Soft-Start Sink Current vs
Temperature
2.5
2.0
1.5
1.0
0.5
0
60
50
40
30
20
10
0
V(SFST) = 0V
V(SFST) = 1.5V
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
125
–50 –25
0
25
75
–50
0
25
75
–25
100
1725 G15
1725 G16
1725f
5
LT1725
U
U
U
PI FU CTIO S
PGND (Pin 1): The power ground pin carries the GATE
node discharge current. This is typically a current spike of
several hundred mA with a duration of tens of nanosec-
onds. It should be connected directly to a good quality
ground plane.
third winding transformer turns ratio is the primary deter-
minant of the output voltage. The Thevenin equivalent
resistance of the feedback divider should be roughly 3k.
See Applications Information for more details.
3VOUT (Pin 9): Output pin for nominal 3V reference. This
facilitatesvarioususerapplications.Thisnodeisinternally
current limited for protection and is intended to drive
either moderate capacitive loads of several hundred pF or
less, or, very large capacitive loads of 0.1µF or more. See
Applications Information for more details.
ISENSE (Pin 2): Pin to measure switch current with exter-
nal sense resistor. The sense resistor should be of a
noninductive construction as high speed performance is
essential. Proper grounding technique is also required to
avoid distortion of the high speed current waveform. A
presetinternallimitofnominally250mVatthispineffects
a switch current limit.
UVLO (Pin 10): This pin allows the use of an optional
external resistor divider to set an undervoltage lockout
based upon VIN (not VCC) level. (Note: If the VCC voltage is
sufficient to allow the part to start up, but the UVLO pin is
held below its threshold, output switching action will be
disabled, but the part will draw its normal quiescent
currentfromVCC. Thistypicallycausesabenignrelaxation
oscillation action on the VCC pin in the conventional
“trickle-charge” bootstrapped configuration.)
SFST (Pin 3): Pin for optional external capacitor to effect
soft-start function.SeeApplicationsInformationfordetails.
ROCMP(Pin4):Inputpinforoptionalexternalloadcompen-
sation resistor. Use of this pin allows nominal compensa-
tionfornonzerooutputimpedanceinthepowertransformer
secondarycircuit,includingsecondarywindingimpedance,
output Schottky diode impedance and output capacitor
ESR. In less demanding applications, this resistor is not
needed. See Applications Information for more details.
The bias current on this pin is a function of the state of the
UVLO comparator; as the threshold is exceeded, the bias
current increases. This creates a hysteresis band equal to
the change in bias current times the Thevenin impedance
of the user’s resistive divider. The user may thereby adjust
the impedance of the UVLO divider to achieve a desired
degree of hysteresis. A 100pF capacitor to ground is
recommended on this pin. See Applications Information
for details.
RCMPC (Pin 5): Pin for external filter capacitor for optional
load compensation function. A common 0.1µF ceramic
capacitor will suffice for most applications. See Applica-
tions Information for further details.
OSCAP (Pin 6): Pin for external timing capacitor to set
oscillator switching frequency. See Applications Informa-
tion for details.
SGND (Pin 11): The signal ground pin is a clean ground.
The internal reference, oscillator and feedback amplifier
are referred to it. Keep the ground path connection to the
FBpin, OSCAPcapacitorandtheVC compensationcapaci-
tor free of large ground currents.
VC (pin 7): This is the control voltage pin which is the
output of the feedback amplifier and the input of the
current comparator. Frequency compensation of the
overall loop is effected in most cases by placing a capaci-
tor between this node and ground.
MINENAB (Pin 12): Pin for external programming resistor
tosetminimumenabletime. SeeApplicationsInformation
for details.
FB (Pin 8): Input pin for external “feedback” resistor
divider. The ratio of this divider, times the internal
bandgap (VBG) reference, times the effective output-to-
1725f
6
LT1725
U
U
U
PI FU CTIO S
ENDLY (Pin 13): Pin for external programming resistor to
set enable delay time. See Applications Information for
details.
V
CC (Pin 15): Supply voltage for the LT1725. Bypass this
pin to ground with 1µF or more.
GATE (Pin 16): This is the gate drive to the external power
MOSFET switch and has large dynamic currents flowing
through it. Keep the trace to the MOSFET as short as
possible to minimize electromagnetic radiation and volt-
age spikes. A series resistance of 5Ω or more may help to
dampen ringing in less than ideal layouts.
t
ON (Pin 14): Pin for external programming resistor to set
switch minimum on time. See Applications Information
for details.
W
BLOCK DIAGRA
V
CC
3V
OUT
UVLO
BIAS
3V REG
(INTERNAL)
t
MINENAB ENDLY
ON
OSCAP
GATE
MOSFET
DRIVER
OSC
LOGIC
PGND
I
SENSE
COMP
I
AMP
SGND
FB
LOAD
COMPENSATION
FDBK
SOFT-START
SFST
1725 BD
V
R
R
CMPC
C
OCMP
1725f
7
LT1725
W U
W
TI I G DIAGRA
V
SW
VOLTAGE
COLLAPSE
DETECT
V
FLBK
0.80×
FLBK
V
V
IN
GND
SWITCH
STATE
OFF
ON
OFF
ON
MINIMUM t
ON
ENABLE DELAY
DISABLED
MINIMUM ENABLE TIME
FLYBACK AMP
STATE
ENABLED
DISABLED
1725 TD
W
FLYBACK ERROR A PLIFIER
T1
D1
•
+
+
ISOLATED
C1
V
OUT
•
–
V
IN
•
M1
I
I
FXD
M
V
C
R1
R2
ENAB
FB
V
BG
C2
Q1 Q2
I
1725 EA
I
M
1725f
8
LT1725
U
OPERATIO
The LT1725 is a current mode switcher controller IC
designedspecificallyfortheisolatedflybacktopology. The
Block Diagram shows an overall view of the system. Many
of the blocks are similar to those found in traditional
designs, including: Internal Bias Regulator, Oscillator,
Logic, Current Amplifier and Comparator, Driver and Out-
put Switch. The novel sections include a special Flyback
Error Amplifier and a Load Compensation mechanism.
Also, due to the special dynamic requirements of flyback
control, the Logic system contains additional functionality
not found in conventional designs.
The relatively high gain in the overall loop will then cause
the voltage at the FB pin to be nearly equal to the bandgap
reference VBG. The relationship between VFLBK and VBG
may then be expressed as:
R1+R2
(
)
VFLBK
=
VBG
R2
Combination with the previous VFLBK expression yields an
expression for VOUT in terms of the internal reference,
programming resistors, transformer turns ratio and diode
forward voltage drop:
TheLT1725operatesmuchthesameastraditionalcurrent
mode switchers, the major difference being a different
type of error amplifier that derives its feedback informa-
tion from the flyback pulse. Due to space constraints, this
discussion will not reiterate the basics of current mode
switcher/controllers and isolated flyback converters. A
good source of information on these topics is Application
Note AN19.
R1+R2
(
)
1
NST
VOUT = VBG
– V –ISEC •ESR
F
R2
Additionally, it includes the effect of nonzero secondary
output impedance, which is discussed below in further
detail, see Load Compensation Theory. The practical as-
pects of applying this equation for VOUT are found in the
Applications Information section.
ERROR AMPLIFIER—PSEUDO DC THEORY
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
This is accomplished by the dotted line connections to the
block labeled “ENAB”. Timing signals are then required to
enable and disable the flyback amplifier.
Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when MOSFET output
switch M1 turns off, its drain voltage rises above the VIN
rail.Theamplitudeofthisflybackpulseasseenonthethird
winding is given as:
V
OUT + VF +ISEC •ESR
(
=
)
VFLBK
NST
ERROR AMPLIFIER—DYNAMIC THEORY
There are several timing signals which are required for
proper LT1725 operation. Please refer to the Timing
Diagram.
VF = D1 forward voltage
ISEC = transformer secondary current
ESR = total impedance of secondary circuit
Minimum Output Switch On Time
NST = transformer effective secondary-to-third
winding turns ratio
The LT1725 effects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse and output voltage informa-
tion is no longer available. This would cause irregular loop
responseandstart-up/latchupproblems.Thesolutioncho-
sen is to require the output switch to be on for an absolute
minimumtimepereachoscillatorcycle.Thisinturnestab-
lishes a minimum load requirement to maintain regula-
The flyback voltage is then scaled by external resistor
divider R1/R2 and presented at the FB pin. This is then
compared to the internal bandgap reference by the differ-
ential transistor pair Q1/Q2. The collector current from Q1
is mirrored around and subtracted from fixed current
source IFXD at the VC pin. An external capacitor integrates
this net current to provide the control voltage to set the
current mode trip point.
tion. See Applications Information for further details.
1725f
9
LT1725
U
OPERATIO
Enable Delay
Minimum Enable Time
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
formerprimarysidevoltagewaveformapproximatelyrep-
resents the output voltage. This is partly due to rise time
on the MOSFET drain node, but more importantly, due to
transformer leakage inductance. The latter causes a volt-
age spike on the primary side not directly related to output
voltage. (Some time is also required for internal settling of
the feedback amplifier circuitry.)
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the VC node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
thelowloadlevelatwhichoutputvoltageregulationislost.
See Applications Information for details.
In order to maintain immunity to these phenomena, a
fixed delay is introduced between the switch turnoff
commandandtheenablingofthefeedbackamplifier.This
is termed “enable delay”. In certain cases where the
leakage spike is not sufficiently settled by the end of the
enable delay period, regulation error may result. See
Applications Information for further details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
during only a portion of the cycle time. This can vary from
thefixed“minimumenabletime”describedtoamaximum
of roughly the “off” switch time minus the enable delay
time. Certain parameters of flyback amp behavior will then
be directly affected by the variable enable period. These
include effective transconductance and VC node slew rate.
Collapse Detect
Oncethefeedbackamplifierisenabled, somemechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of VBG. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodatesbothcontinuousanddiscontinuousmode
operation.
LOAD COMPENSATION THEORY
The LT1725 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
T1
V
IN
I
M
M1
R1
R2
+
–
FB
R3
50k
Q1 Q2
V
BG
Q3
A1
I
SENSE
LOAD
COMP I
R
SENSE
I
M
R
OCMP
R
CMPC
1725 F01
Figure 1. Load Compensation Diagram
1725f
10
LT1725
U
OPERATIO
transformer secondary and output capacitor. This has
been represented previously by the expression “ISEC
VOUT
V •EFF
IIN =
•IOUT
•
IN
ESR.” However, it is generally more useful to convert this
expression to an effective output impedance. Because the
secondary current only flows during the off portion of the
duty cycle, the effective output impedance equals the
lumpedsecondaryimpedancetimestheinverseoftheOFF
duty cycle. That is:
combining the efficiency and voltage terms in a single
variable:
IIN = K1 • IOUT, where
VOUT
V •EFF
IN
K1=
1
ROUT = ESR
where
Switch current is converted to voltage by the external
sense resistor and averaged/lowpass filtered by R3 and
the external capacitor on RCMPC. This voltage is then
impressed across the external ROCMP resistor by op amp
A1 and transistor Q3. This produces a current at the
collector of Q3 which is then mirrored around and then
subtracted from the FB node. This action effectively in-
creases the voltage required at the top of the R1/R2
feedback divider to achieve equilibrium. So the effective
change in VOUT target is:
DCOFF
ROUT = effective supply output impedance
ESR = lumped secondary impedance
DCOFF = OFF duty cycle
Expressing this in terms of the ON duty cycle, remember-
ing DCOFF = 1 – DC,
1
ROUT = ESR
1–DC
RSENSE
ROCMP
DC = ON duty cycle
∆VOUT = K1• ∆IOUT
•(R1||R2)or
(
)
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external FB resistor
divider adjusted to compensate for nominal expected
error. Inmoredemandingapplications, outputimpedance
error may be minimized by the use of the load compensa-
tion function.
∆VOUT
∆IOUT
RSENSE
ROCMP
= K1
•(R1||R2)
Nominal output impedance cancellation is obtained by
equating this expression with ROUT
:
RSENSE
ROCMP
Toimplementtheloadcompensationfunction,avoltageis
developed that is proportional to average output switch
current.Thisvoltageisthenimpressedacrosstheexternal
ROCMP resistor, and the resulting current acts to increase
the VBG reference used by the flyback error amplifier. As
outputloadingincreases,averageswitchcurrentincreases
to maintain rough output voltage regulation. This causes
an increase in ROCMP resistor current which effects a
corresponding increase in target output voltage.
ROUT = K1
•(R1||R2) and
RSENSE
ROUT
R
OCMP = K1
•(R1||R2)where
K1 = dimensionless variable related to VIN, VOUT and
efficiency as above
RSENSE = external sense resistor
ROUT = uncompensated output impedance
Assuming a relatively fixed power supply efficiency, Eff,
(R1||R2) = impedance of R1 and R2 in parallel
Power Out = Eff • Power In
VOUT • IOUT = Eff • VIN • IIN
The practical aspects of applying this equation to deter-
mineanappropriatevaluefortheROCMP resistorarefound
in the Applications Information section.
Average primary side current may be expressed in terms
of output current as follows:
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TRANSFORMER DESIGN CONSIDERATIONS
As a rough guide, total leakage inductances of several
percent (of mutual inductance) or less may require a
snubber, but exhibit little to no regulation error due to
leakage spike behavior. Inductances from several percent
up to perhaps ten percent cause increasing regulation
error.
Transformer specification and design is perhaps the most
critical part of applying the LT1725 successfully. In addi-
tion to the usual list of caveats dealing with high frequency
isolated power supply transformer design, the following
information should prove useful.
Severe leakage inductances in the double digit percentage
range should be avoided if at all possible as there is a
potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leak-
age spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into
thinking that the leakage spike itself is the real flyback
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt-
age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera-
tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:
Turns Ratios
Note that due to the use of the external feedback resistor
divider ratio to set output voltage, the user has relative
freedominselectingtransformerturnsratiotosuitagiven
application. In other words, “screwball” turns ratios like
“1.736:1.0” can scrupulously be avoided! In contrast,
simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can
be employed which yield more freedom in setting total
turns and mutual inductance. Turns ratio can then be
chosen on the basis of desired duty cycle. However,
remember that the input supply voltage plus the second-
ary-to-primary referred version of the flyback pulse (in-
cludingleakagespike)mustnotexceedtheallowedexternal
MOSFET breakdown rating.
Leakage Inductance
1. Operate the prototype supply at maximum expected
load current.
Transformer leakage inductance (on either the primary or
secondary)causesaspikeafteroutputswitchturnoff.This
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In many cases a
“snubber” circuit will be required to avoid overvoltage
breakdown at the output switch node. Application Note
AN19 is a good reference on snubber design.
2. Temporarily short circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at a abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the VSW waveform
on an oscilloscope to observe leakage spike behavior
firsthand. A final note—the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V2/R behavior are less susceptible.
In situations where the flyback pulse extends beyond the
enable delay time, the output voltage regulation will be
affected to some degree. It is important to realize that the
feedback system has a deliberately limited input range,
roughly ±50mV referred to the FB node, and this works to
the user’s advantage in rejecting large, i.e., higher voltage,
leakage spikes. In other words, once a leakage spike is
several volts in amplitude, a further increase in amplitude
has little effect on the feedback system. So the user is
generally advised to arrange the snubber circuit to clamp
at as high a voltage as comfortably possible, observing
MOSFET breakdown, such that leakage spike duration is
as short as possible.
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second-
ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,
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which reduces the size of the primary-referred flyback
pulse used for feedback. This will increase the output
voltage target by a similar percentage. Note that unlike
leakage spike behavior, this phenomena is load indepen-
dent. To the extent that the secondary leakage inductance
is a constant percentage of mutual inductance (over
manufacturing variations), this can be accommodated by
adjusting the feedback resistor divider ratio.
The above equation defines only the ratio of R1 to R2, not
their individual values. However, a “second equation for
two unknowns” is obtained from noting that the Thevenin
impedance of the resistor divider should be roughly 3k for
bias current cancellation and other reasons.
SELECTING ROCMP RESISTOR VALUE
The Operation section previously derived the following
expressions for ROUT, i.e., effective output impedance and
ROCMP, the external resistor value required for its nominal
compensation:
Winding Resistance Effects
Resistance in either the primary or secondary will act to
reduce overall efficiency (POUT/PIN). Resistance in the
secondary increases effective output impedance which
degrades load regulation, (at least before load compensa-
tion is employed).
1
ROUT = ESR
1–DC
RSENSE
ROUT
ROCMP = K1
R1||R2
(
)
Bifilar Winding
A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However re-
member that this will increase primary-to-secondary ca-
pacitance and limit the primary-to-secondary breakdown
voltage, so bifilar winding is not always practical.
While the value for ROCMP may therefore be theoretically
determined, it is usually better in practice to employ
empirical methods. This is because several of the required
input variables are difficult to estimate precisely. For
instance, the ESR term above includes that of the trans-
former secondary, but its effective ESR value depends on
high frequency behavior, not simply DC winding resis-
tance. Similarly, K1 appears to be a simple ratio of VIN to
VOUT times (differential) efficiency, but theoretically esti-
mating efficiency is not a simple calculation. The sug-
gested empirical method is as follows:
Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!
SELECTING FEEDBACK RESISTOR DIVIDER VALUES
The expression for VOUT developed in the Operation sec-
tioncanberearrangedtoyieldthefollowingexpressionfor
the R1/R2 ratio:
Build a prototype of the desired supply using the eventual
secondary components. Temporarily ground the RCMPC
pintodisabletheloadcompensationfunction. Operatethe
supply over the expected range of output current loading
while measuring the output voltage deviation. Approxi-
mate this variation as a single value of ROUT (straight line
approximation). Calculate a value for the K1 constant
based on VIN, VOUT and the measured (differential) effi-
ciency. These are then combined with RSENSE as indicated
R1+R2
VOUT + VF +ISEC •ESR
(
)
(
)
=
NST
R2
where:
VOUT = desired output voltage
VF = switching diode forward voltage
VBG
to yield a value for ROCMP
.
ISEC • ESR = secondary resistive losses
Verify this result by connecting a resistor of roughly this
value from the ROCMP pin to ground. (Disconnect the
ground short to RCMPC and connect the requisite 0.1µF
filter capacitor to ground.) Measure the output impedance
VBG = data sheet reference voltage value
NST = effective secondary-to-third winding turns ratio
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with the new compensation in place. Modify the original
ROCMP value if necessary to increase or decrease the
effective compensation.
1000
500
SELECTING OSCILLATOR CAPACITOR VALUE
The switching frequency of the LT1725 is set by an
external capacitor connected between the OSCAP pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 2 shows the nominal relationship between
external capacitance and switching frequency. To mini-
mize stray capacitance and potential noise pickup, this
capacitor should be placed as close as possible to the IC
and the OSCAP node length/area minimized.
100
20
100
250
R
(kΩ)
T
1725 F03
Figure 3. “One Shot” Times vs Programming Resistor
Minimum On Time
300
This time defines a period whereby the normal switch
current limit is ignored. This feature provides immunity to
the leading edge current spike often seen at the source
nodeoftheexternalpowerMOSFET, duetorapidcharging
of its gate/source capacitance. This current spike is not
indicative of actual current level in the transformer pri-
mary, and may cause irregular current mode switching
action, especially at light load.
200
100
50
However, the user must remember that the LT1725 does
not “skip cycles” at light loads. Therefore, minimum on
time will set a limit on minimum delivered power and con-
sequently a minimum load requirement to maintain regu-
lation (see Minimum Load Considerations). Similarly,
minimum on time has a direct effect on short-circuit be-
havior(seeMaximumLoad/Short-CircuitConsiderations).
30
100
(pF)
200
C
OSCAP
1725 F02
Figure 2. fOSC vs OSCAP Value
SELECTING TIMING RESISTOR VALUES
The user is normally tempted to set the minimum on time
to be short to minimize these load related consequences.
(Afterall, asmallerminimumontimeapproachestheideal
caseofzero, ornominimum.)However, alongertimemay
be required in certain applications based on MOSFET
switching current spike considerations.
There are three internal “one-shot” times that are pro-
grammed by external application resistors: minimum on
time, enable delay time and minimum enable time. These
are all part of the isolated flyback control technique, and
theirfunctionshavebeenpreviouslyoutlinedintheTheory
of Operation section. Figures 3 shows nominal observed
time versus external resistor value for these functions.
Enable Delay Time
This function provides a programmed delay between
turnoffofthegatedrivenodeandthesubsequentenabling
of the feedback amplifier. At high loads, a primary side
voltage spike after MOSFET turnoff may be observed due
The following information should help in selecting and/or
optimizing these timing values.
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to transformer leakage inductance. This spike is not in-
dicative of actual output voltage (see Figure 4B). Delaying
the enabling of the feedback amplifier allows this system
to effectively ignore most or all of the voltage spike and
maintain proper output voltage regulation. The enable
delay time should therefore be set to the maximum ex-
pected duration of the leakage spike. This may have
implications regarding output voltage regulation at mini-
mum load (see Minimum Load Considerations).
Minimum Enable Time
This function sets a minimum duration for the expected
flyback pulse. Its primary purpose is to provide a mini-
mum source current at the VC node to avoid start-up
problems.
Average “start-up” VC current =
MinimumEnable Time
•ISRC
SwitchingFrequency
A second benefit of the enable delay time function occurs
at light load. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage (see Figure 4C). So
the enable delay time should also be set long enough to
ignore the “irrelevant” portion of the flyback waveform at
light load.
Minimum enable time can also have implications at light
load (see Minimum Load Considerations). The temptation
is to set the minimum enable time to be fairly short, as this
is the least restrictive in terms of minimum load behavior.
However,toprovidea“reliable”minimumstart-upcurrent
of say, nominally 1µA, the user should set the minimum
enable time at no less that 2% of the switching period
(= 1/switching frequency).
Additionally, there are cases wherein the gate output is
called upon to drive a large geometry MOSFET such that
the turnoff transition is slowed significantly. Under such
circumstances, the enable delay time may be increased to
accommodate for the lengthy transition.
CURRENT SENSE RESISTOR CONSIDERATIONS
The external current sense resistor allows the user to
optimize the current limit behavior for the particular appli-
cation under consideration. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak switch current goes from a fraction of an ampere to
tens of amperes. Care must be taken to ensure proper
circuit operation, especially with small current sense
resistor values.
MOSFET GATE DRIVE
A
B
IDEALIZED FLYBACK
WAVEFORM
Forexample,apeakswitchcurrentof10Arequiresasense
resistorof0.025Ω.Notethattheinstantaneouspeakpower
in the sense resistor is 2.5W, and it must be rated accord-
ingly. The LT1725 has only a single sense line to this re-
sistor.Therefore,anyparasiticresistanceinthegroundside
connection of the sense resistor will increase its apparent
value.Inthecaseofa0.025Ωsenseresistor, onemilliohm
of parasitic resistance will cause a 4% reduction in peak
switch current. So resistance of printed circuit copper
traces and vias cannot necessarily be ignored.
FLYBACK WAVEFORM
WITH LARGE LEAKAGE
SPIKE AT HEAVY LOAD
ENABLE
DELAY
TIME
DISCONTINUOUS
MODE
NEEDED
RINGING
“SLOW” FLYBACK
WAVEFORM AT
LIGHT LOAD
C
Anadditionalconsiderationisparasiticinductance.Induc-
tance in series with the current sense resistor will accen-
tuate the high frequency components of the current
waveform. In particular, the gate switching spike and
ENABLE DELAY
TIME NEEDED
1725 F04
Figure 4
multimegahertzringingattheMOSFETcanbeconsiderably
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The soft-start function is enagaged whenever VCC power
is removed, or as a result of either undervoltage lockout
or thermal (overtemperature) shutdown. The SFST node
is then discharged to roughly a VBE above ground.
(RememberthattheVCpincontrolnodeswitchingthresh-
old is deliberately set at a VBE plus several hundred
millivolts.) When this condition is removed, a nominal
40µA current acts to charge up the SFST node towards
roughly 3V. So, for example, a 0.1µF soft-start capacitor
will place a 0.4V/ms limit on the ramp rate at the VC node.
amplified. If severe enough, this can cause erratic opera-
tion. For example, assume 3nH of parasitic inductance
(equivalenttoabout0.1inchofwireinfreespace)isinseries
withanideal0.025Ωsenseresistor.A“zero”willbeformed
at f = R/(2πL), or 1.3MHz. Above this frequency the sense
resistor will behave like an inductor.
Several techniques can be used to tame this potential
parasitic inductance problem. First, any resistor used for
current sensing purposes must be of an inherently non-
inductive construction. Mounting this resistor directly
above an unbroken ground plane and minimizing its
ground side connection will serve to absolutely minimize
parasitic inductance. In the case of low valued sense
resistors, these may be implemented as a parallel combi-
nation of several resistors for the thermal considerations
citedabove. Theparallelcombinationwillhelptolowerthe
parasitic inductance. Finally, it may be necessary to place
a “pole” between the current sense resistor and the
LT1725 ISENSE pin to undo the action of the inductive zero
(seeFigure5).Avalueof51Ωissuggestedfortheresistor,
whilethecapacitorisselectedempiricallyfortheparticular
application and layout. Using good high frequency mea-
surement techniques, the ISENSE pin waveform may be
observed directly with an oscilloscope while the capacitor
value is varied.
UVLO PIN FUNCTION
The UVLO pin effects an undervoltage lockout function
with at threshold of roughly 1.25V. An external resistor
divider between the input supply and ground can then be
used to achieve a user-programmable undervoltage lock-
out (see Figure 6a).
An additional feature of this pin is that there is a change in
the input bias current at this pin as a function of the state
of the internal UVLO comparator. As the pin is brought
abovetheUVLOthreshold, thebiascurrentsourcedbythe
part increases. This positive feedback effects a hysteresis
band for reliable switching action. Note that the size of the
hysteresis is proportional to the Thevenin impedance of
the external UVLO resistor divider network, which makes
it user programmable. As a rough rule of thumb, each 4k
or so of impedance generates about 1% of hysteresis.
(This is based on roughly 1.25V for the threshold and 3µA
for the bias current shift.)
SENSE RESISTOR ZERO AT:
R
2πL
SENSE
GATE
SENSE
f =
P
51Ω
I
COMPENSATING POLE AT:
C
COMP
R
SENSE
SGND PGND
1
f =
2π(51Ω)C
COMP
Even in good quality ground plane layouts, it is common
for the switching node (MOSFET drain) to couple to the
UVLO pin with a stray capacitance of several thousandths
of a pF. To ensure proper UVLO action, a 100pF capacitor
is recommended from this pin to ground as shown in
Figure 6b. This will typically reduce the coupled noise to
a few millivolts. The UVLO filter capacitor should not be
mademuchlargerthanafewhundredpF, however, asthe
hysteresis action will become too slow. In cases where
further filtering is required, e.g., to attenuate high speed
supply ripple, the topology in Figure 6c is recommended.
Resistor R1 has been split into two equal parts. This
provides a node for effecting capacitor filtering of high
L
P
FOR CANCELLATION:
PARASITIC
L
P
INDUCTANCE
C
COMP
=
R
(51Ω)
SENSE
1725 F05
Figure 5
SOFT-START FUNCTION
The LT1725 contains an optional soft-start function that is
enabled by connecting an explicit external capacitor be-
tweentheSFSTpinandground. Internalcircuitryprevents
thecontrolvoltageattheVC pinfromexceedingthatonthe
SFST pin.
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V
IN
R1/2
R1/2
R2
V
V
IN
IN
C2
R1
R2
R1
R2
UVLO
UVLO
UVLO
C1
100pF
C1
100pF
1725 F06
(6a) “Standard” UVLO
Divider Topology
(6b) Filter Capacitor
Directly On UVLO Node
(6c) Recommended Topology to
Filter High Frequency Ripple
Figure 6
speed supply ripple, while leaving the UVLO pin node
impedance relatively unchanged at high frequency.
V
IN
R1
V
IN
INTERNAL WIDE HYSTERESIS
UNDERVOLTAGE LOCKOUT
+
I
VCC
C1
V
CC
The LT1725 is designed to implement isolated DC/DC
converters operating from input voltages of typically 48V
or more. The standard operating topology utilizes a third
transformer winding on the primary side that provides
both feedback information and local power for the LT1725
viaitsVCC pin.However,thisarrangementisnotinherently
self-starting. Start-up is effected by the use of an external
“trickle-charge” resistor and the presence of an internal
widehysteresisundervoltagelockoutcircuitthatmonitors
VCC pin voltage (see Figure 7). Operation is as follows:
LT1725 GATE
SGND
PGND
1725 F07
V
THRESHOLD
ON
V
VCC
I
VCC
0
V
GATE
Figure 7
“Trickle charge” resistor R1 is connected to VIN and
supplies a small current, typically on the order of a single
mA, tochargeC1. Atfirst, theLT1725isoffanddrawsonly
its start-up current. After some time, the voltage on C1
(VCC)reachestheVCC turn-onthreshold. TheLT1725then
turns on abruptly and draws its normal supply current.
Switching action commences at the GATE pin and the
MOSFET begins to deliver power. The voltage on C1
begins to decline as the LT1725 draws its normal supply
current, which greatly exceeds that delivered by R1. After
some time, typically tens of milliseconds, the output
voltage approaches its desired value. By this time, the
third transformer winding is providing virtually all the
supply current required by the LT1725.
drawn by the LT1725 will discharge C1 too rapidly; before
the third winding drive becomes effective, the VCC turn-off
threshold will be reached. The LT1725 turns off, and the
V
CC node begins to charge via R1 back up to the turn-on
threshold. Depending upon the particular situation, this
may result in either several on-off cycles before proper
operation is reached, or, permanent relaxation oscillation
at the VCC node.
Component selection is as follows:
Resistor R1 should be selected to yield a worst-case
minimum charging current greater than the maximum
rated LT1725 start-up current, and a worst-case maxi-
mum charging current less than the minimum rated
One potential design pitfall is undersizing the value of
capacitor C1. In this case, the normal supply current
LT1725 supply current.
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Capacitor C1 should then be made large enough to avoid
the relaxation oscillatory behavior described above. This
is complicated to determine theoretically as it depends on
the particulars of the secondary circuit and load behavior.
Empirical testing is recommended. (Use of the optional
soft-start function will lengthen the power-up timing and
require a correspondingly larger value for C1.)
OUTPUT VOLTAGE ERROR SOURCES
Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error: the internal or external resistor divider
network that connects to VOUT and the internal IC refer-
ence.TheLT1725,whichsensestheoutputvoltageinboth
a dynamic and an isolated manner, exhibits additional
potential error sources to contend with. Some of these
errors are proportional to output voltage, others are fixed
in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution.
A further note—certain users may wish to utilize the
general functionality of the LT1725, but may have an
available input voltage significantly lower than, say, 48V.
If this input voltage is within the allowable VCC range, i.e.,
perhaps20Vmaximum, theinternalwidehysteresisrange
UVLOfunctionbecomescounterproductive.Insuchcases
it is simply better to operate the LT1725 directly from the
available DC input supply. The LT1737 is identical to the
LT1725, with the exception that it lacks the internal wide
hysteresis UVLO function. It is therefore designed to
operate directly from DC input supplies in the range of
4.5V to 20V. See the LT1737 data sheet for further
information.
Internal Voltage Reference
The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications.
User Programming Resistors
Outputvoltageiscontrolledbytheuser-suppliedfeedback
resistor divider ratio. To the extent that the resistor ratio
differs from the ideal value, the output voltage will be
proportionally affected. Highest accuracy systems will
demand 1% components.
FREQUENCY COMPENSATION
Loop frequency compensation is performed by connect-
ing a capacitor from the output of the error amplifier (VC
pin) to ground. An additional series resistor, often re-
quired in traditional current mode switcher controllers, is
usually not required and can even prove detrimental. The
phase margin improvement traditionally offered by this
extra resistor will usually be already accomplished by the
nonzerosecondarycircuitimpedance,whichaddsa“zero”
to the loop response.
Schottky Diode Drop
The LT1725 senses the output voltage from the trans-
formerprimarysideduringtheflybackportionofthecycle.
This sensed voltage therefore includes the forward drop,
VF, of the rectifier (usually a Schottky diode). The nominal
VF of this diode should therefore be included in feedback
resistor divider calculations. Lot to lot and ambient tem-
perature variations will show up as output voltage shift/
drift.
In further contrast to traditional current mode switchers,
VC pinrippleisgenerallynotanissuewiththeLT1725. The
dynamic nature of the clamped feedback amplifier forms
an effective track/hold type response, whereby the VC
voltagechangesduringtheflybackpulse,butisthen“held”
during the subsequent “switch on” portion of the next
cycle. This action naturally holds the VC voltage stable
duringthecurrentcomparatorsenseaction(currentmode
switching).
Secondary Leakage Inductance
Leakage inductance on the transformer secondary re-
duces the effective secondary-to-third winding turns ratio
(NS/NT) from its ideal value. This will increase the output
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part to
part, this can be accommodated by adjusting the feedback
resistor ratio.
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f = switching frequency
Output Impedance Error
LPRI = transformer primary side inductance
VIN = input voltage
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the feedback resistor divider ratio adjusted for nomi-
nal expected error. In more demanding applications, out-
put impedance error may be minimized by the use of the
load compensation function (see Load Compensation).
VOUT = output voltage
tON = output switch minimum on time
An additional constraint has to do with the minimum
enable time. The LT1725 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, tED, plus the
minimum enable time, tEN. Minimum power delivered to
the load is then:
MINIMUM LOAD CONSIDERATIONS
2
]
1
f
The LT1725 generally provides better low load perfor-
mance than previous generation switcher/controllers uti-
lizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into discon-
tinuousmode. Nevertheless, therestillremainconstraints
to ultimate low load operation. These relate to the mini-
mum switch on time and the minimum enable time.
Discontinuous mode operation will be assumed in the
following theoretical derivations.
Minimum Power =
VOUT • tEN + tED
(
)
[
2 LSEC
= VOUT •IOUT
Which yields a minimum output constraint:
2
)
1 f • VOUT
IOUT(MIN)
=
tED + tEN
(
where
2
LSEC
f = switching frequency
LSEC = transformer secondary side inductance
VOUT = output voltage
As outlined in the Operation section, the LT1725 utilizes a
minimum output switch on time, tON. This value can be
combined with expected VIN and switching frequency to
yield an expression for minimum delivered power.
tED = enable delay time
tEN = minimum enable time
1
f
2
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum on time”
constrained,or“minimumflybackpulsetime”constrained.
(A final note—LPRI and LSEC refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
Minimum Power =
V • t
IN ON
(
)
2 LPRI
= VOUT •IOUT
This expression then yields a minimum output current
constraint:
2
)
1
f
IOUT(MIN)
=
V • tON
IN
(
where
2 LPRI • VOUT
1725f
19
LT1725
W U U
U
APPLICATIO S I FOR ATIO
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
VIN = input voltage
NSP = secondary-to-primary turns ratio ( NSEC/NPRI
)
The LT1725 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 2.5V, then acts as an output switch peak
current limit.
Trouble is typically only encountered in applications with
a relatively high product of input voltage times secondary-
to-primary turns ratio and/or a relatively long minimum
switchontime.(Additionally,severalrealworldeffectssuch
astransformerleakageinductance,ACwindinglosses,and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate.)
This 2.5V at the VC pin corresponds to a value of 250mV
at the ISENSE pin, when the (ON) switch duty cycle is less
than 40%. For a duty cycle above 40%, the internal slope
compensation mechanism lowers the effective ISENSE
voltage limit. For example, at a duty cycle of 80%, the
nominal ISENSE voltage limit is 220mV. This action be-
comes the switch current limit specification. Maximum
available output power is then determined by the switch
current limit, which is somewhat duty cycle dependent
due to internal slope compensation action.
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage condition does not cause excessive die tempera-
tures. The 16-lead SO package is rated at 100°C/W, and
the 16-lead GN at 110°C/W.
Average supply current is simply the sum of quiescent
current given in the specifications section plus gate drive
current. Gate drive current can be computed as:
Overcurrent conditions are handled by the same mecha-
nism. The output switch turns on, the peak current is
quickly reached and the switch is turned off. Because the
outputswitchisonlyonforasmallfractionoftheavailable
period, power dissipation is controlled.
IG = f • QG where
QG = total gate charge
f = switching frequency
Loss of current limit is possible under certain conditions.
Remember that the LT1725 normally exhibits a minimum
switchontime,irrespectiveofcurrenttrippoint.Iftheduty
cycleexhibitedbythisminimumontimeisgreaterthanthe
ratio of secondary winding voltage (referred-to-primary)
divided by input voltage, then peak current will not be
controlled at the nominal value, and will cycle-by-cycle
ratchet up to some higher level. Expressed mathemati-
cally, the requirement to maintain short-circuit control is:
(Note:TotalgatechargeismorecomplicatedthanCGS •VG
as it is frequently dominated by Miller effect of the CGD.
Furthermore, both capacitances are nonlinear in practice.
Fortunately, most MOSFET data sheets provide figures
and graphs which yield the total gate charge directly per
operating conditions.) Nearly all gate drive power is dissi-
pated in the IC, except for a small amount in the external
gate series resistor, so total IC dissipation may be com-
puted as:
V +ISC •RSEC
(
F
)
PD(TOTAL) = VCC (IQ + • f • QG ), where
tON • f <
where
V •NSP
IN
IQ = quiescent current (from specifications)
QG = total gate charge
tON = output switch minimum on time
f = switching frequency
f = switching frequency
ISC = short-circuit output current
VF = output diode forward voltage at ISC
RSEC = resistance of transformer secondary
VCC = LT1725 supply voltage
1725f
20
LT1725
W U U
APPLICATIO S I FOR ATIO
U
GATE DRIVE RESISTOR CONSIDERATIONS
SWITCH NODE CONSIDERATIONS
The gate drive circuitry internal to the LT1725 has been
designed to have as low an output impedance as practi-
cally possible—only a few ohms. A strong L/C resonance
is potentially presented by the inductance of the path
leading to the gate of the power MOSFET and its overall
gate capacitance. For this reason the path from the GATE
package pin to the physical MOSFET gate should be kept
as short as possible, and good layout/ground plane prac-
tice used to minimize the parasitic inductance.
For maximum efficiency, gate drive rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the
components connected to the IC is essential, especially
the power paths (primary and secondary). B field (mag-
netic) radiation is minimized by keeping MOSFET leads,
output diode, and output bypass capacitor leads as short
as possible. E field radiation is kept low by minimizing the
length and area of all similar traces. A ground plane
should always be used under the switcher circuitry to
prevent interplane coupling.
Anexplicitseriesgatedriveresistormaybeusefulinsome
applications to damp out this potential L/C resonance
(typically tens of MHz). A minimum value of perhaps
several ohms is suggested, and higher values (typically a
few tens of ohms) will offer increased damping. However,
as this resistor value becomes too large, gate voltage rise
time will increase to unacceptable levels, and efficiency
will suffer due to the sluggish switching action.
The high speed switching current paths are shown sche-
matically in Figure 8. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri-
mary and MOSFET, and the path containing the trans-
former secondary, output diode and output capacitor
contain “nanosecond” rise and fall times. Keep these
paths as short as possible.
V
V
IN
CC
+
+
+
V
CC
SECONDARY
POWER
PATH
GATE
PRIMARY
POWER
PATH
GATE
PGND
DISCHARGE
PATH
1725 F08
Figure 8. High Speed Current Switching Paths
1725f
21
LT1725
U
TYPICAL APPLICATIO S
TELECOM 48V TO ISOLATED 15V APPLICATION
ground-referred version of the flyback voltage waveform
for both feedback information and providing power to the
LT1725 itself.
The design in Figure 9 accepts an input voltage in the
range of 36V to 72V and outputs an isolated 15V at up to
2A. Transformer T1 is an off-the-shelf VERSA-PAKTM
#VP5-0155, produced by Coiltronics. As manufactured, it
consists of six ideally identical independent windings. In
this application, three windings are stacked in series on
the primary side and two are placed in parallel on the
secondaryside.Thisarrangementprovidesa3:1primary-
to-secondary turns ratio while maximizing overall effi-
ciency. The remaining winding provides a primary-side
Capacitor C7 sets the switching frequency at approxi-
mately 200kHz. Optimal load compensation for the trans-
formerandsecondarycircuitcomponentsissetbyresistor
R8. Output voltage regulation and overall efficiency are
shown in the accompanying graphs. The resistor divider
formed by R14 and R15 sets the undervoltage lockout
thresholdatabout32V,withahysteresisbandofabout2V.
The soft-start and 3VOUT features are unused as shown.
VERSA-PAK is a trademark of Coiltronics, Inc
T1
VP5-0155
7
D5
BAS16
•
6
V
IN
C2
1.5µF
×3
3
D3
1N5257
•
D1
MBRD660
V
OUT
15V
10
4
R14
R1
R10
18Ω
R11
12
1
11
C5
1µF
C4
150µF
820k
24k
150Ω
•
•
R13
750Ω
1W
D4
+
1N5257
+
C1
22µF
•
•
2
9
5
C3
100pF
C10
R15
100pF 33k
R3
34.0k
1%
D2
MBRS1100
8
15
9
10
R12
5.1Ω
16
M1
3V
OUT
UVLO
V
CC
GATE
8
7
IRF620
R9
FB
LT1725
51Ω
2
V
C
I
SENSE
SGND PGND
11
R4
3.01k
1%
C9
470pF
R2
0.1Ω
OSCAP SFST
t
ENDLY MENAB
13 12
R6 R7
R
R
CMPC
ON
OCMP
4
6
3
14
5
1
1725 F09a
C6
1nF
C7
47pF
R5
51k
R8
6.2k
C8
0.1µF
51k 51k
Figure 9. 48V to Isolated 15V Converter
1725f
22
LT1725
U
TYPICAL APPLICATIO S
Application Regulation
Application Efficiency
15.5
90
80
70
60
50
40
30
20
V
V
= 48V
IN
OUT
= 15V
V
= 48V
IN
V
= 36V
IN
15.0
V
= 72V
IN
14.5
0
0.5
1.0
1.5
(A)
2.0
2.5
0.01
0.1
1
10
I
I
(A)
LOAD
LOAD
1725 F09c
1725 F09b
48V to Isolated 15V Application Parts List
T1: Coiltronics VP5-0155 VERSA-PAK
C8: 0.1µF, 25V, Z5U ceramic capacitor
C9: 470pF, 25V, X7R ceramic capacitor
C10: 100pF, 25V, X7R ceramic capacitor
R1: 24k, 1/4W, 5% resistor
M1: International Rectifier IRF620. 200V, 0.8Ω N-channel
MOSFET
D1: Motorola MBRD660. 6A, 60V Schottky diode
D2: Motorola MBRS1100. 1A, 100V Schottky diode
D3, D4: 1N5257. 33V, 500mW Zener diode
D5: BAS16. 75V rectifier diode
R2: IRC LR2010. 0.1Ω, 1/2W current sense resistor
R3: 34.0k, 1% resistor
R4: 3.01k, 1% resistor
C1: AVX TPSD226M025R0200. 22µF, 25V tantalum
capacitor
R5, R6, R7: 51k, 5% resistor
R8: 6.2k, 5% resistor
C2a,C2b,C2c:Vishay/VitramonVJ1825Y155MXB.1.5µF,
100V X7R ceramic capacitor
R9: 51Ω, 5% resistor
R10: 18Ω, 5% resistor
C3: 100pF, 100V, X7R ceramic capacitor
R11: 150Ω, 1/4W, 5% resistor
R12: 5.1Ω, 5% resistor
C4: Sanyo 20SV150M. 150µF, 20V, OS-CON electrolytic
capacitor
C5: 1µF, 25V, Z5U ceramic capacitor
C6: 1nF, 25V, X7R ceramic capacitor
C7: 47pF, 25V NPO/COG ceramic capacitor
R13a, R13b: 1.5k, 1/2W, 5% resistor
R14: 820k, 5% resistor
R15: 33k, 5% resistor
1725f
23
LT1725
U
TYPICAL APPLICATIO S
TELECOM 48V TO ISOLATED 5V APPLICATION
The design in Figure 10 accepts an input voltage in the
rangeof36Vto72Vandoutputsanisolated5Vatupto2A.
TransformerT1isavailableasaCoiltronicsCTX02-14989.
Capacitor C7 sets the switching frequency at approxi-
mately 275kHz. Optimal load compensation for the trans-
formerandsecondarycircuitcomponentsissetbyresistor
R8. Output voltage regulation and overall efficiency are
shown in the accompanying graphs. Efficiency is shown
bothwithandwithouttheR11preload.Theresistordivider
formed by R13 and R14 sets the undervoltage lockout
thresholdatabout32V,withahysteresisbandofabout2V.
The soft-start and 3VOUT features are unused as shown.
T1
CTX02-14989
6
C5
R9
470pF
D2
18Ω
BAS16
1
2
V
IN
V
OUT
5V
9
C2
1.5µF
R13
R10
R1
47k
D1
12CWQ06
R12
820k
22Ω
R11
51Ω
1W
68Ω
11
10
C4
150pF
C9
R14
100pF 33k
+
+
R3
35.7k
1%
C1
15µF
C10
1µF
C3
150µF
12
4
15
9
10
3V
OUT
UVLO
V
CC
8
7
16
2
M1
IRF620
FB
GATE
SENSE
LT1725
V
C
I
R4
3.01k
1%
R2
OSCAP SFST
t
ENDLY MENAB
13 12
R6 R7
R
R
SGND PGND
11
ON
OCMP
4
CMPC
0.18Ω
6
3
14
5
1
1725 F10a
C6
1nF
C7
47pF
R5
51k
R8
2.7k
C8
0.1µF
51k 51k
Figure 10. 48V to Isolated 5V Converter
Application Regulation
Application Efficiency
5.25
5.00
90
V
IN
= 48V
80
70
60
50
40
30
20
V
= 48V
WITHOUT R11
PRELOAD
IN
V
V
= 36V
= 72V
IN
IN
WITH R11
PRELOAD
4.75
0
0.5
1.0
1.5
2.0
0.01
0.1
1
10
I
(A)
I
(A)
LOAD
LOAD
1725 F10c
1725 F10b
1725f
24
LT1725
U
TYPICAL APPLICATIO S
48V to Isolated 5V Application Parts List
T1: Coiltronics CTX02-14989
C9: 100pF, 25V, X7R ceramic capacitor
C10: 1µF, 25V, Z5U ceramic capacitor
R1: 47k, 1/4W, 5% resistor
M1: International Rectifier IRF620. 200V, 0.8Ω N-channel
MOSFET
D1:InternationalRectifier12CWQ06FN.12A,60VSchottky
diode
R2: Panasonic type ERJ-14RSJ. 0.18Ω, 1/4W, 5%
resistor
D2: BAS16. 75V switching diode
R3: 35.7k, 1% resistor
R4: 3.01k, 1% resistor
R5, R6, R7: 51k, 5% resistor
R8: 2.7k, 5% resistor
C1: AVX TPSD156M035R0300. 15µF, 35V tantalum
capacitor
C2:Vishay/VitramonVJ1825Y155MXB.1.5µF,100V,X7R
ceramic capacitor
R9: 18Ω, 5% resistor
R10: 22Ω, 5% resistor
R11: 51Ω, 1W, 5% resistor
R12: 68Ω, 5% resistor
R13: 820k, 5% resistor
R14: 33k, 5% resistor
C3: Sanyo 6SA150M. 150µF, 6.3V, OS-CON electrolytic
capacitor
C4: 150pF, 100V, X7R ceramic capacitor
C5: 470pF, 50V, X7R ceramic capacitor
C6: 1nF, 25V X7R ceramic capacitor
C7: 47pF, 25V, NPO ceramic capacitor
C8: 0.1µF, 25V, Z5U ceramic capacitor
1725f
25
LT1725
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
1725f
26
LT1725
U
PACKAGE DESCRIPTIO
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
0.228 – 0.244
(3.810 – 3.988)
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
0.016 – 0.050
(0.406 – 1.270)
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1725f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LT1725
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1424-5
Isolated Flyback Switching Regulator
Isolated Flyback Switching Regulator
Isolated Flyback Switching Regulator
Ultralow Noise 1A Switching Regulator
5V Output Voltage, No Optoisolator Required
9V Output , Regulation Maintained Under Light Loads
No Third Winding or Optoisolator Required
LT1424-9
LT1425
LT1533
Low Switching Harmonics and Reduced EMI, V = 2.7V to 23V
IN
LT1681/LTC1698
Isolated DC/DC Controller Chip-Set in Ouarter
and Half-Brick Footprint
36V ≤ V ≤ 72V; V : 3.3V, 5V; P
Half the cost of a DC/DC Module; Low Profile, High Efficiency
≤ 100W;
IN
OUT
OUT
LT1737
High Power Isolated Flyback Controller
Powered from a DC Supply Voltage
1725f
LT/TP 1201 2K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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